F-Tile Interlaken Intel FPGA IP Design Eksample
Quick Bẹrẹ Itọsọna
F-Tile Interlaken Intel® FPGA IP mojuto n pese aaye idanwo kikopa kan. A hardware oniru example ti o ṣe atilẹyin akopọ ati idanwo ohun elo yoo wa ni ẹya sọfitiwia Intel Quartus® Prime Pro Edition 21.4. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe adaṣe, ṣajọ, ati idanwo apẹrẹ naa.
Awọn testbench ati oniru example ṣe atilẹyin NRZ ati ipo PAM4 fun awọn ẹrọ F-tile. F-Tile Interlaken Intel FPGA IP mojuto ṣe ipilẹṣẹ apẹrẹ examples fun awọn akojọpọ atilẹyin atẹle ti nọmba awọn ọna ati awọn oṣuwọn data.
Awọn akojọpọ IP Atilẹyin ti Nọmba Awọn ọna ati Awọn oṣuwọn data
Awọn akojọpọ atẹle ni atilẹyin ni ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.3. Gbogbo awọn akojọpọ miiran yoo ṣe atilẹyin ni ẹya ọjọ iwaju ti Intel Quartus Prime Pro Edition.
|
Nọmba ti Awọn ọna |
Oṣuwọn Lane (Gbps) | ||||
| 6.25 | 10.3125 | 12.5 | 25.78125 | 53.125 | |
| 4 | Bẹẹni | – | Bẹẹni | Bẹẹni | – |
| 6 | – | – | – | Bẹẹni | Bẹẹni |
| 8 | – | – | Bẹẹni | Bẹẹni | – |
| 10 | – | – | Bẹẹni | Bẹẹni | – |
| 12 | – | Bẹẹni | Bẹẹni | Bẹẹni | – |
Ṣe nọmba 1.Awọn Igbesẹ idagbasoke fun Oniru Example
Akiyesi: Akopọ Hardware ati Idanwo yoo wa ni ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.4.
F-Tile Interlaken Intel FPGA IP apẹrẹ mojuto example ṣe atilẹyin awọn ẹya wọnyi:
- Ti abẹnu TX to RX ni tẹlentẹle loopback mode
- Laifọwọyi ṣe ipilẹṣẹ awọn apo-iwe iwọn ti o wa titi
- Awọn agbara iṣayẹwo idii ipilẹ
- Agbara lati lo System Console lati tun apẹrẹ fun idi idanwo tun-ṣe
Ṣe nọmba 2.High-level Block Diagram
Alaye ti o jọmọ
- F-Tile Interlaken Intel FPGA IP Itọsọna olumulo
- F-Tile Interlaken Intel FPGA IP Awọn akọsilẹ idasilẹ
Hardware ati Software Awọn ibeere
Lati ṣe idanwo exampFun apẹrẹ, lo hardware ati sọfitiwia atẹle:
- Ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.3
- Console System
- Simulator atilẹyin:
- Afoyemọ* VCS*
- Synopsys VCS MX
- Siemens* EDA ModelSim* SE tabi Questa*
Akiyesi: Hardware support fun oniru example yoo wa ninu ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.4.
Ti o npese awọn Design
Olusin 3. Ilana
Tẹle awọn igbesẹ wọnyi lati ṣe ina apẹrẹ example ati testbench:
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Intel Quartus Prime tuntun, tabi tẹ File ➤ Ṣii Project lati ṣii iṣẹ Intel Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan.
- Pato ẹbi ẹrọ Agilex ki o yan ẹrọ pẹlu F-Tile fun apẹrẹ rẹ.
- Ninu Katalogi IP, wa ati tẹ F-Tile Interlaken Intel FPGA IP lẹẹmeji. Ferese Iyatọ IP Tuntun yoo han.
- Pato orukọ ipele oke kan fun aṣa IP iyatọ rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
- Tẹ O DARA. Olootu paramita yoo han.
Aworan 4. Eksample Design Tab
6. Lori awọn IP taabu, pato awọn sile fun nyin IP mojuto iyatọ.
7. Lori EksampLe Design taabu, yan Simulation aṣayan lati se ina testbench.
Akiyesi: Aṣayan Synthesis jẹ fun hardware example design, eyi ti yoo wa ni Intel Quartus Prime Pro Edition software version 21.4.
8. Fun Ti ipilẹṣẹ HDL kika, mejeeji Verilog ati VHDL aṣayan wa.
9. Tẹ ina Eksample Design. Awọn Yan Example Design Directory window han.
10. Ti o ba fẹ yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (ilk_f_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example liana orukọ.
11. Tẹ O DARA.
Akiyesi: Ninu F-Tile Interlaken Intel FPGA IP apẹrẹample, a SystemPLL ti wa ni instantiated laifọwọyi, ati ki o ti sopọ si F-Tile Interlaken Intel FPGA IP mojuto. Ọna ilana ilana SystemPLL ni apẹrẹ example ni:
example_design.test_env_inst.test_dut.dut.pll
SystemPLL ninu apẹrẹ example pin kanna aago itọkasi 156.26 MHz bi Transceiver.
Ilana Ilana
F-Tile Interlaken Intel FPGA IP mojuto ṣe ipilẹṣẹ atẹle naa files fun apẹrẹ example:
olusin 5. Directory Be
Tabili 2. Hardware Design Example File Awọn apejuwe
Awọn wọnyi files wa ninuample_installation_dir>/ilk_f_0_example_design liana.
| File Awọn orukọ | Apejuwe |
| example_design.qpf | Intel Quartus NOMBA ise agbese file. |
| example_design.qsf | Intel Quartus NOMBA eto ise agbese file |
| example_design.sdc jtag_timing_template.sdc | Synopsys Design Idiwọn file. O le daakọ ati yipada fun apẹrẹ tirẹ. |
| sysconsole_testbench.tcl | Akọkọ file fun wiwọle System Console |
Akiyesi: Hardware support fun oniru example yoo wa ninu ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.4.
Table 3. Testbench File Apejuwe
Eyi file jẹ ninu awọnample_installation_dir>/ilk_f_0_example_design/ example_design / rtl liana.
| File Oruko | Apejuwe |
| oke_tb.sv | Igbeyewo ipele oke file. |
Table 4. Testbench awọn iwe afọwọkọ
Awọn wọnyi files wa ninuample_installation_dir>/ilk_f_0_example_design/ example_design / testbench liana
| File Oruko | Apejuwe |
| run_vcs.sh | Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench. |
| run_vcsmx.sh | Awọn Synopsys VCS MX iwe afọwọkọ lati ṣiṣe awọn testbench. |
| run_mentor.tcl | Siemens EDA ModelSim SE tabi iwe afọwọkọ Questa lati ṣiṣe testbench naa. |
Simulating awọn Oniru Example Testbench
olusin 6. Ilana
Tẹle awọn igbesẹ wọnyi lati ṣe adaṣe testbench:
- Ni aṣẹ aṣẹ, yipada si iwe ilana kikopa testbench. Ona liana niample_installation_dir>/ example_design / testbench.
- Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo. Iwe afọwọkọ rẹ yẹ ki o ṣayẹwo pe SOP ati awọn iṣiro EOP baramu lẹhin ti kikopa ti pari.
Table 5. Igbesẹ lati Ṣiṣe Simulation
| Simulator | Awọn ilana |
|
VCS |
Ninu laini aṣẹ, tẹ:
sh run_vcs.sh |
|
VCS MX |
Ninu laini aṣẹ, tẹ:
sh run_vcsmx.sh |
|
ModelSim SE tabi Questa |
Ninu laini aṣẹ, tẹ:
vsim -ṣe run_mentor.tcl Ti o ba fẹ lati ṣe adaṣe lai mu ModelSim GUI soke, tẹ:
vsim -c -ṣe run_mentor.tcl |
3. Ṣe itupalẹ awọn abajade. Simulation aṣeyọri kan firanṣẹ ati gba awọn apo-iwe, ati ṣafihan “Idanwo ti kọja”.
Awọn testbench fun apẹrẹ example pari awọn iṣẹ wọnyi:
- Instantiates awọn F-Tile Interlaken Intel FPGA IP mojuto.
- Tẹjade ipo PHY.
- Ṣe ayẹwo amuṣiṣẹpọ metaframe (SYNC_LOCK) ati ọrọ (idinaki) awọn aala (WORD_LOCK).
- Nduro fun awọn ọna onikaluku lati wa ni titiipa ati titọ.
- Bẹrẹ gbigbe awọn apo-iwe.
- Ṣiṣayẹwo awọn iṣiro apo-iwe:
- CRC24 aṣiṣe
- SOPs
- Awọn EOPs
Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri kan:
Iṣakojọpọ Oniru Example
- Rii daju example oniru iran jẹ pari.
- Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣii iṣẹ akanṣe Intel Quartus Primeample_installation_dir>/ example_design.qpf>.
- Lori awọn Processing akojọ, tẹ Bẹrẹ akopo.
Apẹrẹ Example Apejuwe
Apẹrẹ example ṣe afihan awọn iṣẹ ṣiṣe ti Interlaken IP mojuto.
Apẹrẹ Example irinše
Awọn example oniru so eto ati PLL itọkasi asaju ati awọn ti a beere oniru irinše. Awọn example oniru configures IP mojuto ni ti abẹnu loopback mode ati ki o gbogbo awọn apo-iwe lori IP mojuto TX olumulo data ni wiwo. IP mojuto rán awọn wọnyi awọn apo-iwe lori awọn ti abẹnu loopback ona nipasẹ awọn transceiver.
Lẹhin ti olugba IP mojuto gba awọn apo-iwe lori ọna loopback, o ṣe ilana awọn apo-iwe Interlaken ati gbejade wọn lori wiwo gbigbe data olumulo RX. Awọn example oniru sọwedowo wipe awọn apo-iwe gba ati ki o zqwq baramu.
F-Tile Interlaken Intel IP apẹrẹ example pẹlu awọn eroja wọnyi:
- F-Tile Interlaken Intel FPGA IP mojuto
- Packet monomono ati Packet Checker
- F-Tile Reference ati System PLL Agogo Intel FPGA IP mojuto
Awọn ifihan agbara wiwo
Table 6. Design Example Interface Awọn ifihan agbara
| Orukọ Port | Itọsọna | Ìbú (Bits) | Apejuwe |
|
mgmt_clk |
Iṣawọle |
1 |
titẹ sii aago eto. Igbohunsafẹfẹ aago gbọdọ jẹ 100 MHz. |
|
pll_ref_clk |
Iṣawọle |
1 |
Aago itọkasi Transceiver. Wakọ RX CDR PLL. |
| rx_pin | Iṣawọle | Nọmba awọn ọna | PIN olugba SErdES data. |
| tx_pin | Abajade | Nọmba awọn ọna | Ṣe atagba PIN data SErdES. |
| rx_pin_n1) | Iṣawọle | Nọmba awọn ọna | PIN olugba SErdES data. |
| tx_pin_n(1) | Abajade | Nọmba awọn ọna | Ṣe atagba PIN data SErdES. |
|
mac_clk_pll_ref |
Iṣawọle |
1 |
Yi ifihan agbara gbọdọ wa ni ìṣó nipasẹ a PLL ati ki o gbọdọ lo kanna aago orisun ti o iwakọ pll_ref_clk.
Ifihan agbara yi wa nikan ni awọn iyatọ ẹrọ ipo PAM4. |
| usr_pb_reset_n | Iṣawọle | 1 | Eto titunto. |
(1) Nikan wa ni awọn iyatọ PAM4.
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
Forukọsilẹ Map
Akiyesi:
- Apẹrẹ ExampAdirẹsi iforukọsilẹ le bẹrẹ pẹlu 0x20 *** lakoko ti adirẹsi iforukọsilẹ IP mojuto Interlaken bẹrẹ pẹlu 0x10 ***.
- Adirẹsi iforukọsilẹ F-tile PHY bẹrẹ pẹlu 0x30** lakoko ti adirẹsi iforukọsilẹ F-tile FEC bẹrẹ pẹlu 0x40**. Iforukọsilẹ FEC wa ni ipo PAM4 nikan.
- Koodu wiwọle: RO-Ka Nikan, ati RW-Ka/Kọ.
- System console Say oniru Mofiample forukọsilẹ ati awọn ijabọ ipo idanwo loju iboju.
Table 7. Design Example Forukọsilẹ Map
| Aiṣedeede | Oruko | Wiwọle | Apejuwe |
| 8'h00 | Ni ipamọ | ||
| 8'h01 | Ni ipamọ | ||
|
8'h02 |
Eto PLL atunto |
RO |
Awọn die-die atẹle tọkasi ibeere atunto PLL eto ati mu iye ṣiṣẹ:
• Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en |
| 8'h03 | Ona RX ni ibamu | RO | Tọkasi titete ọna RX. |
|
8'h04 |
ORO titii pa |
RO |
[NUM_LANES–1:0] – Ọrọ (ìdènà) idamọ awọn aala. |
| 8'h05 | Amuṣiṣẹpọ ni titiipa | RO | [NUM_LANES–1:0] – Amuṣiṣẹpọ Metaframe. |
| 8'h06 - 8'h09 | CRC32 aṣiṣe kika | RO | Tọkasi kika aṣiṣe CRC32. |
| 8'h0A | CRC24 aṣiṣe kika | RO | Tọkasi kika aṣiṣe CRC24. |
|
8'h0B |
Aponsedanu / Underflow ifihan agbara |
RO |
Awọn ipin wọnyi tọkasi:
• Bit [3] – TX ifihan agbara labẹ sisan • Bit [2] - TX aponsedanu ifihan agbara • Bit [1] - RX aponsedanu ifihan agbara |
| 8'h0C | Iwọn SOP | RO | Tọkasi awọn nọmba ti SOP. |
| 8'h0D | Iwọn EOP | RO | Tọkasi nọmba ti EOP |
|
8'h0E |
Iṣiro aṣiṣe |
RO |
Tọkasi nọmba awọn aṣiṣe wọnyi:
• Isonu ti titete ona Ọrọ iṣakoso arufin • Apẹrẹ fireemu fireemu Sonu SOP tabi EOP Atọka |
| 8'h0F | firanṣẹ_data_mm_clk | RW | Kọ 1 si bit [0] lati mu ifihan agbara monomono ṣiṣẹ. |
|
8'h10 |
Aṣiṣe oluyẹwo |
Tọkasi aṣiṣe oluyẹwo. (Aṣiṣe data SOP, aṣiṣe nọmba ikanni, ati aṣiṣe data PLD) | |
| 8'h11 | Titiipa PLL eto | RO | Bit [0] tọkasi itọkasi titiipa PLL. |
|
8'h14 |
Iye owo ti TX SOP |
RO |
Tọkasi nọmba ti SOP ti ipilẹṣẹ nipasẹ monomono soso. |
|
8'h15 |
Iye owo ti TX EOP |
RO |
Tọkasi nọmba ti EOP ti ipilẹṣẹ nipasẹ monomono soso. |
| 8'h16 | Pakẹti ti o tẹsiwaju | RW | Kọ 1 si bit [0] lati jeki awọn soso lemọlemọfún. |
| tesiwaju… | |||
| Aiṣedeede | Oruko | Wiwọle | Apejuwe |
| 8'h39 | ECC aṣiṣe kika | RO | Tọkasi nọmba ti awọn aṣiṣe ECC. |
| 8'h40 | ECC ṣatunṣe kika aṣiṣe | RO | Tọkasi nọmba ti atunse ECC aṣiṣe. |
| 8'h50 | tile_tx_rst_n | WO | Tile tunto si SRC fun TX. |
| 8'h51 | tile_rx_rst_n | WO | Tile tunto si SRC fun RX. |
| 8'h52 | tile_tx_rst_ack_n | RO | Tile atunkọ jẹwọ lati SRC fun TX. |
| 8'h53 | tile_rx_rst_ack_n | RO | Tile atunkọ jẹwọ lati SRC fun RX. |
Tunto
Ninu F-Tile Interlaken Intel FPGA IP mojuto, o bẹrẹ atunto (reset_n=0) ki o dimu titi ti ipilẹ IP yoo fi pada jẹwọ atunto (reset_ack_n=0). Lẹhin ti atunto ti yọkuro (reset_n=1), jẹwọ atunto yoo pada si ipo ibẹrẹ rẹ
(reset_ack_n=1). Ninu apẹrẹ example, iforukọsilẹ rst_ack_sticky kan ni idaniloju idaniloju atunto ati lẹhinna nfa yiyọkuro ti atunto (reset_n=1). O le lo awọn ọna miiran ti o baamu awọn iwulo apẹrẹ rẹ.
Pataki: Ni eyikeyi ohn ibi ti awọn ti abẹnu ni tẹlentẹle loopback wa ni ti beere, o gbọdọ tu TX ati RX ti F-tile lọtọ ni kan pato ibere. Tọkasi iwe afọwọkọ console eto fun alaye diẹ sii.
Ṣe nọmba 7.Tunto Ọkọọkan ni Ipo NRZ
Ṣe nọmba 8.Tunto Ọkọọkan ni Ipo PAM4
F-Tile Interlaken Intel FPGA IP Design Eksample User Itọsọna Archives
Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.
| Intel Quartus NOMBA Version | IP Core Version | Itọsọna olumulo |
| 21.2 | 2.0.0 | F-Tile Interlaken Intel FPGA IP Design Eksample User Itọsọna |
Itan Atunyẹwo iwe fun F-Tile Interlaken Intel FPGA IP Design Example User Itọsọna
| Ẹya Iwe aṣẹ | Intel Quartus NOMBA Version | Ẹya IP | Awọn iyipada |
| 2021.10.04 | 21.3 | 3.0.0 | Atilẹyin ti a ṣafikun fun awọn akojọpọ oṣuwọn ọna ọna tuntun. Fun alaye diẹ ẹ sii, tọka si Tabili: Awọn akojọpọ atilẹyin IP ti Nọmba Awọn ọna ati Oṣuwọn Data.
Ṣe imudojuiwọn atokọ simulator atilẹyin ni apakan: Hardware ati Software Awọn ibeere. Fikun awọn iforukọsilẹ titun atunto ni apakan: Forukọsilẹ Map. |
| 2021.06.21 | 21.2 | 2.0.0 | Itusilẹ akọkọ. |
Awọn iwe aṣẹ / Awọn orisun
 |
intel F-Tile Interlaken Intel FPGA IP Design Eksample [pdf] Itọsọna olumulo F-Tile Interlaken Intel FPGA IP Design Eksample, F-Tile, Interlaken Intel FPGA IP Design Eksample, Intel FPGA IP Design Eksample, IP Design Example, Apẹrẹ Example |
