Microsemi IGLOO2 HPMS DDR Pule Fa'atonu
Folasaga
O le IGLOO2 HPMS o loʻo i ai se faʻapipiʻi DDR controller (HPMS DDR). O lenei fa'atonu DDR ua fa'amoemoe e fa'atonutonu se fa'amanatu DDR i fafo. O le HPMS DDR controller e mafai ona maua mai le HPMS (fa'aoga HPDMA) fa'apea fo'i ma le ie FPGA.
A e fa'aogaina le Faufale Fa'atonu e fau ai se poloka faiga e aofia ai le HPMS DDR, e fa'atulaga e le Faufale Fa'atonu le fa'atonu HPMS DDR mo oe e fa'atatau i au fa'amatalaga ma au filifiliga.
Leai se seti HPMS DDR eseese e le tagata faʻaoga e manaʻomia. Mo fa'amatalaga, fa'amolemole va'ai ile IGLOO2 System Builder User's Guide.
Fausia Faiga
Fausia Faiga
I totonu o le Faufale e faʻapipiʻi otometi le HPMS DDR.
- I le fa'ailoga o Mea Fa'atonu a le Faufale Fa'atonu, siaki le HPMS External DDR Memory (HPMS DDR).
- I le Memories tab, filifili le DDR Memory Type:
- DDR2
- DDR3
- LPDDR
- Filifili le Lautele o le DDR Memory: 8, 16 poʻo le 32
- Siaki le ECC pe a e mana'o e iai le ECC mo le DDR.
- Ulufale i le taimi seti manatua DDR. O le taimi lea e manaʻomia e le DDR memory e amata ai.
- Kiliki Import Register Configuration e fa'aulu mai ai le Resitala fa'atatau mo le FDDR mai se tusitusiga o lo'o iai file o lo'o iai fa'atauga resitala. Va'ai le Laulau 1 mo le fa'atulagaina o le resitala file syntax.
E otometi lava ona teuina e Libero nei faʻamaumauga faʻatulagaina i le eNVM. I le toe setiina o le FPGA, o le a otometi lava ona kopiina lenei faʻamaumauga i le HPMS DDR.
Ata 1 • Fausia Faiga ma HPMS DDR
Laulau 1 • Resitala Fa'atonu File Syntax
- ddrc_dyn_soft_reset_CR 0x00 ;
- ddrc_dyn_refresh_1_CR 0x27DE ;
- ddrc_dyn_refresh_2_CR 0x30F ;
- ddrc_dyn_powerdown_CR 0x02 ;
- ddrc_dyn_debug_CR 0x00 ;
- ddrc_ecc_data_mask_CR 0x0000 ;
- ddrc_addr_map_col_1_CR 0x3333 ;
HPMS DDR Pule Fa'atonu
A e fa'aogaina le HPMS DDR Pule e fa'aoga ai se DDR Memory i fafo, e tatau ona fa'amataina le DDR Controller i le taimi e ta'avale ai. E faia lenei mea e ala i le tusiaina o faʻamaumauga o faʻamaumauga i faʻamaumauga tuʻufaʻatasia o le DDR controller. I IGLOO2, o lo'o teuina e le eNVM fa'amaumauga o fa'amaumauga a le resitara ma a mae'a le toe setiina o le FPGA, o le fa'amaumauga o fa'amaumauga e kopiina mai le eNVM i tusi resitala tu'ufa'atasi a le HPMS DDR mo le amataga.
HPMS DDR Pule Resitala
O le HPMS DDR Controller o loʻo i ai se seti o tusi resitala e manaʻomia ona faʻatulagaina i le taimi e taʻavale ai. O tulaga fa'atulagaina mo nei tusi resitala o lo'o fa'atusalia ai ta'iala eseese, pei ole DDR mode, PHY lautele, burst mode, ma ECC. Mo fa'amatalaga atoatoa e uiga i le DDR controller configurations resitara fa'amolemole tagai ile Microsemi IGLOO2 User's Guide
HPMS MDDR Resitala Fa'atonuga
Ina ia faʻamaonia le tau o le Resitala DDR:
- Fa'aoga se fa'atonu tusitusiga i fafo atu o Libero SoC, saunia se tusitusiga file o lo'o i ai igoa Resitala ma tau, pei o le Ata 1-1.
- Mai le System Builder's Memory tab, kiliki le Fa'auluina o le Resitala Fa'atonu.
- Fa'asaga i le nofoaga o lo'o iai le tusitusiga Fa'amaufa'ailoga file ua e saunia i le Laasaga 1 ma filifili le file e faaulufale mai.
Ata 1-1 • Resitala Fa'amatalaga Fa'atonu - Fa'asologa o Tusitusiga
HPMS DDR Initialization
O fa'amaumauga Fa'amaufa'ailoga Tusi Resitala o lo'o e fa'aulufale mai mo le HPMS DDR o lo'o fa'apipi'iina i totonu o le eNVM ma kopiina i le HPMS DDR fa'atulagaina resitala pe a toe setiina le FPGA. Leai se fa'aoga fa'aoga e mana'omia e amatalia ai le HPMS DDR i le taimi fa'atino. O lenei fa'amatagofieina otometi e fa'ata'ita'iina fo'i ile fa'ata'ita'iga.
Fa'amatalaga Taulaga
DDR PHY Interface
O nei uafu o lo'o fa'aalia ile pito i luga ole poloka faufale faufale. Mo fa'amatalaga, fa'afeso'ota'i le IGLOO2 System Builder User Guide. Faʻafesoʻotaʻi nei ports i lau DDR memory.
Laulau 2-1 • DDR PHY Feso'ota'iga
| Igoa o le Taulaga | Fa'atonuga | Fa'amatalaga |
| MDDR_CAS_N | IFO | DRAM CASN |
| MDDR_CKE | IFO | DRAM CKE |
| MDDR_CLK | IFO | Uati, itu P |
| MDDR_CLK_N | IFO | Uati, itu N |
| MDDR_CS_N | IFO | DRAM CSN |
| MDDR_ODT | IFO | DRAM ODT |
| MDDR_RAS_N | IFO | DRAM RASN |
| MDDR_RESET_N | IFO | Toe seti DRAM mo DDR3 |
| MDDR_WE_N | IFO | DRAM WEN |
| MDDR_ADDR[15:0] | IFO | Dram Address bits |
| MDDR_BA[2:0] | IFO | tuatusi Dram Bank |
| MDDR_DM_RDQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Mask |
| MDDR_DQS ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input / Output - Itu P |
| MDDR_DQS_N ([3:0]/[1:0]/[0]) | INOUT | Dram Data Strobe Input/Autput – N Itu |
| MDDR_DQ ([31:0]/[15:0]/[7:0]) | INOUT | DRAM Fa'amatalaga Fa'amatalaga/Auga |
| MDDR_DQS_TMATCH_0_IN | IN | FIFO i le faailo |
| MDDR_DQS_TMATCH_0_OUT | IFO | FIFO out signal |
| MDDR_DQS_TMATCH_1_IN | IN | FIFO i le faailo (32-bit na'o) |
| MDDR_DQS_TMATCH_1_OUT | IFO | FIFO out signal (na'o le 32-bit) |
| MDDR_DM_RDQS_ECC | INOUT | Dram ECC Fa'amatalaga Mask |
| MDDR_DQS_ECC | INOUT | Dram ECC Fa'amatalaga Strobe Input/Autput – P Itu |
| MDDR_DQS_ECC_N | INOUT | Dram ECC Fa'amatalaga Strobe Input/Autput – N Itu |
| MDDR_DQ_ECC ([3:0]/[1:0]/[0]) | INOUT | DRAM ECC Faʻamatalaga Faʻamatalaga / Faʻamatalaga |
| MDDR_DQS_TMATCH_ECC_IN | IN | ECC FIFO i le faailo |
| MDDR_DQS_TMATCH_ECC_OUT | IFO | ECC FIFO i fafo faailoilo (32-bit na'o) |
Ole lautele ole uafu mo nisi uafu e suia e fuafua ile filifiliga ole lautele ole PHY. O le fa'ailoga “[a:0]/[b:0]/[c:0]” o lo'o fa'aaogaina e fa'ailoa ai ia ports, lea o le "[a:0]" e fa'asino i le lautele o le uafu pe a filifilia se 32-bit PHY lautele. , “[b:0]” e tutusa ma le 16-bit PHY lautele, ma “[c:0]” e fetaui ma le 8-bit PHY lautele.
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