Interlaken (2nd Generation) Intel®
Agilex™ FPGA IP Design Example
Wogwiritsa Ntchito

Quick Start Guide

Interlaken (2nd Generation) FPGA IP pachimake imapereka testbench yoyeserera komanso kapangidwe kazinthu kakale.ample yomwe imathandizira kusonkhanitsa ndi kuyesa kwa hardware. Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware. Mapangidwe example ikupezekanso pa mawonekedwe a Interlaken Look-aside.
Testbench ndi kapangidwe example imathandizira mawonekedwe a NRZ ndi PAM4 pazida za E-tile. Interlaken (2nd Generation) FPGA IP core imapanga zojambula zakaleamples pazophatikizika zonse zothandizidwa za kuchuluka kwa mayendedwe ndi mitengo ya data.

Chithunzi 1. Njira Zachitukuko za Design Example

Interlaken (2nd Generation) IP core design example imathandizira zotsatirazi:

• Internal TX to RX serial loopback mode
• Amapanga mapaketi okhazikika
• Mayeso owerengera paketi
• Kutha kugwiritsa ntchito System Console kukhazikitsanso mapangidwe kuti ayesenso
• Kusintha kwa mtengo wa PMA

Chithunzi 2. Chojambula cha Block chapamwamba cha Interlaken (2nd Generation) Design Example

Zambiri Zogwirizana

• Interlaken (2nd Generation) FPGA IP User Guide
• Interlaken (2nd Generation) Intel FPGA IP Release Notes

1.1. Zofunikira pa Hardware ndi Mapulogalamu
Kuyesa example design, gwiritsani ntchito zida ndi mapulogalamu awa:

• Pulogalamu ya Intel® Prime Pro Edition 21.3
• System Console
• Ma simulators othandizira:
  — Siemens* EDA ModelSim* SE kapena QuestaSim*
  - Synopsy* VCS*
  - Cadence * Xcelium *
• Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

Zambiri Zogwirizana
Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
1.2. Kapangidwe ka Kalozera
Interlaken (2nd Generation) IP core design example file akalozera ali ndi zotsatirazi zopangidwa files kwa kapangidwe example.
Chithunzi 3. Kapangidwe ka Kalozera wa Generated Interlaken (2nd Generation) Exampndi Design

Kusintha kwa hardware, kuyerekezera, ndi kuyesa files zili muample_installation_dir>/uflex_ilk_0_example_design.
Table 1. Interlaken (2nd Generation) IP Core Hardware Design Example File Kufotokozera
Izi files muample_installation_dir>/uflex_ilk_0_example_design/ example_design/quartus directory.

File Mayina	Kufotokozera
example_design.qpf	Intel Quartus Prime Project file.
example_design.qsf	Zokonda pa Intel Quartus Prime project file
example_design.sdc jtag_timing_template.sdc	Synopsys Design Constraint file. Mutha kukopera ndikusintha pamapangidwe anu.
sysconsole_testbench.tcl	Chachikulu file kuti mupeze System Console

Table 2. Interlaken (2nd Generation) IP Core Testbench File Kufotokozera
Izi file ndi muample_installation_dir>/uflex_ilk_0_example_design/ example_design/rtl chikwatu.

File Dzina	Kufotokozera
pamwamba_tb.sv	Testbench yapamwamba kwambiri file.

Table 3. nterlaken (2nd Generation) IP Core Testbench Scripts
Izi files muample_installation_dir>/uflex_ilk_0_example_design/ example_design/testbench directory.

File Dzina	Kufotokozera
vcstest.sh	Zolemba za VCS zoyendetsa testbench.
vlog_pro.do	The ModelSim SE kapena QuestaSim script kuyendetsa testbench.
xcelium.sh	Zolemba za Xcelium kuti mugwiritse ntchito testbench.

1.3. Mapangidwe a Hardware Exampndi Components
Example design imagwirizanitsa mawotchi amtundu wa PLL ndi mawotchi ofunikira. Example design imakonza IP core mumayendedwe a loopback yamkati ndikupanga mapaketi pa IP core TX yosinthira data ya ogwiritsa ntchito. IP core imatumiza mapaketi awa panjira yamkati ya loopback kudzera pa transceiver.
Pambuyo pa IP core receiver ilandila mapaketi panjira ya loopback, imayang'anira mapaketi a Interlaken ndikuwatumiza pa mawonekedwe osinthira a RX. Example design imayang'ana kuti mapaketiwo adalandiridwa ndikufalitsidwa.
Hardware exampkapangidwe kake kumaphatikizapo ma PLL akunja. Mukhoza kufufuza malemba omveka bwino files kuti view sample code yomwe imagwiritsa ntchito njira imodzi yolumikizira ma PLL akunja ku Interlaken (2nd Generation) FPGA IP.
Interlaken (2nd Generation) kapangidwe ka hardware example ili ndi zigawo zotsatirazi:

1. Interlaken (2nd Generation) FPGA IP
2. Packet Generator ndi Packet Checker
3. JTAG wolamulira yemwe amalumikizana ndi System Console. Mumalumikizana ndi malingaliro a kasitomala kudzera mu System Console.

Chithunzi 4. Interlaken (2nd Generation) Hardware Design Example High Level Block Chojambula cha E-tile NRZ Mode Kusiyana

Interlaken (2nd Generation) kapangidwe ka hardware exampLe yomwe imayang'ana mitundu ya E-tile PAM4 imafunikira wotchi yowonjezera mac_clkin yomwe IO PLL imapanga. PLL iyi iyenera kugwiritsa ntchito wotchi yomweyi yomwe imayendetsa pll_ref_clk.

Chithunzi 5. Interlaken (2nd Generation) Hardware Design Exampndi High Level
Chojambula cha Block cha E-tile PAM4 Mode Kusiyana

Pamitundu yosiyanasiyana ya E-tile PAM4, mukamatsegula Sungani ma transceiver osagwiritsidwa ntchito a PAM4 parameter, doko lowonjezera la wotchi limawonjezedwa (pll_ref_clk [1]). Dokoli liyenera kuyendetsedwa pafupipafupi monga momwe zafotokozedwera mu IP parameter editor (Reference clock frequency for reserved channels). Sungani ma transceiver osagwiritsidwa ntchito a PAM4 ndi osankha. Pini ndi zopinga zina zomwe zaperekedwa ku wotchiyi zimawoneka mu QSF mukasankha Intel Stratix® 10 kapena Intel Agilex zida zopangira mapangidwe.
Za kapangidwe exampndi kuyerekezera, testbench nthawi zonse imatanthauzira pafupipafupi pll_ref_clk[0] ndi pll_ref_clk[1].
Zambiri Zogwirizana
Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
1.4. Kupanga Mapangidwe

Chithunzi 6. Ndondomeko

Tsatirani izi kuti mupange hardware example design ndi testbench:

1. Mu pulogalamu ya Intel Quartus Prime Pro Edition, dinani File ➤ New Project Wizard kuti mupange pulojekiti yatsopano ya Intel Quartus Prime, kapena dinani File ➤ Open Project kuti mutsegule pulojekiti yomwe ilipo ya Intel Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo.
2. Tchulani chipangizo cha banja la Agilex ndikusankha chipangizo chomwe mungapangire.
3. Mu IP Catalog, pezani ndikudina kawiri Interlaken (2nd Generation) Intel FPGA IP. Zenera la New IP Variant likuwonekera.
4. Tchulani dzina lapamwamba pakusintha kwanu kwa IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
5. Dinani Chabwino. The parameter editor ikuwonekera.
   Chithunzi 7. Example Design Tab mu Interlaken (2nd Generation) Intel FPGA IP Parameter Editor
6. Pa tabu ya IP, tchulani magawo akusintha kwanu kwa IP.
7. Pa PMA Adaptation tabu, tchulani magawo osinthira a PMA ngati mukufuna kugwiritsa ntchito kusintha kwa PMA pazosintha zanu za E-tile.
   Sitepe iyi ndi yosankha:
   • Sankhani Yambitsani kusintha kwa IP njira yofewa.
   Zindikirani: Muyenera kuyatsa njira ya Yambitsani Native PHY Debug Master Endpoint (NPDME) pa IP tabu pamene kusintha kwa PMA kwayatsidwa.
   • Sankhani PMA adaptation preset kwa PMA adaptation Sankhani parameter.
   • Dinani PMA Adaptation Preload kuti mutsegule zoyambira komanso zopitiliza zosinthira.
   • Tchulani chiwerengero cha masinthidwe a PMA kuti athandizire pamene masinthidwe angapo a PMA atsegulidwa pogwiritsa ntchito Nambala ya PMA configuration parameter.
   • Sankhani kasinthidwe ka PMA kotani kuti mutsegule kapena kusunga pogwiritsa ntchito Sankhani makonzedwe a PMA kuti mulowetse kapena kusunga.
   • Dinani Lowani kusintha kuchokera ku kasinthidwe kosankhidwa kwa PMA kuti mukweze zokonda zosankhidwa za PMA.
   Kuti mudziwe zambiri za PMA adaptation parameters, onani E-tile Transceiver PHY User Guide.
8. Pa Eksample Design tabu, sankhani njira ya Simulation kuti mupange testbench, ndikusankha njira ya Synthesis kuti mupange ma hardware ex.ampkupanga.
   Zindikirani: Muyenera kusankha chimodzi mwa Zoyeserera kapena kaphatikizidwe zomwe zimapanga Exampndi Design Files.
9. Kwa Mtundu Wopangidwa wa HDL, Verilog yokha ndiyomwe ikupezeka.
10. Kwa Target Development Kit sankhani njira yoyenera.
    Zindikirani: Njira ya Intel Agilex F-Series Transceiver SoC Development Kit imapezeka pokhapokha polojekiti yanu itchula dzina la chipangizo cha Intel Agilex kuyambira AGFA012 kapena AGFA014. Mukasankha njira ya Development Kit, ntchito za pini zimayikidwa molingana ndi gawo la chipangizo cha Intel Agilex Development Kit AGFB014R24A2E2V ndipo zingasiyane ndi chipangizo chomwe mwasankha. Ngati mukufuna kuyesa mapangidwe a hardware pa PCB ina, sankhani Palibe njira yopangira chitukuko ndipo pangani ma pini oyenera mu .qsf file.
11. Dinani Pangani Exampndi Design. Sankhani Exampzenera la Design Directory likuwonekera.
12. Ngati mukufuna kusintha kapangidwe example chikwatu njira kapena dzina kuchokera zosasintha zomwe zikuwonetsedwa (uflex_ilk_0_example_design), sakatulani njira yatsopano ndikulemba mawonekedwe atsopanoample directory name.
13. Dinani Chabwino.

Zambiri Zogwirizana

• Intel Agilex F-Series Transceiver-SoC Development Kit User Guide
• E-tile Transceiver PHY User Guide

1.5. Kutsanzira Design Exampndi Testbench
Onani ku Interlaken (2nd Generation) Hardware Design Example High Level Block ya E-tile NRZ Mode Kusiyana ndi Interlaken (2nd Generation) Hardware Design Example High Level Block ya E-tile PAM4 Mode Variations block zojambula za testbench yoyeserera.

Chithunzi 8. Ndondomeko

Tsatirani izi kuti muyesere testbench:

1. Pakulamula, sinthani ku bukhu la testbench simulation. Chikwatu ndiample_installation_dir>/example_design/ testbench ya zida za Intel Agilex.
2. Yendetsani script yoyeserera ya simulator yothandizidwa yomwe mungasankhe. Zolembazo zimaphatikiza ndikuyendetsa testbench mu simulator. Zolemba zanu ziyenera kuyang'ana kuti SOP ndi EOP ziwerengero zofananira pambuyo pomaliza. Onani tebulo Masitepe Kuthamanga Kayeseleledwe.
   Table 4. Masitepe Kuthamanga Kayeseleledwe

   Woyeserera	Malangizo
   ModelSim SE kapena QuestaSim	Mu mzere wolamula, lembani -do vlog_pro.do. Ngati mukufuna kuyerekezera popanda kubweretsa ModelSim GUI, lembani vsim -c -do vlog_pro.do
   Zithunzi za VCS	Mu mzere wolamula, lembani sh vcstest.sh
   Xcelium	Mu mzere wolamula, lembani sh xcelium.sh

3. Unikani zotsatira. Kuyerekeza kopambana kumatumiza ndikulandila mapaketi, ndikuwonetsa "Test PASSED".

Testbench ya kapangidwe kakaleampamamaliza ntchito zotsatirazi:

• Imakhazikitsa Interlaken (2nd Generation) Intel FPGA IP.
• Imasindikiza mawonekedwe a PHY.
• Imafufuza malire a metaframe (SYNC_LOCK) ndi malire a mawu (block) (WORD_LOCK).
• Imadikirira kuti mayendedwe apawokha atsekedwe ndikuyanjanitsidwa.
• Amayamba kutumiza mapaketi.
• Imafufuza ziwerengero za paketi:
  - CRC24 zolakwika
  - SOP
  -EOPs

Zotsatirazi sample output ikuwonetsa kuyesa koyeserera koyeserera koyendetsedwa mu Interlaken mode:
**************************************
INFO: Kudikirira kuti mayendedwe agwirizane.
Misewu yonse yolandila ndi yolumikizidwa ndipo ndi okonzeka kulandira magalimoto.
********************************************
********************************************
INFO: Yambani kutumiza mapaketi
********************************************
********************************************
INFO: Lekani kutumizira mapaketi
********************************************
********************************************
INFO: Kuyang'ana ziwerengero zamapaketi
********************************************
Zolakwa za CRC 24 zidanenedwa: 0
SOPs kutumizidwa: 100
Ma EOPs otumizidwa: 100
SOPs adalandira: 100
EOPs adalandira: 100
Chiwerengero cha zolakwika za ECC: 0
********************************************
INFO: Mayeso APATSIDWA
********************************************
Zindikirani: Interlaken Design example simulation testbench imatumiza mapaketi 100 ndikulandila mapaketi 100.
Zotsatirazi sampzotulutsa zikuwonetsa kuyesa koyeserera koyeserera koyendetsedwa mu Interlaken Look-aside mode:
Onani TX ndi RX Counter zofanana kapena ayi.
————————————————————-
WERENGANI_MM: adilesi 4000014 = 00000001.
————————————————————-
De-assert Counter yofanana pang'ono.
————————————————————-
WRITE_MM: adilesi 4000001 imapeza 00000001.
WRITE_MM: adilesi 4000001 imapeza 00000000.
————————————————————-
RX_SOP COUNTER.
————————————————————-
READ_MM: adilesi 400000c = 0000006a.
————————————————————-
RX_EOP COUNTER.
READ_MM: adilesi 400000d = 0000006a.
————————————————————-
WERENGANI_MM: adilesi 4000010 = 00000000.
————————————————————-
Onetsani Lipoti Lomaliza.
————————————————————-
0 Cholakwika Chodziwika
0 zolakwa za CRC24 zanenedwa
106 SOPs yofalitsidwa
106 EOPs yofalitsidwa
106 SOPs adalandira
106 EOPs adalandira
————————————————————-
Malizani Kuyerekezera
————————————————————-
KUYESA KWAPATSA
————————————————————-
Zindikirani: Chiwerengero cha mapaketi (SOPs ndi EOPs) zimasiyanasiyana panjira mu Interlaken Lookaside design ex.ampndi kayeseleledwe sample output.
Zambiri Zogwirizana
Mapangidwe a Hardware Example Components patsamba 6
1.6. Kupanga ndi Kukonza Design Exampndi mu Hardware

Chithunzi 9. Ndondomeko

Kupanga ndikuyesa kuyesa kwachiwonetsero pa hardware example design, tsatirani izi:

1. Onetsetsani kuti hardware example design generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime Pro Edition, tsegulani pulojekiti ya Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Pa Processing menyu, dinani Start Compilation.
4. Pambuyo pophatikiza bwino, a .sof file likupezeka m'ndandanda yanu yomwe mwasankha.
   Tsatirani izi kuti mupange pulogalamu ya Hardware example design pa chipangizo cha Intel Agilex:
5. Lumikizani Intel Agilex F-Series Transceiver-SoC Development Kit ku kompyuta yanu.
   b. Yambitsani pulogalamu ya Clock Control, yomwe ili gawo la zida zachitukuko, ndikukhazikitsa ma frequency atsopano a kapangidwe kakale.ample. Pansipa pali ma frequency a Clock Control application:
   • Si5338 (U37), CLK1- 100 MHz
   • Si5338 (U36), CLK2- 153.6 MHz
   • Si549 (Y2), OUT- Khazikitsani mtengo wa pll_ref_clk (1) malinga ndi zomwe mukufuna kupanga.
   c. Pa Zida menyu, dinani Programmer.
   d. Mu Programmer, dinani Hardware Setup.
   e. Sankhani chipangizo chokonzera.
   f. Sankhani ndikuwonjezera Intel Agilex F-Series Transceiver-SoC Development Kit komwe gawo lanu la Intel Quartus Prime lingalumikizane.
   g. Onetsetsani kuti Mode yakhazikitsidwa ku JTAG.
   h. Sankhani chipangizo cha Intel Agilex ndikudina Add Chipangizo. The Programmer akuwonetsa chithunzi cholumikizira cha kulumikizana pakati pa zida pa bolodi lanu.
   ndi. Mu mzere ndi .sof yanu, fufuzani bokosi la .sof.
   j. Chongani bokosi mu gawo la Pulogalamu/Sinthani.
   k. Dinani Yambani.

Zambiri Zogwirizana

• Mapulogalamu a Intel FPGA Devices patsamba 0
• Kusanthula ndi Kuthetsa Mapangidwe ndi System Console
• Intel Agilex F-Series Transceiver-SoC Development Kit User Guide

1.7. Kuyesa Hardware Design Example
Mukapanga Interlaken (2nd Generation) Intel FPGA IP core design example ndikusintha chipangizo chanu, mutha kugwiritsa ntchito System Console kukonza IP core ndi zolembetsa zake za Native PHY IP.
Tsatirani izi kuti mubweretse System Console ndikuyesa kapangidwe ka hardware kaleampLe:

1. Mu pulogalamu ya Intel Quartus Prime Pro Edition, pazosankha Zida, dinani Zida Zowonongeka Zadongosolo ➤ System Console.
2. Kusintha kwaample_installation_dir>mwachitsanzoample_design/hwtest directory.
3. Kuti mutsegule kulumikizana ndi JTAG mbuye, lembani lamulo ili: source sysconsole_testbench.tcl
4. Mutha kuyatsa ma serial loopback mode ndi mapangidwe otsatirawaampndi malamulo:
   a. stat: Sindikizani zambiri zanthawi zonse.
   b. sys_reset: Kukhazikitsanso dongosolo.
   c. loop_on: Kuyatsa serial loopback yamkati.
   d. run_example_design: Imayendetsa kapangidwe kakaleample.
   Zindikirani: Muyenera kuyendetsa lamulo la loop_on musanayambe run_examplamulo la_design.
   The run_example_design imayendetsa malamulo awa motsatizana:
   sys_reset->stat->gen_on->stat->gen_off.
   Zindikirani: Mukasankha Yambitsani kusintha kwa IP njira yofewa, run_exampLamulo la le_design limapanga kusintha koyambira kumbali ya RX poyendetsa lamulo la run_load_PMA_configuration.
5. Mutha kuzimitsa mawonekedwe amkati amtundu wa loopback ndi mawonekedwe otsatirawaampndi command:
   a. loop_off: Izimitsa serial loopback yamkati.
6. Mutha kukonza IP pachimake ndi mawonekedwe owonjezera awaampndi malamulo:
   a. gen_on: Imathandizira jenereta ya paketi.
   b. gen_off: Imayimitsa jenereta ya paketi.
   c. run_test_loop: Imayesa mayeso a nthawi zamitundu ya E-tile NRZ ndi PAM4.
   d. clear_err: Imachotsa zolakwika zonse zomata.
   e. set_test_mode : Amakhazikitsa mayeso kuti ayendetse munjira inayake.
   f. get_test_mode: Sindikizani mayeso apano.
   g. set_burst_size : Imakhazikitsa kukula kwa mabayiti.
   h. get_burst_size: Zosindikiza za kukula kwake.

Mayeso opambana amasindikiza HW_TEST: uthenga waPASS. M'munsimu muli njira zopambana zoyeserera:

• Palibe zolakwika za CRC32, CRC24, ndi cheki.
• Ma SOP otumizidwa ndi EOP ayenera kugwirizana ndi kulandiridwa.

Zotsatirazi sample output ikuwonetsa kuyesa kopambana mu Interlaken mode:
INFO: INFO: Lekani kupanga mapaketi
==== STATUS REPORT ====
TX KHz: 402813
RX KHz 402813
Kutseka pafupipafupi: 0x0000ff
TX PLL loko: 0x000001
Gwirizanitsani: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
loko mawu: 0x0000ff
kulunzanitsa loko: 0x0000ff
Zolakwika za CRC32: 0
Zolakwika za CRC24: 0
Zolakwika za Checker: 0
Zizindikiro za zolakwika za FIFO: 0x000000
SOPs kutumizidwa: 1087913770
Ma EOPs otumizidwa: 1087913770
SOPs adalandira: 1087913770
EOPs adalandira: 1087913770
Kusintha kwa ECC: 0
ECC cholakwika: 0
Zadutsa mphindi 161 kuchokera pamagetsi
HW_TEST : PASS
Mayeso opambana amasindikiza HW_TEST : Uthenga wa PASS. M'munsimu muli njira zopambana zoyeserera:

• Palibe zolakwika za CRC32, CRC24, ndi cheki.
• Ma SOP otumizidwa ndi EOP ayenera kugwirizana ndi kulandiridwa.

Zotsatirazi sample output ikuwonetsa kuyesa kopambana mu Interlaken Lookaside mode:
INFO: INFO: Lekani kupanga mapaketi
==== STATUS REPORT ====
TX KHz: 402813
RX KHz 402812
Kutseka pafupipafupi: 0x000fff
TX PLL loko: 0x000001
Gwirizanitsani: 0x00c10f
Rx LOA: 0x000000
Tx LOA: 0x000000
loko mawu: 0x000fff
kulunzanitsa loko: 0x000fff
Zolakwika za CRC32: 0
Zolakwika za CRC24: 0
Zolakwika za Checker: 0
SOPs kutumizidwa: 461
Ma EOPs otumizidwa: 461
SOPs adalandira: 461
EOPs adalandira: 461
Zadutsa mphindi 171 kuchokera pamagetsi
HW_TEST : PASS

Design Example Kufotokozera

Mapangidwe example akuwonetsa magwiridwe antchito a Interlaken IP core.
Zambiri Zogwirizana
Interlaken (2nd Generation) FPGA IP User Guide
2.1. Kupanga Eksampndi Behaviour
Kuti muyese kapangidwe ka Hardware, lembani malamulo otsatirawa mu System Console:

1. Tsitsani khwekhwe file:
   % gweroample>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
2. Yendetsani mayeso:
   % run_example_design
3. Interlaken (2nd Generation) kapangidwe ka hardware example amamaliza izi:
   a. Kukhazikitsanso IP ya Interlaken (2nd Generation).
   b. Imakonza IP ya Interlaken (2nd Generation) mumayendedwe amkati a loopback.
   c. Imatumiza mapaketi angapo a Interlaken okhala ndi data yofotokozedweratu muzolipira ku mawonekedwe a TX osamutsa deta a IP core.
   d. Imayang'ana mapaketi omwe alandilidwa ndikuwonetsa momwe zilili. Choyang'anira paketi chophatikizidwa ndi kapangidwe ka hardware example imapereka mphamvu zowunikira paketi zotsatirazi:
   • Onani ngati ndondomeko ya paketi yopatsirana ndiyolondola.
   • Kuona ngati zomwe mwalandira zikufanana ndi zomwe zikuyembekezeredwa poonetsetsa kuti poyambira paketi (SOP) ndi mapeto a paketi (EOP) zikugwirizana pamene deta ikutumizidwa ndi kulandiridwa.

2.2. Zizindikiro za Interface
Table 5. Design Exampndi Interface Signals

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
mgmt_clk	Zolowetsa	1	Kulowetsa wotchi yadongosolo. Wotchi pafupipafupi iyenera kukhala 100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2)	Zolowetsa	2-Jan	Wotchi yowonetsera transceiver. Imayendetsa RX CDR PLL.

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
			pll_ref_clk[1] imapezeka pokhapokha mutatsegula Sungani zosagwiritsidwa ntchito Zindikirani: ma transceiver a PAM4 parameter mu E-tile PAM4 mode IP kusiyana.
rx_pin	Zolowetsa	Nambala yamayendedwe	Pini ya data yolandila SERDES.
tx_pin	Zotulutsa	Nambala yamayendedwe	Tumizani pini ya data ya SERDES.
rx_pin_n	Zolowetsa	Nambala yamayendedwe	Pini ya data yolandila SERDES. Chizindikirochi chimapezeka kokha mumitundu ya E-tile PAM4 mode.
tx_pin_n	Zotulutsa	Nambala yamayendedwe	Tumizani pini ya data ya SERDES. Chizindikirochi chimapezeka kokha mumitundu ya E-tile PAM4 mode.
mac_clk_pll_ref	Zolowetsa	1	Chizindikirochi chiyenera kuyendetsedwa ndi PLL ndipo chiyenera kugwiritsa ntchito wotchi yomweyi yomwe imayendetsa pll_ref_clk. Chizindikirochi chimapezeka kokha mumitundu ya E-tile PAM4 mode.
usr_pb_reset_n	Zolowetsa	1	Konzanso dongosolo.

Zambiri Zogwirizana
Zizindikiro za Interface
2.3. Lembani Mapu
Zindikirani:

• Design Example registry adilesi imayamba ndi 0x20** pomwe Interlaken IP core registry adilesi imayamba ndi 0x10 **.
• Khodi yofikira: RO—Werengani Pokha, ndi RW—Werengani/Lembani.
• System console imawerenga zojambula zakaleample amalembetsa ndi kupereka lipoti mayeso pa zenera.

Table 6. Design Example Register Mapu a Interlaken Design Example

Offset	Dzina	Kufikira	Kufotokozera
8h00 ku	Zosungidwa
8h01 ku	Zosungidwa
8h02 ku	Kusintha kwadongosolo kwa PLL	RO	Ma bits otsatirawa akuwonetsa pempho la dongosolo la PLL ndikuyambitsanso mtengo: • Pang'ono [0] - sys_pll_rst_req • Pang'ono [1] - sys_pll_rst_en
8h03 ku	Njira ya RX yolumikizidwa	RO	Imawonetsa njira ya RX.
8h04 ku	MAWU otsekedwa	RO	[NUM_LANES–1:0] – Chizindikiritso cha malire cha Mawu (chidacho).

(2) Mukatsegula Sungani ma transceiver osagwiritsidwa ntchito a PAM4 parameter, doko lowonjezera la wotchi limawonjezeredwa kuti musunge njira ya akapolo ya PAM4 yosagwiritsidwa ntchito.

Offset	Dzina	Kufikira	Kufotokozera
8h05 ku	Kulunzanitsa kwatsekedwa	RO	[NUM_LANES–1:0] - Kulunzanitsa kwa Metaframe.
8'h06 - 8'h09	Chiwerengero cha zolakwika za CRC32	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC32.
8h0a ku	Chiwerengero cha zolakwika za CRC24	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC24.
8h0b ku	Kusefukira/Kuyenda kwapansi	RO	Zizindikiro zotsatirazi zikuwonetsa: • Pang'ono [3] - chizindikiro cha TX pansi • Pang'ono [2] - chizindikiro cha kusefukira kwa TX • Pang'ono [1] - chizindikiro cha RX kusefukira
8h0c ku	Mtengo wa SOP	RO	Imawonetsa nambala ya SOP.
8h0d ku	Mtengo wa EOP	RO	Imawonetsa nambala ya EOP
8h0e	Chiwerengero cha zolakwika	RO	Ikuwonetsa kuchuluka kwa zolakwika zotsatirazi: • Kutayika kwa njira • Mawu oletsa malamulo • Mapangidwe osaloledwa • Chizindikiro cha SOP kapena EOP chikusoweka
8h0f ku	send_data_mm_clk	RW	Lembani 1 mpaka pang'ono [0] kuti mutsegule chizindikiro cha jenereta.
8h10 ku	Cholakwika cha Checker		Imawonetsa cholakwika cha cheki. (Zolakwika za data za SOP, cholakwika cha nambala ya Channel, ndi vuto la data la PLD)
8h11 ku	System PLL loko	RO	Bit [0] imasonyeza chizindikiro cha PLL.
8h14 ku	Mtengo wa TX SOP	RO	Imawonetsa nambala ya SOP yopangidwa ndi jenereta ya paketi.
8h15 ku	Mtengo wa TXEOP	RO	Ikuwonetsa nambala ya EOP yopangidwa ndi jenereta ya paketi.
8h16 ku	Paketi yosalekeza	RW	Lembani 1 mpaka pang'ono [0] kuti mutsegule paketi yopitilira.
8h39 ku	Chiwerengero cha zolakwika za ECC	RO	Imawonetsa kuchuluka kwa zolakwika za ECC.
8h40 ku	ECC yakonza zolakwika	RO	Ikuwonetsa kuchuluka kwa zolakwika za ECC zokonzedwa.

Table 7. Design Example Register Mapu a Interlaken Look-aside Design Example
Gwiritsani ntchito mapu olembetsawa mukapanga zojambula zakaleample ndi Yambitsani Interlaken Look-aside mode parameter yotsegulidwa.

Offset	Dzina	Kufikira	Kufotokozera
8h00 ku	Zosungidwa
8h01 ku	Counter reset	RO	Lembani 1 mpaka pang'ono [0] kuti muchotse TX ndi RX counter bit yofanana.
8h02 ku	Kusintha kwadongosolo kwa PLL	RO	Ma bits otsatirawa akuwonetsa pempho la dongosolo la PLL ndikuyambitsanso mtengo: • Pang'ono [0] - sys_pll_rst_req • Pang'ono [1] - sys_pll_rst_en
8h03 ku	Njira ya RX yolumikizidwa	RO	Imawonetsa njira ya RX.
8h04 ku	MAWU otsekedwa	RO	[NUM_LANES–1:0] – Chizindikiritso cha malire cha Mawu (chidacho).
8h05 ku	Kulunzanitsa kwatsekedwa	RO	[NUM_LANES–1:0] - Kulunzanitsa kwa Metaframe.
8'h06 - 8'h09	Chiwerengero cha zolakwika za CRC32	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC32.
8h0a ku	Chiwerengero cha zolakwika za CRC24	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC24.

Offset	Dzina	Kufikira	Kufotokozera
8h0b ku	Zosungidwa
8h0c ku	Mtengo wa SOP	RO	Imawonetsa nambala ya SOP.
8h0d ku	Mtengo wa EOP	RO	Imawonetsa nambala ya EOP
8h0e	Chiwerengero cha zolakwika	RO	Ikuwonetsa kuchuluka kwa zolakwika zotsatirazi: • Kutayika kwa njira • Mawu oletsa malamulo • Mapangidwe osaloledwa • Chizindikiro cha SOP kapena EOP chikusoweka
8h0f ku	send_data_mm_clk	RW	Lembani 1 mpaka pang'ono [0] kuti mutsegule chizindikiro cha jenereta.
8h10 ku	Cholakwika cha Checker	RO	Imawonetsa cholakwika cha cheki. (Zolakwika za data za SOP, cholakwika cha nambala ya Channel, ndi vuto la data la PLD)
8h11 ku	System PLL loko	RO	Bit [0] imasonyeza chizindikiro cha PLL.
8h13 ku	Chiwerengero cha latency	RO	Imawonetsa nambala ya latency.
8h14 ku	Mtengo wa TX SOP	RO	Imawonetsa nambala ya SOP yopangidwa ndi jenereta ya paketi.
8h15 ku	Mtengo wa TXEOP	RO	Ikuwonetsa nambala ya EOP yopangidwa ndi jenereta ya paketi.
8h16 ku	Paketi yosalekeza	RO	Lembani 1 mpaka pang'ono [0] kuti mutsegule paketi yopitilira.
8h17 ku	TX ndi RX counter ndi ofanana	RW	Zimasonyeza kuti TX ndi RX counter ndi ofanana.
8h23 ku	Yambitsani kuchedwa	WO	Lembani 1 mpaka pang'ono [0] kuti muthe kuyeza kwa latency.
8h24 ku	Kuchedwa kokonzeka	RO	Zimasonyeza kuti latency muyeso wakonzeka.

Interlaken (2nd Generation) Intel Agilex FPGA IP Design Exampndi User Guide Archives

Kwa mitundu yaposachedwa komanso yam'mbuyomu ya bukhuli, onani Interlaken (2nd Generation) Intel Agilex FPGA IP Design Exampndi User Guide Mtundu wa HTML. Sankhani Baibulo ndi kumadula Download. Ngati IP kapena pulogalamu ya pulogalamu sinalembedwe, chiwongolero cha ogwiritsa ntchito pa IP yam'mbuyomu kapena pulogalamu yamapulogalamu imagwira ntchito.
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.

Mbiri Yokonzanso Zolemba za Interlaken (2nd Generation) Intel Agilex FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2022.08.03	21.3	20.0.1	Anakonza chipangizo cha OPN cha Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Thandizo lowonjezera la QuestaSim simulator. • Kuchotsa kuthandizira kwa NCSim simulator.
2021.02.24	20.4	20.0.1	• Zowonjezera zokhudzana ndi kusunga tchanelo cha transceiver chosagwiritsidwa ntchito cha PAM4 mu gawo: Hardware Design Exampndi Components. • Anawonjeza mafotokozedwe a sigino ya pll_ref_clk[1] mu gawo: Ziwonetsero za Chiyankhulo.
2020.12.14	20.4	20.0.0	• Kusinthidwa sample Hardware test test for Interlaken mode ndi Interlaken Look-aside mode mu gawo Kuyesa Hardware Design Example. • Mapu olembetsa osinthidwa a Interlaken Look-aside design examplembani mgawo Register Mapu. • Anawonjezera njira yopambana yoyeserera bwino kwa hardware mu gawo Kuyesa Mapangidwe a Hardware Example.
2020.10.16	20.2	19.3.0	Lamulo lowongolera kuti muyambe kusinthira koyambira kumbali ya RX poyesa Hardware Design Exampgawo le.
2020.06.22	20.2	19.3.0	• Mapangidwe mwachitsanzoample ikupezeka pa Interlaken Look-side mode. • Kuyesa kwa Hardware kwa kapangidwe kakaleample imapezeka pamitundu yosiyanasiyana ya Intel Agilex. • Chithunzi Chowonjezera: Chojambula cha Block chapamwamba cha Interlaken (2nd Generation) Design Example. • Zasinthidwa zigawo zotsatirazi: - Zofunikira pa Hardware ndi Mapulogalamu - Kapangidwe kaakakwake • Adasintha ziwerengero zotsatirazi kuti ziphatikizepo zosintha zokhudzana ndi Interlaken Look-aside: - Chithunzi: Interlaken (2nd Generation) Hardware Design Exampndi High Chithunzi cha Block Block cha E- tile NRZ Mode Kusiyana - Chithunzi: Interlaken (2nd Generation) Hardware Design Example High Level Block Chojambula cha E- tile PAM4 Mode Kusiyana • Chithunzi Chosinthidwa: IP Parameter Editor. • Zina zowonjezera zokhudza masanjidwe afupipafupi mu pulogalamu yowongolera wotchi mu gawo Kupanga ndi Kukonza Design Exampndi mu Hardware.

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
			• Zowonjezera zoyeserera za Interlaken Look- pambali m'zigawo zotsatirazi: - Kutengera Design Exampndi Testbench - Kuyesa Mapangidwe a Hardware Example • Onjezani zizindikiro zatsopano zotsatirazi mu gawo la Interface Signals: -mgmt_clk -rx_pin_n -tx_pin_n - mac_clk_pll_ref • Anawonjezera mapu olembetsa a Interlaken Look-aside design example mu gawo: Register Mapu.
2019.09.30	19.3	19.2.1	Kuchotsa clk100. The mgmt_clk imakhala ngati wotchi yowunikira ku IO PLL motere: • Chithunzi: Interlaken (2nd Generation) Hardware Design Example High Level Block Chojambula cha E-tile NRZ Mode Kusiyana. • Chithunzi: Interlaken (2nd Generation) Hardware Design Example High Level Block Chojambula cha E-tile PAM4 Mode Kusiyana.
2019.07.01	19.2	19.2	Kutulutsidwa koyamba.

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Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Exampndi User Guide

Baibulo Lomasulira
Tumizani Ndemanga
ID: 683800
UG-20239
Mtundu: 2022.08.03

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