altera Nios V Ifibọ isise olumulo Itọsọna

About the Nios® V Embedded Processor
1.1. Altera® FPGA and Embedded Processors Overview
Altera FPGA devices can implement logic that functions as a complete microprocessor while providing many options.
Iyatọ pataki laarin awọn microprocessors ọtọtọ ati Altera FPGA ni pe aṣọ Altera FPGA ko ni imọran nigba ti o ni agbara. Nios® V ero isise jẹ ohun-ini imọ-jinlẹ rirọ (IP) ti o da lori sipesifikesonu RISC-V. Ṣaaju ki o to ṣiṣẹ sọfitiwia lori eto orisun ero isise Nios V, o gbọdọ tunto ẹrọ Altera FPGA pẹlu apẹrẹ ohun elo ti o ni ero isise Nios V kan. O le gbe ero isise Nios V nibikibi lori Altera FPGA, da lori awọn ibeere ti apẹrẹ naa.

To enable your Altera® FPGA IP-based embedded system to behave as a discrete microprocessor-based system, your system should include the following: · A JTAG interface to support Altera FPGA configuration, hardware and software
n ṣatunṣe aṣiṣe · Ilana iṣeto ni Altera FPGA agbara
Ti eto rẹ ba ni awọn agbara wọnyi, o le bẹrẹ isọdọtun apẹrẹ rẹ lati inu apẹrẹ ohun elo ti a ti yan tẹlẹ ti kojọpọ ni Altera FPGA. Lilo Altera FPGA tun ngbanilaaye lati yipada apẹrẹ rẹ ni kiakia lati koju awọn iṣoro tabi lati ṣafikun iṣẹ ṣiṣe tuntun. O le ṣe idanwo awọn apẹrẹ ohun elo tuntun wọnyi ni irọrun nipa atunto Altera FPGA ni lilo JTAG ni wiwo.
Awọn JTAG interface supports hardware and software development. You can perform the following tasks using the JTAG ni wiwo: · Tunto Altera FPGA · Ṣe igbasilẹ ati yokokoro sọfitiwia · Ibasọrọ pẹlu Altera FPGA nipasẹ wiwo UART kan (J)TAG UART
ebute) · Ohun elo yokokoro (pẹlu Oluyanju ọgbọn ti a fi sii ifihan agbara) · Iranti filasi eto
After you configure the Altera FPGA with a Nios V processor-based design, the software development flow is similar to the flow for discrete microcontroller designs.

Related Information · AN 985: Nios V Processor Tutorial
A quick start guide about creating a simple Nios V processor system and running the Hello World application.
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

1. About the Nios® V Embedded Processor 726952 | 2025.07.16
· Nios V Processor Reference Manual Provides information about the Nios V processor performance benchmarks, processor architecture, the programming model, and the core implementation.
Itọnisọna Olumulo IP Awọn agbeegbe ti a fi sinu · Nios V Processor Software Handbook

Describes the Nios V processor software development environment, the tools that are available, and the process to build software to run on Nios V processor. · Ashling* RiscFree* Integrated Development Environment (IDE) for Altera FPGAs User Guide Describes the RiscFree* integrated development environment (IDE) for Altera FPGAs Arm*-based HPS and Nios V core processor. · Nios V Processor Altera FPGA IP Release Notes
1.2. Quartus® Prime Software Support
Nios V processor build flow is different for Quartus® Prime Pro Edition software and Quartus Prime Standard Edition software. Refer to AN 980: Nios V Processor Quartus Prime Software Support for more information about the differences.
Related Information AN 980: Nios V Processor Quartus Prime Software Support
1.3. Nios V Processor Licensing
Iyatọ ero isise Nios V kọọkan ni bọtini iwe-aṣẹ rẹ. Ni kete ti o ba gba bọtini iwe-aṣẹ, o le lo bọtini iwe-aṣẹ kanna fun gbogbo awọn iṣẹ ero isise Nios V titi di ọjọ ipari. O le gba Nios V Processor Altera FPGA IP awọn iwe-aṣẹ ni idiyele odo.
The Nios V processor license key list is available in the Altera FPGA Self-Service Licensing Center. Click the Sign up for Evaluation or Free License tab, and select the corresponding options to make the request.
Figure 1. Altera FPGA Self-Service Licensing Center

Pẹlu awọn bọtini iwe-aṣẹ, o le:
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· Implement a Nios V processor within your system. · Simulate the behavior of a Nios V processor system. · Verify the functionality of the design, such as size and speed. · Generate device programming files. · Ṣe eto ẹrọ kan ati rii daju apẹrẹ ni ohun elo.
You do not need a license to develop software in the Ashling* RiscFree* IDE for Altera FPGAs.
Related Information · Altera FPGA Self-Service Licensing Center
For more information about obtaining the Nios V Processor Altera FPGA IP license keys. · Altera FPGA Software Installation and Licensing For more information about licensing the Altera FPGA software and setting up a fixed license and network license server.
1.4. Ifibọ System Design
Nọmba ti o tẹle n ṣapejuwe ṣiṣan ero ero isise Nios V ti o rọrun, pẹlu ohun elo mejeeji ati idagbasoke sọfitiwia.

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Olusin 2.

Nios V Processor System Design Flow
Eto Erongba

Analyze System Requirements

Nios® V
Processor Cores and Standard Components

Define and Generate System in
Platform onise

Hardware Flow: Integrate and Compile Intel Quartus Prime Project

Ṣiṣan sọfitiwia: Dagbasoke ati Kọ sọfitiwia igbero Nios V

Hardware Flow: Download FPGA Design
to Target Board

Ṣiṣan sọfitiwia: Idanwo ati Ṣatunkọ Nios V Software Processor

Software No Meets Spec?
Bẹẹni
Hardware No Meets Spec? Yes
Eto Pari

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Olusin 3.

Aworan atọka atẹle yii ṣe afihan apẹrẹ ohun elo ero isise Nios V aṣoju kan. Nios V Prosessor System Hardware Design Sisan

Bẹrẹ

Nios V Cores and Standard Components

Lo Apẹrẹ Platform lati ṣe apẹrẹ Eto Ipilẹ Nios V kan
Generate Platform Designer Design

Integrate Platform Designer System with Intel Quartus Prime Project
Fi Awọn ipo Pin, Awọn ibeere akoko, ati Awọn ihamọ Oniru miiran
Ṣe akopọ Hardware fun Ẹrọ Àkọlé ni Intel Quartus Prime

Setan lati gba lati ayelujara
2.1. Creating Nios V Processor System Design with Platform Designer
The Quartus Prime software includes the Platform Designer system integration tool that simplifies the task of defining and integrating Nios V processor IP core and other IPs into an Altera FPGA system design. The Platform Designer automatically creates interconnect logic from the specified high-level connectivity. The interconnect automation eliminates the time-consuming task of specifying system-level HDL connections.
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Lẹhin ti n ṣatupalẹ awọn ibeere ohun elo eto, o lo Quartus Prime lati ṣalaye ipilẹ ero isise Nios V, iranti, ati awọn paati miiran ti eto rẹ nilo. Oluṣeto Platform laifọwọyi n ṣe agbekalẹ kannaa isọpọ lati ṣepọ awọn paati ninu eto ohun elo.

2.1.1. Instantiating Nios V Processor Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

The IP core of each processor supports different configuration options based on its unique architecture. You can define these configurations to better suit your design needs.

Tabili 1.

Configuration Options Across Core Variants

Awọn aṣayan iṣeto ni

Nios V/c isise

Nios V / m isise

Debug Use Reset Request

—

Traps, Exceptions, and Interrupts

Sipiyu Architecture

ECC

Awọn caches, Awọn agbegbe agbeegbe ati awọn TCM

—

Aṣa Ilana

—

Lockstep

—

Nios V/g isise

2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Figure 4. Nios V/c Compact Microcontroller Altera FPGA IP

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2.1.1.1.1. Sipiyu Architecture Tab

Tabili 2.

CPU Architecture Tab

Ẹya ara ẹrọ

Apejuwe

Mu Avalon® Interface ṣiṣẹ Mu Interface Avalon ṣiṣẹ fun oluṣakoso itọnisọna ati oluṣakoso data. Ti o ba jẹ alaabo, eto naa nlo wiwo AXI4-Lite.

mhartid CSR value

· Invalid IP option. · Do not use mhartid CSR value in Nios V/c processor.

2.1.1.1.2. Use Reset Request Tab

Tabili 3.

Use Reset Request Tab Parameter

Use Reset Request Tab

Apejuwe

Add Reset Request Interface

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

2.1.1.1.3. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 4.

Traps, Exceptions, and Interrupts Tab Parameters

Traps, Exceptions, and Interrupts

Apejuwe

Aṣoju atunto

Tun aiṣedeede

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.

Akiyesi:

Platform Designer provides an Absolute option, which allows you to specify an absolute address in Reset Offset. Use this option when the memory storing the reset vector is located outside the processor system and subsystems.

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2.1.1.1.4. ECC Tab

Tabili 5.

ECC Taabu

ECC

Jeki Wiwa aṣiṣe ati Ijabọ Ipo

Apejuwe
· Enable this option to apply ECC feature for Nios V processor internal RAM blocks. · ECC features detect up to 2-bits errors and react based on the following behavior:
— If it is a correctable error 1-bit, the processor continues to operate after correcting the error in the processor pipeline. However, the correction is not reflected in the source memories.
- Ti aṣiṣe naa ko ba ṣe atunṣe, ero isise naa tẹsiwaju lati ṣiṣẹ laisi atunṣe ni opo gigun ti epo ati awọn iranti orisun, eyiti o le fa ki ero isise naa tẹ ipo ti kii ṣe ipinnu.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Figure 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Debug Tab

Tabili 6.

yokokoro Tab paramita

Debug Tab

Apejuwe

Mu yokokoro ṣiṣẹ
Jeki Tunto lati Module yokokoro

· Enable this option to add the JTAG target connection module to the Nios V processor. · The JTAG target connection module allows connecting to the Nios V processor through the
JTAG interface pins of the FPGA. · The connection provides the following basic capabilities:
— Start and stop the Nios V processor — Examine and edit registers and memory. — Download the Nios V application .elf file to the processor memory at runtime via
niosv-download. — Debug the application running on the Nios V processor · Connect dm_agent port to the processor instruction and data bus. Ensure the base address between both buses are the same.
· Enable this option to expose dbg_reset_out and ndm_reset_in ports. · JTAG debugger or niosv-download -r command trigger the dbg_reset_out, which
ngbanilaaye ero isise Nios V lati tun awọn agbeegbe eto ti o sopọ si ibudo yii. O gbọdọ so dbg_reset_out ni wiwo si ndm_reset_in dipo atunto
ni wiwo lati ma nfa si ipilẹ to ero isise mojuto ati aago module. O ko gbodo so dbg_reset_out ni wiwo lati tun ni wiwo lati se idinamọ iwa.

2.1.1.2.2. Use Reset Request Tab

Tabili 7.

Use Reset Request Tab Parameter

Use Reset Request Tab

Apejuwe

Add Reset Request Interface

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· Imudaniloju ifihan agbara restreq ni ipo yokokoro ko ni ipa lori ipo ero isise naa.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

2.1.1.2.3. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 8.

Traps, Exceptions, and Interrupts Tab

Apejuwe

Aṣoju atunto

Reset Offset Interrupt Mode

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.
Specific the type of interrupt controller either Direct or Vectored. Note: The Nios V/m non-pipelined processor does not support Vectored interrupts.
Nitorinaa, yago fun lilo ipo idalọwọduro Vectored nigbati ero isise ba wa ni ipo Nonpipelined.

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Akiyesi:

2.1.1.2.4. CPU Architecture

Tabili 9.

Sipiyu Architecture Tab paramita

Sipiyu Architecture

Apejuwe

Enable Pipelining in CPU

· Enable this option to instantiate pipelined Nios V/m processor. — IPC is higher at the cost of higher logic area and lower Fmax frequency.
Mu aṣayan yii ṣiṣẹ lati mu ẹrọ isise Nios V/m ti kii ṣe opo pọ si. - Ni iṣẹ mojuto iru bi ero isise Nios V/c. - Atilẹyin n ṣatunṣe aṣiṣe ati da gbigbi agbara - Agbegbe oye kekere ati igbohunsafẹfẹ Fmax ti o ga julọ ni idiyele ti IPC kekere.

Enable Avalon Interface

Mu Avalon Interface ṣiṣẹ fun oluṣakoso itọnisọna ati oluṣakoso data. Ti o ba jẹ alaabo, eto naa nlo wiwo AXI4-Lite.

mhartid CSR value

· Hart ID Forukọsilẹ (mhartid) iye 0 ni aiyipada. · Fi iye kan laarin 0 ati 4094. · Ni ibamu pẹlu Altera FPGA Avalon Mutex Core HAL API.

Related Information Embedded Peripheral IP User Guide – Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Tab
Table 10. ECC Tab
ECC Enable Error Detection and Status Reporting

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2.1.1.3. Instantiating Nios V/g General Purpose Processor Altera FPGA IP
Figure 6. Nios V/g General Purpose Processor Altera FPGA IP – Part 1

Olusin 7.

Nios V/g General Purpose Processor Altera FPGA IP – Part 2 (Turn Off Enable Core Level Interrupt Controller)

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Olusin 8.

Nios V/g General Purpose Processor Altera FPGA IP – Part 2 (Turn On Enable Core Level Interrupt Controller)

Figure 9. Nios V/g General Purpose Processor Altera FPGA IP – Part 3

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Figure 10. Nios V/g General Purpose Processor Altera FPGA IP – Part 4

2.1.1.3.1. CPU Architecture

Table 11. CPU Architecture Parameters

CPU Architecture Tab Mu Lilefoofo Point Unit

Description Enable this option to add the floating-point unit (“F” extension) in the processor core.

Enable Branch Prediction

Enable static branch prediction (Backward Taken and Forward Not Taken) for branch instructions.

mhartid CSR value

· Hart ID Forukọsilẹ (mhartid) iye 0 ni aiyipada. · Fi iye kan laarin 0 ati 4094. · Ni ibamu pẹlu Altera FPGA Avalon Mutex Core HAL API.

Disable FSQRT & FDIV instructions for FPU

· Remove floating-point square root (FSQRT) and floating-point division (FDIV) operations in FPU.
· Apply software emulation on both instructions during runtime.

Related Information Embedded Peripheral IP User Guide – Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. Debug Tab

Table 12. Debug Tab Parameters

Debug Tab

Apejuwe

Mu yokokoro ṣiṣẹ
Jeki Tunto lati Module yokokoro

2.1.1.3.3. Lockstep Tabili Tabili 13. Titiipa Taabu
Parameters Enable Lockstep Default Timeout Period Enable Extended Reset Interface

Apejuwe · Mu eto titiipa mojuto meji ṣiṣẹ. Iye aiyipada ti akoko iseto lori ijade atunto (laarin 0 ati 255). · Jeki awọn iyan Extended Tun Interface fun o gbooro sii tun Iṣakoso. Nigbati o ba jẹ alaabo, fRSmartComp n ṣe Ipilẹ Iṣakoso Atunto.

2.1.1.3.4. Use Reset Request Tab

Table 14. Use Reset Request Tab Parameter

Use Reset Request Tab

Apejuwe

Add Reset Request Interface

Mu aṣayan yii ṣiṣẹ lati ṣafihan awọn ibudo atunto agbegbe nibiti oluwa agbegbe le lo lati ṣe okunfa ero isise Nios V lati tunto laisi ni ipa awọn paati miiran ninu eto ero isise Nios V.
· Atunto ni wiwo oriširiši input resetreq ifihan agbara ati awọn ẹya o wu ack ifihan agbara.
O le beere fun atunto si ipilẹ ero isise Nios V nipa jijẹri ifihan agbara resetreq.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· Imudaniloju ifihan agbara restreq ni ipo yokokoro ko ni ipa lori ipo ero isise naa.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

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2.1.1.3.5. Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ

Tabili 15.

Awọn ẹgẹ, Awọn imukuro, ati Taabu Idilọwọ nigbati Muu Adarí Idilọwọ Ipele Ipele Core ti wa ni Pipa

Traps, Exceptions, and Interrupts Tab
Aṣoju atunto

Apejuwe
· Iranti alejo gbigba fekito atunto (adirẹsi atunto ero isise Nios V) nibiti koodu atunto gbe.
· O le yan eyikeyi iranti module ti a ti sopọ si awọn Nios V isise ilana titunto si ati ki o ni atilẹyin nipasẹ a Nios V isise bata sisan bi awọn ipilẹ oluranlowo.

Tun aiṣedeede

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.

Enable Core Level Interrupt Controller (CLIC)

· Mu CLIC ṣiṣẹ lati ṣe atilẹyin awọn idalọwọduro iṣaju-ofo ati ipo okunfa idalọwọduro atunto.
· When enabled, you can configure the number of platform interrupts, set trigger conditions, and designate some of the interrupts as pre-emptive.

Interrupt Mode Shadow Register Files

Specify the interrupt types as Direct, or Vectored Enable shadow register to reduce context switching upon interrupt.

Tabili 16.

Traps, Exceptions and Interrupts when Enable Core Level Interrupt Controller is Turned On

Traps, Exceptions, and Interrupts

Awọn apejuwe

Aṣoju atunto
Tun aiṣedeede
Enable Core Level Interrupt Controller (CLIC)

· Iranti alejo gbigba fekito atunto (adirẹsi atunto ero isise Nios V) nibiti koodu atunto gbe.
· O le yan eyikeyi iranti module ti a ti sopọ si awọn Nios V isise ilana titunto si ati ki o ni atilẹyin nipasẹ a Nios V isise bata sisan bi awọn ipilẹ oluranlowo.
· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.
· Enable CLIC to support pre-emptive interrupts and configurable interrupt trigger condition. · When enabled, you can configure the number of platform interrupts, set trigger conditions,
ki o si designate diẹ ninu awọn idalọwọduro bi ami-emptive.

Ipo Idilọwọ

Pato awọn iru idalọwọduro bi Taara, Vectored, tabi CLIC.

Shadow Register Files

· Mu iforukọsilẹ ojiji ṣiṣẹ lati dinku iyipada ọrọ-ọrọ lori idalọwọduro.
· Offers two approaches:
— Number of CLIC interrupt levels
— Number of CLIC interrupt levels – 1: This option is useful when you want the number of register file copies to fit in an exact number of M20K or M9K blocks.
Mu ẹrọ isise Nios V ṣiṣẹ lati lo iforukọsilẹ ojiji files which reduce context switching overhead upon interrupt.
For more information about shadow register files, refer to the Nios V Processor Reference Manual.

Nọmba awọn orisun idalọwọduro Platform

· Sọ nọmba ti idalọwọduro iru ẹrọ laarin 16 si 2048.
Akiyesi: CLIC ṣe atilẹyin awọn igbewọle idalọwọduro 2064, ati awọn igbewọle idalọwọduro 16 akọkọ tun ni asopọ si oluṣakoso idalọwọduro ipilẹ.

CLIC Vector Table Alignment

· Automatically determined based on the number of platform interrupt sources. · If you use an alignment that is below the recommended value, the CLIC increases logic
complexity by adding an extra adder to perform vectoring calculations. · If you use an alignment that is below the recommended value, this results in increased
kannaa complexity ni CLIC.
tesiwaju…

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Traps, Exceptions, and Interrupts
Number of Interrupt Levels
Number of Interrupt Priorities per level
Configurable da gbigbi polarity Atilẹyin eti jeki awọn idalọwọduro

Awọn apejuwe
· Specifies the number of interrupt levels with an additional level 0 for application code. Interrupts of a higher level can interrupt (pre-empt) a running handler for a lower-level interrupt.
· With non-zero interrupt levels as the only options for interrupts, the application code is always at the lowest level 0. Note: Run-time configuration of an interrupt’s level and priority is done in a single 8-bit register. If the number of interrupt levels is 256, it is not possible to configure the interrupt priority at run-time. Otherwise, the maximum number of configurable priorities is 256 / (number of interrupt levels – 1).
· Specifies the number of interrupt priorities, which the CLIC uses to determine the order in which non pre-empting interrupt handlers are called. Note: Concatenation of binary values of the selected interrupt level and selected interrupt priority must be less than 8 bits.
· Faye gba o lati tunto da gbigbi polarity nigba asiko isise. · Polarity aiyipada jẹ polarity rere.
· Allows you to configure interrupt trigger condition during runtime, i.e. high-level triggered or positive-edge triggered (when interrupt polarity is positive in Configurable interrupt polarity).
· Ipo okunfa aipe jẹ idalọwọduro ipele ti nfa.

Akiyesi:

Alaye ti o jọmọ Nios® V Ilana Itọkasi Olupilẹṣẹ

2.1.1.3.6. Memory Configurations Tab

Table 17. Memory Configuration Tab Parameters

Ẹka

Memory Configuration Tab

Apejuwe

Caches

Data Cache Size

· Specifies the size of the data cache. · Valid sizes are from 0 kilobytes (KB) to 16 KB. · Turn off data cache when size is 0 KB.

Ilana kaṣe Iwon

· Specifies the size of the instruction cache. · Valid sizes are from 0 KB to 16 KB. · Turn off instruction cache when size is 0 KB.

Agbegbe Agbeegbe A ati B

Iwọn

· Sọ iwọn agbegbe agbeegbe.
· Awọn iwọn to wulo jẹ lati 64 KB si 2 gigabytes (GB), tabi Ko si. Yiyan Ko si ọkan ti o mu agbegbe agbeegbe duro.

Adirẹsi mimọ

· Sọtọ adirẹsi ipilẹ ti agbegbe agbeegbe lẹhin ti o yan iwọn naa.
Gbogbo awọn adirẹsi ni agbeegbe agbegbe gbe awọn uncacheable data wiwọle.
Adirẹsi ipilẹ agbegbe gbọdọ wa ni ibamu si iwọn agbegbe agbeegbe.

Tightly Coupled Memories

Iwọn

· Specifies the size of the tightly-coupled memory. — Valid sizes are from 0 MB to 512 MB.

Base Address Initialization File

· Specifies the base address of tightly-coupled memory. · Specifies the initialization file for tightly-coupled memory.

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Akiyesi:

Ninu eto ero isise Nios V pẹlu ṣiṣiṣẹ kaṣe, o gbọdọ gbe awọn agbeegbe eto laarin agbegbe agbeegbe kan. O le lo awọn agbegbe agbeegbe lati ṣalaye iṣowo ti kii ṣe cacheable fun awọn agbeegbe bii UART, PIO, DMA, ati awọn miiran.

2.1.1.3.7. ECC Tab

Table 18. ECC Tab
ECC Enable Error Detection and Status Reporting
Mu Atunse Bit Nikan Kan ṣiṣẹ

Apejuwe
· Enable this option to apply ECC feature for Nios V processor internal RAM blocks. · ECC features detect up to 2-bits errors and react based on the following behavior:
- Ti o ba jẹ aṣiṣe bit ti o le ṣe atunṣe ati Mu Atunse Nikan Bit ṣiṣẹ, ero isise naa tẹsiwaju lati ṣiṣẹ lẹhin atunṣe aṣiṣe ninu opo gigun ti ẹrọ. Sibẹsibẹ, atunṣe ko han ninu awọn iranti orisun.
— If it is a correctable single bit error and Enable Single Bit Correction is turned on, the processor continues to operate after correcting the error in the processor pipeline and the source memories.
— If it is an uncorrectable error, the processor halts its operation.
Enable single bit correction on embedded memory blocks in the core.

2.1.1.3.8. Custom Instruction Tab

Akiyesi:

This tab is only available for the Nios V/g processor core.

Aṣa ilana Nios V Aṣa ilana Hardware ni wiwo Table
Nios V Custom Instruction Software Macro Table

Apejuwe
· Nios V isise nlo yi tabili lati setumo awọn oniwe-aṣa ilana alakoso atọkun.
· Defined custom instruction manager interfaces are uniquely encoded by an Opcode (CUSTOM0-3) and 3 bits of funct7[6:4].
· You can define up to a total of 32 individual custom instruction manager interfaces.
· Nios V processor uses this table is used to define custom instruction software encodings for defined custom instruction manager interfaces.
Fun fifi koodu sọfitiwia aṣa aṣa kọọkan ti a ṣalaye, Opcode (CUSTOM0-3) ati awọn bits 3 ti funct7 [6:4] fifi ẹnọ kọ nkan gbọdọ ni ibamu si wiwo oluṣakoso itọnisọna aṣa ti asọye ni Tabili Interface Hardware Itọnisọna Aṣa.
O le lo funct7[6:4], funct7[3:0], ati funct3[2:0] lati setumo fifi koodu sii fun itọnisọna aṣa ti a fun, tabi ti a sọ bi Xs ti yoo kọja bi awọn ariyanjiyan itọnisọna afikun.
· Nios V processor provides defined custom instruction software encodings as generated C-macros in system.h, and follow the R-type RISC-V instruction format.
· Mnemonics may be used to define custom names for: — The generated C-Macros in system.h.
- Awọn mnemonics yokokoro GDB ti ipilẹṣẹ ni custom_instruction_debug.xml.

Alaye ti o jọmọ
AN 977: Nios V Processor Custom Instruction For more information about custom instructions that allow you to customize the Nios® V processor to meet the needs of a particular application.

Nios® V Embedded Processor Design Handbook 22

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2.1.2. Defining System Component Design
Use the Platform Designer to define the hardware characteristics of the Nios V processor system and add in the desired components. The following diagram demonstrates a basic Nios V processor system design with the following components: · Nios V processor core · On-Chip Memory · JTAG UART · Aago Aarin (aṣayan)(1)
Nigbati Iranti On-Chip tuntun ba ṣafikun si eto Onise Platform, ṣe Awọn alaye Eto amuṣiṣẹpọ lati ṣe afihan awọn paati iranti ti a ṣafikun ni ipilẹ. Ni omiiran, o le mu Amuṣiṣẹpọ Aifọwọyi ṣiṣẹ ni Apẹrẹ Platform lati ṣe afihan awọn ayipada paati tuntun laifọwọyi
Aworan 11. Eksample asopọ ti Nios V ero isise pẹlu miiran awọn pẹẹpẹẹpẹ ni Platform onise

(1) You have the option to use the Nios V Internal Timer features to replace the external Interval Timer in Platform Designer.

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You must also define operation pins to export as conduit in your Platform Designer system. For example, atokọ pin iṣẹ eto FPGA to dara jẹ asọye bi isalẹ ṣugbọn ko ni opin si:
· Aago
· Tunto
· I/O signals
2.1.3. Specifying Base Addresses and Interrupt Request Priorities
To specify how the components added in the design interact to form a system, you need to assign base addresses for each agent component and assign interrupt request (IRQ) priorities for the JTAG UART and the interval timer. The Platform Designer provides a command – Assign Base Addresses – which automatically assigns proper base addresses to all components in a system. However, you can adjust the base addresses based on your needs.
Awọn atẹle jẹ diẹ ninu awọn itọnisọna fun yiyan awọn adirẹsi ipilẹ:
· Nios V ero isise mojuto ni o ni a 32-bit adirẹsi igba. Lati wọle si awọn paati aṣoju, adirẹsi ipilẹ wọn gbọdọ wa laarin 0x00000000 ati 0xFFFFFFFF.
· Awọn eto Nios V lo awọn ibakan aami lati tọka si awọn adirẹsi. O ko ni lati yan awọn iye adirẹsi ti o rọrun lati ranti.
· Awọn iye adirẹsi ti o ṣe iyatọ awọn paati pẹlu iyatọ adirẹsi ọkan-bit kan ṣe agbejade ohun elo ti o munadoko diẹ sii. O ko ni lati ṣapọ gbogbo awọn adirẹsi ipilẹ sinu iwọn adirẹsi ti o kere julọ nitori iṣiṣẹpọ le ṣẹda ohun elo ti ko ni agbara.
· Platform Designer does not attempt to align separate memory components in a contiguous memory range. For example, ti o ba ti o ba fẹ ọpọ On-Chip Memory irinše addressable bi ọkan contiguous iranti ibiti, o gbọdọ kedere sọtọ mimọ adirẹsi.
Platform Designer also provides an automation command – Assign Interrupt Numbers which connects IRQ signals to produce valid hardware results. However, assigning IRQs effectively requires an understanding of the overall system response behavior. Platform Designer cannot make educated guesses about the best IRQ assignment.
The lowest IRQ value has the highest priority. In an ideal system, Altera recommends that the timer component to have the highest priority IRQ, i.e., the lowest value, to maintain the accuracy of the system clock tick.
In some cases, you might assign a higher priority to real time peripherals (such as video controllers), which demands a higher interrupt rate than timer components.
Alaye ti o jọmọ
Quartus Prime Pro Edition User Guide: More information about creating a System with Platform Designer.

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2.2. Integrating Platform Designer System into the Quartus Prime Project
After generating the Nios V system design in Platform Designer, perform the following tasks to integrate the Nios V system module into the Quartus Prime FPGA design project. · Instantiate the Nios V system module in the Quartus Prime project · Connect signals from Nios V system module to other signals in the FPGA logic · Assign physical pins location · Constrain the FPGA design
2.2.1. Instantiating the Nios V Processor System Module in the Quartus Prime Project
Platform Designer generates a system module design entity which you can instantiate in Quartus Prime. How you instantiate the system module depends on the design entry method for the overall Quartus Prime project. For example, if you were using Verilog HDL for design entry, instantiate the Verilog based system module. If you prefer to use the block diagram method for design entry, instantiate a system module symbol .bdf file.
2.2.2. Awọn ifihan agbara Nsopọ ati Yiyan Awọn ipo Pin Ti ara
Lati so apẹrẹ Altera FPGA rẹ pọ si apẹrẹ ipele igbimọ rẹ, ṣe awọn iṣẹ ṣiṣe wọnyi: · Ṣe idanimọ ipele-oke file for your design and signals to connect to external Altera
FPGA ẹrọ pinni. Loye iru awọn pinni lati sopọ nipasẹ itọsọna olumulo apẹrẹ ipele igbimọ rẹ tabi
schematics. · Assign signals in the top-level design to ports on your Altera FPGA device with pin
assignment tools.
Your Platform Designer system can be the top level design. However, the Altera FPGA can also include additional logic based on your needs and thus introduces a custom top-level file. The top-level file connects the Nios V processor system module signals to other Altera FPGA design logic.
Related Information Quartus Prime Pro Edition User Guide: Design Constraints
2.2.3. Constraining the Altera FPGA Design
A proper Altera FPGA system design includes design constraints to ensure the design meets timing closure and other logic constraint requirements. You must constrain your Altera FPGA design to meet these requirements explicitly using tools provided in the Quartus Prime software or third-party EDA providers. The Quartus Prime software uses the provided constraints during the compilation phase to get the optimum placement results.

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Related Information · Quartus Prime Pro Edition User Guide: Design Constraints · Third-party EDA Partners · Quartus Prime Pro Edition User Guide: Timing Analyzer
2.3. Ṣiṣeto Eto Iranti ero isise Nios V kan
Abala yii ṣapejuwe awọn iṣe ti o dara julọ fun yiyan awọn ẹrọ iranti ni eto ifibọ Apẹrẹ Platform pẹlu ero isise Nios V ati iyọrisi iṣẹ ṣiṣe to dara julọ. Awọn ẹrọ iranti ṣe ipa pataki ni imudarasi iṣẹ gbogbogbo ti eto ifibọ. Ifibọ eto iranti tọjú awọn ilana eto ati data.
2.3.1. Volatile Memory
A primary distinction in a memory type is volatility. Volatile memory only holds its contents while you supply power to the memory device. As soon as you remove the power, the memory loses its contents.
Examples of volatile memory are RAM, cache, and registers. These are fast memory types that increases running performance. Altera recommends you load and execute Nios V processor instructions in RAM and pair Nios V IP core with On-Chip Memory IP or External Memory Interface IP for optimum performance.
To improve performance, you can eliminate additional Platform Designer adaptation components by matching Nios V processor data manager interface type or width with boot RAM. For example, o le tunto On-Chip Memory II pẹlu kan 32-bits AXI-4 ni wiwo, eyi ti o ibaamu Nios V data ni wiwo faili.
Related Information · External Memory Interfaces IP Support Center · On-Chip Memory (RAM or ROM) Altera FPGA IP · On-Chip Memory II (RAM or ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place from OCRAM on page 54
2.3.1.1. On-Chip Memory iṣeto ni Ramu tabi ROM
O le tunto Altera FPGA On-Chip Memory IPs bi Ramu tabi ROM. · Ramu n pese agbara kika ati kikọ ati pe o ni ẹda iyipada. Ti o ba wa
booting the Nios V processor from an On-Chip RAM, you must make sure boot content is preserved and not corrupted in the event of a reset during run time. · If a Nios V processor is booting from ROM, any software bug on the Nios V processor cannot erroneously overwrite the contents of On-Chip Memory. Thus, reducing the risk of boot software corruption.
Alaye ti o jọmọ · Iranti Lori Chip (Ramu tabi ROM) Altera FPGA IP · On-Chip Memory II (Ramu tabi ROM) Altera FPGA IP · Nios V Ohun elo Processor Ṣiṣẹ-Ni-Ibi lati OCRAM loju iwe 54

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2.3.1.2. Awọn caches
Awọn iranti lori-chip ni a lo nigbagbogbo lati ṣe iṣẹ ṣiṣe kaṣe nitori airi kekere wọn. Awọn ero isise Nios V nlo iranti lori-chip fun itọnisọna rẹ ati awọn caches data. Agbara to lopin ti iranti lori-chip kii ṣe ọran fun awọn kaṣe nitori wọn jẹ deede kekere.
Awọn caches ni a lo nigbagbogbo labẹ awọn ipo wọnyi:
· Iranti deede wa ni pipa-ërún ati pe o ni akoko wiwọle to gun ju iranti on-chip lọ.
· The performance-critical sections of the software code can fit in the instruction cache, improving system performance.
· Iṣe-pataki, apakan ti a lo nigbagbogbo ti data le baamu ni kaṣe data, imudarasi iṣẹ ṣiṣe eto.
Enabling caches in Nios V processor creates a memory hierarchy, which minimize the memory access time.
2.3.1.2.1. Peripheral region
Any embedded peripherals IP, such as UART, I2C, and SPI must not be cached. Cache is highly recommended for external memories which are affected by long access time, while internal on-chip memories may be excluded due to their short access time. You must not cache any embedded peripheral IPs, such as UART, I2C, and SPI, except for memories. This is important because events from external devices, such as agent devices updating the soft IPs, are not captured by the processor cache, in turn not received by the processor. As a result, these events can go unnoticed until you flush the cache, which can lead to unintended behavior in your system. In summary, the memory-mapped region of embedded peripheral IPs is uncacheable and must reside within the processor’s peripheral regions.
To set a peripheral region, follow these steps:
1. Ṣii awọn eto ká adirẹsi Map ni Platform onise.
2. Lilö kiri si maapu adirẹsi ti oluṣakoso itọnisọna ti ero isise ati Oluṣakoso data.
3. Ṣe idanimọ awọn agbeegbe ati awọn iranti ninu eto rẹ.
Aworan 12. Eksample of Address Map

Note: The blue arrows are pointing to memories. 4. Group the peripherals:
a. Memory as cacheable b. Peripherals as uncacheable

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Table 19. Cacheable and Uncacheable Region

Alabojuto

Maapu adirẹsi

Ipo

Agbegbe agbeegbe

Iwọn

Adirẹsi mimọ

user_application_mem.s1

0x0 ~ 0x3ffff

Kaṣe

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 baiti N / A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 baiti (iwọn min jẹ 65536 awọn baiti)

0x54000

sysid_qsys_0.control_slave

0x54080 ~ 0x54087

Ailokun

uart.avalon_jtag_ẹrú

0x54088 ~ 0x5408f

Ailokun

5. Ṣepọ awọn agbegbe agbeegbe pẹlu awọn iwọn pato wọn:
· Fun example, if the size is 65536 bytes, it corresponds to 0x10000 bytes. Therefore, the allowed base address must be a multiple of 0x10000.
· The CPU.dm_agent uses a base address of 0x40000, which is a multiple of 0x10000. As a result, Peripheral Region A, with a size of 65536 bytes and a base address of 0x40000, meets the requirements.
· The base address of the collection of uncacheable regions at 0x54000 is not a multiple of 0x10000. You must reassign them to 0x60000 or other multiple of 0x10000. Thus, Peripheral Region B, which has a size of 65536 bytes and a base address of 0x60000, satisfies the criteria.

Table 20. Cacheable and Uncacheable Region with Reassignment

Alabojuto

Maapu adirẹsi

Ipo

Agbegbe agbeegbe

Iwọn

Adirẹsi mimọ

user_application_mem.s1

0x0 ~ 0x3ffff

Kaṣe

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

Uncacheable 65536 baiti

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Kaṣe

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Cacheable Uncacheable Uncacheable Uncacheable

144 baiti (iwọn min jẹ 65536 awọn baiti)

0x60000

uart.avalon_jtag_ẹrú

0x60088 ~ 0x6008f

Ailokun

2.3.1.3. Tightly Coupled Memory
Tightly coupled memories (TCMs) are implemented using on-chip memory as their low latency makes them well suited to the task. TCMs are memories mapped in the typical address space but have a dedicated interface to the microprocessor and possess the high-performance, low-latency properties of cache memory. TCM also provides a subordinate interface for the external host. The processor and external host have the same permission level to handle the TCM.

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Akiyesi:

When the TCM subordinate port is connected to an external host, it may be displayed with a different base address than the base address assigned in the processor core. Altera recommends to align both addresses to the same value.

2.3.1.4. External Memory Interface (EMIF)
EMIF (External Memory Interface) functions similarly to SRAM (Static Random Access Memory), but it is dynamic and requires periodic refreshing to maintain its content. The dynamic memory cells in EMIF are much smaller than the static memory cells in SRAM, which results in higher capacity and lower-cost memory devices.
Ni afikun si ibeere isọdọtun, EMIF ni awọn ibeere wiwo kan pato ti o ṣe pataki ohun elo oluṣakoso amọja. Ko dabi SRAM, eyiti o ni awọn laini adirẹsi ti o wa titi, EMIF ṣeto aaye iranti rẹ sinu awọn banki, awọn ori ila, ati awọn ọwọn. Yipada laarin awọn banki ati awọn ori ila ṣafihan diẹ ninu awọn oke, nitorinaa o gbọdọ farabalẹ paṣẹ awọn iraye si iranti lati lo EMIF daradara. EMIF tun multiplexes kana ati iwe adirẹsi lori awọn kanna adirẹsi ila, atehinwa awọn nọmba ti awọn pinni beere fun a fi EMIF iwọn.
Awọn ẹya iyara to ga julọ ti EMIF, gẹgẹbi DDR, DDR2, DDR3, DDR4, ati DDR5, fa awọn ibeere iduroṣinṣin ifihan agbara ti o muna ti awọn apẹẹrẹ PCB gbọdọ gbero.
Awọn ẹrọ EMIF ni ipo laarin awọn iye owo-doko julọ ati awọn iru Ramu ti o ga julọ ti o wa, ṣiṣe wọn ni aṣayan olokiki. Ẹya bọtini kan ti wiwo EMIF ni EMIF IP, eyiti o ṣakoso awọn iṣẹ ṣiṣe ti o nii ṣe pẹlu isodipupo pupọ, onitura, ati yi pada laarin awọn ori ila ati awọn banki. Apẹrẹ yii ngbanilaaye eto iyokù lati wọle si EMIF laisi iwulo lati loye faaji inu rẹ.

Jẹmọ Alaye Ita Memory atọkun IP Support Center

2.3.1.4.1. Adirẹsi Span Extender IP
Adirẹsi Span Extender Altera FPGA IP ngbanilaaye awọn atọkun ogun ti a ya aworan iranti lati wọle si maapu adirẹsi ti o tobi tabi kere ju iwọn awọn ifihan agbara adirẹsi wọn gba laaye. Adirẹsi Span Extender IP pin aaye ti a le koju si ọpọlọpọ awọn ferese lọtọ ki agbalejo le wọle si apakan ti o yẹ ti iranti nipasẹ window.
The Address Span Extender does not limit host and agent widths to a 32-bit and 64bit configuration. You can use the Address Span Extender with 1-64 bit address windows.

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olusin 13. Adirẹsi Span Extender Altera FPGA IP
Agent Word Address

Adirẹsi Span Extender

Table ìyàwòrán
Control Port A

…

Control Register 0 Control Register Z-1

Expanded Host Address H

Alaye ti o jọmọ
Itọsọna olumulo Quartus® Prime Pro Edition: Apẹrẹ Platform Tọkasi koko ọrọ Adirẹsi Span Extender Intel® FPGA IP fun alaye diẹ sii.

2.3.1.4.2. Using Address Span Extender IP with Nios V Processor
The 32-bit Nios V processor can address up to 4 GB of an address span. If the EMIF contains more than 4GB of memory, it exceeds the maximum supported address span, rendering the Platform Designer system as erroneous. An Address Span Extender IP is required to resolve this issue by dividing a single EMIF address space into multiple smaller windows.
Altera recommends that you consider the following parameters.

Table 21. Adirẹsi Span Extender paramita

Paramita

Niyanju Eto

Datapath Width
Expanded Master Byte Address Width

Select 32-bits, which corelates to the 32-bit processor. Depends on the EMIF memory size.

Slave Word Address Width Burstcount Width

Select 2 GB or less. Remaining address span of Nios V processor is reserved for other embedded soft IPs.
Bẹrẹ pẹlu 1 ati maa pọ si iye yii lati mu ilọsiwaju sii.

Nọmba ti iha-windows

Select 1 sub-window if you are connecting EMIF to the Nios V processor as instruction and data memory, or both. Switching between multiple sub-windows while Nios V processor is executing from EMIF is hazardous.

Mu Ibudo Iṣakoso Ẹrú ṣiṣẹ

Pa ibudo iṣakoso ẹrú kuro ti o ba n so EMIF pọ si ero isise Nios V gẹgẹbi itọnisọna ati/tabi iranti data. Awọn ifiyesi kanna bi Nọmba ti awọn window-ipin.

Maximum Pending Reads

Bẹrẹ pẹlu 1 ati maa pọ si iye yii lati mu ilọsiwaju sii.

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Ṣe nọmba 14. Itọnisọna Nsopọ ati Oluṣakoso Data si Adirẹsi Span Extender

olusin 15. Adirẹsi Mapping

Ṣe akiyesi pe Adirẹsi Span Extender le wọle si gbogbo aaye iranti 8GB ti EMIF. Sibẹsibẹ, nipasẹ Adirẹsi Span Extender, ẹrọ isise Nios V le wọle si aaye iranti 1GB akọkọ ti EMIF nikan.

Figure 16. Simplified Block Diagram

Platform onise System

Remaining 3 GB

Nios V processor address

span is for embedded

NNioios sVV PProrocecsesosor r
M

asọ IPs ni kanna eto.
1 GB window

Adirẹsi Span

Extender

Only the first 1 GB

of EMIF memory is connected to Nios V

EMIF

isise.

8 GB
S

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2.3.1.4.3. Asọye Adirẹsi Span Extender Linker Memory Device 1. Setumo awọn adirẹsi Span Extender (EMIF) bi awọn atunto fekito. Ni omiiran, o le fi eto atunto ero isise Nios V si awọn iranti miiran, gẹgẹbi OCRAM tabi awọn ẹrọ filasi.
Figure 17. Multiple Options as Reset Vector
However, the Board Support Package (BSP) Editor cannot automatically register the Address Span Extender (EMIF) as a valid memory. Depending on the choice you made, you see two different situations as shown in the following figures. Figure 18. BSP Error when Defining Address Span Extender (EMIF) as Reset Vector

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Ṣe nọmba 19. EMIF ti o padanu nigbati Itumọ Awọn iranti miiran bi Vector Tunto

2. O gbọdọ fi ọwọ kun Adirẹsi Span Extender (EMIF) ni lilo Fikun-un Ẹrọ Iranti, Fikun Agbegbe Iranti Asopọmọra, ati Fi Awọn aworan Abala Linker kun ni taabu BSP Linker Script.
3. Tẹle awọn igbesẹ wọnyi:
a. Determine the address span of the Address Span Extender using the Memory Map (The example in the following figure uses Address Span Extender range from 0x0 to 0x3fff_ffff).
Figure 20. Memory Map

b. Tẹ Fi Memory Device, ati ki o fọwọsi ni da lori awọn alaye ninu rẹ oniru ká Memory Map: i. Orukọ ẹrọ: emif_ddr4. Akiyesi: Rii daju pe o daakọ orukọ kanna lati Maapu Iranti. ii. Adirẹsi mimọ: 0x0 iii. Iwọn: 0x40000000
c. Click Add to add a new linker memory region:

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Table 22. Adding Linker Memory Region

Awọn igbesẹ

Tunto Vector

emif_ddr4

Awọn iranti miiran

Add a new Linker Memory Region called reset. Add a new Linker Memory Region for the

· Region Name: reset

emif_ddr4.

· Region Size: 0x20

· Region Name: emif_ddr4

· Memory Device: emif_ddr4

· Region Size: 0x40000000

· Memory Offset: 0x0

· Memory Device: emif_ddr4

· Memory Offset: 0x0

Add a new Linker Memory Region for the

emif_ddr4 ti o ku.

· Region Name: emif_ddr4

· Region Size: 0x3fffffe0

· Memory Device: emif_ddr4

· Memory Offset: 0x20

Ṣe nọmba 21. Agbegbe Linker nigbati o n ṣalaye Adirẹsi Span Extender (EMIF) gẹgẹbi Atunto Vector

olusin 22. Linker Region nigbati asọye Miiran Memo bi Tun Vector
d. Ni kete ti emif_ddr4 ti wa ni afikun si BSP, o le yan fun eyikeyi Abala Linker.
Figure 23. Added Address Span Extender (EMIF) Successfully

e. Foju ikilọ nipa ẹrọ Iranti emif_ddr4 ko han ni apẹrẹ SOPC.
f. Tẹsiwaju lati Ṣẹda BSP.
Related Information Introduction to Nios V Processor Booting Methods on page 51

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2.3.2. Non-iyipada Memory
Iranti ti kii ṣe iyipada ṣe idaduro awọn akoonu rẹ nigbati agbara ba wa ni pipa, ti o jẹ ki o jẹ yiyan ti o dara fun titoju alaye ti eto naa gbọdọ gba pada lẹhin iwọn agbara eto kan. Iranti ti kii ṣe iyipada ni igbagbogbo tọju koodu bata-isise, awọn eto ohun elo itẹramọṣẹ, ati data atunto Altera FPGA. Botilẹjẹpe iranti ti kii ṣe iyipada ni advantage of retaining its data when you remove the power, it is much slower compare to volatile memory, and often has more complex writing and erasing procedures. Non-volatile memory is also usually only guaranteed to be erasable a given number of times, after which it may fail.
Examples of non-volatile memory include all types of flash, EPROM, and EEPROM. Altera recommends you to store Altera FPGA bitstreams and Nios V program images in a non-volatile memory, and use serial flash as the boot device for Nios V processors.
Alaye ti o jọmọ
· Generic Serial Flash Interface Altera FPGA IP User Guide
Onibara Apoti ifiweranṣẹ Altera FPGA IP Itọsọna olumulo
2.4. Clocks and Resets Best Practices
Loye bii aago ero isise Nios V ati ibugbe atunto ṣe n ṣe ajọṣepọ pẹlu gbogbo agbeegbe ti o sopọ mọ jẹ pataki. Eto ero isise Nios V ti o rọrun bẹrẹ pẹlu agbegbe aago kan, ati pe o le ni idiju pẹlu eto agbegbe aago pupọ nigbati agbegbe aago iyara ba kọlu pẹlu agbegbe aago o lọra. O nilo lati ṣe akiyesi ati loye bawo ni awọn oriṣiriṣi awọn ibugbe wọnyi ṣe n ṣe ilana ti atunto ati rii daju pe ko si awọn iṣoro arekereke eyikeyi.
Fun adaṣe ti o dara julọ, Altera ṣeduro gbigbe ero isise Nios V ati iranti bata ni agbegbe aago kanna. Ma ṣe tu ero isise Nios V silẹ lati tunto ni agbegbe aago iyara nigbati o ba bata lati iranti ti o ngbe ni agbegbe aago ti o lọra pupọ, eyiti o le fa aṣiṣe gbigba itọnisọna. O le nilo diẹ ninu awọn ilana afọwọṣe ju ohun ti Platform Designer pese nipasẹ aiyipada, ati gbero itusilẹ itusilẹ topology ni ibamu da lori ọran lilo rẹ. Ti o ba fẹ tun eto rẹ pada lẹhin ti o ba wa ni oke ati ṣiṣe fun igba diẹ, lo awọn ero kanna si ilana atunto eto ati ibeere ipilẹṣẹ atunto lẹhin.
2.4.1. System JTAG Aago
Specifying the clock constraints in every Nios V processor system is an important system design consideration and is required for correctness and deterministic behavior. The Quartus Prime Timing Analyzer performs static timing analysis to validate the timing performance of all logic in your design using industry-standard constraint, analysis, and reporting methodology.
Example 1. Basic 100 MHz Clock with 50/50 Duty Cycle and 16 MHz JTAG Aago
#************************************************************** # Create 100MHz Clock #************************************************************** create_clock -name {clk} -period 10 [get_ports {clk}] #************************ Create 16MHz JTAG Aago #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [gba_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Alaye ti o jọmọ Quartus Prime Time Analyzer Iwe Onjewiwa
2.4.2. Tun Ibeere Interface
Nios V ero isise pẹlu ohun iyan tun ìbéèrè apo. Ohun elo ibeere atunto ni reset_req ati awọn ifihan agbara reset_req_ack.
To enable the reset request in Platform Designer: 1. Launch the Nios V Processor IP Parameter Editor. 2. On the Use Reset Request setting, turn on the Add Reset Request Interface
aṣayan.
olusin 24. Jeki Nios V Processor Ibere Ibere
Ifihan agbara reset_req n ṣiṣẹ bi idalọwọduro. Nigbati o ba so reset_req, o n beere lati tunto si mojuto. Awọn mojuto duro fun eyikeyi dayato akero idunadura lati pari awọn oniwe-isẹ. Fun example, if there is a pending memory access transaction, the core waits for a complete response. Similarly, the core accepts any pending instruction response but does not issue an instruction request after receiving the reset_req signal.
The reset operation consists of the following flow: 1. Complete all pending operations 2. Flush the internal pipeline 3. Set the Program Counter to the reset vector 4. Reset the core The whole reset operation takes a few clock cycles. The reset_req must remain asserted until reset_req_ack is asserted indicating core reset operation has successfully completed. Failure to do so results in core’s state being non-deterministic.

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2.4.2.1. Aṣoju lilo igba
· O le sọ ifihan agbara reset_req lati agbara-lori lati ṣe idiwọ mojuto ero isise Nios V lati bẹrẹ ipaniyan eto lati inu fekito atunto rẹ titi awọn ogun FPGA miiran ninu eto bẹrẹ iranti bata ero isise Nios V. Ni idi eyi, gbogbo subsystem le ni iriri kan mimọ hardware si ipilẹ. Awọn ero isise Nios V wa ni idaduro titilai ni ipo ibeere atunto titi ti awọn ọmọ-ogun FPGA miiran yoo bẹrẹ iranti bata ero isise naa.
· In a system where you must reset the Nios V processor core without disrupting the rest of the system, you can assert the reset_req signal to cleanly halt the current operation of the core and restart the processor from the reset vector once the system releases the reset_req_ack signal.
· An external host can use the reset request interface to ease the implementations of the following tasks:
— Halt the current Nios V processor program.
— Load a new program into the Nios V processor boot memory.
- Gba ero isise naa laaye lati bẹrẹ ṣiṣe eto tuntun naa.
Altera ṣeduro rẹ lati ṣe ilana ilana akoko kan lati ṣe atẹle ipo ifihan agbara reset_req_ack. Ti mojuto ero isise Nios V ṣubu sinu ipo iduro ailopin ati duro fun idi aimọ, reset_req_ack ko le sọ titilai. Ilana akoko ipari gba ọ laaye lati:
· Define a recovery timeout period and perform system recovery with system level reset.
· Perform a hardware level reset.
2.4.3. Tun IP Tu silẹ
Altera SDM-based devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Altera recommends you to use the Reset Release Altera FPGA IP as one of the initial inputs to the reset circuit. Intel® SDMbased devices includes Stratix® 10, and AgilexTM devices. Control-block based devices are not affected by this requirement.
Alaye ti o jọmọ
AN 891: Lilo Tu Tu Altera FPGA IP
2.5. Fifiranṣẹ Aṣoju Aiyipada
Onise Platform gba ọ laaye lati pato aṣoju aiyipada eyiti o ṣe bi aṣoju aiyipada idahun aṣiṣe. Aṣoju aiyipada ti o yan n pese iṣẹ esi aṣiṣe fun awọn ọmọ-ogun ti o gbiyanju awọn iraye si ti kii ṣe iyipada sinu maapu adirẹsi naa.
Awọn oju iṣẹlẹ wọnyi nfa iṣẹlẹ ti kii ṣe iyipada:
· Bosi idunadura aabo ipinle ṣẹ
· Wiwọle si iṣowo si agbegbe iranti aisọ asọye
· Exception event and etc.

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A default agent should be assigned to handle such events, where undefined transaction is rerouted to the default agent and subsequently responds to Nios V processor with an error response.
Alaye ti o jọmọ
· Quartus Prime Pro Edition User Guide: Platform Designer. Designating a Default Agent
· Quartus Prime Pro Edition User Guide: Platform Designer. Error Response Slave Altera FPGA IP
· Github – Supplemental Reset Components for Qsys

2.6. Assigning a UART Agent for Printing
Printing is useful for debugging the software application, as well as for monitoring the status of your system. Altera recommends printing basic information such as a startup message, error message, and execution progress of the software application.
Avoid using the printf() library function under the following circumstances: · The printf() library causes the application to stall if no host is reading output.
This is applicable to the JTAG UART only. · The printf() library consumes large amounts of program memory.

2.6.1. Preventing Stalls by the JTAG UART

Table 23. Differences between Traditional UART and JTAG UART

UART Type Traditional UART

Apejuwe
Transmits serial data regardless of whether an external host is listening. If no host reads the serial data, the data is lost.

JTAG UART

Kọ data ti a tan kaakiri si ifipamọ iṣelọpọ ati gbarale agbalejo ita lati ka lati inu ifipamọ lati sọ di ofo.

Awọn JTAG Iwakọ UART n duro de igba ti ifipajade ti kun. Awọn JTAG Awakọ UART n duro de agbalejo ita lati ka lati inu ifipamọ iṣelọpọ ṣaaju kikọ data atagba diẹ sii. Ilana yi idilọwọ awọn isonu ti atagba data.
However, when system debugging is not required, such as during production, embedded systems are deployed without a host PC connected to JTAG UART. If the system selected the JTAG UART gẹgẹbi aṣoju UART, o le fa eto idaduro nitori ko si ogun ita ti o sopọ.
To prevent stalling by JTAG UART, lo awọn aṣayan wọnyi:

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Table 24. Idena lori Stalling nipasẹ JTAG UART

Awọn aṣayan
Ko si UART ni wiwo ati ki o iwakọ bayi
Lo wiwo UART miiran ati awakọ
Ṣetọju JTAG UART interface (without driver)

During Hardware Development (in Platform Designer)

During Software Development (in Board Support Package Editor)

Remove JTAG UART from the system

Tunto hal.stdin, hal.stdout ati hal.stderr bi Ko si.

Replace JTAG UART with other soft Configure hal.stdin, hal.stdout and hal.stderr

UART IP

with other soft UART IP.

Ṣetọju JTAG UART in the system

· Configure hal.stdin, hal.stdout and hal.stderr as None in the Board Support Package Editor.
· Disable JTAG UART driver in BSP Driver tab.

2.7. JTAG Awọn ifihan agbara
The Nios V processor debug module uses the JTAG ni wiwo fun software ELF download ati software n ṣatunṣe aṣiṣe. Nigbati o ba ṣatunṣe apẹrẹ rẹ pẹlu JTAG wiwo, JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design. Specifying the JTAG signal constraints in every Nios V processor system is an important system design consideration and is required for correctness and deterministic behavior.
Altera recommends that any design’s system clock frequency be at least four times the JTAG clock frequency to ensure that the on-chip instrumentation (OCI) core functions properly.
Related Information · Quartus® Prime Timing Analyzer Cookbook: JTAG Awọn ifihan agbara
Fun alaye siwaju sii nipa JTAG awọn itọnisọna awọn ihamọ akoko. KDB: Kini idi ti igbasilẹ niosv ṣe kuna pẹlu ero isise Nios® V/m ti kii-pipelined ni
JTAG igbohunsafẹfẹ 24MHz tabi 16Mhz?
2.8. Ti o dara ju Platform onise System Performance
Platform Designer provides tools for optimizing the performance of the system interconnect for Altera FPGA designs.

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olusin 25. Iṣapeye Examples

Awọn example shown in the figure demonstrates the following steps:
1. Adds Pipeline Bridge to alleviate critical paths by placing it: a. Between the Instruction Manager and its agents b. Between the Data Manager and its agents
2. Apply True Dual port On-Chip RAM, with each port dedicated to the Instruction Manager and the Data Manager respectively

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Tọkasi awọn ọna asopọ ti o ni ibatan ti o wa ni isalẹ, eyiti o ṣafihan awọn ilana fun gbigbe awọn irinṣẹ to wa ati awọn iṣowo ti imuse kọọkan.
Alaye ti o jọmọ · Quartus® Prime Pro Edition Itọsọna olumulo: Apẹrẹ Platform
Refer to the topic Optimizing Platform Designer System Performance for more information. · Quartus® Prime Standard Edition User Guide: Platform Designer Refer to the topic Optimizing Platform Designer System Performance for more information.

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3. Nios V Prosessor Software System Design
Ipin yii ṣapejuwe ṣiṣan idagbasoke sọfitiwia ero isise Nios V ati awọn irinṣẹ sọfitiwia ti o le lo ninu idagbasoke eto apẹrẹ ifibọ rẹ. Awọn akoonu Sin bi ohun loriview before developing a Nios V processor software system.
Figure 26. Software Design Flow
Bẹrẹ

Generate the BSP in the Platform Designer Using the BSP Editor

Generate the BSP Using the Nios V Command Shell
Ṣẹda Ohun elo CMake Kọ File Using the Nios V Command Shell

Akiyesi:

Ṣe agbewọle BSP ati Ohun elo CMake Kọ File
Build the Nios V Processor Application using the
RiscFree IDE fun Intel FPGA

Kọ ohun elo Nios V Processor nipa lilo eyikeyi
Olootu koodu orisun laini aṣẹ, CMake, ati Ṣe
ase
Ipari

Altera recommends that you use an Altera FPGA development kit or a custom prototype board for software development and debugging. Many peripherals and system-level features are available only when your software runs on an actual board.

© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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3.1. Nios V Prosessor Software Sisan
3.1.1. Board Support Package Project
Ise agbese Nios V Board Support Package (BSP) jẹ ile-ikawe amọja ti o ni koodu atilẹyin eto-pato. BSP kan n pese agbegbe asiko asiko sọfitiwia ti a ṣe adani fun ero isise kan ninu eto ohun elo ero isise Nios V kan.
The Quartus Prime software provides Nios V Board Support Package Editor and niosv-bsp utility tools to modify settings that control the behavior of the BSP.
A BSP contains the following elements: · Hardware abstraction layer · Device drivers · Optional software packages · Optional real-time operating system
3.1.2. Application Project
A Nios V C/C++ application project has the following features: · Consists of a collection of source code and a CMakeLists.txt.
— CMakeLists.txt ṣe akopọ koodu orisun ati so pọ pẹlu BSP kan ati ọkan tabi diẹ sii awọn ile-ikawe yiyan, lati ṣẹda ọkan .elf file
· One of the source files ni akọkọ iṣẹ (). Pẹlu koodu ti o pe awọn iṣẹ ni awọn ile-ikawe ati awọn BSPs.
Altera provides niosv-app utility tool in the Quartus Prime software utility tools to create the Application CMakeLists.txt, and RiscFree IDE for Altera FPGAs to modify the source code in an Eclipse-based environment.
3.2. Awọn Irinṣẹ Idagbasoke Altera FPGA
The Nios V processor supports the following tools for software development: · Graphical User Interface (GUI) – Graphical development tools that are available in
mejeeji Windows* ati Lainos* Awọn ọna ṣiṣe (OS). - Nios V Board Support Package Olootu (Nios V BSP Olootu) - Ashling RiscFree IDE fun Altera FPGAs · Command-Line Tools (CLI) - Awọn irinṣẹ idagbasoke ti o bẹrẹ lati Nios V Command Shell. Ọpa kọọkan n pese iwe ti ara rẹ ni irisi iranlọwọ ti o wa lati laini aṣẹ. Ṣii ikarahun aṣẹ Nios V ki o tẹ aṣẹ wọnyi: - iranlọwọ view the Help menu. — Nios V Utilities Tools — File Awọn irinṣẹ Iyipada ọna kika - Awọn Irinṣẹ Ohun elo miiran

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Table 25. GUI Tools and Command-line Tools Tasks Summary

Iṣẹ-ṣiṣe

GUI Ọpa

Command-line Tool

Ṣiṣẹda BSP kan

Nios V BSP Editor

· In Quartus Prime Pro Edition software: niosv-bsp -c -s=<.qsys file> -t=<bsp type> [OPTIONS] settings.bsp
· In Quartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t= Awọn eto [Awọn aṣayan].bsp

Ṣiṣẹda BSP kan nipa lilo .bsp ti o wa file
Nmu imudojuiwọn BSP kan

Nios V BSP Olootu Nios V BSP Olootu

niosv-bsp -g [OPTIONS] settings.bsp niosv-bsp -u [OPTIONS] settings.bsp

Examining a BSP

Nios V BSP Editor

niosv-bsp -q -E=<tcl script> [OPTIONS] settings.bsp

Creating an application

–

niosv-app -a=<application directory> -b=<bsp directory> -s=<source files directory> [OPTIONS]

Ṣiṣẹda a olumulo ìkàwé

–

niosv-app -l= -s= files liana> -p= [Awọn aṣayan]

Modifying an application Modifying a user library Building an application

RiscFree IDE fun Altera FPGAs
RiscFree IDE fun Altera FPGAs
RiscFree IDE fun Altera FPGAs

Eyikeyi olootu orisun laini aṣẹ
Eyikeyi olootu orisun laini aṣẹ
· make · cmake

Building a user library

RiscFree IDE fun Altera FPGAs

· make · cmake

Gbigba ohun elo ELF kan
Converting the .elf file

RiscFree IDE fun Altera FPGAs
–

niosv-download
· elf2flash · elf2hex

Alaye ti o jọmọ
Ashling RiscFree Integrated Development Environment (IDE) for Altera FPGAs User Guide

3.2.1. Nios V Processor Board Support Package Editor
You can use the Nios V processor BSP Editor to perform the following tasks: · Create or modify a Nios V processor BSP project · Edit settings, linker regions, and section mappings · Select software packages and device drivers.
The capabilities of the BSP Editor include the capabilities of the niosv-bsp utilities. Any project created in the BSP Editor can also be created using the command-line utilities.

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Akiyesi:

For Quartus Prime Standard Edition software, refer to AN 980: Nios V Processor Quartus Prime Software Support for the steps to invoke the BSP Editor GUI.

To launch the BSP Editor, follow these steps: 1. Open Platform Designer, and navigate to the File akojọ aṣayan.
a. To open an existing BSP setting file, click Open… b. To create a new BSP, click New BSP… 2. Select the BSP Editor tab and provide the appropriate details.

Figure 27. Launch BSP Editor

Related Information AN 980: Nios V Processor Quartus Prime Software Support
3.2.2. RiscFree IDE fun Altera FPGAs
The RiscFree IDE for Altera FPGAs is an Eclipse-based IDE for the Nios V processor. Altera recommends that you develop the Nios V processor software in this IDE for the following reasons: · The features are developed and verified to be compatible with the Nios V
isise Kọ sisan. · Ni ipese pẹlu gbogbo awọn irinṣẹ irinṣẹ pataki ati awọn irinṣẹ atilẹyin eyiti o fun ọ laaye
to easily start Nios V processor development.
Alaye ti o jọmọ Ashling RiscFree Integrated Development Environment (IDE) fun Itọsọna olumulo Altera FPGAs
3.2.3. Nios V Awọn irinṣẹ Awọn ohun elo
You can create, modify, and build Nios V programs with commands typed at a command line or embedded in a script. The Nios V command-line tools described in this section are in the <Intel Quartus Prime software installation directory>/niosv/bin directory.

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Table 26. Nios V Awọn irinṣẹ Awọn ohun elo

Command-Line Tools

Lakotan

niosv-app niosv-bsp niosv-download niosv-shell niosv-stack-report

Lati ṣe ipilẹṣẹ ati tunto iṣẹ akanṣe kan.
To create or update a BSP settings file and create the BSP files. Lati ṣe igbasilẹ ELF file to a Nios® V processor.
To open the Nios V Command Shell. To inform you of the left-over memory space available to your application .elf for stack or heap usage.

3.2.4. File Format Conversion Tools

File format conversion is sometimes necessary when passing data from one utility to another. The file awọn irinṣẹ iyipada ọna kika wa ninu
liana fifi sori software>/niosv/bin liana.

Tabili 27. File Format Conversion Tools

Awọn irinṣẹ Laini Aṣẹ elf2flash elf2hex

Lakotan Lati tumọ .elf file to .srec kika fun filasi iranti siseto. Lati tumọ .elf file to .hex format for memory initialization.

3.2.5. Awọn Irinṣẹ Ohun elo miiran

You might require the following command-line tools when building a Nios V processor based system. These command-line tools are either provided by Intel in <Intel Quartus Prime installation directory>/quartus/bin or acquired from
open-source tools.

Table 28. Other Command-Line Tools

Command-Line Tools

Iru

Lakotan

juart-ebute

Intel-provided

Lati ṣe atẹle stdout ati stderr, ati lati pese igbewọle si ero isise Nios® V
subsystem through stdin. This tool only applies to the JTAG UART IP when it is connected to the Nios® V processor.

ìmọocd

Intel-provided To execute OpenOCD.

openocd-cfg-gen

Ti pese Intel · Lati ṣe agbekalẹ iṣeto OpenOCD file. · Lati ṣafihan JTAG pq ẹrọ atọka.

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4. Nios V Processor Configuration and Booting Solutions
You can configure the Nios V processor to boot and execute software from different memory locations. The boot memory is the Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), or Tightly Coupled Memory (TCM).
Alaye ti o jọmọ · Awọn ipo Nfa agbara-soke loju iwe 193 · Awọn okunfa agbara-soke
For more information about power-up triggers.
4.1. Ifihan
The Nios V processor supports two types of boot processes: · Execute-in-Place (XIP) using alt_load() function · Program copied to RAM using boot copier. The Nios V embedded programs development is based on the hardware abstraction layer (HAL). The HAL provides a small boot loader program (also known as boot copier) that copies relevant linker sections from the boot memory to their run time location at boot time. You can specify the program and data memory run time locations by manipulating the Board Support Package (BSP) Editor settings. This section describes: · Nios V processor boot copier that boots your Nios V processor system according to
awọn aṣayan iranti bata · Nios V isise booting awọn aṣayan ati gbogbo sisan · Nios V siseto solusan fun awọn ti a ti yan bata iranti
4.2. Awọn ohun elo asopọ
When you generate the Nios V processor project, the BSP Editor generates two linker related files: · linker.x: The linker pipaṣẹ file that the generated application’s makefile nlo
to create the .elf binary file. · linker.h: Contains information about the linker memory layout. All linker setting modifications you make to the BSP project affect the contents of these two linker files. Every Nios V processor application contains the following linker sections:
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

4. Nios V Processor Configuration and Booting Solutions 726952 | 2025.07.16

Table 29. Linker Sections

.ọrọ

Linker Sections

.rodata

.rwdata

.bss

.heap

.stack

Descriptions Executable code. Any read-only data used in the execution of the program. Stores read-write data used in the execution of the program. Contains uninitialized static data. Contains dynamically allocated memory. Stores function-call parameters and other temporary data.

O le ṣafikun awọn apakan ọna asopọ afikun si .elf file to hold custom code and data. These linker sections are placed in named memory regions, defined to correspond with physical memory devices and addresses. By default, BSP Editor automatically generates these linker sections. However, you can control the linker sections for a particular application.

4.2.1. Iwa asopọ
This section describes the BSP Editor default linking behavior and how to control the linking behavior.

4.2.1.1. Asopọmọra BSP aiyipada
Lakoko iṣeto BSP, awọn irinṣẹ ṣe awọn igbesẹ wọnyi laifọwọyi:
1. Fi awọn orukọ agbegbe iranti: Fi orukọ kan si ẹrọ iranti eto kọọkan ki o ṣafikun orukọ kọọkan si ọna asopọ file bi agbegbe iranti.
2. Find largest memory: Identify the largest read-and-write memory region in the linker file.
3. Assign linker sections: Place the default linker sections (.text, .rodata, .rwdata, .bss, .heap, and .stack) in the memory region identified in the previous step.
4. Kọ files: Write the linker.x and linker.h files.
Ni deede, ero ipin apakan ọna asopọ ṣiṣẹ lakoko ilana idagbasoke sọfitiwia nitori pe ohun elo naa jẹ iṣeduro lati ṣiṣẹ ti iranti ba tobi to.
The rules for the default linking behavior are contained in the Altera-generated Tcl scripts bsp-set-defaults.tcl and bsp-linker-utils.tcl found in the <Intel Quartus Prime installation directory>/niosv/scripts/bsp-defaults directory. The niosv-bsp command invokes these scripts. Do not modify these scripts directly.

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4.2.1.2. Asopọmọra BSP atunto
O le ṣakoso ihuwasi sisopọ aiyipada ni taabu Afọwọkọ Linker ti Olootu BSP. Ṣe afọwọyi iwe afọwọkọ ọna asopọ ni lilo awọn ọna wọnyi: · Fi agbegbe iranti kun: Ṣe maapu orukọ agbegbe iranti si ẹrọ iranti ti ara. Ṣafikun aworan agbaye: Ṣe maapu orukọ apakan si agbegbe iranti kan. BSP
Editor allows you to view the memory map before and after making changes.

4.3. Nios V Processor Booting Methods

There are a few methods to boot up the Nios V processor in Altera FPGA devices. The methods to boot up Nios V processor vary according to the flash memory selection and device families.

Table 30. Supported Flash Memories with Respective Boot Options

Awọn iranti Boot atilẹyin

Ẹrọ

On-Chip Flash (for Internal configuration)

Awọn ẹrọ 10 ti o pọju nikan (pẹlu On-Chip Flash IP)

General Purpose QSPI Flash (for user data only)

All supported FPGA devices (with Generic Serial Flash Interface FPGA IP)

Configuration QSPI Flash (for Active Serial configuration)

Control block-based
devices (with Generic
Serial Flash Interface Intel FPGA IP)(2)

Nios V Prosessor Booting Awọn ọna

Application Runtime Location

Copier bata

Nios V processor application executein-place from On-Chip Flash

Filaṣi On-Chip (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load() function

Ohun elo ero isise Nios V daakọ lati On-Chip Filaṣi si Ramu ni lilo adakọ bata

OCRAM/External RAM

Reusing Bootloader via GSFI

Nios V processor application executein-place from general purpose QSPI flash

Idi gbogbogbo QSPI filasi (XIP) + OCRAM/ Ramu ita (fun awọn apakan data kikọ)

alt_load() function

Ohun elo ero isise Nios V daakọ lati idi gbogbogbo QSPI filasi si Ramu ni lilo adakọ bata

OCRAM/External RAM

Bootloader nipasẹ GSFI

Nios V isise elo executein-ibi lati iṣeto ni QSPI filasi

Iṣeto ni QSPI filasi (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load() function

Nios V processor application copied from configuration QSPI flash to RAM using boot copier

OCRAM/ Bootloader Ramu ti ita nipasẹ GSFI tẹsiwaju…

(2) Tọkasi AN 980: Nios V Processor Quartus Prime Software Atilẹyin fun atokọ ẹrọ.

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Awọn iranti Boot atilẹyin
On-chip Memory (OCRAM) Tightly Coupled Memory (TCM)

Ẹrọ
SDM-based devices (with Mailbox Client Intel FPGA IP). (2)
All supported Altera FPGA devices (2)
All supported Altera FPGA devices(2)

Nios V Prosessor Booting Awọn ọna
Nios V processor application copied from configuration QSPI flash to RAM using boot copier
Nios V processor application executein-place from OCRAM
Nios V processor application executein-place from TCM

Application Runtime Location

Copier bata

OCRAM/ External RAM Bootloader via SDM

OCRAM

alt_load() function

Instruction TCM (XIP) None + Data TCM (for writable data sections)

Figure 28. Nios V Processor Boot Flow

Tunto

Awọn ero isise fo lati tun fekito (ibẹrẹ koodu bata)

Application code may be copied to another memory location (depending on boot options)
Boot code initializes the processor

Depending on boot options, the boot code may copy initial values for data/code to another memory space (alt_load)
Koodu bata bẹrẹ koodu ohun elo ati aaye iranti data
Koodu bata bẹrẹ gbogbo awọn agbeegbe eto pẹlu awọn awakọ HAL (alt_main)
Entry to main
Alaye jẹmọ · Generic Serial Flash Interface Altera FPGA IP Itọsọna olumulo
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Onibara Apoti ifiweranṣẹ Altera FPGA IP Itọsọna olumulo · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Ifihan si Nios V Processor Booting Awọn ọna
Nios V processor systems require the software images to be configured in system memory before the processor can begin executing the application program. Refer to Linker Sections for the default linker sections.
The BSP Editor generates a linker script that performs the following functions: · Ensures that the processor software is linked in accordance with the linker settings
of the BSP editor and determines where the software resides in memory. · Positions the processor’s code region in the memory component according to the
sọtọ iranti irinše.
The following section briefly describes the available Nios V processor booting methods.
4.4.1. Ohun elo Nios V Processor Execute-Ni-Place lati Boot Flash
Altera designed the flash controllers such that the boot flash address space is immediately accessible to the Nios V processor upon system reset, without the need to initialize the memory controller or memory devices. This enables the Nios V processor to execute application code stored on the boot devices directly without using a boot copier to copy the code to another memory type. The flash controllers are: · On-Chip Flash with On-Chip Flash IP (only in MAX® 10 device) · General purpose QSPI flash with Generic Serial Flash Interface IP · Configuration QSPI flash with Generic Serial Flash Interface IP (except MAX 10
awọn ẹrọ)
When the Nios V processor application execute-in-place from boot flash, the BSP Editor performs the following functions: · Sets the .text linker sections to the boot flash memory region. · Sets the .bss,.rodata, .rwdata, .stack and .heap linker sections to the RAM
agbegbe iranti. O gbọdọ mu iṣẹ alt_load () ṣiṣẹ ni Eto BSP lati daakọ awọn apakan data (.rodata, .rwdata,, .awọn imukuro) si Ramu lori ipilẹ eto. Awọn koodu apakan (.ọrọ) si maa wa ni bata filasi iranti ekun.
Alaye ti o jọmọ · Generic Serial Flash Interface Altera FPGA IP Itọsọna Olumulo · Altera MAX 10 Olumulo Filaṣi Iranti Itọsọna olumulo
4.4.1.1. alt_load()
You can enable the alt_load() function in the HAL code using the BSP Editor.
Nigbati o ba lo ni ṣiṣiṣẹ bata-ni-ibi, iṣẹ alt_load () ṣe awọn iṣẹ ṣiṣe wọnyi:

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· Ṣiṣẹ bi adakọ bata kekere ti o daakọ awọn apakan iranti si Ramu ti o da lori awọn eto BSP.
· Awọn ẹda data apakan (.rodata, .rwdata, .awọn imukuro) si Ramu ṣugbọn kii ṣe awọn apakan koodu (.ọrọ) apakan koodu (.ọrọ) apakan jẹ apakan kika-nikan ati pe o wa ni agbegbe iranti filasi booting. Pipin yii ṣe iranlọwọ lati dinku lilo Ramu ṣugbọn o le ṣe idinwo iṣẹ ṣiṣe koodu nitori awọn iraye si iranti filasi losokepupo ju awọn iraye si Ramu on-chip.

The following table lists the BSP Editor settings and functions:

Table 31. BSP Editor Eto
BSP Editor Setting hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Function Enables alt_load() function. alt_load() copies .rodata section to RAM. alt_load() copies .rwdata section to RAM. alt_load() copies .exceptions section to RAM.

4.4.2. Nios V Processor Application Copied from Boot Flash to RAM Using Boot Copier
Awọn ero isise Nios V ati HAL pẹlu adakọ bata ti o pese iṣẹ ṣiṣe to fun pupọ julọ awọn ohun elo ero isise Nios V ati pe o rọrun lati ṣe pẹlu ṣiṣan idagbasoke sọfitiwia Nios V.
Nigbati ohun elo ba nlo adakọ bata, o ṣeto gbogbo awọn apakan asopọ (.ọrọ, .heap, .rwdata, .rodata, .bss, .stack) si Ramu inu tabi ita. Lilo aladakọ bata lati daakọ ohun elo ero isise Nios V lati filasi bata si Ramu inu tabi ita fun ipaniyan ṣe iranlọwọ lati mu ilọsiwaju iṣẹ ṣiṣe ṣiṣẹ.
For this boot option, the Nios V processor starts executing the boot copier software upon system reset. The software copies the application from the boot flash to the internal or external RAM. Once the process is complete, the Nios V processor transfers the program control over to the application.

Akiyesi:

If the boot copier is in flash, then the alt_load() function does not need to be called because they both serve the same purpose.

4.4.2.1. Nios V Prosessor Bootloader nipasẹ Generic Serial Flash Interface
The Bootloader via GSFI is the Nios V processor boot copier that supports QSPI flash memory in control block-based devices. The Bootloader via GSFI includes the following features:
· Wa ohun elo software ni iranti ti kii ṣe iyipada.
· Unpacks and copies the software application image to RAM.
· Yipada ipaniyan ero isise laifọwọyi si koodu ohun elo ni Ramu lẹhin ti ẹda ti pari.

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The boot image is located right after the boot copier. You need to ensure the Nios V processor reset offset points to the start of the boot copier. The Figure: Memory Map for QSPI Flash with Bootloader via GSFI memory map for QSPI Flash with Bootloader via GSFI shows the flash memory map for QSPI flash when using a boot copier. This memory map assumes the flash memory memory stores the FPGA image and the application software.

Table 32. Bootloader nipasẹ GSFI fun Nios V Processor mojuto

Nios V isise mojuto
Nios V/m processor

Bootloader nipasẹ GSFI File Ipo
<Intel Quartus Installation Directory>/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/awọn paati/bootloader/ niosv_g_bootloader.srec

Figure 29. Memory Map for QSPI Flash with Bootloader via GSFI

Customer Data (*.hex)

Koodu elo

Akiyesi:

Tun Vector aiṣedeede

Copier bata

0x01E00000

Aworan FPGA (*.sof)

0x00000000

1. At the start of the memory map is the FPGA image followed by your data, which consists of boot copier and application code.
2. O gbọdọ ṣeto aiṣedeede atunto ero isise Nios V ni Platform Designer ati tọka si ibẹrẹ ti adakọ bata.
3. The size of the FPGA image is unknown.You can only know the exact size after the Quartus Prime project compilation. You must determine an upper bound for the size of the Altera FPGA image. For example, if the size of the FPGA image is estimated to be less than 0x01E00000, set the Reset Offset to 0x01E00000 in Platform Designer, which is also the start of the boot copier.
4. A good design practice consists of setting the reset vector offset at a flash sector boundary to ensure no partial erase of the FPGA image occurs in case the software application is updated.

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4.4.2.2. Nios V Processor Bootloader via Secure Device Manager
Bootloader nipasẹ Oluṣakoso Ẹrọ Aabo (SDM) jẹ koodu ohun elo HAL kan ti o nlo Olubara Apoti ifiweranṣẹ Altera FPGA IP HAL awakọ fun sisọ ero isise. Altera ṣeduro ohun elo bootloader yii nigba lilo iṣeto QSPI filasi ni awọn ẹrọ orisun SDM lati bata ero isise Nios V.
Upon system reset, the Nios V processor first boots the Bootloader via SDM from a tiny on-chip memory and executes the Bootloader via SDM to communicate with the configuration QSPI flash using the Mailbox Client IP.
The Bootloader via SDM performs the following tasks: · Locates the Nios V software in the configuration QSPI flash. · Copies the Nios V software into the on-chip RAM or external RAM. · Switches the processor execution to the Nios V software within the on-chip RAM or
Ramu ita.
Ni kete ti ilana naa ti pari, Bootloader nipasẹ SDM gbigbe eto iṣakoso lori ohun elo olumulo. Altera ṣeduro agbari iranti bi a ti ṣe ilana ni Igbimọ Iranti fun Bootloader nipasẹ SDM.
Figure 30. Bootloader via SDM Process Flow

Iṣeto ni

Filaṣi

Nios V Software

SDM

SDM-Based FPGA Device

Mailbox Client IP

FPGA Logic Nios V

4 External RAM
Nios V Software

Lori-Chip 4

EMIF

Àgbo

On-Chip Iranti

Nios V

Software

Bootloader nipasẹ SDM

1. Nios V processor runs the Bootloader via SDM from the on-chip memory.
2. Bootloader via SDM communicates with the configuration flash and locates the Nios V software.
3. Bootloader via SDM copies the Nios V software from the Configuration Flash into on-chip RAM / external RAM.
4. Bootloader nipasẹ SDM yipada ipaniyan ero isise Nios V si sọfitiwia Nios V ninu Ramu on-chip / Ramu ita.

4.4.3. Nios V Processor Application Execute-In-Place from OCRAM
In this method, the Nios V processor reset address is set to the base address of the on-chip memory (OCRAM). The application binary (.hex) file ti wa ni ti kojọpọ sinu OCRAM nigbati FPGA ti wa ni tunto, lẹhin ti awọn hardware oniru ti wa ni compiled ninu Quartus Prime software. Ni kete ti ero isise Nios V tun bẹrẹ, ohun elo naa bẹrẹ ṣiṣe ati awọn ẹka si aaye titẹsi.

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Akiyesi:

· Execute-In-Place from OCRAM does not require boot copier because Nios V processor application is already in place at system reset.
· Altera recommends enabling alt_load() for this booting method so that the embedded software behaves identically when reset without reconfiguring the FPGA device image.
O gbọdọ mu iṣẹ alt_load () ṣiṣẹ ni Eto BSP lati daakọ apakan .rwdata lori ipilẹ eto. Ni ọna yii, awọn iye akọkọ fun awọn oniyipada ipilẹṣẹ ti wa ni ipamọ lọtọ lati awọn oniyipada ti o baamu lati yago fun atunkọ lori ipaniyan eto.

4.4.4. Ohun elo Nios V Processor Execute-In-Place lati TCM
The execute-in-place method sets the Nios V processor reset address to the base address of the tightly coupled memory (TCM). The application binary (.hex) file is loaded into the TCM when you configure the FPGA after you compile the hardware design in the Quartus Prime software. Once the Nios V processor resets, the application begins executing and branches to the entry point.

Akiyesi:

Execute-In-Place from TCM does not require boot copier because Nios V processor application is already in place at system reset.

4.5. Nios V Processor Booting from On-Chip Flash (UFM)

Nios V processor booting and executing software from on-chip flash (UFM) is available in MAX 10 FPGA devices. The Nios V processor supports the following two boot options using On-Chip Flash under Internal Configuration mode:
· Nios V processor application executes in-place from On-Chip Flash.
· Nios V processor application is copied from On-Chip Flash to RAM using boot copier.

Table 33. Atilẹyin Flash Memories pẹlu oniwun Boot Aw

Awọn iranti Boot atilẹyin

Nios V Booting Methods

Application Runtime Location

Copier bata

Awọn ohun elo MAX 10 nikan (pẹlu OnChip Flash IP)

Nios V processor application executein-place from On-Chip Flash
Ohun elo ero isise Nios V daakọ lati On-Chip Filaṣi si Ramu ni lilo adakọ bata

Filaṣi On-Chip (XIP) + OCRAM / Ramu ita (fun awọn apakan data kikọ)

alt_load() function

OCRAM / Ramu ita

Reusing Bootloader via GSFI

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Olusin 31.

Apẹrẹ, Iṣeto ni, ati Booting Sisan
Apẹrẹ · Ṣẹda iṣẹ akanṣe orisun Nios V Processor rẹ nipa lilo Apẹrẹ Platform. · Rii daju wipe o wa ni ita Ramu tabi lori-chip Ramu ninu awọn eto oniru.

FPGA Configuration and Compilation
Ṣeto ipo iṣeto inu inu kanna ni On-chip Flash IP ni Platform Designer ati Quartus Prime software. Ṣeto aṣoju atunto ero isise Nios V si Filaṣi On-chip. Yan ọna ibẹrẹ UFM ti o fẹ. · Ṣe agbekalẹ apẹrẹ rẹ ni Apẹrẹ Platform. · Ṣe akojọpọ iṣẹ akanṣe rẹ ni sọfitiwia Prime Prime.

Ohun elo olumulo BSP Project · Ṣẹda Nios V isise HAL BSP da lori .sopcinfo file da nipa Platform onise. Ṣatunkọ Nios V ero isise BSP eto ati Linker Script ni BSP Olootu. · Ṣe ipilẹṣẹ iṣẹ akanṣe BSP.
User Application APP Project · Develop Nios V processor application code. · Compile Nios V processor application and generate Nios V processor application (.hex) file. Ṣe atunkopọ iṣẹ akanṣe rẹ ni sọfitiwia Prime Minister ti o ba ṣayẹwo Bibẹrẹ aṣayan akoonu iranti ni Intel FPGA On-Chip Flash IP.

Siseto Files Conversion, Download and Run · Generate the On-Chip Flash .pof file using Convert Programming Files feature in Quartus Prime software.
· Program the .pof file sinu rẹ MAX 10 ẹrọ. · Power ọmọ rẹ hardware.
4.5.1. MAX 10 FPGA On-Chip Flash Description
MAX 10 FPGA devices contain on-chip flash that is segmented into two parts: · Configuration Flash Memory (CFM) — stores the hardware configuration data for
MAX 10 FPGAs. · User Flash Memory (UFM) — stores the user data or software applications.
Itumọ UFM ti ẹrọ MAX 10 jẹ apapo awọn IPs rirọ ati lile. O le wọle si UFM nikan ni lilo On-Chip Flash IP Core ni sọfitiwia Quartus Prime.
On-chip Filaṣi IP mojuto ṣe atilẹyin awọn ẹya wọnyi: · Ka tabi kọ awọn iraye si UFM ati CFM (ti o ba ṣiṣẹ ni Oluṣeto Platform)
using the Avalon MM data and control slave interface. · Supports page erase, sector erase and sector write. · Simulation model for UFM read/write accesses using various EDA simulation tools.

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Table 34. Lori-chip Flash awọn ẹkun ni MAX 10 FPGA Devices

Flash Regions

Iṣẹ ṣiṣe

Configuration Flash Memory (sectors CFM0-2)

FPGA iṣeto ni file ibi ipamọ

Iranti Filaṣi olumulo (awọn apakan UFM0-1)

Nios V processor application and user data

Awọn ẹrọ MAX 10 FPGA ṣe atilẹyin ọpọlọpọ awọn ipo atunto ati diẹ ninu awọn ipo wọnyi gba CFM1 ati CFM2 laaye lati lo bi agbegbe UFM afikun. Tabili ti o tẹle n ṣe afihan ipo ibi ipamọ ti awọn aworan iṣeto ni FPGA ti o da lori awọn ipo iṣeto MAX 10 FPGA.

Table 35. Ibi ipamọ ti awọn aworan iṣeto ni FPGA

Ipo Iṣeto ni Awọn aworan fisinuirindigbindigbin Meji

CFM2 Compressed Image 2

CFM1

CFM0 Compressed Image 1

Aworan ti ko fisinu kan

Virtual UFM

Aworan ti ko ni titẹ

Single uncompressed image with Memory Initialization

Uncompressed image (with pre-initialized on-chip memory content)

Single compressed image with Memory Initialization Compressed image (with pre-initialized on-chip memory content)

Nikan fisinuirindigbindigbin aworan

Virtual UFM

Aworan Fisinu

O gbọdọ lo On-chip Flash IP mojuto lati wọle si iranti filasi ni Max 10 FPGAs. O le ese ati so On-chip Flash IP si sọfitiwia Prime Minister Quartus. Nios V asọ ti mojuto ero isise nlo Platform Designer interconnects lati baraẹnisọrọ pẹlu On-chip Flash IP.
olusin 32. Asopọ laarin On-chip Flash IP ati Nios V Processor

Akiyesi:

Rii daju pe ibudo Csr Flash On-chip ti sopọ si data_manager ero isise Nios V lati jẹ ki ero isise naa le ṣakoso kikọ ati paarẹ awọn iṣẹ rẹ.
On-chip Flash IP mojuto le pese iraye si awọn apa filasi marun - UFM0, UFM1, CFM0, CFM1, ati CFM2.
Important information about the UFM and CFM sectors.: · CFM sectors are intended for configuration (bitstream) data (*.pof) storage.
· Awọn data olumulo le wa ni ipamọ ni awọn apa UFM ati pe o le farapamọ, ti o ba yan awọn eto to pe ni irinṣẹ Onise Platform.
· Certain devices do not have a UFM1 sector. You can refer to the table: UFM and CFM Sector Size for available sectors in each individual MAX 10 FPGA device.

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· You can configure CFM2 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
· You can configure CFM2 and CFM1 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
Iwọn ti eka kọọkan yatọ pẹlu awọn ẹrọ MAX 10 FPGA ti a yan.

Tabili 36.

UFM and CFM Sector Size
Tabili yii ṣe atokọ awọn iwọn ti awọn ọna UFM ati CFM.

Ẹrọ

Pages per Sector

UFM1 UFM0 CFM2 CFM1 CFM0

Iwọn oju-iwe (Kbit)

O pọju olumulo
Flash Memory Size (Kbit) (3)

Total Configuration Memory Size (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

Iwọn OCRAM (Kbit)
108 189 378 549 675 1260 1638

Alaye ti o jọmọ · MAX 10 Itọsọna Olumulo Iṣeto ni FPGA · Altera MAX 10 Itọsọna Olumulo Iranti Filaṣi olumulo olumulo

4.5.2. Nios V Processor Application Execute-In-Place lati UFM

The Execute-In-Place from UFM solution is suitable for Nios V processor applications which require limited on-chip memory usage. The alt_load() function operates as a mini boot copier that copies the data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM based on the BSP settings. The code section (.text),
eyi ti o jẹ a kika nikan apakan, si maa wa ni MAX 10 Lori-chip Flash iranti ekun. Iṣeto yii dinku lilo Ramu ṣugbọn o le ṣe idinwo iṣẹ ṣiṣe koodu bi iraye si iranti filasi ti lọra ju Ramu on-chip lọ.

The Nios V processor application is programmed into the UFM sector. The Nios V processor’s reset vector points to the UFM base address to execute code from the UFM after the system resets.

If you are using the source-level debugger to debug your application, you must use a hardware breakpoint. This is because the UFM does not support random memory access, which is necessary for soft breakpoint debugging.

Akiyesi:

O ko le parẹ tabi kọ UFM lakoko ṣiṣe ṣiṣe-ni-ibi ni MAX 10. Yipada si ọna iṣagbekọ bata ti o ba nilo lati nu tabi kọ UFM naa.

(3) Awọn ti o pọju ti ṣee ṣe iye, eyi ti o jẹ ti o gbẹkẹle lori awọn iṣeto ni mode ti o yan.

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olusin 33. Nios V Processor elo XIP lati UFM

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

Filaṣi On-Chip

CFM

Nios V Hardware

UFM

Nios V Software

Iṣeto inu inu

On-Chip Flash IP

FPGA kannaa
Nios V isise

On-Chip RAM

Ita

Àgbo

EMIF

4.5.2.1. Hardware Design Flow
The following section describes a step-by-step method for building a bootable system for a Nios V processor application from On-Chip Flash. The example isalẹ wa ni itumọ ti lilo MAX 10 ẹrọ.
Awọn Eto paati IP
1. Ṣẹda iṣẹ ero isise Nios V rẹ nipa lilo Quartus Prime ati Onise Platform. 2. Rii daju Ramu ita tabi On-Chip Memory (OCRAM) ti wa ni afikun si rẹ Platform
Designer system.

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Aworan 34. Eksample IP Connections in Platform Designer for Booting Nios V from OnChip Flash (UFM)

3. Ninu oluṣatunṣe paramita IP Filaṣi On-Chip, ṣeto Ipo Iṣeto si ọkan ninu awọn atẹle, ni ibamu si ààyò apẹrẹ rẹ: · Aworan Ti a ko fisinuirindigbindigbin · Aworan Fisinuirindigbindigbin Kan · Aworan Kanṣoṣo pẹlu Ibẹrẹ Iranti · Aworan Fisinu pẹlu Ibẹrẹ Iranti
Fun alaye diẹ sii nipa Awọn aworan Fisinuirindigbindigbin Meji, tọka si Itọsọna olumulo Iṣeto MAX 10 FPGA - Igbesoke Eto Latọna jijin.

Akiyesi:

You must assign Hidden Access to every CFM regions in the On-Chip Flash IP.

Figure 35. Configuration Mode Selection in On-Chip Flash Parameter Editor

On-Chip Flash IP Settings – UFM Initialization You can choose one of the following methods according to your preference:

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Akiyesi:

The steps in the subsequent subchapters (Software Design Flow and Programming) depend on the selection you make here.

· Method 1: Initialize the UFM data in the SOF during compilation
Quartus Prime includes the UFM initialization data in the SOF during compilation. SOF recompilation is needed if there are changes in the UFM data.
1. Check Initialize flash content and Enable non-default initialization file.

Figure 36. Initialize Flash Contents and Enable Non-default Initialization File

2. Pato ọna ti ipilẹṣẹ .hex file (from the elf2hex command) in the User created hex or mif file.
Figure 37. Adding the .hex File Ona

· Ọna 2: Darapọ data UFM pẹlu SOF ti a ṣajọpọ lakoko iran POF
Awọn data UFM ti ni idapo pẹlu SOF ti o ṣajọ nigbati o ba n yi siseto pada files. O ko nilo lati tun SOF ṣe, paapaa ti data UFM ba yipada. Lakoko idagbasoke, o ko ni lati ṣajọpọ SOF files for changes in the application. Alterarecommends this method for application developers.
1. Ṣiṣayẹwo Bibẹrẹ akoonu filasi.
Figure 38. Initialize Flash Content with Non-default Initialization File

Reset Agent Settings for Nios V Processor Execute-In-Place Method
1. In the Nios V processor parameter editor, set the Reset Agent to On-Chip Flash.
Nọmba 39. Awọn Eto Olootu Parameter Processor Nios V pẹlu Atunto Aṣoju Ṣeto si Filaṣi On-Chip

2. Click Generate HDL when the Generation dialog box appears. 3. Specify output file generation options and click Generate.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Click OK to exit the Device and Pin Options window,
3. Tẹ O DARA lati jade ni Device window.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Akiyesi:

If the configuration mode setting in Quartus Prime software and Platform Designer parameter editor is different, the Quartus Prime project fails with the following error message.

Olusin 41.

Error Message for Different Configuration Mode Setting Error (14740): Configuration mode on atom “q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block|ufm_block” does not match the project setting. Update and regenerate the Qsys system to match the project setting.

Related Information MAX 10 FPGA Configuration User Guide

4.5.2.2. Software Design Flow
Abala yii n pese ṣiṣan apẹrẹ lati ṣe ipilẹṣẹ ati kọ iṣẹ sọfitiwia ero isise Nios V. Lati rii daju ṣiṣan kikọ ṣiṣanwọle, o gba ọ niyanju lati ṣẹda igi ilana ti o jọra ninu iṣẹ akanṣe rẹ. Ṣiṣan apẹrẹ sọfitiwia atẹle yii da lori igi liana yii.
To create the software project directory tree, follow these steps: 1. In your design project folder, create a folder called software. 2. In the software folder, create two folders called hal_app and hal_bsp.
Figure 42. Software Project Directory Tree

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Creating the Application BSP Project
Lati ṣe ifilọlẹ Olootu BSP, tẹle awọn igbesẹ wọnyi: 1. Tẹ Nios V Command Shell sii. 2. Pe Olootu BSP pẹlu aṣẹ niosv-bsp-editor. 3. Ni BSP Olootu, tẹ File New BSP to start your BSP project. 4. Configure the following settings:
· SOPC Alaye File name: Provide the SOPCINFO file (.sopcinfo). · CPU name: Select Nios V processor. · Operating system: Select the operating system of the Nios V processor. · Version: Leave as default. · BSP target directory: Select the directory path of the BSP project. You can
pre-set it at <Project directory>/software/hal_bsp by enabling Use default locations. · BSP Settings File name: Type the name of the BSP Settings File. · Additional Tcl scripts: Provide a BSP Tcl script by enabling Enable Additional Tcl script. 5. Click OK.
Figure 43. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Yipada siseto Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Eto
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file iyipada.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Akiyesi:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

Ramu ita
Nios V Software

Filaṣi On-Chip

CFM

Nios V Hardwa

Awọn iwe aṣẹ / Awọn orisun

altera Nios V Embedded Processor [pdf] Itọsọna olumulo
Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

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Itọsọna olumulo

altera Nios V Embedded Processor

Awọn pato

Nios V Processor Hardware System Design

Nios V Processor Software System Design

Nios V Processor Configuration and Booting Solutions

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