altera Nios V Embedded processor User Guide

About the Nios® V Embedded Processor
1.1. Altera® FPGA uye Embedded processors Pamusoroview
Altera FPGA zvishandiso zvinogona kuita logic inoshanda seyakazara microprocessor uku ichipa akawanda sarudzo.
Musiyano wakakosha pakati pe discrete microprocessors uye Altera FPGA ndewekuti Altera FPGA jira harina pfungwa kana richiita simba. Iyo Nios® V processor ndeye yakapfava yenjere pfuma (IP) processor yakavakirwa pane iyo RISC-V yakatarwa. Usati wamhanyisa software pane Nios V processor yakavakirwa system, iwe unofanirwa kugadzirisa iyo Altera FPGA mudziyo une hardware dhizaini ine Nios V processor. Iwe unogona kuisa iyo Nios V processor chero kupi paAltera FPGA, zvichienderana nezvinodiwa zvedhizaini.

Kuti ugonese yako Altera® FPGA IP-yakavakirwa embedded system kuti iite se discrete microprocessor-based system, system yako inofanira kusanganisira zvinotevera: · AJ.TAG interface yekutsigira Altera FPGA kumisikidzwa, Hardware uye software
debugging · Simba-up Altera FPGA kumisikidza michina
Kana sisitimu yako iine hunyanzvi uhu, unogona kutanga kukwenenzvera dhizaini yako kubva kune yakatemerwa hardware dhizaini yakarodha muAltera FPGA. Kushandisa Altera FPGA zvakare inobvumidza iwe kuti uchinje dhizaini yako nekukurumidza kugadzirisa matambudziko kana kuwedzera mashandiro matsva. Unogona kuyedza aya madhizaini matsva nyore nekugadzirisa iyo Altera FPGA uchishandisa yako system's JTAG interface.
Iye JTAG interface inotsigira Hardware uye software kuvandudza. Unogona kuita mabasa anotevera uchishandisa JTAG interface: · Gadzirisa iyo Altera FPGA · Dhawunirodha uye debug software · Taurirana neAltera FPGA kuburikidza neUART-senge interface (JTAG UART
terminal) · Debug hardware (ine Signal Tap yakamisikidzwa logic analyzer) · Chirongwa flash memory
Mushure mekugadzirisa iyo Altera FPGA ine Nios V processor-yakavakirwa dhizaini, iyo software yekuvandudza inoyerera yakafanana nekuyerera kwe discrete microcontroller dhizaini.

Ruzivo Rwakabatana · AN 985: Nios V processor Tutorial
Yekukurumidza kutanga gwara nezve kugadzira iri nyore Nios V processor system uye kumhanyisa iyo Hello World application.
© Altera Corporation. Altera, iyo Altera logo, iyo `a' logo, uye mamwe maAltera mamaki zviratidzo zveAltera Corporation. Altera inochengetedza kodzero yekuita shanduko kune chero zvigadzirwa uye masevhisi chero nguva pasina chiziviso. Altera haatore mutoro kana mutoro unobva mukushandisa kana kushandisa chero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neAltera. Vatengi veAltera vanorayirwa kuti vatore yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba neruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

1. About the Nios® V Embedded processor 726952 | 2025.07.16
· Nios V processor Reference Manual Inopa ruzivo nezve Nios V processor mabhenji mabhenji, processor architecture, modhi yepurogiramu, uye musimboti kuita.
· Embedded Peripherals IP User Guide · Nios V Processor Software Developer Handbook

Inotsanangura Nios V processor software yekuvandudza nharaunda, maturusi aripo, uye maitiro ekuvaka software kuti ishande paNios V processor. · Ashling* RiscFree* Yakabatanidzwa Yekuvandudza Nzvimbo (IDE) yeAltera FPGAs Mushandisi Gadhi Inotsanangura iyo RiscFree* yakasanganiswa budiriro nharaunda (IDE) yeAltera FPGAs Arm*-yakavakirwa HPS uye Nios V core processor. · Nios V processor Altera FPGA IP Release Notes
1.2. Quartus® Prime Software Tsigiro
Nios V processor kuvaka kuyerera kwakasiyana kune Quartus® Prime Pro Edition software uye Quartus Prime Standard Edition software. Tarisa kune AN 980: Nios V processor Quartus Prime Software Tsigiro kuti uwane rumwe ruzivo nezve misiyano.
Ruzivo Rwakabatana AN 980: Nios V processor Quartus Prime Software Tsigiro
1.3. Nios V processor Licensing
Imwe neimwe Nios V processor musiyano ine kiyi yayo yerezinesi. Kana wangowana kiyi rezinesi, unogona kushandisa imwechete rezinesi kiyi kune ese Nios V processor mapurojekiti kusvika zuva rekupera. Iwe unogona kuwana iyo Nios V processor Altera FPGA IP marezinesi ne zero mutengo.
Iyo Nios V processor rezinesi kiyi runyorwa inowanikwa muAltera FPGA Self-Service Licensing Center. Dzvanya iyo Sign up for Evaluation kana Yemahara License tebhu, uye sarudza dzinoenderana sarudzo kuti uite chikumbiro.
Mufananidzo 1. Altera FPGA Self-Service Licensing Center

Nemakiyi erezinesi, unogona:
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* Shandisa Nios V processor mukati mehurongwa hwako. · Tevedzera maitiro eNios V processor system. · Simbisa kushanda kwedhizaini, senge saizi nekumhanya. · Gadzira dhizaini hurongwa files. · Ronga mudziyo uye simbisa dhizaini muhardware.
Iwe haudi rezinesi rekugadzira software muAshling * RiscFree * IDE yeAltera FPGAs.
Ruzivo rwunoenderana · Altera FPGA Self-Service Licensing Center
Kuti uwane rumwe ruzivo nezve kutora iyo Nios V processor Altera FPGA IP rezinesi makiyi. · Altera FPGA Kuisirwa uye Kupihwa Marezenisi Kuti uwane rumwe ruzivo nezve kubvumidza iyo Altera FPGA software uye kumisikidza rezinesi rakagadziriswa uye network rezinesi server.
1.4. Embedded System Dhizaini
Iyi inotevera nhamba inoratidza yakarerutswa Nios V processor yakavakirwa system dhizaini kuyerera, kusanganisira zvese zviri zviviri Hardware uye software kuvandudza.

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Mufananidzo 2.

Nios V processor System Dhizaini Inoyerera
System Concept

Ongorora System Zvinodiwa

Nios® V
processor Cores uye Standard Zvikamu

Tsanangura uye Gadzira System mukati
Platform Designer

Hardware Flow: Batanidza uye Gadzira Intel Quartus Prime Project

Kuyerera kweSoftware: Gadzira uye Vaka Nios V Proposal Software

Hardware Flow: Dhawunirodha FPGA Dhizaini
kune Target Board

Kuyerera kweSoftware: Kuedza uye Debug Nios V processor Software

Software Hapana Inosangana Zvakasiyana?
Ehe
Hardware Hapana Meets Spec? Ehe
System Yakakwana

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2. Nios V Processor Hardware System Dhizaini neQuartus Prime Software uye Platform Designer

Mufananidzo 3.

Iyo inotevera dhizaini inoratidza yakajairwa Nios V processor hardware dhizaini. Nios V processor System Hardware Dhizaini Flow

Tanga

Nios V Cores uye Yakajairwa Zvikamu

Shandisa Platform Dhizaini Kugadzira iyo Nios V Yakavakirwa System
Gadzira Platform Dhizaini Dhizaini

Batanidza Platform Dhizaini System neIntel Quartus Prime Project
Govera Pini Nzvimbo, Nguva Inodiwa, uye zvimwe Zvipingamupinyi Zvekugadzira
Gadzira Hardware yeTarget Chishandiso muIntel Quartus Prime

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2.1. Kugadzira Nios V processor System Dhizaini nePlatform Dhizaini
Iyo Quartus Prime software inosanganisira Platform Dhizaini system yekubatanidza chishandiso inorerutsa basa rekutsanangura nekubatanidza Nios V processor IP musimboti uye mamwe maIP muAltera FPGA system dhizaini. Iyo Platform Dhizaini inogadzira otomatiki yekubatanidza logic kubva kune yakatsanangurwa yepamusoro-level yekubatanidza. Iyo yekubatanidza otomatiki inobvisa iro rinotora nguva basa rekutsanangura system-level HDL yekubatanidza.
© Altera Corporation. Altera, iyo Altera logo, iyo `a' logo, uye mamwe maAltera mamaki zviratidzo zveAltera Corporation. Altera inochengetedza kodzero yekuita shanduko kune chero zvigadzirwa uye masevhisi chero nguva pasina chiziviso. Altera haatore mutoro kana mutoro unobva mukushandisa kana kushandisa chero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neAltera. Vatengi veAltera vanorayirwa kuti vatore yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba neruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

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Mushure mekuongorora iyo system hardware zvinodiwa, unoshandisa Quartus Prime kutsanangura iyo Nios V processor musimboti, ndangariro, uye zvimwe zvinhu zvaunoda system yako. Iyo Platform Dhizaini inogadzira otomatiki iyo yekubatanidza logic yekubatanidza zvinhu zviri muhardware system.

2.1.1. Instantiating Nios V processor Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

Iyo IP musimboti we processor yega yega inotsigira akasiyana ekugadzirisa sarudzo zvichienderana neyakasiyana dhizaini. Iwe unogona kutsanangura izvi zvigadziriso kuti zvienderane zviri nani nedhizaini yako.

Tafura 1.

Kugadzirisa Sarudzo Pakati peCore Variants

Kugadzirisa Sarudzo

Nios V/c processor

Nios V/m processor

Debug Shandisa Reset Chikumbiro

—

Misungo, Kunze, uye Kuvhiringidza

CPU Architecture

ECC

Caches, Peripheral Regions uye TCMs

—

Tsika Mirayiridzo

—

Lockstep

—

Nios V/g processor

2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Mufananidzo 4. Nios V/c Compact Microcontroller Altera FPGA IP

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2.1.1.1.1. CPU Architecture Tab

Tafura 2.

CPU Architecture Tab

Feature

Tsanangudzo

Gonesa Avalon® Interface Inogonesa Avalon Interface yekuraira maneja uye data maneja. Kana yakaremara, iyo system inoshandisa AXI4-Lite interface.

mhartid CSR kukosha

·Iyo isiriyo IP sarudzo. · Usashandise mhartid CSR kukosha muNios V/c processor.

2.1.1.1.2. Shandisa Reset Chikumbiro Tab

Tafura 3.

Shandisa Reset Chikumbiro Tab Parameter

Shandisa Reset Chikumbiro Tab

Tsanangudzo

Wedzera Reset Chikumbiro Interface

· Ita kuti sarudzo iyi ibudise pachena zviteshi zvepamusha panogona kushandiswa natenzi wepanzvimbo kukonzeresa Nios V processor kuti igadzirise pasina kukanganisa zvimwe zvikamu muNios V processor system.
· Iyo reset interface ine yekuisa retreq siginecha uye inobuda ack chiratidzo.
· Unogona kukumbira kusetwazve kuNios V processor core nekusimbisa chiratidzo che retreq.
· Iyo retreq siginecha inofanirwa kuramba yakasimbiswa kudzamara processor yataura ack chiratidzo. Kutadza kuti chiratidzo chirambe chakatsinhirwa chinogona kukonzera kuti processor ive munzvimbo isiri-inotemesa.
· Iyo Nios V processor inopindura kuti reset yakabudirira nekusimbisa ack chiratidzo.
· Mushure mekunge processor yanyatso gadziridzwa, chirevo cheiyo ack chiratidzo chinogona kuitika kakawanda nguva nenguva kudzamara de-kusimbisa kwechiratidzo che retreq.

2.1.1.1.3. Misungo, Kunze, uye Inovhiringidza Tab

Tafura 4.

Misungo, Kunze, uye Inokanganisa Tab Paramita

Misungo, Kunze, uye Kuvhiringidza

Tsanangudzo

Reset Agent

Reset Offset

• Inotsanangura kudzikiswa kweiyo reset vector inoenderana neakasarudzwa kero yebhesi yemumiririri. · Platform Dhizaini inopa otomatiki kukosha kweiyo reset offset.

Cherechedza:

Platform Designer inopa Mhedziso sarudzo, iyo inokutendera kuti utaure kero yakakwana muReset Offset. Shandisa iyi sarudzo kana ndangariro inochengeta reset vector iri kunze kwe processor system uye subsystems.

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2.1.1.1.4. ECC Tab

Tafura 5.

ECC Tab

ECC

Gonesa Kuonekwa Kwemhosho uye Mamiriro Ekubika

Tsanangudzo
· Gonesa iyi sarudzo yekushandisa ECC chimiro cheNios V processor yemukati RAM zvidhinha. · ECC maficha anoona anosvika maviri-bits zvikanganiso uye anoita zvinoenderana neanotevera maitiro:
- Kana chiri chikanganiso chinogadziriswa 1-bit, processor inoramba ichishanda mushure mekugadzirisa chikanganiso mupombi yeprosesa. Zvisinei, ruramiso yacho hairatidziri mumabviro endangariro.
- Kana iko kukanganisa kusiri kurongeka, processor inoramba ichishanda isina kuigadzirisa mupombi ye processor uye sosi ndangariro, izvo zvinogona kuita kuti processor ipinde munzvimbo isingaite.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Mufananidzo 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Debug Tab

Tafura 6.

Debug Tab Parameters

Debug Tab

Tsanangudzo

Enesa Debug
Bvisa Reset kubva kuDebug Module

· Gonesa iyi sarudzo kuwedzera iyo JTAG chinangwa chekubatanidza module kune iyo Nios V processor. · Iye JTAG target yekubatanidza module inobvumira kubatanidza kune Nios V processor kuburikidza neiyo
JTAG interface mapini eFPGA. · Iyo yekubatanidza inopa anotevera ekutanga kugona:
- Tanga uye misa Nios V processor - Ongorora uye gadzirisa marejista uye ndangariro. - Dhawunirodha Nios V application .elf file kune processor memory panguva yekumhanya kuburikidza
niosv-download. - Debug iyo application inoshanda paNios V processor · Batanidza dm_agent port kune processor kuraira uye data bhazi. Ita shuwa kuti kero yekutanga pakati pemabhazi ese akafanana.
· Ita kuti sarudzo iyi ibudise pachena dbg_reset_out uye ndm_reset_in ports. ·JTAG debugger kana niosv-download -r command inokonzeresa iyo dbg_reset_out, iyo
inobvumira iyo Nios V processor kuti igadzirisezve masisitimu ekubatanidza kune iyi chiteshi. · Iwe unofanirwa kubatanidza iyo dbg_reset_out interface kune ndm_reset_in pane kugadzirisa patsva.
interface yekukonzeresa kuseta kune processor core uye timer module. Haufanire kubatanidza dbg_reset_out interface kuti ugadzirise chimiro kudzivirira maitiro asina kusimba.

2.1.1.2.2. Shandisa Reset Chikumbiro Tab

Tafura 7.

Shandisa Reset Chikumbiro Tab Parameter

Shandisa Reset Chikumbiro Tab

Tsanangudzo

Wedzera Reset Chikumbiro Interface

· Ita kuti sarudzo iyi ibudise pachena zviteshi zvepamusha panogona kushandiswa natenzi wepanzvimbo kukonzeresa Nios V processor kuti igadzirise pasina kukanganisa zvimwe zvikamu muNios V processor system.
· Iyo reset interface ine yekuisa retreq siginecha uye inobuda ack chiratidzo.
· Unogona kukumbira kusetwazve kuNios V processor core nekusimbisa chiratidzo che retreq.
· Iyo retreq siginecha inofanirwa kuramba yakasimbiswa kudzamara processor yataura ack chiratidzo. Kutadza kuti chiratidzo chirambe chakatsinhirwa chinogona kukonzera kuti processor ive munzvimbo isiri-inotemesa.
· Kusimbisa kweiyo resetreq siginecha mune debug modhi haina mhedzisiro pane processor mamiriro.
· Iyo Nios V processor inopindura kuti reset yakabudirira nekusimbisa ack chiratidzo.
· Mushure mekunge processor yanyatso gadziridzwa, chirevo cheiyo ack chiratidzo chinogona kuitika kakawanda nguva nenguva kudzamara de-kusimbisa kwechiratidzo che retreq.

2.1.1.2.3. Misungo, Kunze, uye Inovhiringidza Tab

Tafura 8.

Misungo, Kunze, uye Inovhiringidza Tab

Tsanangudzo

Reset Agent

Reset Offset Interrupt Mode

• Inotsanangura kudzikiswa kweiyo reset vector inoenderana neakasarudzwa kero yebhesi yemumiririri. · Platform Dhizaini inopa otomatiki kukosha kweiyo reset offset.
Taurai mhando yekukanganisa controller ingave Direct kana Vectored. Ongorora: Iyo Nios V/m isiri-pombi processor haitsigire Vectored inovhiringidza.
Naizvozvo, dzivisa kushandisa iyo Vectored interrupt mode kana processor iri muNonpipelined mode.

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Cherechedza:

2.1.1.2.4. CPU Architecture

Tafura 9.

CPU Architecture Tab Parameters

CPU Architecture

Tsanangudzo

Gonesa Pipelining muCPU

· Gonesa iyi sarudzo yekusimbisa pombi yeNios V/m processor. - IPC yakakwira pamutengo wepamusoro logic nzvimbo uye yakaderera Fmax frequency.
· Dzima iyi sarudzo yekumisikidza isina-pombi Nios V/m processor. -Ine yakafanana musimboti kuita seNios V/c processor. - Inotsigira kugadzirisa uye kukanganisa kugona - Yakaderera logic nzvimbo uye yakakwirira Fmax frequency pamutengo wepasi IPC.

Gonesa Avalon Interface

Inogonesa Avalon Interface yekuraira maneja uye data maneja. Kana yakaremara, iyo system inoshandisa AXI4-Lite interface.

mhartid CSR kukosha

· Hart ID rejista (mhartid) kukosha ndeye 0 pa default. · Ipa kukosha pakati pe0 ne4094. · Inoenderana neAltera FPGA Avalon Mutex Core HAL API.

Ruzivo Rwakamisikidzwa Peripheral IP User Guide - Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Tab
Tafura 10. ECC Tab
ECC Gonesa Kukanganisa Kuonekwa uye Mamiriro Ekubika

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2.1.1.3. Instantiating Nios V/g General Chinangwa Processor Altera FPGA IP
Mufananidzo 6. Nios V / g General Chinangwa Processor Altera FPGA IP - Chikamu 1

Mufananidzo 7.

Nios V/g General Chinangwa processor Altera FPGA IP - Chikamu 2 (Dzima Gonesa Core Level Kukanganisa Controller)

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Mufananidzo 8.

Nios V/g General Chinangwa processor Altera FPGA IP - Chikamu 2 (Batidza Gonesa Core Level Kukanganisa Controller)

Mufananidzo 9. Nios V / g General Chinangwa Processor Altera FPGA IP - Chikamu 3

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Mufananidzo 10. Nios V / g General Chinangwa Processor Altera FPGA IP - Chikamu 4

2.1.1.3.1. CPU Architecture

Tafura 11. CPU Architecture Parameters

CPU Architecture Tab Gonesa Inoyangarara Point Unit

Tsanangudzo Gonesa iyi sarudzo kuti uwedzere inoyangarara-point unit ("F" yekuwedzera) mucore processor.

Gonesa Kufanotaura kweBazi

Gonesa static bazi rekufungidzira (Kumashure Kwatorwa uye Pamberi Hakusi Kutorwa) kune mirairo yebazi.

mhartid CSR kukosha

· Hart ID rejista (mhartid) kukosha ndeye 0 pa default. · Ipa kukosha pakati pe0 ne4094. · Inoenderana neAltera FPGA Avalon Mutex Core HAL API.

Dzima FSQRT & FDIV mirairo yeFPU

Bvisa inoyangarara-nzvimbo square midzi (FSQRT) uye inoyangarara-point division (FDIV) mashandiro muFPU.
· Isa software emulation pane ese ari maviri mirairo panguva yekumhanya.

Ruzivo Rwakamisikidzwa Peripheral IP User Guide - Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. Debug Tab

Tafura 12. Debug Tab Parameters

Debug Tab

Tsanangudzo

Enesa Debug
Bvisa Reset kubva kuDebug Module

2.1.1.3.3. Lockstep Tab Table 13. Lockstep Tab
Parameters Inogonesa Lockstep Default Timeout Period Gonesa Yakawedzerwa Reset Interface

Tsanangudzo · Gonesa iyo mbiri core Lockstep system. · Default value ye programmable timeout pakubuda patsva (pakati pe0 ne255). · Gonesa sarudzo Yakawedzerwa Reset Interface yeYakawedzerwa Reset Control. Kana yaremara, fRSmartComp inoshandisa Basic Reset Control.

2.1.1.3.4. Shandisa Reset Chikumbiro Tab

Tafura 14. Shandisa Reset Chikumbiro Tab Parameter

Shandisa Reset Chikumbiro Tab

Tsanangudzo

Wedzera Reset Chikumbiro Interface

· Ita kuti sarudzo iyi ibudise pachena zviteshi zvepamusha panogona kushandiswa natenzi wepanzvimbo kukonzeresa Nios V processor kuti igadzirise pasina kukanganisa zvimwe zvikamu muNios V processor system.
· Iyo reset interface ine yekuisa retreq siginecha uye inobuda ack chiratidzo.
· Unogona kukumbira kusetwazve kuNios V processor core nekusimbisa chiratidzo che retreq.
· Iyo retreq siginecha inofanirwa kuramba yakasimbiswa kudzamara processor yataura ack chiratidzo. Kutadza kuti chiratidzo chirambe chakatsinhirwa chinogona kukonzera kuti processor ive munzvimbo isiri-inotemesa.
· Kusimbisa kweiyo resetreq siginecha mune debug modhi haina mhedzisiro pane processor mamiriro.
· Iyo Nios V processor inopindura kuti reset yakabudirira nekusimbisa ack chiratidzo.
· Mushure mekunge processor yanyatso gadziridzwa, chirevo cheiyo ack chiratidzo chinogona kuitika kakawanda nguva nenguva kudzamara de-kusimbisa kwechiratidzo che retreq.

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2.1.1.3.5. Misungo, Kunze, uye Inovhiringidza Tab

Tafura 15.

Misungo, Kunze, uye Inovhiringidza Tab kana Inogonesa Core Level Kukanganisa Controller yakadzimwa

Misungo, Kunze, uye Inovhiringidza Tab
Reset Agent

Tsanangudzo
· Iyo ndangariro inobata reset vector (iyo Nios V processor reset kero) panogara kodhi reset.
· Unogona kusarudza chero memory module yakabatana neNios V processor yekuraira tenzi uye inotsigirwa neNios V processor bhutsu inoyerera semumiriri wekugadzirisa.

Reset Offset

• Inotsanangura kudzikiswa kweiyo reset vector inoenderana neakasarudzwa kero yebhesi yemumiririri. · Platform Dhizaini inopa otomatiki kukosha kweiyo reset offset.

Gonesa Core Level Interrupt Controller (CLIC)

· Bvumira CLIC kuti itsigire pre-emptive kukanganisa uye inogadziriswa yekukanganisa inokonzeresa mamiriro.
· Kana wagoneswa, unogona kugadzirisa huwandu hwekuvhiringidza kwepuratifomu, kuseta mamiriro ezvinokonzeresa, uye sarudza zvimwe zvekuvhiringidza se pre-emptive.

Kuvhiringidza Mode Shadow Register Files

Rondedzera mhando dzekuvhiringidza seYakananga, kana Vectored Gonesa shadow rejista kuti uderedze shanduko yemamiriro ekukanganisa.

Tafura 16.

Misungo, Kunze uye Kuvhiringidza kana Inogonesa Core Level Kukanganisa Controller yakavhurwa

Misungo, Kunze, uye Kuvhiringidza

Tsanangudzo

Reset Agent
Reset Offset
Gonesa Core Level Interrupt Controller (CLIC)

· Iyo ndangariro inobata reset vector (iyo Nios V processor reset kero) panogara kodhi reset.
· Unogona kusarudza chero memory module yakabatana neNios V processor yekuraira tenzi uye inotsigirwa neNios V processor bhutsu inoyerera semumiriri wekugadzirisa.
• Inotsanangura kudzikiswa kweiyo reset vector inoenderana neakasarudzwa kero yebhesi yemumiririri. · Platform Dhizaini inopa otomatiki kukosha kweiyo reset offset.
· Bvumira CLIC kuti itsigire pre-emptive kukanganisa uye inogadziriswa yekukanganisa inokonzeresa mamiriro. · Kana yagoneswa, unogona kugadzirisa huwandu hwekukanganisa kwepuratifomu, kuseta mamiriro ekutangisa,
uye sarudza dzimwe dzedzodzo sedzinotangira.

Kukanganisa Mode

* Rondedzera mhando dzekuvhiringidza seYakananga, Vectored, kana CLIC.

Shadow Register Files

· Gonesa shadow register kuti uderedze kuchinjika kwemamiriro ekuvhiringidza.
· Inopa nzira mbiri:
- Nhamba yeCLIC inovhiringidza mazinga
- Nhamba yeCLIC inokanganisa mazinga - 1: Iyi sarudzo inobatsira kana iwe uchida nhamba yerejista file makopi kuti akwane muhuwandu chaihwo hweM20K kana M9K mabhuroko.
· Gonesa iyo Nios V processor kushandisa mumvuri regisita files izvo zvinoderedza kuchinjika kwechinyorwa pamusoro pekuvhiringidza.
Kuti uwane rumwe ruzivo nezve shadow register files, tarisa kuNios V processor Reference Manual.

Nhamba yePlatform inovhiringidza masosi

· Inotsanangura huwandu hwekukanganisa kwepuratifomu pakati pe16 kusvika 2048.
Ongorora: CLIC inotsigira anosvika 2064 kuvhiringa mapipu, uye ekutanga gumi nematanhatu ekukanganisa mapipu akabatanidzwa zvakare kune yekutanga kukanganisa controller.

CLIC Vector Tafura Alignment

· Yakatemerwa otomatiki zvichienderana nehuwandu hwepuratifomu inovhiringidza masosi. · Kana ukashandisa kurongeka kuri pazasi pemutengo unokurudzirwa, iyo CLIC inowedzera pfungwa
kuoma nekuwedzera imwe adder kuita vectoring calculations. · Kana iwe ukashandisa kurongeka kuri pasi pemutengo unokurudzirwa, izvi zvinoguma nekuwedzera
logic kuoma muCLIC.
akaenderera…

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Misungo, Kunze, uye Kuvhiringidza
Nhamba Yekukanganisa Ma Level
Nhamba Yekukanganisa Zvinokosha padanho
Configurable inovhiringidza polarity Tsigira mupendero yakakonzera kukanganisa

Tsanangudzo
· Inotsanangura huwandu hwematanho ekukanganisa ane imwe nhanho yekuwedzera 0 yekodhi yekushandisa. Kuvhiringidza kwemwero wepamusoro kunogona kukanganisa (pre-empt) chibatiso chinomhanya chedanho repasi.
· Nezvisina-zero zvinokanganisa mazinga seyo chete sarudzo dzekuvhiringidza, kodhi yekushandisa inogara iri padanho rakaderera 0. Cherechedza: Run-time configuration yenhanho yekuvhiringidza uye kukosha kunoitwa mune imwechete 8-bit rejisita. Kana huwandu hwekuvhiringidza mazinga ari 256, hazvigoneke kugadzirisa iyo yekukanganisa yekutanga panguva yekumhanya-nguva. Zvikasadaro, huwandu hwepamusoro hwezvinhu zvinogadziriswa zvinonyanya kukosha ndeye 256 / (nhamba yekukanganisa mazinga - 1).
• Inotsanangura nhamba yezvinodanwa zvinonyanya kukosha, izvo zvinoshandiswa neCLIC kuona marongero anoitwa vabatiki vasina pre-empting vanodaidzwa. Cherechedzo: Concatenation yemabhinari emhando yakasarudzwa yekukanganisa uye yakasarudzwa yekukanganisa yakakosha inofanirwa kuve isingasviki 8 bits.
· Inokutendera kuti ugadzirise kukanganisa polarity panguva yekumhanya. • Default polarity ndeye positive polarity.
· Inokutendera kuti ugadzirise chinokonzeresa chinokanganisa panguva yekumhanya, kureva chepamusoro-soro chinokonzeresa kana chinonaka-mupendero chakonzereswa (kana kukanganisa polarity kuri kwakanaka mu Configurable interrupt polarity).
· Default trigger mamiriro idanho rakakonzeresa kukanganisa.

Cherechedza:

Ruzivo Rwakabatana Nios® V processor Reference Manual

2.1.1.3.6. Memory Configurations Tab

Tafura 17. Memory Configuration Tab Parameters

Category

Memory Configuration Tab

Tsanangudzo

Caches

Data Cache size

· Inotsanangura saizi yedata cache. · Saizi dzinoshanda dzinobva pa0 kilobytes (KB) kusvika pa16 KB. Dzima cache yedata kana saizi iri 0 KB.

Murairo Cache Size

· Inotsanangura saizi yedzidziso cache. · Saizi dzinoshanda dzinobva pa0 KB kusvika pa16 KB. · Dzima cache yekuraira kana saizi iri 0 KB.

Peripheral Region A uye B

Size

• Inotsanangura saizi yedunhu renharaunda.
· Saizi dzinoshanda dzinobva pa64 KB kusvika pa2 gigabytes (GB), kana Hapana. Kusarudza Hapana kunodzima nharaunda yekutenderera.

Base Address

· Inotsanangura kero yekutanga yedunhu renharaunda mushure mekusarudza saizi.
* Kero dzese dziri munharaunda inotenderedza dzinoburitsa zvisingagoneke kuwana data.
· Peripheral region base address inofanirwa kuenderana nesaizi yedunhu.

Ndangariro Dzakabatana

Size

· Inotsanangura saizi yendangariro yakabatana-yakasimba. - Saizi dzinoshanda dzinobva pa0 MB kusvika pa512 MB.

Base Kero Kutanga File

· Inotsanangura kero yekutanga yendangariro dzakasimba-dzakabatana. · Inotsanangura yekutanga file yendangariro yakabatana-yakasimba.

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Cherechedza:

MuNios V processor system ine cache inogoneswa, iwe unofanirwa kuisa masisitimu ekutenderera mukati medunhu redunhu. Iwe unogona kushandisa matunhu ekutenderera kutsanangura isinga-cacheable transaction yemaperipherals akadai UART, PIO, DMA, nevamwe.

2.1.1.3.7. ECC Tab

Tafura 18. ECC Tab
ECC Gonesa Kukanganisa Kuonekwa uye Mamiriro Ekubika
Gonesa Single Bit Kururamisa

Tsanangudzo
· Gonesa iyi sarudzo yekushandisa ECC chimiro cheNios V processor yemukati RAM zvidhinha. · ECC maficha anoona anosvika maviri-bits zvikanganiso uye anoita zvinoenderana neanotevera maitiro:
- Kana chiri chikanganiso chimwechete chinogadziriswa uye Gonesa Imwechete Bit Correction yakadzimwa, processor inoramba ichishanda mushure mekugadzirisa chikanganiso mupombi yeprosesa. Zvisinei, ruramiso yacho hairatidziri mumabviro endangariro.
- Kana chiri chikanganiso chimwechete chinogadziriswa uye Gonesa Imwechete Bit Correction yakabatidzwa, processor inoramba ichishanda mushure mekugadzirisa chikanganiso mupombi ye processor uye ndangariro dzinobva.
- Kana iri kukanganisa kusingagadziriswe, processor inomisa kushanda kwayo.
Gonesa imwe chete bhiti kururamisa pane akamisikidzwa memory block mukati mepakati.

2.1.1.3.8. Custom Instruction Tab

Cherechedza:

Iyi tebhu inowanikwa chete yeNios V/g processor core.

Tsika Murairo Nios V Tsika Yekuraira Hardware Interface Tafura
Nios V Tsika Yekuraira Software Macro Tafura

Tsanangudzo
· Nios V processor inoshandisa iyi tafura kutsanangudza yayo tsika yekuraira maneja nzvimbo.
· Yakatsanangurwa tsika yekuraira maneja maficha akaiswa encoded neOpcode (CUSTOM0-3) uye 3 bits efunc7[6:4].
· Unogona kutsanangura anosvika makumi matatu nemaviri ega ega kuraira maneja nzvimbo.
· Nios V processor inoshandisa iyi tafura inoshandiswa kutsanangura tsika yekuraira software encodings kune yakatsanangurwa tsika yekuraira maneja nzvimbo.
· Kune yega yega yakatsanangurwa tsika yekuraira software encoding, iyo Opcode (CUSTOM0-3) uye 3 bits efunc7[6:4] encoding inofanirwa kuenderana kune yakatsanangurwa tsika yekuraira maneja interface encoding muCustom Instruction Hardware Interface Table.
· Unogona kushandisa funct7[6:4], funct7[3:0], uye funct3[2:0] kutsanangura imwe encoding yemurayiridzo wetsika wakapihwa, kana kutsanangurwa semaXs kuti apiswe sedzimwe nharo dzemirayiridzo.
· Nios V processor inopa yakatsanangurwa tsika yekuraira software encodings seyakagadzirwa C-macros musystem.h, uye tevera R-mhando RISC-V yekuraira fomati.
· Mnemonics inogona kushandiswa kutsanangura mazita echivanhu e: — Iyo yakagadzirwa C-Macros musystem.h.
- Yakagadzirwa GDB debug mnemonics mucustom_instruction_debug.xml.

Related Information
AN 977: Nios V processor Custom Instruction Kuti uwane rumwe ruzivo nezve tsika mirairo iyo inokutendera iwe kugadzirisa iyo Nios® V processor kuti isangane nezvinodiwa zveimwe application.

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2.1.2. Kutsanangura System Component Dhizaini
Shandisa Platform Dhizaini kutsanangura maitiro emahara eiyo Nios V processor system uye wedzera mune zvaunoda zvikamu. Iyi dhayagiramu inotevera inoratidza yakakosha Nios V processor dhizaini ine zvinotevera zvikamu: · Nios V processor core · On-Chip Memory · JTAG UART · Nguva Yenguva (sarudzo)(1)
Kana nyowani On-Chip Memory yawedzerwa kuPlatform Dhizaini system, ita Sync System Infos kuratidza yakawedzera ndangariro zvikamu mukusetazve. Neimwe nzira, unogona kugonesa Auto Sync muPlatform Designer kuti iratidze otomatiki shanduko yechikamu
Mufananidzo 11. Example yekubatanidza yeNios V processor nemamwe maperipheral muPlatform Designer

(1) Iwe une sarudzo yekushandisa iyo Nios V Yemukati Timer maficha kutsiva yekunze Interval Timer muPlatform Designer.

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Iwe unofanirwawo kutsanangura mapini ekushanda ekutumira kunze senzira muPlatform Designer system yako. For example, yakakodzera FPGA system operation pini runyoro inotsanangurwa sepazasi asi isina kuganhurirwa ku:
· Wachi
· Reset
· I/O zviratidzo
2.1.3. Kudoma Base Kero uye Kukanganisa Chikumbiro Zvinokosha
Kuti utsanangure kuti zvikamu zvakawedzerwa mudhizaini zvinopindirana sei kugadzira sisitimu, unofanirwa kugovera kero dzekutanga kune yega yega chikamu chemumiririri uye nekupa kukanganisa chikumbiro (IRQ) zvekutanga zveJ.TAG UART uye nguva yenguva. Iyo Platform Dhizaini inopa murairo - Govera Base Kero - iyo inogovera otomatiki kero dzebhesi kune zvese zvikamu muhurongwa. Nekudaro, iwe unogona kugadzirisa mabhesi kero zvichienderana nezvaunoda.
Aya anotevera mamwe nhungamiro yekugovera base kero:
· Nios V processor core ine 32-bit kero span. Kuti uwane zvikamu zveagent, kero yavo yekutanga inofanira kubva pakati pe0x00000000 ne0xFFFFFFFF.
· Zvirongwa zveNios V zvinoshandisa zvimiro zvekufananidzira kureva kero. Haufanire kusarudza kero tsika dziri nyore kurangarira.
· Kero dzekero dzinosiyanisa zvikamu zvine chete-bit kero musiyano unoburitsa zvakanyanya kushanda zvakanaka. Iwe haufanirwe kubatanidza ese mabhesi kero mune diki diki kero renji nekuti compacting inogona kugadzira isingashande inoshanda.
· Platform Mugadziri haaedze kuenzanisa zvikamu zvendangariro zvakapatsanurwa mune inobatika ndangariro renji. For exampuye, kana iwe uchida akawanda On-Chip Memory zvikamu zvinogadziriswa seimwe contiguous memory renji, iwe unofanirwa kugovera zvakajeka base kero.
Platform Dhizaini inopawo otomatiki kuraira - Govera Kupindira Nhamba iyo inobatanidza IRQ masaini kuti abudise echokwadi hardware mhinduro. Nekudaro, kugovera maIRQs zvinobudirira kunoda kunzwisiswa kweyese system mhinduro maitiro. Platform Dhizaini haigone kuita fungidziro dzakadzidziswa nezve yakanakisa IRQ basa.
Iyo yakaderera IRQ kukosha ine yakanyanya kukosha. Mune yakanakira sisitimu, Altera inokurudzira kuti iyo timer chikamu ive nepamusoro pekutanga IRQ, kureva, iyo yakaderera kukosha, kuchengetedza huchokwadi hweiyo system clock tick.
Mune zvimwe zviitiko, iwe unogona kugovera chepamusoro pekutanga kune chaiyo nguva peripherals (senge vhidhiyo controller), iyo inoda yakakwira yekuvhiringidza mwero kupfuura zvikamu zvenguva.
Related Information
Quartus Prime Pro Edition Mushandisi Yekushandisa: Ruzivo rwakawanda nezve kugadzira Sisitimu ine Platform Dhizaini.

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2.2. Kubatanidza Platform Dhizaini System muQuartus Prime Project
Mushure mekugadzira iyo Nios V system dhizaini muPlatform Dhizaini, ita anotevera mabasa kubatanidza iyo Nios V system module muQuartus Prime FPGA dhizaini dhizaini. · Gadzirisa iyo Nios V system module muQuartus Prime project · Batanidza masiginecha kubva kuNios V system module kune mamwe masiginecha muFPGA logic · Govera mapini emuviri nzvimbo · Dzvinyirira iyo FPGA dhizaini.
2.2.1. Kusimbisa iyo Nios V processor System Module muQuartus Prime Project
Platform Dhizaini inogadzira system module dhizaini yaunogona kusimbisa muQuartus Prime. Maitiro aunoita sisitimu module zvinoenderana nedhizaini yekupinda nzira yeiyo yakazara Quartus Prime chirongwa. For example, kana wanga uchishandisa Verilog HDL yekupinda dhizaini, simbisa iyo Verilog yakavakirwa system module. Kana uchida kushandisa nzira yedhiyagiramu yebhuroka yekupinda dhizaini, isa chiratidzo chemodule system .bdf file.
2.2.2. Kubatanidza Zvikwangwani uye Kugovera Nzvimbo dzePini Yenyama
Kuti ubatanidze dhizaini yako yeAltera FPGA kune yako bhodhi-level dhizaini, ita mabasa anotevera: · Ziva iyo yepamusoro-level file kuitira dhizaini yako uye masaini kuti abatanidze kune ekunze Altera
FPGA mudziyo pini. · Nzwisisa kuti ndeapi mapini ekubatanidza kuburikidza nebhodhi-level dhizaini yako mushandisi gwara kana
schematics. · Govera zvikwangwani mudhizaini yepamusoro-soro kumadoko pane yako Altera FPGA mudziyo une pini
assignment tools.
Yako Platform Dhizaini system inogona kuve yepamusoro dhizaini. Nekudaro, iyo Altera FPGA inogona zvakare kusanganisira yekuwedzera logic zvichienderana nezvido zvako uye nekudaro inosuma tsika yepamusoro-level. file. Iyo yepamusoro-nhanho file inobatanidza iyo Nios V processor system module masaini kune imwe Altera FPGA dhizaini dhizaini.
Ruzivo Rwakabatana Quartus Prime Pro Edition Mushandisi Gadhi: Dhizaini Zvipinganidzo
2.2.3. Kumanikidza iyo Altera FPGA Dhizaini
Iyo yakakodzera Altera FPGA sisitimu dhizaini inosanganisira zvipingamupinyi zvekugadzira kuona kuti dhizaini inosangana nekuvharwa kwenguva uye zvimwe zvinodiwa zvinomanikidza. Iwe unofanirwa kumanikidza yako Altera FPGA dhizaini kuti isangane nezvinodikanwa izvi zvakajeka uchishandisa maturusi akapihwa muQuartus Prime software kana wechitatu-bato EDA vanopa. Iyo Quartus Prime software inoshandisa iyo yakapihwa zvipingaidzo panguva yekubatanidza chikamu kuti iwane yakakwana yekuisa mhedzisiro.

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Ruzivo rwakabatana · Quartus Prime Pro Edition Mushandisi Wekushandisa: Dhizaini Zvipinganidzo · Wechitatu-bato EDA Partners · Quartus Prime Pro Edition Mushandisi Wekushandisa: Nguva Yekuongorora
2.3. Kugadzira Nios V processor Memory System
Ichi chikamu chinotsanangura maitiro akanakisa ekusarudza ndangariro zvishandiso muPlatform Designer yakamisikidzwa system ine Nios V processor uye kuwana optimum performance. Memory midziyo inoita basa rakakosha mukuvandudza kuita kwese kweiyo yakadzikwa system. Embedded system memory inochengetedza mirairo yechirongwa uye data.
2.3.1. Volatile Memory
Musiyano mukuru murudzi rwendangariro kushanduka. Volatile memory inongobata zvirimo iwe uchipa simba kune memory mudziyo. Paunongobvisa simba, chiyeuchidzo chinorasikirwa nezviri mukati maro.
Exampndangariro shoma shoma ndeye RAM, cache, uye marejista. Aya ndiwo anokurumidza ndangariro mhando anowedzera kumhanya kuita. Altera inokurudzira kuti utore uye uite Nios V processor mirairo mu RAM uye peya Nios V IP musimboti neOn-Chip Memory IP kana Yekunze Memory Interface IP kuti iite zvakakwana.
Kuti uvandudze mashandiro, unogona kubvisa zvimwe zvePlatform Designer adaptation nekufananidza Nios V processor data maneja mhando kana hupamhi nebhutsu RAM. For example, unogona kugadzirisa On-Chip Memory II ine 32-bits AXI-4 interface, inofanana neNios V data maneja interface.
Ruzivo Rwakabatana · Yekunze Memory Interfaces IP Support Center · On-Chip Memory (RAM kana ROM) Altera FPGA IP · On-Chip Memory II (RAM kana ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place kubva kuOCRAM papeji 54
2.3.1.1. On-Chip Memory Configuration RAM kana ROM
Iwe unogona kugadzirisa Altera FPGA On-Chip Memory IPs se RAM kana ROM. · RAM inopa kugona kuverenga nekunyora uye ine hunhu hwekusagadzikana. Kana uri
kubhura iyo Nios V processor kubva kuOn-Chip RAM, iwe unofanirwa kuve nechokwadi chebhoti yemukati inochengetedzwa uye haina kushatiswa muchiitiko chekugadzirisa panguva yekumhanya. · Kana Nios V processor iri kubhowa kubva kuROM, chero software bug paNios V processor haigone kunyora zvisizvo zviri mukati meOn-Chip Memory. Saka, kuderedza njodzi yehuori hwebhoti software.
Ruzivo Rwakabatana · On-Chip Memory (RAM kana ROM) Altera FPGA IP · On-Chip Memory II (RAM kana ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place kubva kuOCRAM papeji 54

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2.3.1.2. Caches
On-chip ndangariro dzinowanzo shandiswa kuita iyo cache mashandiro nekuda kwekuderera kwavo latency. Iyo Nios V processor inoshandisa pa-chip memory yekuraira kwayo uye data caches. Iko kushomeka kweiyo on-chip memory kazhinji haisi nyaya yemacache nekuti iwo anowanzo diki.
Caches inowanzoshandiswa pasi pemamiriro anotevera:
· Yenguva dzose ndangariro iri kure-chip uye ine nguva yakareba yekuwana kupfuura pane-chip memory.
· Zvikamu-zvakakosha zvikamu zvesoftware kodhi zvinogona kukwana mune yekuraira cache, kuvandudza mashandiro ehurongwa.
· The performance-critical, inonyanya kushandiswa chikamu che data inogona kukwana mu data cache, kuvandudza mashandiro ehurongwa.
Kugonesa cache muNios V processor inogadzira ndangariro hierarchy, iyo inoderedza ndangariro yekuwana nguva.
2.3.1.2.1. Peripheral region
Chero maperipherals akamisikidzwa IP, akadai seUART, I2C, uye SPI haifanirwe kuvharirwa. Cache inokurudzirwa zvakanyanya kune dzekunze ndangariro dzinokanganiswa nenguva yakareba yekuwana, nepo zvemukati pa-chip ndangariro dzinogona kusabatanidzwa nekuda kwenguva pfupi yekuwana. Iwe haufanirwe kuchengera chero yakadzamidzirwa yeperipheral IPs, senge UART, I2C, uye SPI, kunze kwendangariro. Izvi zvakakosha nekuti zviitiko kubva kumidziyo yekunze, senge maajenti ekugadzirisa maIP akapfava, haatorerwe ne processor cache, zvakare haana kugamuchirwa ne processor. Nekuda kweizvozvo, zviitiko izvi zvinogona kuenda zvisina kucherechedzwa kudzamara wabvisa cache, izvo zvinogona kutungamirira kumaitiro asina kutarisirwa muhurongwa hwako. Muchidimbu, iyo ndangariro-yakamepuwa dunhu reyakadzamidzirwa peripheral IPs haigoneke uye inofanirwa kugara mukati meiyo processor yedunhu.
Kuseta nharaunda yeperipheral, tevera matanho aya:
1. Vhura kero kero Mepu muPlatform Designer.
2. Enda kumepu yekero yeProsesa Instruction Manager uye Data Manager.
3. Ziva peripherals uye ndangariro muhurongwa hwako.
Mufananidzo 12. Example yeKero Mepu

Cherechedza: Miseve yebhuruu iri kunongedzera kundangariro. 4. Rongedza maperipherals:
a. Memory as cacheable b. Peripherals seisingagoneki

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Tafura 19. Cacheable uye Uncacheable Dunhu

Subordinate

Mepu Kero

Status

Peripheral Region

Size

Base Address

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 bytes N/A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 bytes (min size is 65536 bytes)

0x54000

sysid_qsys_0.control_slave

0x54080 ~ 0x54087

Uncacheable

uart.avalon_jtag_muranda

0x54088 ~ 0x5408f

Uncacheable

5. Gadzirisa matunhu ari pedyo nehukuru hwawo chaiwo:
· Zvekareample, kana saizi iri 65536 bytes, inoenderana ne0x10000 bytes. Naizvozvo, iyo kero yepasi inotenderwa inofanirwa kuve yakawanda ye0x10000.
· Iyo CPU.dm_agent inoshandisa base kero ye0x40000, inova yakawanda ye0x10000. Nekuda kweizvozvo, Peripheral Region A, ine saizi ye65536 bytes uye base kero ye0x40000, inosangana nezvinodiwa.
· Kero yekutanga yekuunganidzwa kwenzvimbo dzisingagoneki pa0x54000 haisi yakawanda ye0x10000. Iwe unofanirwa kuvapa zvakare ku0x60000 kana mamwe akawanda e0x10000. Saka, Peripheral Region B, ine saizi ye65536 bytes uye base kero ye0x60000, inogutsa maitiro.

Tafura 20. Cacheable uye Uncacheable Dunhu pamwe Reassignment

Subordinate

Mepu Kero

Status

Peripheral Region

Size

Base Address

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

Uncacheable 65536 bytes

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Cacheable

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Cacheable Uncacheable Uncacheable Uncacheable

144 bytes (min size is 65536 bytes)

0x60000

uart.avalon_jtag_muranda

0x60088 ~ 0x6008f

Uncacheable

2.3.1.3. Memory Akabatana
Ndangariro dzakasimba dzakabatanidzwa (TCMs) dzinoitwa uchishandisa on-chip memory sezvo yavo yakaderera latency inoita kuti vakwanise kuita basa racho. TCMs ndangariro dzakamepuwa mune yakajairika kero nzvimbo asi ine yakatsaurirwa interface kune microprocessor uye ine yakakwirira-kuita, yakaderera-latency zvimiro zvecache memory. TCM inopawo yakaderera interface kune wekunze muenzi. Iyo processor uye yekunze muenzi ane yakafanana mvumo nhanho yekubata iyo TCM.

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Cherechedza:

Kana iyo TCM yepasi chiteshi yakabatana kune yekunze mugamuchiri, inogona kuratidzwa ine imwe base kero pane iyo base kero yakapihwa mucore processor. Altera inokurudzira kuenzanisa kero dzese kune imwechete kukosha.

2.3.1.4. Yekunze Memory Interface (EMIF)
EMIF (External Memory Interface) inoshanda zvakafanana neSRAM (Static Random Access Memory), asi ine simba uye inoda kuzorodza nguva nenguva kuchengetedza zvirimo. Iwo ane simba masero endangariro muEMIF madiki zvakanyanya pane static memori masero muSRAM, izvo zvinoguma nehupamhi hwepamusoro uye yakaderera-inodhura ndangariro michina.
Pamusoro pezvinodiwa zvekuzorodza, EMIF ine chaiyo interface zvinodiwa izvo zvinowanzoda nyanzvi yekudzora hardware. Kusiyana neSRAM, iyo ine yakagadziriswa seti yekero mitsara, EMIF inoronga nzvimbo yayo yekurangarira mumabhangi, mitsara, uye makoramu. Kuchinja pakati pemabhangi nemitsara kunosuma imwe pamusoro, saka unofanira kunyatso kuraira kuwana ndangariro kuti ushandise EMIF nemazvo. EMIF zvakare inowanza mitsara uye makoramu kero pamusoro pemitsara yekero yakafanana, ichidzikisa huwandu hwepini inodiwa kune yakapihwa EMIF saizi.
Yepamusoro-kumhanya shanduro dzeEMIF, senge DDR, DDR2, DDR3, DDR4, uye DDR5, inoisa yakasimba chiratidzo chekuvimbika zvinodiwa izvo PCB vagadziri vanofanira kufunga.
EMIF zvishandiso zvinomira pakati pemhando dzinodhura-inoshanda uye yepamusoro-soro RAM dziripo, zvichiita kuti ive yakakurumbira sarudzo. Chinhu chakakosha cheiyo EMIF interface ndeye EMIF IP, iyo inogadzirisa mabasa ane chekuita nekugadzirisa kuwanda, kuzorodza, uye kushandura pakati pemitsara nemabhangi. Iyi dhizaini inobvumira yasara sisitimu kuwana EMIF pasina kuda kunzwisisa mavakirwo ayo emukati.

Ruzivo Rwakabatana Kunze Memory Interfaces IP Support Center

2.3.1.4.1. Kero Span Extender IP
Iyo Kero Span Extender Altera FPGA IP inobvumira ndangariro-mapped host interfaces kuti iwane yakakura kana diki kero mepu pane hupamhi hwemasaini ekero yavo inobvumira. Iyo Kero Span Extender IP inotsemura nzvimbo inogadziriswa kuita akawanda akaparadzana windows kuitira kuti muenzi akwanise kuwana chikamu chakakodzera chendangariro kuburikidza nepahwindo.
Iyo Kero Span Extender haigadzikise host uye mumiriri hupamhi kune 32-bit uye 64bit kumisikidzwa. Unogona kushandisa Kero Span Extender ine 1-64 bit kero windows.

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Mufananidzo 13. Kero Span Extender Altera FPGA IP
Agent Word Kero

Kero Span Extender

Mapping Table
Kudzora Port A

…

Kudzora Rejista 0 Kudzora Rejista Z-1

Yakawedzerwa Kero Yekugamuchira H

Related Information
Quartus® Prime Pro Edition Mushandisi Wekushandisa: Platform Dhizaini Tarisa kune musoro wenyaya Kero Span Extender Intel® FPGA IP kuti uwane rumwe ruzivo.

2.3.1.4.2. Uchishandisa Kero Span Extender IP ine Nios V processor
Iyo 32-bit Nios V processor inogona kugadzirisa kusvika ku4 GB yekero span. Kana iyo EMIF iine inodarika 4GB yendangariro, inodarika iyo yakanyanya kutsigirwa kero span, ichipa iyo Platform Designer system seyakakanganisa. Kero Span Extender IP inodiwa kugadzirisa nyaya iyi nekupatsanura imwe kero EMIF nzvimbo mumahwindo madiki akawanda.
Altera inokurudzira kuti utarise zvinotevera paramita.

Tafura 21. Kero Span Extender Parameters

Parameter

Recommended Settings

Datapath Width
Yakawedzera Master Byte Kero Upamhi

Sarudza 32-bits, iyo inobatana neiyo 32-bit processor. Zvinoenderana neiyo EMIF ndangariro saizi.

Muranda Shoko Kero Width Burstcount Width

Sarudza 2 GB kana pasi. Yasara kero span yeNios V processor yakachengeterwa mamwe akamisikidzwa akapfava IPs.
Tanga ne1 uye zvishoma nezvishoma uwedzere kukosha uku kuti uvandudze kushanda.

Nhamba ye sub-mahwindo

Sarudza 1 sub-hwindo kana uri kubatanidza EMIF kuNios V processor sekuraira uye data memory, kana zvese zviri zviviri. Kuchinja pakati peakawanda mahwindo madiki apo Nios V processor iri kuita kubva kuEMIF kune njodzi.

Gonesa Slave Control Port

Dzima chiteshi chevaranda chekutonga kana uri kubatanidza EMIF kuNios V processor sekuraira uye/kana data memory. Kunetseka kwakafanana seNhamba ye sub-windows.

Maximum Pending Reads

Tanga ne1 uye zvishoma nezvishoma uwedzere kukosha uku kuti uvandudze kushanda.

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Mufananidzo 14. Kubatanidza Instruction uye Data Manager kuKero Span Extender

Mufananidzo 15. Kero Mepu

Ziva kuti Kero Span Extender inogona kuwana iyo yese 8GB ndangariro nzvimbo yeEMIF. Nekudaro, kuburikidza neKero Span Extender, iyo Nios V processor inogona kuwana chete yekutanga 1GB ndangariro nzvimbo yeEMIF.

Mufananidzo 16. Yakareruka Block Diagram

Platform Designer System

Yasara 3 GB

Nios V processor kero

span ndeye yakamisikidzwa

NNioios sVV PProrocesosor r
M

nyoro IPs mune imwecheteyo system.
1 GB hwindo

Kero Span

Extender

Chekutanga chete 1 GB

yeEMIF ndangariro yakabatana neNios V

EMIF

processor.

8 GB
S

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2.3.1.4.3. Kutsanangura Kero Span Extender Linker Memory Device 1. Tsanangura Kero Span Extender (EMIF) sevheta reset. Neimwe nzira, unogona kugovera iyo Nios V processor reset vector kune dzimwe ndangariro, senge OCRAM kana flash zvishandiso.
Mufananidzo 17. Multiple Options seReset Vector
Nekudaro, iyo Board Support Package (BSP) Mharidzo haigone kunyoresa Kero Span Extender (EMIF) seyeuko inoshanda. Zvichienderana nesarudzo yawakaita, unoona mamiriro maviri akasiyana sezvakaratidzwa munhamba dzinotevera. Mufananidzo 18. BSP Kukanganisa paKutsanangura Kero Span Extender (EMIF) seReset Vector

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Mufananidzo 19. Kushaikwa EMIF paKutsanangura Dzimwe ndangariro seReset Vector

2. Unofanira kuwedzera nemaoko Kero Span Extender (EMIF) uchishandisa Add Memory Device, Add Linker Memory Region, uye Wedzera Linker Section Mappings muBSP Linker Script tab.
3. Tevedzera matanho aya:
a. Sarudza iyo kero span yeKero Span Extender uchishandisa Memory Mepu (Iyo example mune inotevera nhamba inoshandisa Kero Span Extender renji kubva pa0x0 kusvika 0x3fff_ffff).
Mufananidzo 20. Memory Mepu

b. Dzvanya Wedzera Memory Chishandiso, uye zadza maererano neruzivo rwuri muMemori Mepu yedhizaini yako: i. Zita reChishandiso: emif_ddr4. Cherechedza: Ita shuwa kuti wakopa zita rimwe chete kubva kuMemory Mepu. ii. Nzvimbo yekutanga: 0x0 iii. Saizi: 0x40000000
c. Dzvanya Wedzera kuti uwedzere nzvimbo itsva yekubatanidza memory:

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Tafura 22. Kuwedzera Linker Memory Region

Matanho

Reset Vector

emif_ddr4

Dzimwe ndangariro

Wedzera itsva Linker Memory Region inonzi reset. Wedzera itsva Linker Memory Region ye

· Zita reNzvimbo: gadzirisa

emif_ddr4.

· Dunhu Saizi: 0x20

· Zita reNzvimbo: emif_ddr4

Memory Chishandiso: emif_ddr4

· Dunhu Saizi: 0x40000000

Memory Offset: 0x0

Memory Chishandiso: emif_ddr4

Memory Offset: 0x0

Wedzera itsva Linker Memory Region ye

yasara emif_ddr4.

· Zita reNzvimbo: emif_ddr4

· Dunhu Saizi: 0x3fffffe0

Memory Chishandiso: emif_ddr4

Memory Offset: 0x20

Mufananidzo 21. Linker Dunhu paunotsanangura Kero Span Extender (EMIF) seReset Vector

Mufananidzo 22. Linker Region apo Kutsanangura Zvimwe Zviyeuchidzo seReset Vector
d. Kana iyo emif_ddr4 yawedzerwa kuBSP, unogona kuisarudza kune chero Chikamu Chekubatanidza.
Mufananidzo 23. Yakawedzerwa Kero Span Extender (EMIF) Zvakabudirira

e. Rega yambiro nezve Memory mudziyo emif_ddr4 haisi kuoneka muSOPC dhizaini.
f. Enderera Kugadzira BSP.
Ruzivo Rwakabatana Nhanganyaya kuNios V processor Booting Methods pane peji 51

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2.3.2. Non-Volatile Memory
Non-volatile memory inochengeta zviri mukati kana simba radzima, zvichiita kuti ive sarudzo yakanaka yekuchengetedza ruzivo rwunofanirwa kudzoserwa nesystem mushure mekutenderera kwesimba remagetsi. Non-volatile memory inowanzo chengeta processor boot-code, inoshingirira application marongero, uye Altera FPGA yekumisikidza data. Kunyangwe isiri-inotenderera ndangariro ine advantage yekuchengeta data rayo paunobvisa simba, inononoka zvakanyanya kuenzanisa neyekuvhuvhuta ndangariro, uye kazhinji ine yakanyanya kuoma kunyora nekudzima maitiro. Non-volatile memory inowanzo vimbiswa chete kudzima nhamba yakapihwa yenguva, mushure mezvo inogona kutadza.
Exampzvishoma zvekusagadzikana ndangariro zvinosanganisira marudzi ese ekupenya, EPROM, uye EEPROM. Altera inokukurudzira kuti uchengete Altera FPGA bitstreams uye Nios V chirongwa chemifananidzo mune isina-inoshanduka ndangariro, uye shandisa serial flash semudziyo webhutsu yeNios V processors.
Related Information
· Generic seri Flash Interface Altera FPGA IP User Guide
· Bhokisi retsamba Mutengi Altera FPGA IP User Guide · MAX® gumi remushandisi Flash Memory Mushandisi Yekushandisa: On-Chip Flash Altera FPGA IP Core
2.4. Mawachi uye Reset Maitiro Akanakisisa
Kunzwisisa kuti Nios V processor wachi uye reset domain inopindirana sei nechero peripheral inobatanidza nayo kwakakosha. Iyo yakapfava Nios V processor system inotanga neimwechete wachi domain, uye inogona kuomeswa neakawanda-wachi domain system kana inokurumidza wachi domain ichidhumhana neinononoka wachi domain. Iwe unofanirwa kucherechedza uye kunzwisisa kuti aya madomasi akasiyana anoteedzana sei kubva pakusetwa patsva uye ita shuwa kuti hapana matambudziko akajeka.
Kuti uite zvakanakisa, Altera inokurudzira kuisa iyo Nios V processor uye boot memory mune imwechete wachi domain. Usaburitse iyo Nios V processor kubva pakugadzirisa zvakare mune inokurumidza wachi domain kana ichibhutsu kubva mundangariro inogara mune inononoka wachi domain, izvo zvinogona kukonzera kukanganisa kutora yekuraira. Iwe unogona kuda kuteedzera kwemanyore kupfuura izvo zvinopihwa nePlatform Designer nekukasira, uye ronga reset kuburitsa topology zvinoenderana nekese yako yekushandisa. Kana iwe uchida kumisikidza system yako mushure mekunge yauya uye ichimhanya kwekanguva, shandisa iwo mafungidziro akafanana kune sisitimu reset sequencing uye post reset yekutanga zvinodiwa.
2.4.1. System JTAG Clock
Kudoma zvipingaidzo zvewachi mune yega yega Nios V processor system yakakosha sisitimu dhizaini yekutarisisa uye inodiwa pakurongeka uye hunhu hwekutsikisa. Iyo Quartus Prime Timing Analyzer inoita static nguva yekuongorora kuti isimbise kuita nguva kwese pfungwa mudhizaini yako uchishandisa indasitiri-yakajairwa kumanikidza, kuongorora, uye nzira yekubika.
Example 1. Basic 100 MHz Clock ine 50/50 Duty Cycle uye 16 MHz JTAG Clock
#************************************************************ # Gadzira 100MHz Clock #********************************************************************************************************************** creat_clock -zita {clk} -period 10 [get_ports {clk}] #************************ Gadzira 16MHz JTAG Wachi #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Ruzivo Rwakabatana Quartus Prime Time Analyzer Cookbook
2.4.2. Reset Chikumbiro Interface
Nios V processor inosanganisira sarudzo yekukumbira reset nzvimbo. Iyo reset yekukumbira nzvimbo ine reset_req uye reset_req_ack masaini.
Kugonesa chikumbiro chekugadzirisa zvakare muPlatform Designer: 1. Tangisa Nios V processor IP Parameter Editor. 2. PaKushandisa Reset Reset setting, batidza Add Reset Request Interface
sarudzo.
Mufananidzo 24. Ita kuti Nios V processor Reset Chikumbiro
Iyo reset_req siginecha inoita sekuvhiringidza. Paunenge uchiti reset_req, urikukumbira kuseta kune iyo yakakosha. Iyo yakakosha inomirira chero yakasarirwa kutengeserana kwebhazi kuti ipedze kushanda kwayo. For example, kana paine yakamirira ndangariro yekuwana transaction, musimboti unomirira mhinduro yakakwana. Saizvozvo, iyo yakakosha inobvuma chero yakamirira mhinduro yekuraira asi haiburitse chikumbiro chekuraira mushure mekugamuchira reset_req chiratidzo.
Basa rekugadzirisa rinosanganisira kuyerera kunotevera: 1. Pedzisa mabasa ose akamirira 2. Bvisa pombi yemukati 3. Isa Purogiramu yePurogiramu kune reset vector 4. Reset the core Basa rose reset reset rinotora mashoma clock cycles. Iyo reset_req inofanira kuramba yakasimbiswa kusvika reset_req_ack yanzi ichiratidza core reset operation yapera. Kutadza kuita izvi kunokonzeresa kuti core state ive isiri-deterministic.

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2.4.2.1. Typical Use Cases
· Unogona kutaura reset_req siginecha kubva kusimba-pakudzivirira iyo Nios V processor musimboti kubva pakutanga chirongwa chekuita kubva kune yayo reset vector kudzamara mamwe maFPGA mauto ari muhurongwa atanga Nios V processor boot memory. Muchiitiko ichi, iyo subsystem yese inogona kuwana yakachena hardware reset. Iyo Nios V processor inobatwa nekusingaperi munzvimbo yekukumbira reset kudzamara mamwe maFPGA mauto atanga processor boot memory.
· Mune sisitimu yaunofanirwa kuseta zvakare iyo Nios V processor core pasina kukanganisa iyo yasara sisitimu, unogona kutaura reset_req chiratidzo kuti umise zvakachena kushanda kwazvino kwepakati uye wotangazve processor kubva kune reset vector kana sisitimu yaburitsa reset_req_ack chiratidzo.
· Wekunze anotambira anogona kushandisa reset yekukumbira interface kurerutsira kuita kweanotevera mabasa:
-Misa yazvino Nios V processor chirongwa.
-Rodha chirongwa chitsva muNios V processor boot memory.
- Bvumira processor kuti itange kuita chirongwa chitsva.
Altera inokurudzira kuti ushandise nzira yekupedza nguva yekutarisa mamiriro ereset_req_ack chiratidzo. Kana iyo Nios V processor core ikawira mune isingaperi yekumirira mamiriro uye masiteki nechikonzero chisingazivikanwe, reset_req_ack haigone kutaura nekusingaperi. Iyo nzira yekupedza nguva inoita kuti iwe ugone:
· Tsanangura nguva yekudzikinura nguva uye ita system kudzoreredza nesystem level reset.
· Gadzirisa hardware level reset.
2.4.3. Reset Release IP
Altera SDM-yakavakirwa michina inoshandisa yakafanana, chikamu-chakavakirwa dhizaini inogovera iyo yepakati machira logic muzvikamu zvakawanda. Altera anokukurudzira kuti ushandise Reset Release Altera FPGA IP seimwe yekutanga yekuisa kudunhu reset. Intel® SDMbased zvishandiso zvinosanganisira Stratix® 10, uye AgilexTM zvishandiso. Kudzora-block kwakavakirwa michina haina kukanganiswa nezvinodiwa izvi.
Related Information
AN 891: Kushandisa Reset Kuburitsa Altera FPGA IP
2.5. Kugovera Default Agent
Platform Dhizaini inobvumidza iwe kuti utaure mumiririri anogara achiita seye kukanganisa mhinduro default agent. Iyo default agent yaunosarudza inopa sevhisi yekupindura kukanganisa kune vanogamuchira vasina-decoded kupinda mumepu yekero.
Izvi zvinotevera zvinokonzeresa chiitiko chisina decoded:
· Bus transaction kuchengetedza mamiriro ekutyorwa
· Transaction yekuwana kune isina kutsanangurwa ndangariro dunhu
· Chiitiko chakasarudzika uye nezvimwe.

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A default agent anofanirwa kupihwa kubata zviitiko zvakadaro, uko kusatsanangurwa transaction kunodzoserwa kune iyo default mumiriri uye yozopindura Nios V processor nemhinduro yekukanganisa.
Related Information
· Quartus Prime Pro Edition Mushandisi Wekushandisa: Platform Dhizaini. Kugadzira Default Agent
· Quartus Prime Pro Edition Mushandisi Wekushandisa: Platform Dhizaini. Kukanganisa Mhinduro Muranda Altera FPGA IP
Github - Yekuwedzera Reset Zvikamu zveQsys

2.6. Kugovera UART Mumiririri weKudhinda
Kudhinda kunobatsira pakugadzirisa software application, pamwe nekutarisa mamiriro ehurongwa hwako. Altera inokurudzira kudhinda ruzivo rwekutanga senge meseji yekutanga, meseji yekukanganisa, uye kufambira mberi kwekuita kwesoftware application.
Rega kushandisa printf() raibhurari basa mumamiriro ezvinhu anotevera: · Iyo printf() raibhurari inokonzeresa kuti application imire kana pasina muridzi ari kuverenga zvinobuda.
Izvi zvinoshanda kune JTAG UART chete. · Iyo printf() raibhurari inodya yakawanda yepurogiramu memory.

2.6.1. Kudzivirira Stalls naJTAG UART

Tafura 23. Kusiyana pakati peTraditional UART neJTAG UART

UART Type Traditional UART

Tsanangudzo
Inotumira serial data zvisinei nekuti munhu wekunze ari kuteerera. Kana pasina muenzi anoverenga serial data, iyo data inorasika.

JTAG UART

Inonyora data yakatumirwa kune inobuda buffer uye inovimba neanotambira kunze kuti averenge kubva mubuffer kuti aidururire.

Iye JTAG Mutyairi weUART anomirira kana buffer yekubuda yazara. Iye JTAG Mutyairi weUART anomirira wekunze kuti averenge kubva kune inobuda buffer asati anyora yakawanda kutumira data. Iyi nzira inodzivirira kurasikirwa kwekutumira data.
Nekudaro, kana system debugging isiri kudikanwa, senge panguva yekugadzira, masisitimu akaiswa anoiswa pasina anogamuchira PC yakabatana naJ.TAG UART. Kana iyo system yakasarudza iyo JTAG UART semumiriri weUART, inogona kukonzera kumisa system nekuti hapana wekunze akabatana.
Kudzivirira kumisa naJTAG UART, shandisa zvinotevera sarudzo:

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Tafura 24. Dziviriro paKumira naJTAG UART

Options
Hapana UART interface uye mutyairi aripo
Shandisa imwe UART interface uye mutyairi
Chengetedza JTAG UART interface (isina mutyairi)

Panguva Yekuvandudza Hardware (muPlatform Designer)

Panguva Yekuvandudza Kwesoftware (muBhodhi Tsigiro Package Edhita)

Bvisa JTAG UART kubva kuhurongwa

Gadzirisa hal.stdin, hal.stdout uye hal.stderr seNone.

Tsiva JTAG UART nedzimwe dzakapfava Gadzirisa hal.stdin, hal.stdout uye hal.stderr

UART IP

neimwe yakapfava UART IP.

Chengetedza JTAG UART muhurongwa

· Gadzirisa hal.stdin, hal.stdout uye hal.stderr seHapana muBhodhi Rutsigiro Package Edhita.
· Dzima JTAG UART mutyairi muBSP Driver tab.

2.7. JTAG Signals
Iyo Nios V processor debug module inoshandisa iyo JTAG interface yesoftware ELF kurodha uye software debugging. Paunogadzirisa dhizaini yako neJTAG interface, iyo JTAG masaini TCK, TMS, TDI, uye TDO anoitwa sechikamu chedhizaini. Kutaura nezve JTAG masign constraints mune yega yega Nios V processor system yakakosha sisitimu dhizaini yekutarisisa uye inodiwa pakurongeka uye hunhu hwekutsunga.
Altera inokurudzira kuti chero dhizaini yewachi frequency iite kanokwana kana JTAG wachi frequency kuona kuti on-chip instrumentation (OCI) musimboti unoshanda nemazvo.
Ruzivo Rwakabatana · Quartus® Prime Timing Analyzer Cookbook: JTAG Signals
Kuti uwane rumwe ruzivo nezve JTAG nhungamiro yezvipingaidzo zvenguva. KDB: Nei niosv-kudhawunirodha ichitadza neisina-pombi Nios® V/m processor pa
JTAG frequency 24MHz kana 16Mhz?
2.8. Kugadzirisa Platform Dhizaini System Performance
Platform Designer inopa maturusi ekugonesa kuita kweiyo system yekubatanidza kune Altera FPGA dhizaini.

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Mufananidzo 25. Kugadziridza Examples

The exampinoratidzwa mumufananidzo inoratidza matanho anotevera:
1. Inowedzera Pipeline Bridge kuderedza nzira dzakakosha nekuiisa: a. Pakati peMutariri Wemirairo nevamiririri vayo b. Pakati peData Manager nevamiririri vayo
2. Nyorera Chokwadi Dual port On-Chip RAM, nechiteshi chega chega chakatsaurirwa kuMutungamiriri weInstruction uye Data Manager zvakateerana.

Nios® V Yakamisikidzwa processor Dhizaini Handbook 40

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Tarisa kune anotevera anoenderana link pazasi, ayo anopa matekiniki ekushandisa maturusi aripo uye kutengeserana-offs kwega kwega kuita.
Ruzivo rwunoenderana · Quartus® Prime Pro Edition Mushandisi Wekushandisa: Platform Designer
Tarisa kune musoro wenyaya Kukwirisa Platform Dhizaini System Performance kuti uwane rumwe ruzivo. · Quartus® Prime Standard Edition Mushandisi Wekushandisa: Platform Dhizaini Tarisa kune musoro wenyaya Kukwirisa Platform Dhizaini Mashandiro eSitimu kuti uwane rumwe ruzivo.

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3. Nios V Processor Software System Design
Ichi chitsauko chinotsanangura iyo Nios V processor software yekuvandudza kuyerera uye maturusi esoftware aunogona kushandisa mukugadzira yako yakamisikidzwa dhizaini system. Izvo zvirimo zvinoshanda sekupfuuraview usati wagadzira Nios V processor software system.
Mufananidzo 26. Software Design Flow
Tanga

Gadzira iyo BSP muPlatform Dhizaini Uchishandisa iyo BSP Mharidzo

Gadzira iyo BSP Uchishandisa iyo Nios V Raira Shell
Gadzira Chikumbiro CMake Build File Kushandisa iyo Nios V Command Shell

Cherechedza:

Ngenisa iyo BSP uye Chikumbiro CMake Build File
Vaka iyo Nios V processor yekushandisa uchishandisa iyo
RiscFree IDE yeIntel FPGA

Vaka iyo Nios V processor application uchishandisa chero
command-line source code editor, CMake, uye Gadzira
mirairo
End

Altera inokurudzira kuti ushandise Altera FPGA yekuvandudza kit kana tsika prototype board yekuvandudza software uye kugadzirisa. Mazhinji maperipherals uye system-level maficha anowanikwa chete kana software yako ichimhanya pabhodhi chairo.

© Altera Corporation. Altera, iyo Altera logo, iyo `a' logo, uye mamwe maAltera mamaki zviratidzo zveAltera Corporation. Altera inochengetedza kodzero yekuita shanduko kune chero zvigadzirwa uye masevhisi chero nguva pasina chiziviso. Altera haatore mutoro kana mutoro unobva mukushandisa kana kushandisa chero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neAltera. Vatengi veAltera vanorayirwa kuti vatore yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba neruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

3. Nios V Processor Software System Design 726952 | 2025.07.16
3.1. Nios V processor Software Development Flow
3.1.1. Board Support Package Project
Iyo Nios V Bhodhi Rutsigiro Package (BSP) chirongwa chehunyanzvi raibhurari ine system-chaiyo kodhi yekutsigira. A BSP inopa software yekumhanyisa nharaunda yakagadzirirwa imwe processor muNios V processor hardware system.
Iyo Quartus Prime software inopa Nios V Bhodhi Rutsigiro Package Mharidzo uye niosv-bsp zvishandiso zvekushandisa kugadzirisa marongero anodzora maitiro eBSP.
BSP ine zvinhu zvinotevera: · Hardware abstraction layer · Device drivers · Optional software packages · Optional real-time operating system
3.1.2. Application Project
A Nios VC/C++ application project ine zvinotevera zvinhu: · Inosanganisira muunganidzwa wekodhi yekodhi uye CMakeLists.txt.
- Iyo CMakeLists.txt inounganidza iyo kodhi kodhi uye inoibatanidza neBSP uye imwe kana akawanda esarudzo raibhurari, kugadzira imwe .elf file
· Imwe yemabviro files ine basa guru (). · Inosanganisira kodhi inodaidza mabasa mumaraibhurari uye BSPs.
Altera inopa niosv-app yekushandisa chishandiso muQuartus Prime software utility zvishandiso kugadzira iyo Application CMakeLists.txt, uye RiscFree IDE yeAltera FPGAs kugadzirisa iyo kodhi kodhi munzvimbo yeEclipse-based.
3.2. Altera FPGA Embedded Development Zvishandiso
Iyo Nios V processor inotsigira anotevera maturusi ekugadzira software: · Graphical User Interface (GUI) - Graphical kuvandudza maturusi anowanikwa mu.
zvese Windows* neLinux* Operating Systems (OS). - Nios V Bhodhi Inotsigira Package Edhita (Nios V BSP Mharidzo) - Ashling RiscFree IDE yeAltera FPGAs · Command-Line Zvishandiso (CLI) - Zvishandiso zvekuvandudza zvinotangwa kubva kuNios V Command Shell. Chishandiso chega chega chinopa zvinyorwa zvayo nenzira yerubatsiro inowanikwa kubva kumutsara wekuraira. Vhura iyo Nios V Command Shell uye nyora unotevera kuraira: -kubatsira view iyo Rubatsiro menyu. - Nios V Utilities Zvishandiso - File Format Shanduko Zvishandiso - Zvimwe Zvishandiso Zvishandiso

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Tafura 25. GUI Zvishandiso uye Command-line Zvishandiso Mabasa Summary

Basa

GUI Tool

Command-line Tool

Kugadzira BSP

Nios V BSP Mupepeti

· MuQuartus Prime Pro Edition software: niosv-bsp -c -s=<.qsys file> -t= [OPTIONS] zvigadziriso.bsp
· MuQuartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t= [OPTIONS] zvigadziriso.bsp

Kugadzira BSP uchishandisa iripo .bsp file
Kugadziridza BSP

Nios V BSP Mupepeti Nios V BSP Mupepeti

niosv-bsp -g [OPTIONS] settings.bsp niosv-bsp -u [OPTIONS] settings.bsp

Kuongorora BSP

Nios V BSP Mupepeti

niosv-bsp -q -E= [OPTIONS] zvigadziriso.bsp

Kugadzira application

–

niosv-app -a= -b= -s= files dhairekitori> [ZVINODA]

Kugadzira raibhurari yemushandisi

–

niosv-app -l= -s= files dhairekitori> -p= [ZVISARUDZO]

Kugadzirisa application Kugadzirisa raibhurari yemushandisi Kuvaka application

RiscFree IDE yeAltera FPGAs
RiscFree IDE yeAltera FPGAs
RiscFree IDE yeAltera FPGAs

Chero yekuraira-mutsara sosi edhita
Chero yekuraira-mutsara sosi edhita
· make · cmke

Kuvaka raibhurari yemushandisi

RiscFree IDE yeAltera FPGAs

· make · cmke

Kudhaunirodha application ELF
Kushandura .elf file

RiscFree IDE yeAltera FPGAs
–

niosv-download
· elf2flash · elf2hex

Related Information
Ashling RiscMahara Yakabatanidzwa Yekuvandudza Nzvimbo (IDE) yeAltera FPGAs Mushandisi Wekushandisa

3.2.1. Nios V processor Bhodhi Tsigira Package Edhita
Unogona kushandisa Nios V processor BSP Mharidzo kuita mabasa anotevera: · Gadzira kana kugadzirisa Nios V processor BSP purojekiti · Rongedza marongero, matunhu ekubatanidza, uye chikamu mappings · Sarudza software mapakeji uye madhiraivha emidziyo.
Iko kugona kweBSP Mharidzo kunosanganisira kugona kweiyo niosv-bsp zvishandiso. Chero purojekiti yakagadzirwa muBSP Mharidzo inogona zvakare kugadzirwa uchishandisa yekuraira-mutsara zvishandiso.

Nios® V Yakamisikidzwa processor Dhizaini Handbook 44

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Cherechedza:

YeQuartus Prime Standard Edition software, tarisa kune AN 980: Nios V processor Quartus Prime Software Tsigiro yematanho ekudaidza iyo BSP Mharidzo GUI.

Kuti utange BSP Editor, tevera matanho aya: 1. Vhura Platform Designer, uye enda ku File menyu.
a. Kuvhura iyo iripo BSP marongero file, tinya Vhura… b. Kuti ugadzire BSP itsva, baya BSP Itsva... 2. Sarudzai BSP Editor tab uye ipa ruzivo rwakakodzera.

Mufananidzo 27. Tanga BSP Editor

Ruzivo Rwakabatana AN 980: Nios V processor Quartus Prime Software Tsigiro
3.2.2. RiscFree IDE yeAltera FPGAs
Iyo RiscFree IDE yeAltera FPGAs ndeye Eclipse-yakavakirwa IDE yeNios V processor. Altera inokurudzira kuti ugadzire Nios V processor software mune ino IDE nekuda kwezvikonzero zvinotevera: · Iwo maficha anogadzirwa uye anosimbiswa kuti aenderane neNios V.
processor kuvaka kuyerera. · Yakashongedzerwa neese anodiwa maturusi cheni uye anotsigira maturusi ayo anogonesa iwe
kutanga nyore Nios V processor kuvandudza.
Ruzivo Rwakabatana Ashling RiscMahara Yakabatanidzwa Yekuvandudza Nzvimbo (IDE) yeAltera FPGAs Mushandisi Wekushandisa
3.2.3. Nios V Utilities Zvishandiso
Iwe unogona kugadzira, kugadzirisa, uye kuvaka Nios V zvirongwa nemirairo yakanyorwa pamutsetse wemirairo kana yakanyudzwa mune script. Iyo Nios V yekuraira-mutsara maturusi anotsanangurwa muchikamu chino ari mune /niosv/bin dhairekitori.

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Tafura 26. Nios V Utilities Tools

Command-Mutsara Zvishandiso

Summary

niosv-app niosv-bsp niosv-download niosv-shell niosv-stack-report

Kugadzira uye kugadzirisa chirongwa chekushandisa.
Kugadzira kana kugadzirisa zvirongwa zveBSP file uye gadzira iyo BSP files. Kuti utore ELF file kune Nios® V processor.
Kuvhura iyo Nios V Command Shell. Kuti ndikuzivise nezvenzvimbo yakasara yendangariro inowanikwa kune yako application .elf yekushandisa stack kana murwi.

3.2.4. File Maturusi eKushandura Format

File kushandura fomati dzimwe nguva kunodiwa kana uchipfuudza data kubva kune imwe yekushandisa kuenda kune imwe. The file maturusi ekushandura mafomati ari mu
software yekuisa dhairekitori>/niosv/bin dhairekitori.

Tafura 27. File Maturusi eKushandura Format

Command-Mutsetse Zvishandiso elf2flash elf2hex

Summary Kuturikira .elf file to .srec format yeflash memory programming. Kushandura .elf file ku .hex fomati yekutanga ndangariro.

3.2.5. Zvimwe Zvishandiso Zvishandiso

Iwe unogona kuda inotevera yekuraira-mutsara maturusi paunenge uchivaka Nios V processor yakavakirwa system. Aya maturusi emirairo-mutsara anopihwa neIntel in /quartus/bin kana kuwanikwa kubva
open-source tools.

Tafura 28. Zvimwe Zvishandiso zveMutsetse-Mutsetse

Command-Mutsara Zvishandiso

Type

Summary

juart-terminal

Intel-yakapihwa

Kutarisa stdout uye stderr, uye nekupa mapindiro kune Nios® V processor
subsystem kuburikidza ne stdin. Ichi chishandiso chinongoshanda kune JTAG UART IP kana yakabatana neNios® V processor.

openocd

Intel-inopihwa Kuita OpenOCD.

openocd-cfg-gen

Intel-yakapihwa · Kugadzira iyo OpenOCD kumisikidzwa file. · Kuratidza JTAG cheni mudziyo index.

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4. Nios V processor Configuration uye Booting Solutions
Iwe unogona kugadzirisa iyo Nios V processor kubhuta uye kuita software kubva kwakasiyana ndangariro nzvimbo. Iyo boot memory ndeye Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), kana Tightly Coupled Memory (TCM).
Related Information · Power-Up Trigger Conditions papeji 193 · Power-Up Triggers
Kuti uwane rumwe ruzivo nezve simba-up zvinokonzeresa.
4.1. Nhanganyaya
Iyo Nios V processor inotsigira mhando mbiri dzemabhutsu maitiro: · Execute-in-Place (XIP) uchishandisa alt_load() basa · Chirongwa chakakopwa kuRAM uchishandisa boot copier. Iyo Nios V yakamisikidzwa zvirongwa zvekuvandudza yakavakirwa pane hardware abstraction layer (HAL). Iyo HAL inopa diki bhoti loader chirongwa (inozivikanwawo sebhoti copier) iyo inokopa yakakodzera linker zvikamu kubva kubhutsu memory kuenda kune yavo yekumhanya nguva nzvimbo panguva yebhoti. Iwe unogona kutsanangura chirongwa uye data memory yekumhanyisa nguva nzvimbo nekushandisa Bhodhi Tsigiro Package (BSP) Edhita zvigadziriso. Ichi chikamu chinotsanangura: · Nios V processor boot copier iyo inobhutsu yako Nios V processor system zvinoenderana
iyo boot memory kusarudzwa · Nios V processor booting sarudzo uye kuyerera kwakawanda · Nios V zvirongwa zvekugadzirisa zveyakasarudzwa boot memory
4.2. Kubatanidza maApplication
Paunogadzira iyo Nios V processor purojekiti, iyo BSP Mharidzo inogadzira maviri akabatana ane hukama files: · linker.x: The linker command file iyo iyo yakagadzirwa application inogadzirafile inoshandisa
kugadzira iyo .elf binary file. · linker.h: Ine ruzivo nezve linker memory marongerwo. Zvese linker kuseta magadzirirwo aunoita kuBSP purojekiti anokanganisa zviri mukati meaya maviri linker files. Yese Nios V processor application ine zvinotevera linker zvikamu:
© Altera Corporation. Altera, iyo Altera logo, iyo `a' logo, uye mamwe maAltera mamaki zviratidzo zveAltera Corporation. Altera inochengetedza kodzero yekuita shanduko kune chero zvigadzirwa uye masevhisi chero nguva pasina chiziviso. Altera haatore mutoro kana mutoro unobva mukushandisa kana kushandisa chero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neAltera. Vatengi veAltera vanorayirwa kuti vatore yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba neruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

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Tafura 29. Linker Sections

.text

Linker Sections

.rodata

.rwdata

.bss

.murwi

.stack

Tsananguro Inobatika kodhi. Chero data rekuverenga-chete rinoshandiswa mukuitwa kwechirongwa. Zvitoro zvekuverenga-kunyora data rinoshandiswa mukuitwa kwechirongwa. Iine uninitialized static data. Ine dynamically allocated memory. Zvitoro zvekushanda-kufona paramita uye imwe data yenguva pfupi.

Unogona kuwedzera mamwe linker zvikamu ku.elf file kubata tsika kodhi uye data. Izvi zvinongedzo zvikamu zvakaiswa munzvimbo dzine mazita ekurangarira, anotsanangurwa kuti aenderane nemidziyo yekurangarira yepanyama uye kero. Nekutadza, BSP Mharidzo inogadzira otomatiki aya ekubatanidza zvikamu. Nekudaro, iwe unogona kudzora iyo linker zvikamu zveimwe application.

4.2.1. Kubatanidza Maitiro
Ichi chikamu chinotsanangura iyo BSP Mharidzo yekusarudzika yekubatanidza maitiro uye maitiro ekudzora maitiro ekubatanidza.

4.2.1.1. Default BSP Kubatanidza
Munguva yeBSP kumisikidzwa, maturusi anoita nhanho dzinotevera otomatiki:
1. Ipa mazita enzvimbo yekuyeuka: Ipa zita kune imwe neimwe system memory device uye wedzera zita rimwe nerimwe kune linker file senzvimbo yekuyeuka.
2. Tsvaga chiyeuchidzo chikuru: Ziva nzvimbo huru yekuverenga-ne-kunyora yendangariro mune linker file.
3. Ipa zvikamu zvekubatanidza: Isa zvigadziriswe zvinogadzirisa zvikamu (.text, .rodata, .rwdata, .bss, .heap, uye .stack) munharaunda yekuyeuka yakaonekwa munhanho yapfuura.
4. Nyora files: Nyora linker.x uye linker.h files.
Kazhinji, iyo linker chikamu chekugovera chirongwa chinoshanda panguva yekuvandudza software nekuti application inovimbiswa kushanda kana ndangariro yakakura zvakakwana.
Mitemo yeiyo default linking behavior iri muAltera-generated Tcl scripts bsp-set-defaults.tcl uye bsp-linker-utils.tcl inowanikwa mu /niosv/scripts/bsp-defaults dhairekitori. Mutemo we niosv-bsp unodaidza zvinyorwa izvi. Usashandura zvinyorwa izvi zvakananga.

Nios® V Yakamisikidzwa processor Dhizaini Handbook 48

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4.2.1.2. Configurable BSP Kubatanidza
Iwe unogona kubata iyo yakasarudzika yekubatanidza maitiro muLinker Script tebhu yeBSP Mharidzo. Shandisa chinongedzo script uchishandisa nzira dzinotevera: · Wedzera nzvimbo yekuyeuka: Mepu zita renzvimbo yendangariro kune chigadziriso chendangariro. · Wedzera chikamu chemepu: Mepu zita rechikamu kunzvimbo yendangariro. Iye BSP
Editor inokubvumira kuti uite view mepu yendangariro pamberi uye mushure mekuita shanduko.

4.3. Nios V processor Booting Nzira

Pane nzira shoma dzekuvhura iyo Nios V processor muAltera FPGA zvishandiso. Nzira dzekubhura Nios V processor dzinosiyana zvichienderana nesarudzo yekurangarira uye mhuri dzemidziyo.

Tafura 30. Inotsigirwa Flash Memories ine Respective Boot Options

Inotsigirwa Boot Memories

Mudziyo

On-Chip Flash (yekugadziriswa Kwemukati)

Max midziyo gumi chete (ine On-Chip Flash IP)

General Chinangwa QSPI Flash (yemushandisi data chete)

Zvese zvinotsigirwa zveFPGA zvishandiso (ane Generic Serial Flash Interface FPGA IP)

Kugadzirisa QSPI Flash (yeActive Serial kumisikidza)

Kudzora block-based
zvishandiso (neGeneric
Serial Flash Interface Intel FPGA IP)(2)

Nios V processor Booting Nzira

Application Runtime Nzvimbo

Boot Copier

Nios V processor application executein-nzvimbo kubva On-Chip Flash

On-Chip Flash (XIP) + OCRAM/ Ekunze RAM (yezvikamu zve data zvinonyorwa)

alt_load () basa

Nios V processor application yakakopwa kubva kuOn-Chip Flash kuenda kuRAM uchishandisa boot copier

OCRAM/Kunze RAM

Kushandisazve Bootloader kuburikidza neGSFI

Nios V processor application executein-nzvimbo kubva kune yakajairika chinangwa QSPI flash

General chinangwa QSPI flash (XIP) + OCRAM/ Yekunze RAM (yezvinyorwa zvinonyorwa data)

alt_load () basa

Nios V processor application yakakopwa kubva kune yakajairika chinangwa QSPI flash kuenda kuRAM uchishandisa boot copier

OCRAM/Kunze RAM

Bootloader kuburikidza neGSFI

Nios V processor application executein-nzvimbo kubva kumisikidzwa QSPI flash

Kugadzirisa QSPI flash (XIP) + OCRAM/ Yekunze RAM (yezvikamu zvinonyorwa data)

alt_load () basa

Nios V processor application yakakopwa kubva pakumisikidzwa QSPI flash kuenda kuRAM uchishandisa boot copier

OCRAM/ Ekunze RAM Bootloader kuburikidza neGSFI inoenderera…

(2) Tarisa kune AN 980: Nios V processor Quartus Prime Software Tsigiro yerunyorwa rwechishandiso.

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Inotsigirwa Boot Memories
On-chip Memory (OCRAM) Yakasimba Yakabatana Memory (TCM)

Mudziyo
SDM-based devices (ine Mailbox Client Intel FPGA IP). (2)
Zvese zvinotsigirwa Altera FPGA zvishandiso (2)
Zvese zvinotsigirwa Altera FPGA zvishandiso (2)

Nios V processor Booting Nzira
Nios V processor application yakakopwa kubva pakumisikidzwa QSPI flash kuenda kuRAM uchishandisa boot copier
Nios V processor application executein-nzvimbo kubva kuOCRAM
Nios V processor application executein-nzvimbo kubva kuTCM

Application Runtime Nzvimbo

Boot Copier

OCRAM/ Yekunze RAM Bootloader kuburikidza neSDM

OCRAM

alt_load () basa

Mirayiridzo TCM (XIP) Hapana + Dhata TCM (yezvikamu zve data zvinonyorwa)

Mufananidzo 28. Nios V Processor Boot Flow

Reset

processor inosvetuka kuti igadzirise vector (boot kodhi kutanga)

Kodhi yekushandisa inogona kukopwa kune imwe nzvimbo yekurangarira (zvinoenderana nesarudzo dzebhoti)
Boot code inotanga processor

Zvichienderana nesarudzo dzebhoti, iyo boot kodhi inogona kukopa yekutanga kukosha kwedata / kodhi kune imwe nzvimbo yekurangarira (alt_load)
Boot kodhi inotanga kodhi yekushandisa uye nzvimbo yekurangarira data
Boot code inotangisa ese masisitimu peripherals ane HAL madhiraivha (alt_main)
Entry to main
Ruzivo rwunoenderana · Generic Serial Flash Interface Altera FPGA IP User Guide
Nios® V Yakamisikidzwa processor Dhizaini Handbook 50

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· Bhokisi retsamba Mutengi Altera FPGA IP User Guide · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Nhanganyaya yeNios V Processor Booting Methods
Nios V processor masisitimu inoda iyo software mifananidzo kuti igadziriswe mundangariro system processor isati yatanga kuita chirongwa chekunyorera. Tarisa kune Linker Zvikamu zveiyo default linker zvikamu.
Iyo BSP Mharidzo inogadzira chinongedzo script chinoita zvinotevera mabasa: · Inove nechokwadi chekuti processor software yakabatana zvinoenderana neiyo linker marongero.
yeBSP mupepeti uye inosarudza panogara software mundangariro. · Inoisa iyo processor kodhi dunhu muchikamu chendangariro zvinoenderana ne
akagoverwa ndangariro zvikamu.
Chikamu chinotevera chinotsanangura muchidimbu nzira dziripo dzeNios V processor booting.
4.4.1. Nios V processor Chikumbiro Chengetedza-In-Nzvimbo kubva kuBoot Flash
Altera yakagadzira madhiraivha ekuti bhutsu yekero yekero isvike nekukurumidza kuNios V processor pakugadzirisazve sisitimu, pasina chikonzero chekutanga chidzori chendangariro kana ndangariro. Izvi zvinoita kuti Nios V processor iite kodhi yekushandisa yakachengetwa pamidziyo yebhoti zvakananga pasina kushandisa bhutsu yekukopa kukopa kodhi kune imwe ndangariro mhando. Iwo maflash controller ndeaya: · On-Chip Flash ine On-Chip Flash IP (chete muMAX® 10 mudziyo) · Chinangwa chese QSPI flash ine Generic Serial Flash Interface IP · Kugadzirisa QSPI flash neGeneric Serial Flash Interface IP (kunze kweMAX 10
zvishandiso)
Kana iyo Nios V processor application ichiita-mu-nzvimbo kubva kubhoti flash, iyo BSP Mharidzo inoita zvinotevera mabasa: · Sets the .text linker zvikamu kune boot flash memory region. · Sets the .bss,.rodata, .rwdata, .stack uye .heap linker zvikamu ku RAM
ndangariro nharaunda. Iwe unofanirwa kugonesa iyo alt_load () basa muBSP Settings kuti ukope zvikamu zve data (.rodata, .rwdata,, .exceptions) ku RAM pakugadziriswa kwehurongwa. Chikamu chekodhi (.text) chinoramba chiri mubhoot flash memory region.
Ruzivo rwunoenderana · Generic Serial Flash Interface Altera FPGA IP User Guide · Altera MAX 10 User Flash Memory User Guide
4.4.1.1. alt_load()
Iwe unogona kugonesa iyo alt_load () basa muHAL kodhi uchishandisa iyo BSP Mharidzo.
Kana ichishandiswa mukuita-mu-nzvimbo bhoti kuyerera, iyo alt_load () basa rinoita anotevera mabasa:

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· Inoshanda semini bhutsu yekukopa iyo inokopa ndangariro zvikamu kuRAM zvichibva pane iyo BSP marongero.
· Inokopa zvikamu zve data (.rodata, .rwdata, .exceptions) ku RAM asi kwete zvikamu zvekodhi (.text) .Chikamu chekodhi (.text) chikamu chikamu chekuverenga chete uye chinoramba chiri mubhoot flash memory region. Kupatsanura uku kunobatsira kudzikisira mashandisirwo eRAM asi kunogona kudzikisira mashandiro ekodhi nekuti kuwana kune flash memory kunononoka pane kupinda kune pa-chip RAM.

Tafura inotevera inonyora iyo BSP Mharidzo marongero uye mabasa:

Tafura 31. BSP Editor Settings
BSP Mupepeti Setting hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Basa Rinogonesa alt_load () basa. alt_load() copies .rodata chikamu ku RAM. alt_load() copies .rwdata chikamu ku RAM. alt_load() copies .exceptions chikamu ku RAM.

4.4.2. Nios V processor Chikumbiro chakakopwa kubva kuBoot Flash kuenda kuRAM Uchishandisa Boot Copier
Iyo Nios V processor uye HAL inosanganisira bhutsu yekukopa inopa kushanda kwakakwana kune yakawanda Nios V processor application uye iri nyore kuita neNios V software yekuvandudza kuyerera.
Apo purogiramu inoshandisa boot copier, inogadzirisa zvikamu zvose zvekubatanidza ( .text, .heap , .rwdata, .rodata , .bss, .stack) kune RAM yemukati kana kunze. Kushandisa bhutsu yekukopa kukopa Nios V processor application kubva kubhutsu flash kuenda kune yemukati kana yekunze RAM yekuuraya kunobatsira kuvandudza mashandiro ekuita.
Kune iyi bhutsu sarudzo, iyo Nios V processor inotanga kuita iyo boot copier software pane system reset. Iyo software inokopa application kubva kubhoti flash kuenda kune yemukati kana yekunze RAM. Kana maitirwo apera, Nios V processor inotamisa chirongwa chekutonga kune application.

Cherechedza:

Kana iyo boot copier iri muflash, ipapo iyo alt_load () basa haidi kunzi nekuti ivo vese vanoshandira chinangwa chimwe.

4.4.2.1. Nios V processor Bootloader kuburikidza neGeneric Serial Flash Interface
Iyo Bootloader kuburikidza neGSFI ndiyo Nios V processor boot copier inotsigira QSPI flash memory mukudzora block-based zvishandiso. Iyo Bootloader kuburikidza neGSFI inosanganisira zvinotevera maficha:
· Inotsvaga iyo software application mune isiri-inoshanduka ndangariro.
* Unpacks uye kukopa iyo software application mufananidzo kuRAM.
* Inoshandura otomatiki processor kuitisa kodhi yekushandisa muRAM mushure mekunge kopi yapera.

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Iyo boot image inowanikwa mushure meiyo boot copier. Iwe unofanirwa kuve nechokwadi chekuti Nios V processor inogadzirisazve offset mapoinzi kusvika kutanga kweiyo boot copier. Mufananidzo: Mepu Yendangariro yeQSPI Flash ine Bootloader kuburikidza neGSFI memory mepu yeQSPI Flash ine Bootloader kuburikidza neGSFI inoratidza flash memory mepu yeQSPI flash kana uchishandisa boot copier. Iyi mepu yekurangarira inotora flash memory memory inochengeta iyo FPGA mufananidzo uye application software.

Tafura 32. Bootloader kuburikidza neGSFI yeNios V Processor Core

Nios V processor Core
Nios V/m processor

Bootloader kuburikidza neGSFI File Nzvimbo
/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/components/bootloader/ niosv_g_bootloader.srec

Mufananidzo 29. Memori Mepu yeQSPI Flash neBootloader kuburikidza neGSFI

Mutengi Data (*.hex)

Application Code

Cherechedza:

Reset Vector Offset

Boot Copier

0x01E00000

Mufananidzo weFPGA (*.sof)

0x00000000

1. Pakutanga kwemepu yekurangarira ndiyo mufananidzo weFPGA unoteverwa nedata rako, iro rine boot copier uye kodhi yekushandisa.
2. Iwe unofanirwa kuseta iyo Nios V processor reset offset muPlatform Designer uye inongedza iyo pakutanga kwebhoti copier.
3. Hukuru hwemufananidzo weFPGA hauzivikanwi.Unokwanisa chete kuziva ukuru chaihwo mushure mekugadzirwa kwepurojekiti yeQuartus Prime. Iwe unofanirwa kusarudza yekumusoro inosungirwa saizi yeAltera FPGA mufananidzo. For example, kana saizi yemufananidzo weFPGA inofungidzirwa kuve isingasviki 0x01E00000, isa iyo Reset Offset ku0x01E00000 muPlatform Designer, iri zvakare kutanga kweiyo boot copier.
4. Yakanaka dhizaini tsika inosanganisira kuseta reset vector offset pamuganho weflash sector kuti uone kuti hapana kudzima chikamu chemufananidzo weFPGA kunoitika kana software ikagadziridzwa.

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4.4.2.2. Nios V processor Bootloader kuburikidza neSecure Device Manager
Iyo Bootloader kuburikidza Yakachengeteka Chishandiso Maneja (SDM) iHAL application kodhi inoshandisa Mailbox Client Altera FPGA IP HAL mutyairi we processor booting. Altera inokurudzira iyi bootloader application kana uchishandisa iyo yekumisikidza QSPI flash muSDM-based zvishandiso kubhuya Nios V processor.
Pamusoro pekugadzirisa zvakare, iyo Nios V processor inotanga kubhutsu Bootloader kuburikidza neSDM kubva padiki pa-chip memory uye inoita iyo Bootloader kuburikidza neSDM kutaurirana neiyo QSPI dhizaini uchishandisa iyo Mailbox Client IP.
Iyo Bootloader kuburikidza neSDM inoita mabasa anotevera: · Inotsvaga iyo Nios V software mukugadzirisa QSPI flash. · Inokopa iyo Nios V software mu-on-chip RAM kana yekunze RAM. · Inochinja mashandiro e processor kuNios V software mukati me-chip RAM kana
kunze RAM.
Kana maitiro apera, Bootloader kuburikidza neSDM inotamisa chirongwa chekutonga pamusoro pemushandisi application. Altera inokurudzira sangano rekuyeuka sezvakatsanangurwa muMemory Organization yeBootloader kuburikidza neSDM.
Mufananidzo 30. Bootloader kuburikidza neSDM Process Flow

Configuration

Flash

Nios V Software

SDM

SDM-Yakavakirwa FPGA Chishandiso

Mailbox Client IP

FPGA Logic Nios V

4 Kunze RAM
Nios V Software

On-Chip 4

EMIF

RAM

On-Chip Memory

Nios V

Software

Bootloader kuburikidza neSDM

1. Nios V processor inoshandisa Bootloader kuburikidza neSDM kubva pane-chip memory.
2. Bootloader kuburikidza neSDM inotaurirana nekugadzirisa flash uye inotsvaga Nios V software.
3. Bootloader kuburikidza neSDM inokopa Nios V software kubva paKugadzirisa Flash mu-chip RAM / kunze RAM.
4. Bootloader kuburikidza neSDM inoshandura Nios V processor execution kune Nios V software mune-chip RAM / kunze RAM.

4.4.3. Nios V processor Application Execute-In-Nzvimbo kubva kuOCRAM
Nenzira iyi, iyo Nios V processor reset kero yakaiswa kune base kero ye-on-chip memory (OCRAM). The application binary (.hex) file inoiswa muOCRAM kana FPGA yagadziriswa, mushure mekunge dhizaini yehardware yaumbwa muQuartus Prime software. Kana iyo Nios V processor ikagadziridza, application inotanga kuita uye matavi kunzvimbo yekupinda.

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Cherechedza:

* Execute-In-Place kubva kuOCRAM haidi boot copier nekuti Nios V processor application yatove panzvimbo pakugadzirisa system.
· Altera inokurudzira kugonesa alt_load() yeiyi nzira yekubhuta kuitira kuti software yakamisikidzwa iite zvakafanana kana ikagadziridzwa pasina kugadzirisa zvakare mufananidzo weFPGA mudziyo.
· Unofanira kugonesa alt_load() basa muBSP Settings kukopa .rwdata chikamu pakugadzirisa zvakare system. Munzira iyi, maitiro ekutanga ezvinyorwa zvekutanga anochengetwa zvakasiyana kubva kune zvakasiyana-siyana kuti arege kunyorera pamusoro pekuita kwepurogiramu.

4.4.4. Nios V processor Application Execute-In-Nzvimbo kubva kuTCM
Iyo yekuuraya-mu-nzvimbo nzira inoseta iyo Nios V processor reset kero kune base kero yeyakasimba yakabatana memory (TCM). The application binary (.hex) file inoiswa muTCM kana iwe uchigadzirisa iyo FPGA mushure mekunyora dhizaini yehardware muQuartus Prime software. Kana iyo Nios V processor ikagadziridza, application inotanga kuita uye matavi kunzvimbo yekupinda.

Cherechedza:

Execute-In-Place kubva kuTCM haidi boot copier nekuti Nios V processor application yatove panzvimbo pakugadzirisa system.

4.5. Nios V Processor Booting kubva kuOn-Chip Flash (UFM)

Nios V processor booting uye kuuraya software kubva pa-chip flash (UFM) inowanikwa muMAX 10 FPGA zvishandiso. Iyo Nios V processor inotsigira maviri anotevera mabhutsu sarudzo uchishandisa On-Chip Flash pasi peInternal Configuration mode:
· Nios V processor application inoita-munzvimbo kubva kuOn-Chip Flash.
· Nios V processor application inokopwa kubva kuOn-Chip Flash kuenda kuRAM uchishandisa boot copier.

Tafura 33. Inotsigirwa Flash Memories pamwe neBoot Options

Inotsigirwa Boot Memories

Nios V Booting Nzira

Application Runtime Nzvimbo

Boot Copier

MAX 10 zvishandiso chete (ine OnChip Flash IP)

Nios V processor application executein-nzvimbo kubva On-Chip Flash
Nios V processor application yakakopwa kubva kuOn-Chip Flash kuenda kuRAM uchishandisa boot copier

On-Chip Flash (XIP) + OCRAM/ Ekunze RAM (yezvikamu zve data zvinonyorwa)

alt_load () basa

OCRAM/Kunze RAM

Kushandisazve Bootloader kuburikidza neGSFI

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Mufananidzo 31.

Dhizaini, Configuration, uye Booting Flow
Dhizaini · Gadzira yako Nios V processor yakavakirwa purojekiti uchishandisa Platform Dhizaini. · Ita shuwa kuti kune yekunze RAM kana pa-chip RAM mune sisitimu dhizaini.

FPGA Kugadzirisa uye Kubatanidza
Seta iyo yakafanana yemukati yekumisikidza modhi muOn-chip Flash IP muPlatform Dhizaini uye Quartus Prime software. Set Nios V processor reset agent kuOn-chip Flash. · Sarudza yako yaunofarira UFM yekutanga nzira. · Gadzira dhizaini yako muPlatform Designer. · Unganidza purojekiti yako muQuartus Prime software.

Mushandisi Kushandisa BSP Project · Gadzira Nios V processor HAL BSP zvichibva pa.sopcinfo file yakagadzirwa nePlatform Designer. * Rongedza Nios V processor BSP marongero uye Linker Script muBSP Mharidzo. · Gadzira BSP chirongwa.
Mushandisi Yekushandisa APP Project · Gadzira Nios V processor application kodhi. · Unganidza Nios V processor application uye gadzira Nios V processor application (.hex) file. · Dzokorora purojekiti yako muQuartus Prime software kana iwe ukatarisa Tanga ndangariro yemukati sarudzo muIntel FPGA On-Chip Flash IP.

Programming Files Shanduko, Dhawunirodha uye Mhanya · Gadzira iyo On-Chip Flash .pof file uchishandisa Convert Programming Files chimiro muQuartus Prime software.
· Chirongwa .pof file mune yako MAX 10 mudziyo. · Simba kutenderera Hardware yako.
4.5.1. MAX 10 FPGA On-Chip Flash Tsananguro
MAX 10 FPGA zvishandiso zvine on-chip flash iyo yakakamurwa kuita zvikamu zviviri: · Configuration Flash Memory (CFM) - inochengeta iyo hardware yekumisikidza data ye
MAX 10 FPGAs. * Mushandisi Flash Memory (UFM) - inochengeta data remushandisi kana software yekushandisa.
Iyo UFM dhizaini yeMAX 10 mudziyo musanganiswa weakapfava uye akaoma IPs. Unogona chete kuwana UFM uchishandisa On-Chip Flash IP Core muQuartus Prime software.
Iyo On-chip Flash IP musimboti inotsigira zvinotevera maficha: · Kuverenga kana kunyora masvikiro kuUFM neCFM (kana yakagoneswa muPlatform Designer) zvikamu.
uchishandisa iyo Avalon MM data uye kudzora muranda interface. · Inotsigira kudzima peji, kudzima chikamu uye kunyora kwechikamu. · Simulation modhi yeUFM yekuverenga / kunyora inowanikwa uchishandisa akasiyana EDA simulation maturusi.

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Tafura 34. On-chip Flash Regions muMAX 10 FPGA Devices

Flash Regions

Kushanda

Kugadzirisa Flash Memory (zvikamu CFM0-2)

FPGA kugadzirisa file storage

Mushandisi Flash Memory (zvikamu UFM0-1)

Nios V processor application uye data yemushandisi

MAX 10 FPGA zvishandiso zvinotsigira akati wandei ekumisikidza modhi uye mamwe eaya modhi inobvumira CFM1 uye CFM2 kushandiswa seimwe yekuwedzera UFM dunhu. Tafura inotevera inoratidza nzvimbo yekuchengetera iyo FPGA yekumisikidza mifananidzo yakavakirwa paMAX 10 FPGA's magadzirirwo modhi.

Tafura 35. Nzvimbo yekuchengetedza yeFPGA Configuration Images

Configuration Mode Mapikicha akamanikidzwa maviri

CFM2 Yakadzvanywa Mufananidzo 2

CFM1

CFM0 Yakadzvanywa Mufananidzo 1

Mufananidzo mumwe chete usina kumisikidzwa

Virtual UFM

Mufananidzo usina kudzvanywa

Mufananidzo mumwe usina kudzvanywa une Memory Initialization

Mufananidzo usina kuomeswa (une pre-yakatanga pa-chip memory yemukati)

Imwe chete yakamanikidzwa mufananidzo ine Memory Initialization Yakadzvanywa mufananidzo (ine pre-yakatanga pa-chip memory yemukati)

Single compressed image

Virtual UFM

Compressed Image

Iwe unofanirwa kushandisa iyo On-chip Flash IP musimboti kuti uwane kune iyo flash memory muMAX 10 FPGAs. Iwe unogona kusimbisa uye kubatanidza iyo On-chip Flash IP kune Quartus Prime software. Iyo Nios V yakapfava core processor inoshandisa iyo Platform Dhizaini inobatana kuti itaure neOn-chip Flash IP.
Mufananidzo 32. Kubatana pakati peOn-chip Flash IP uye Nios V Processor

Cherechedza:

Ita shuwa kuti On-chip Flash csr port yakabatana neNios V processor data_manager kugonesa processor kudzora kunyora uye kudzima mashandiro.
Iyo On-chip Flash IP musimboti inogona kupa mukana kune mashanu flash sectors - UFM0, UFM1, CFM0, CFM1, uye CFM2.
Ruzivo rwakakosha nezve UFM neCFM zvikamu.: · CFM zvikamu zvakagadzirirwa kugadzirisa (bitstream) data (*.pof) kuchengetedza.
· Data yemushandisi inogona kuchengetwa muzvikamu zveUFM uye inogona kuvanzwa, kana zvigadziriso zvakasarudzwa muPlatform Designer tool.
· Mimwe michina haina UFM1 chikamu. Iwe unogona kureva tafura: UFM uye CFM Sector Saizi yezvikamu zviripo mune yega yega MAX 10 FPGA mudziyo.

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· Unogona kumisikidza CFM2 senge yeUFM chaiyo nekusarudza Imwe chete isina kuomeswa mufananidzo kumisikidzwa modhi.
· Unogona kumisikidza CFM2 uye CFM1 senge UFM chaiyo nekusarudza Imwe Usina Kuomeswa Chimiro chekumisikidza modhi.
· Saizi yechikamu chimwe nechimwe inosiyana neakasarudzwa MAX 10 FPGA zvishandiso.

Tafura 36.

UFM uye CFM Chikamu Saizi
Tafura iyi inonyora zviyero zveUFM neCFM arrays.

Mudziyo

Mapeji paSector

UFM1 UFM0 CFM2 CFM1 CFM0

Saizi Yepeji (Kbit)

Maximum User
Flash Memory Size (Kbit) (3)

Yese Yekugadzirisa Memory Size (Kbit)

10m02 3

34 16

544

10m04 0

41 29 70 16

1248

2240

10m08 8

41 29 70 16

1376

2240

10m16 4

38 28 66 32

2368

4224

10m25 4

52 40 92 32

3200

5888

10m40 4

48 36 84 64

5888

10752

10m50 4

48 36 84 64

5888

10752

OCRAM Size (Kbit)
108 189 378 549 675 1260 1638

Ruzivo rwunoenderana · MAX 10 FPGA Configuration User Guide · Altera MAX 10 User Flash Memory User Guide

4.5.2. Nios V processor Chikumbiro Chengetedza-In-Nzvimbo kubva kuUFM

Iyo Execute-In-Nzvimbo kubva kuUFM mhinduro inokodzera Nios V processor maapplication ayo anoda mashoma pa-chip memory kushandiswa. The alt_load() basa rinoshanda se mini boot copier iyo inokopa zvikamu zve data (.rodata, .rwdata, kana .exceptions) kubva pa boot memory kuenda ku RAM zvichienderana neBSP marongero. Chikamu chekodhi (.text),
inova chikamu chekuverenga chete, inoramba iri muMAX 10 On-chip Flash memory dunhu. Kuseta uku kunoderedza kushandiswa kweRAM asi kunogona kudzikisira kodhi dhizaini sezvo kuwana kune flash memory kunononoka pane pa-chip RAM.

Iyo Nios V processor application yakarongerwa muchikamu cheUFM. Iyo Nios V processor's reset vector inonongedza kuUFM base kero kuti iite kodhi kubva kuUFM mushure mekugadzirisa system.

Kana iwe uri kushandisa iyo source-level debugger kugadzirisa application yako, unofanirwa kushandisa hardware breakpoint. Izvi zvinodaro nekuti iyo UFM haitsigire isina kujairika ndangariro yekuwana, iyo inodiwa kune yakapfava breakpoint debugging.

Cherechedza:

Iwe haugone kudzima kana kunyora UFM paunenge uchiita execute-mu-nzvimbo muMAX 10. Chinja kune boot copier nzira kana uchida kudzima kana kunyora UFM.

(3) Iyo yakanyanya kukosha kukosha, iyo inotsamira pane yekumisikidza mode yaunosarudza.

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Mufananidzo 33. Nios V Processor Application XIP kubva kuUFM

Max 10 Chishandiso

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

On-Chip Flash

CFM

Nios V Hardware

UFM

Nios V Software

Internal Configuration

On-Chip Flash IP

FPGA Logic
Nios V processor

On-Chip RAM

External

RAM

EMIF

4.5.2.1. Hardware Dhizaini Flow
Chikamu chinotevera chinotsanangura nhanho-ne-nhanho nzira yekuvaka bootable sisitimu yeNios V processor application kubva kuOn-Chip Flash. The exampLe pazasi inovakwa uchishandisa MAX 10 mudziyo.
IP Component Settings
1. Gadzira yako Nios V processor project uchishandisa Quartus Prime uye Platform Designer. 2. Ita chokwadi chekunze RAM kana On-Chip Memory (OCRAM) inowedzerwa kuPlatform yako
Mugadziri system.

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Mufananidzo 34. Example IP Kubatanidza muPlatform Dhizaini yeBoot Nios V kubva kuOnChip Flash (UFM)

3. MuOn-Chip Flash IP parameter editor, isa iyo Configuration Mode kune imwe yezvinotevera, maererano nesarudzo yako yekugadzira: · Single Uncompressed Image · Single Compressed Image · Single Uncompressed Image with Memory Initialization · Single Compressed Image with Memory Initialization.
Kuti uwane rumwe ruzivo nezve Dual Compressed Images, tarisa iyo MAX 10 FPGA Configuration User Guide - Remote System Kukwidziridza.

Cherechedza:

Iwe unofanirwa kugovera Yakavanzika Kuwana kune ese eCFM matunhu muOn-Chip Flash IP.

Mufananidzo 35. Kugadzirisa Mode Kusarudzwa muOn-Chip Flash Parameter Editor

On-Chip Flash IP Settings - UFM Initialization Unogona kusarudza imwe yeinotevera nzira zvinoenderana nezvaunoda:

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Cherechedza:

Matanho ari mune anotevera subchapters (Software Dhizaini Kuyerera uye Chirongwa) zvinoenderana nesarudzo yaunoita pano.

· Nzira 1: Tanga iyo UFM data muSOF panguva yekuunganidza
Quartus Prime inosanganisira iyo UFM yekutanga data muSOF panguva yekuunganidza. SOF recompilation inodiwa kana paine shanduko muUFM data.
1. Tarisa Tangai kupenya kwemukati uye Gonesa kusiri-default kutanga file.

Mufananidzo 36. Tanga Flash Contents uye Gonesa Non-default Initialization File

2. Taura nzira yezvakagadzirwa .hex file (kubva pamurairo elf2hex) muMushandisi akasika hex kana mif file.
Mufananidzo 37. Kuwedzera .hex File Path

· Nzira yechipiri: Sanganisa data yeUFM neSOF yakaunganidzwa panguva yePOF chizvarwa
UFM dhata inosanganiswa neiyo yakaunganidzwa SOF paunenge uchishandura hurongwa files. Iwe haufanire kudzosera iyo SOF, kunyangwe iyo UFM data yachinja. Panguva yekuvandudza, haufanirwe kudzorera SOF files yekuchinja mukushandisa. Alterarecommers nzira iyi kune vanogadzira application.
1. Uncheck Tanga flash content..
Mufananidzo 38. Tanga Flash Content neNon-default Initialization File

Reset Agent Settings yeNios V Processor Execute-In-Place Method
1. MuNios V processor parameter editor, isa Reset Agent kune On-Chip Flash.
Mufananidzo 39. Nios V Processor Parameter Editor Zvirongwa neReset Agent Set to On-Chip Flash.

2. Dzvanya Gadzira HDL apo Generation dialog box inooneka. 3. Taura zvakabuda file chizvarwa sarudzo uye tinya Gadzira.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Dzvanya OK kuti ubudise Device uye Pin Options hwindo,
3. Click OK kuti abude Device hwindo.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Cherechedza:

Kana iyo yekumisikidza modhi yekumisikidza muQuartus Prime software uye Platform Dhizaini paramende inosiyana, iyo Quartus Prime purojekiti inotadza neinotevera mhosho meseji.

Mufananidzo 41.

Mharidzo Yemhosho kune Yakasiyana Configuration Mode Setting Error (14740): Configuration mode paatomu "q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block|ufm_block" haienderane negadziriro yeparutivi. Gadziridza uye gadzirazve iyo Qsys system kuti ienderane negadziriro yeprojekiti.

Ruzivo Rwakabatana MAX 10 FPGA Configuration User Guide

4.5.2.2. Software Dhizaini Flow
Ichi chikamu chinopa kuyerera kwedhizaini kugadzira nekuvaka iyo Nios V processor software chirongwa. Kuti uve nechokwadi chekuyerera kwekuvaka kwakakwenenzverwa, unokurudzirwa kugadzira yakafanana dhairekitori muti mune yako dhizaini purojekiti. Iyo inotevera software dhizaini inoyerera yakavakirwa pane ino dhairekitori muti.
Kugadzira iyo software yeprojekiti dhairekitori muti, tevera matanho aya: 1. Mune yako dhizaini dhizaini folda, gadzira folda inonzi software. 2. Muchirongwa chepurogiramu, gadzira mapepa maviri anonzi hal_app uye hal_bsp.
Mufananidzo 42. Software Project Directory Tree

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Kugadzira iyo Yekushandisa BSP Project
Kuti utange BSP Editor, tevera matanho aya: 1. Pinda Nios V Command Shell. 2. Koka BSP Mupepeti ne niosv-bsp-editor command. 3. MuBSP Editor, tinya File BSP nyowani yekutanga BSP yako chirongwa. 4. Gadzirisa zvinotevera marongero:
· SOPC Ruzivo File zita: Ipa iyo SOPCINFO file (.sopcinfo). · CPU zita: Sarudza Nios V processor. · Operating system: Sarudza iyo inoshanda sisitimu yeNios V processor. · Shanduro: Siya seyakagadzika. · BSP chinangwa dhairekitori: Sarudza dhairekitori nzira yeBSP chirongwa. Unogona
pre-iise pa /software/hal_bsp nekugonesa Shandisa nzvimbo dzakasarudzika. · BSP Zvirongwa File zita: Nyora zita reBSP Settings File. · Mamwe manyoro eTcl: Ipa BSP Tcl script nekugonesa Gonesa Yekuwedzera Tcl script. 5. Dzvanya OK.
Mufananidzo 43. Gadzira Itsva BSP

Kugadzirisa iyo BSP Mharidzo uye Kugadzira iyo BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Shandura Programming Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Settings
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file kutendeuka.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Cherechedza:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Max 10 Chishandiso

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

Kunze RAM
Nios V Software

On-Chip Flash

CFM

Nios V Hardwa

Zvinyorwa / Zvishandiso

altera Nios V Embedded Processor [pdf] Bhuku reMushandisi
Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

References

User Manual

altera Nios V Embedded Processor

Zvinotsanangurwa

Nios V Processor Hardware System Design

Nios V Processor Software System Design

Nios V Processor Configuration and Booting Solutions

Zvinyorwa / Zvishandiso

References

Siya mhinduro

Kanzura mhinduro