altera Nios V Embedded Processor User Guide

Hais txog Nios® V Embedded Processor
1.1. Altera® FPGA thiab Embedded Processors Tshajview
Altera FPGA cov khoom siv tuaj yeem siv cov logic uas ua haujlwm ua tiav microprocessor thaum muab ntau txoj hauv kev.
Ib qho tseem ceeb sib txawv ntawm discrete microprocessors thiab Altera FPGA yog tias Altera FPGA ntaub tsis muaj logic thaum nws powers. Nios® V processor yog cov cuab yeej txawj ntse (IP) processor raws li RISC-V specification. Ua ntej koj khiav software ntawm Nios V processor raws li qhov system, koj yuav tsum teeb tsa Altera FPGA ntaus ntawv nrog cov khoom siv kho vajtse uas muaj Nios V processor. Koj tuaj yeem tso Nios V processor nyob qhov twg ntawm Altera FPGA, nyob ntawm qhov yuav tsum tau ua ntawm tus tsim.

Txhawm rau ua kom koj lub Altera® FPGA IP-raws li kev teeb tsa kom coj tus cwj pwm tsis zoo ntawm microprocessor, koj lub cev yuav tsum suav nrog cov hauv qab no: · AJTAG interface los txhawb Altera FPGA configuration, kho vajtse thiab software
debugging · Lub zog-up Altera FPGA configuration mechanism
Yog tias koj lub kaw lus muaj cov peev txheej no, koj tuaj yeem pib kho koj tus qauv tsim los ntawm kev tsim kho kho vajtse ua ntej thauj khoom hauv Altera FPGA. Siv Altera FPGA kuj tso cai rau koj hloov kho koj tus qauv sai sai los daws cov teeb meem lossis ntxiv cov haujlwm tshiab. Koj tuaj yeem sim cov qauv kho vajtse tshiab no yooj yim los ntawm kev teeb tsa Altera FPGA siv koj lub cev JTAG interface.
Tus J.TAG interface txhawb kho vajtse thiab software txhim kho. Koj tuaj yeem ua cov haujlwm hauv qab no siv JTAG interface: · Configure the Altera FPGA · Download and debug software · Sib txuas lus nrog Altera FPGA los ntawm UART-zoo li interface (JTAG UART
davhlau ya nyob twg) · Debug kho vajtse (nrog rau lub Signal Tap embedded logic analyzer) · Program flash nco
Tom qab koj teeb tsa Altera FPGA nrog Nios V processor-based tsim, software txhim kho ntws zoo ib yam li cov dej ntws rau cov qauv tsim microcontroller.

Related Information · AN 985: Nios V Processor Tutorial
Daim ntawv qhia pib sai txog kev tsim Nios V processor yooj yim thiab khiav daim ntawv thov Hello World.
© Altera Corporation. Altera, Altera logo, 'a' logo, thiab lwm yam Altera cov cim yog cov cim lag luam ntawm Altera Corporation. Altera muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Altera xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, khoom, lossis kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo los ntawm kev sau ntawv los ntawm Altera. Altera cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

1. Hais txog Nios® V Embedded Processor 726952 | 2025.07.16
· Nios V Processor Reference Manual Muab cov ntaub ntawv hais txog Nios V processor kev ua tau zoo ntawm cov qauv, processor architecture, cov qauv kev ua haujlwm, thiab cov kev siv tseem ceeb.
· Embedded Peripherals IP User Guide · Nios V Processor Software Developer Handbook

Piav qhia txog Nios V processor software txhim kho ib puag ncig, cov cuab yeej uas muaj, thiab cov txheej txheem tsim software los khiav ntawm Nios V processor. · Ashling* RiscFree* Integrated Development Environment (IDE) for Altera FPGAs User Guide Piav qhia txog RiscFree* integrated development environment (IDE) for Altera FPGAs Arm*-based HPS and Nios V core processor. · Nios V Processor Altera FPGA IP Tso Lus Sau
1.2. Quartus® Prime Software Support
Nios V processor tsim ntws txawv rau Quartus® Prime Pro Edition software thiab Quartus Prime Standard Edition software. Xa mus rau AN 980: Nios V Processor Quartus Prime Software Txhawb nqa kom paub ntau ntxiv txog qhov sib txawv.
Cov ntaub ntawv ntsig txog AN 980: Nios V Processor Quartus Prime Software Support
1.3. Nios V Processor Licensing
Txhua Nios V processor variant muaj nws daim ntawv tso cai yuam sij. Thaum koj tau txais daim ntawv tso cai tus yuam sij, koj tuaj yeem siv tib daim ntawv tso cai yuam sij rau tag nrho Nios V processor project kom txog rau thaum hnub tas sij hawm. Koj tuaj yeem tau txais Nios V Processor Altera FPGA IP daim ntawv tso cai ntawm tus nqi xoom.
Nios V processor daim ntawv tso cai daim ntawv tso cai muaj nyob rau hauv Altera FPGA Self-Service Licensing Center. Nyem qhov Sau npe rau kev ntsuam xyuas lossis Daim Ntawv Tso Cai Dawb tab, thiab xaiv cov kev xaiv sib xws los ua qhov kev thov.
Daim duab 1. Altera FPGA Self-Service Licensing Center

Nrog rau daim ntawv tso cai yuam sij, koj tuaj yeem:
Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 7

1. Hais txog Nios® V Embedded Processor 726952 | 2025.07.16
· Siv Nios V processor hauv koj lub cev. · Simulate tus cwj pwm ntawm Nios V processor system. · Txheeb xyuas qhov kev ua haujlwm ntawm tus tsim, xws li qhov loj thiab ceev. · Tsim cov cuab yeej programming files. · Program ib lub cuab yeej thiab txheeb xyuas qhov tsim hauv kho vajtse.
Koj tsis tas yuav muaj daim ntawv tso cai los tsim software hauv Ashling* RiscFree* IDE rau Altera FPGAs.
Cov ntaub ntawv ntsig txog · Altera FPGA Self-Service Licensing Center
Yog xav paub ntxiv txog kev tau txais Nios V Processor Altera FPGA IP daim ntawv tso cai yuam sij. · Altera FPGA Software Installation thiab Licensing Yog xav paub ntxiv txog kev tso cai rau Altera FPGA software thiab teeb tsa ib daim ntawv tso cai ruaj khov thiab cov ntawv tso cai network server.
1.4. Embedded System Design
Cov duab hauv qab no qhia txog qhov yooj yim Nios V processor raws li kev tsim qauv ntws, suav nrog kev txhim kho kho vajtse thiab software.

Nios® V Embedded Processor Design Phau Ntawv 8

Xa lus tawm tswv yim

1. Hais txog Nios® V Embedded Processor 726952 | 2025.07.16

Daim duab 2.

Nios V Processor System Design Flow
Lub tswvyim

Txheeb xyuas qhov System Requirements

Nios® V
Processor Cores thiab Standard Cheebtsam

Txhais thiab tsim System hauv
Platform Designer

Hardware Flow: Integrate thiab Compile Intel Quartus Prime Project

Software Flow: Tsim thiab Tsim Nios V Proposal Software

Hardware Flow: Download FPGA Tsim
rau Target Board

Software Flow: Test thiab Debug Nios V Processor Software

Software Tsis Tau Raws li Spec?
Yog lawm
Hardware Tsis Muaj Raws li Spec? Yog lawm
Ua kom tiav

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 9

726952 | 2025.07.16 Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer

Daim duab 3.

Cov duab hauv qab no qhia txog cov qauv Nios V processor hardware tsim. Nios V Processor System Hardware Design Flow

Pib

Nios V Cores thiab Standard Cheebtsam

Siv Platform Designer los tsim Nios V Based System
Tsim Platform Designer Design

Integrate Platform Designer System nrog Intel Quartus Prime Project
Muab Pin Qhov Chaw, Lub Sijhawm Yuav Tsum Tau, thiab lwm yam kev txwv tsim
Compile Hardware rau Lub Hom Phiaj Ntaus hauv Intel Quartus Prime

Npaj kom Download
2.1. Tsim Nios V Processor System Tsim nrog Platform Designer
Quartus Prime software suav nrog Platform Designer system kev sib koom ua ke uas ua kom yooj yim rau txoj haujlwm ntawm kev txhais thiab kev koom ua ke Nios V processor IP core thiab lwm tus IPs rau hauv Altera FPGA system tsim. Lub Platform Designer cia li tsim kev sib cuam tshuam logic los ntawm cov txheej txheem kev sib txuas siab. Lub interconnect automation tshem tawm lub sij hawm-siv txoj hauj lwm ntawm kev qhia txog qhov system-level HDL kev sib txuas.
© Altera Corporation. Altera, Altera logo, 'a' logo, thiab lwm yam Altera cov cim yog cov cim lag luam ntawm Altera Corporation. Altera muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Altera xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, khoom, lossis kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo los ntawm kev sau ntawv los ntawm Altera. Altera cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Tom qab txheeb xyuas cov txheej txheem kho vajtse, koj siv Quartus Prime los qhia txog Nios V processor core, nco, thiab lwm yam uas koj lub cev xav tau. Lub Platform Designer cia li tsim cov kev sib txuas lus sib txuas los ua ke cov khoom hauv cov khoom siv kho vajtse.

2.1.1. Instantiating Nios V Processor Altera FPGA IP

Koj tuaj yeem instantiate ib qho ntawm cov processor IP cores hauv Platform Designer IP Catalog Processors thiab Peripherals Embedded Processors.

Cov tub ntxhais IP ntawm txhua tus processor txhawb kev xaiv sib txawv raws li nws qhov tshwj xeeb architecture. Koj tuaj yeem txhais cov kev teeb tsa no kom zoo dua rau koj cov kev xav tau tsim.

Table 1.

Configuration Options Hla Core Variants

Configuration Options

Nios V/c Processor

Nios V/m Processor

Debug Siv Reset Thov

—

Traps, Exceptions, thiab Interrupts

CPU Architecture

ECC

Caches, Peripheral Regions thiab TCMs

—

Cov lus qhia kev cai

—

Lockstep

—

Nios V/g Processor

2.1.1.1 ib. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Daim duab 4. Nios V/c Compact Microcontroller Altera FPGA IP

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 11

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

2.1.1.1.1 ib. CPU Architecture Tab

Table 2.

CPU Architecture Tab

Feature

Kev piav qhia

Qhib Avalon® Interface Enables Avalon Interface rau tus thawj tswj kev qhia thiab tus thawj tswj ntaub ntawv. Yog tias tsis ua haujlwm, lub kaw lus siv AXI4-Lite interface.

mhartid CSR tus nqi

· Kev xaiv IP tsis raug. · Tsis txhob siv mhartid CSR tus nqi hauv Nios V/c processor.

2.1.1.1.2. Siv Reset Request Tab

Table 3.

Siv Reset Request Tab Parameter

Siv Reset Request Tab

Kev piav qhia

Ntxiv Reset Request Interface

· Pab kom qhov kev xaiv no nthuav tawm cov chaw nres nkoj hauv zos uas tus tswv hauv zos tuaj yeem siv nws los ua rau Nios V processor kom rov pib dua yam tsis muaj kev cuam tshuam lwm yam hauv Nios V processor system.
· Lub reset interface muaj ib lub input resetreq teeb liab thiab ib tug tso zis ack teeb liab.
· Koj tuaj yeem thov rov pib dua rau Nios V processor core los ntawm kev lees paub lub teeb liab resetreq.
· Lub teeb liab resetreq yuav tsum nyob twj ywm kom txog thaum lub processor lees tias ack teeb liab. Kev ua tsis tiav rau lub teeb liab kom nyob twj ywm tuaj yeem ua rau lub processor nyob rau hauv lub xeev tsis txiav txim siab.
· Nios V processor teb tias qhov rov pib dua tau ua tiav los ntawm kev lees paub lub teeb liab ack.
· Tom qab lub processor tau ua tiav rov pib dua, qhov kev lees paub ntawm lub teeb liab ack tuaj yeem tshwm sim ntau zaus ib ntus kom txog thaum de-assertion ntawm lub teeb liab resetreq.

2.1.1.1.3. Traps, Exceptions, thiab Interrupts Tab

Table 4.

Traps, Exceptions, thiab Interrupts Tab Parameters

Traps, Exceptions, thiab Interrupts

Kev piav qhia

Rov pib tus neeg sawv cev

Pib dua Offset

· Qhia meej qhov offset ntawm qhov rov pib vector txheeb ze rau tus neeg sawv cev rov qab xaiv qhov chaw nyob. · Platform Designer cia li muab tus nqi pib rau qhov rov pib dua offset.

Nco tseg:

Platform Designer muab qhov kev xaiv tsis meej, uas tso cai rau koj los qhia meej qhov chaw nyob hauv Reset Offset. Siv qhov kev xaiv no thaum lub cim xeeb khaws cia rov pib dua vector nyob sab nraum lub processor thiab subsystems.

Nios® V Embedded Processor Design Phau Ntawv 12

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

2.1.1.1.4 ib. ECC Tab

Table 5.

ECC Tab

ECC

Pab kom paub qhov yuam kev thiab qhia txog xwm txheej

Kev piav qhia
· Pab kom qhov kev xaiv no siv ECC feature rau Nios V processor nrog RAM blocks. · ECC nta kuaj tau txog li 2-ntsis yuam kev thiab ua raws li tus cwj pwm hauv qab no:
- Yog tias nws yog qhov kho tau qhov yuam kev 1-ntsis, tus processor txuas ntxiv ua haujlwm tom qab kho qhov yuam kev hauv cov kav xa dej. Txawm li cas los xij, qhov kev kho tsis raug cuam tshuam los ntawm qhov chaw nco.
- Yog tias qhov ua yuam kev tsis tuaj yeem kho tau, tus txheej txheem txuas ntxiv ua haujlwm yam tsis tau kho nws hauv cov raj xa dej thiab qhov chaw nco, uas yuav ua rau tus processor nkag mus rau lub xeev tsis muaj kev txiav txim siab.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Daim duab 5. Nios V/m Microcontroller Altera FPGA IP

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 13

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

2.1.1.2.1. Debug Tab

Table 6.

Debug Tab Parameters

Debug Tab

Kev piav qhia

Pab kom Debug
Qhib Reset los ntawm Debug Module

· Pab kom qhov kev xaiv no ntxiv rau JTAG lub hom phiaj kev sib txuas module rau Nios V processor. · The JTAG lub hom phiaj kev sib txuas module tso cai txuas rau Nios V processor los ntawm
JTAG interface pins ntawm FPGA. · Kev sib txuas muab cov peev txheej hauv qab no:
- Pib thiab nres Nios V processor - Tshawb xyuas thiab kho cov ntawv sau npe thiab nco. - Rub tawm Nios V daim ntawv thov .elf file mus rau lub processor nco ntawm runtime ntawm
niosv-download. - Debug daim ntawv thov khiav ntawm Nios V processor · Txuas dm_agent chaw nres nkoj mus rau lub processor qhia thiab cov ntaub ntawv tsheb npav. Xyuas kom meej tias lub hauv paus chaw nyob ntawm ob lub npav yog tib yam.
· Pab kom qhov kev xaiv no nthuav tawm dbg_reset_out thiab ndm_reset_in ports. · JTAG debugger lossis niosv-download -r hais kom ua rau dbg_reset_out, uas
tso cai rau Nios V processor rov pib qhov system peripherals txuas rau qhov chaw nres nkoj no. · Koj yuav tsum txuas lub dbg_reset_out interface rau ndm_reset_in es tsis txhob pib dua
interface los ua kom rov pib dua processor core thiab timer module. Koj yuav tsum tsis txhob txuas dbg_reset_out interface los pib dua interface los tiv thaiv tus cwj pwm tsis meej.

2.1.1.2.2. Siv Reset Request Tab

Table 7.

Siv Reset Request Tab Parameter

Siv Reset Request Tab

Kev piav qhia

Ntxiv Reset Request Interface

· Pab kom qhov kev xaiv no nthuav tawm cov chaw nres nkoj hauv zos uas tus tswv hauv zos tuaj yeem siv nws los ua rau Nios V processor kom rov pib dua yam tsis muaj kev cuam tshuam lwm yam hauv Nios V processor system.
· Lub reset interface muaj ib lub input resetreq teeb liab thiab ib tug tso zis ack teeb liab.
· Koj tuaj yeem thov rov pib dua rau Nios V processor core los ntawm kev lees paub lub teeb liab resetreq.
· Lub teeb liab resetreq yuav tsum nyob twj ywm kom txog thaum lub processor lees tias ack teeb liab. Kev ua tsis tiav rau lub teeb liab kom nyob twj ywm tuaj yeem ua rau lub processor nyob rau hauv lub xeev tsis txiav txim siab.
· Kev lees paub ntawm lub teeb liab resetreq hauv hom kev debug tsis muaj kev cuam tshuam rau lub xeev processor.
· Nios V processor teb tias qhov rov pib dua tau ua tiav los ntawm kev lees paub lub teeb liab ack.
· Tom qab lub processor tau ua tiav rov pib dua, qhov kev lees paub ntawm lub teeb liab ack tuaj yeem tshwm sim ntau zaus ib ntus kom txog thaum de-assertion ntawm lub teeb liab resetreq.

2.1.1.2.3. Traps, Exceptions, thiab Interrupts Tab

Table 8.

Traps, Exceptions, thiab Interrupts Tab

Kev piav qhia

Rov pib tus neeg sawv cev

Pib dua Offset Interrupt hom

· Qhia meej qhov offset ntawm qhov rov pib vector txheeb ze rau tus neeg sawv cev rov qab xaiv qhov chaw nyob. · Platform Designer cia li muab tus nqi pib rau qhov rov pib dua offset.
Tshwj xeeb hom kev cuam tshuam xws li Direct lossis Vectored. Nco tseg: Nios V / m uas tsis yog-pipelined processor tsis txhawb Vectored cuam tshuam.
Yog li ntawd, tsis txhob siv Vectored cuam tshuam hom thaum lub processor nyob rau hauv Nonpipelined hom.

Nios® V Embedded Processor Design Phau Ntawv 14

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Nco tseg:

2.1.1.2.4 ib. CPU Architecture

Table 9.

CPU Architecture Tab Parameters

CPU Architecture

Kev piav qhia

Qhib Pipelining hauv CPU

· Pab kom qhov kev xaiv no los instantiate pipelined Nios V/m processor. - IPC yog siab dua ntawm tus nqi ntawm thaj tsam siab dua thiab qis Fmax zaus.
· Disable qhov kev xaiv no kom instantiate uas tsis yog-pipelined Nios V/m processor. - Muaj kev ua haujlwm zoo ib yam li Nios V/c processor. - Txhawb kev debugging thiab cuam tshuam muaj peev xwm - qis dua qhov chaw logic thiab siab dua Fmax zaus ntawm tus nqi qis IPC.

Qhib Avalon Interface

Enables Avalon Interface rau tus thawj tswj kev qhia thiab tus thawj tswj ntaub ntawv. Yog tias tsis ua haujlwm, lub kaw lus siv AXI4-Lite interface.

mhartid CSR tus nqi

· Hart ID sau npe (mhartid) tus nqi yog 0 ntawm lub neej ntawd. · Muab tus nqi ntawm 0 thiab 4094. · Tau tshaj Altera FPGA Avalon Mutex Core HAL API.

Cov ntaub ntawv ntsig txog Embedded Peripheral IP Tus Neeg Siv Qhia - Intel FPGA Avalon® Mutex Core

2.1.1.2.5 ib. ECC Tab
Table 10. ECC Tab
ECC Pab kom paub qhov yuam kev thiab qhia txog xwm txheej

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 15

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
2.1.1.3. Instantiating Nios V/g General Purpose Processor Altera FPGA IP
Daim duab 6. Nios V/g General Purpose Processor Altera FPGA IP – Part 1

Daim duab 7.

Nios V/g General Purpose Processor Altera FPGA IP - Ntu 2 (Tau Tawm Pab Cuam Tub Ntxhais Qib Interrupt Controller)

Nios® V Embedded Processor Design Phau Ntawv 16

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Daim duab 8.

Nios V/g General Purpose Processor Altera FPGA IP - Ntu 2 (Tig Rau Pab Txhawb Cov Tub Ntxhais Kawm Qib Siab)

Daim duab 9. Nios V/g General Purpose Processor Altera FPGA IP – Part 3

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 17

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
Daim duab 10. Nios V/g General Purpose Processor Altera FPGA IP – Part 4

2.1.1.3.1 ib. CPU Architecture

Table 11. CPU Architecture Parameters

CPU Architecture Tab Pab kom Floating Point Unit

Kev piav qhia Pab kom qhov kev xaiv no ntxiv rau chav nyob ntab ntab ("F" txuas ntxiv) hauv cov tub ntxhais processor.

Qhib Kev Txiav Txim Siab

Pab kom zoo li qub ceg twv twv (rov qab Taken thiab Forward Not Taken) rau ceg lus qhia.

mhartid CSR tus nqi

· Hart ID sau npe (mhartid) tus nqi yog 0 ntawm lub neej ntawd. · Muab tus nqi ntawm 0 thiab 4094. · Tau tshaj Altera FPGA Avalon Mutex Core HAL API.

Disable FSQRT & FDIV cov lus qhia rau FPU

· Tshem tawm floating-point square root (FSQRT) thiab floating-point division (FDIV) ua haujlwm hauv FPU.
· Siv software emulation ntawm ob cov lus qhia thaum lub sijhawm khiav.

Cov ntaub ntawv ntsig txog Embedded Peripheral IP Tus Neeg Siv Qhia - Intel FPGA Avalon® Mutex Core

Nios® V Embedded Processor Design Phau Ntawv 18

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

2.1.1.3.2. Debug Tab

Table 12. Debug Tab Parameters

Debug Tab

Kev piav qhia

Pab kom Debug
Qhib Reset los ntawm Debug Module

2.1.1.3.3. Lockstep Tab Table 13. Lockstep Tab
Parameters Enable Lockstep Default Timeout Period Enable Extended Reset Interface

Nqe lus piav qhia · Pab kom lub kaw lus dual core Lockstep. · Default value of programmable timeout on reset exit (nruab nrab 0 thiab 255). · Pab kom qhov kev xaiv ncua sij hawm rov pib dua Interface rau Extended Reset Control. · Thaum muaj kev xiam oob qhab, fRSmartComp siv Kev Tswj Xyuas Pib Pib dua.

2.1.1.3.4. Siv Reset Request Tab

Table 14. Siv Reset Request Tab Parameter

Siv Reset Request Tab

Kev piav qhia

Ntxiv Reset Request Interface

· Pab kom qhov kev xaiv no nthuav tawm cov chaw nres nkoj hauv zos uas tus tswv hauv zos tuaj yeem siv nws los ua rau Nios V processor kom rov pib dua yam tsis muaj kev cuam tshuam lwm yam hauv Nios V processor system.
· Lub reset interface muaj ib lub input resetreq teeb liab thiab ib tug tso zis ack teeb liab.
· Koj tuaj yeem thov rov pib dua rau Nios V processor core los ntawm kev lees paub lub teeb liab resetreq.
· Lub teeb liab resetreq yuav tsum nyob twj ywm kom txog thaum lub processor lees tias ack teeb liab. Kev ua tsis tiav rau lub teeb liab kom nyob twj ywm tuaj yeem ua rau lub processor nyob rau hauv lub xeev tsis txiav txim siab.
· Kev lees paub ntawm lub teeb liab resetreq hauv hom kev debug tsis muaj kev cuam tshuam rau lub xeev processor.
· Nios V processor teb tias qhov rov pib dua tau ua tiav los ntawm kev lees paub lub teeb liab ack.
· Tom qab lub processor tau ua tiav rov pib dua, qhov kev lees paub ntawm lub teeb liab ack tuaj yeem tshwm sim ntau zaus ib ntus kom txog thaum de-assertion ntawm lub teeb liab resetreq.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 19

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

2.1.1.3.5. Traps, Exceptions, thiab Interrupts Tab

Table 15.

Traps, Exceptions, thiab Interrupts Tab thaum Enable Core Level Interrupt Controller raug tua

Traps, Exceptions, thiab Interrupts Tab
Rov pib tus neeg sawv cev

Kev piav qhia
· Lub cim xeeb hosting lub rov pib vector (lub Nios V processor reset chaw nyob) qhov twg tus reset code nyob.
· Koj tuaj yeem xaiv ib qho kev nco module txuas nrog Nios V processor qhia tus tswv thiab txhawb nqa los ntawm Nios V processor boot flow raws li tus neeg sawv cev pib dua.

Pib dua Offset

· Qhia meej qhov offset ntawm qhov rov pib vector txheeb ze rau tus neeg sawv cev rov qab xaiv qhov chaw nyob. · Platform Designer cia li muab tus nqi pib rau qhov rov pib dua offset.

Qhib Core Level Interrupt Controller (CLIC)

· Pab CLIC los txhawb kev cuam tshuam ua ntej thiab kev cuam tshuam kev cuam tshuam.
· Thaum qhib, koj tuaj yeem teeb tsa tus lej ntawm lub platform cuam tshuam, teeb tsa cov xwm txheej tshwm sim, thiab xaiv qee qhov cuam tshuam ua ntej.

Interrupt hom duab ntxoov ntxoo sau npe Files

Qhia meej hom kev cuam tshuam raws li Direct, lossis Vectored Ua kom pom duab ntxoov ntxoo rau txo cov ntsiab lus hloov pauv thaum cuam tshuam.

Table 16.

Traps, Exceptions thiab Interrupts thaum Enable Core Level Interrupt Controller qhib

Traps, Exceptions, thiab Interrupts

Cov lus piav qhia

Rov pib tus neeg sawv cev
Pib dua Offset
Qhib Core Level Interrupt Controller (CLIC)

· Lub cim xeeb hosting lub rov pib vector (lub Nios V processor reset chaw nyob) qhov twg tus reset code nyob.
· Koj tuaj yeem xaiv ib qho kev nco module txuas nrog Nios V processor qhia tus tswv thiab txhawb nqa los ntawm Nios V processor boot flow raws li tus neeg sawv cev pib dua.
· Qhia meej qhov offset ntawm qhov rov pib vector txheeb ze rau tus neeg sawv cev rov qab xaiv qhov chaw nyob. · Platform Designer cia li muab tus nqi pib rau qhov rov pib dua offset.
· Pab CLIC los txhawb kev cuam tshuam ua ntej thiab kev cuam tshuam kev cuam tshuam. · Thaum qhib, koj tuaj yeem teeb tsa tus lej ntawm kev cuam tshuam lub platform, teeb tsa cov xwm txheej tshwm sim,
thiab xaiv qee qhov kev cuam tshuam ua ntej emptive.

Interrupt hom

· Qhia cov kev cuam tshuam xws li Direct, Vectored, lossis CLIC.

Duab ntxoov ntxoo sau npe Files

· Pab kom tus duab ntxoov ntxoo sau npe los txo cov ntsiab lus hloov pauv thaum cuam tshuam.
· Muaj ob txoj hauv kev:
- Tus naj npawb ntawm CLIC cuam tshuam theem
- Tus naj npawb ntawm CLIC cuam tshuam theem - 1: Qhov kev xaiv no muaj txiaj ntsig zoo thaum koj xav tau tus lej sau npe file cov ntawv luam kom haum rau tus naj npawb ntawm M20K lossis M9K blocks.
· Pab kom Nios V processor siv duab ntxoov ntxoo files uas txo cov ntsiab lus hloov pauv nyiaj siv ua haujlwm thaum cuam tshuam.
Yog xav paub ntxiv txog duab ntxoov ntxoo sau npe files, xa mus rau Nios V Processor Reference Manual.

Tus naj npawb ntawm Platform cuam tshuam qhov chaw

· Qhia txog tus lej ntawm lub platform cuam tshuam ntawm 16 txog 2048.
Nco tseg: CLIC txhawb nqa txog 2064 cuam tshuam cov khoom siv, thiab thawj 16 qhov cuam tshuam cov khoom siv kuj tseem txuas nrog tus tswj hwm cuam tshuam.

CLIC Vector Table Alignment

· Txiav txim siab raws li tus naj npawb ntawm cov platform cuam tshuam. · Yog tias koj siv qhov kev sib tw uas qis dua tus nqi pom zoo, CLIC nce logic
complexity los ntawm kev ntxiv ib tug ntxiv adder los ua vectoring xam. · Yog tias koj siv qhov kev sib tw uas qis dua tus nqi pom zoo, qhov no ua rau nce ntxiv
logic complexity hauv CLIC.
txuas ntxiv…

Nios® V Embedded Processor Design Phau Ntawv 20

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Traps, Exceptions, thiab Interrupts
Number of Interrupt Levels
Number of Interrupt Priorities ib theem
Configurable interrupt polarity Kev them nyiaj yug ntug triggered interrupts

Cov lus piav qhia
· Qhia cov lej ntawm kev cuam tshuam nrog qib 0 ntxiv rau daim ntawv thov code. Kev cuam tshuam ntawm qib siab tuaj yeem cuam tshuam (pre-empt) tus neeg khiav dej num rau kev cuam tshuam qis dua.
· Nrog tsis-zero interrupt theem raws li ib qho kev xaiv rau kev cuam tshuam, daim ntawv thov code yog ib txwm nyob rau hauv qis tshaj theem 0. Nco ntsoov: Khiav-lub sij hawm configuration ntawm ib tug interrupt theem thiab qhov tseem ceeb yog ua nyob rau hauv ib tug 8-ntsis register. Yog hais tias tus naj npawb ntawm kev cuam tshuam theem yog 256, nws tsis tuaj yeem teeb tsa qhov cuam tshuam qhov tseem ceeb ntawm lub sijhawm ua haujlwm. Txwv tsis pub, tus lej siab tshaj plaws ntawm kev teeb tsa ua ntej yog 256 / (tus lej ntawm kev cuam tshuam - 1).
· Qhia txog tus naj npawb ntawm kev cuam tshuam qhov tseem ceeb, uas CLIC siv los txiav txim qhov kev txiav txim uas tsis yog tus neeg ua haujlwm cuam tshuam ua ntej raug hu. Nco tseg: Concatenation ntawm binary qhov tseem ceeb ntawm cov kev xaiv cuam tshuam thiab xaiv qhov tseem ceeb cuam tshuam yuav tsum tsawg dua 8 khoom.
· Tso cai rau koj los teeb tsa kev cuam tshuam polarity thaum lub sijhawm ua haujlwm. · Default polarity yog polarity zoo.
· Tso cai rau koj los teeb tsa kev cuam tshuam cuam tshuam thaum lub sijhawm ua haujlwm, piv txwv li qib siab ua rau lossis qhov zoo-ntug tshwm sim (thaum cuam tshuam polarity yog qhov zoo hauv Configurable interrupt polarity).
· Default trigger condition yog theem triggered interrupt.

Nco tseg:

Cov ntaub ntawv ntsig txog Nios® V Processor Reference Manual

2.1.1.3.6. Memory Configurations Tab

Table 17. Memory Configuration Tab Parameters

Qeb

Memory Configuration Tab

Kev piav qhia

Caches

Cov ntaub ntawv Cache Loj

· Qhia qhov loj ntawm cov ntaub ntawv cache. · Qhov ntau thiab tsawg yog los ntawm 0 kilobytes (KB) txog 16 KB. · Tua cov ntaub ntawv cache thaum loj yog 0 KB.

Kev qhia Cache Loj

· Qhia qhov loj ntawm cov lus qhia cache. · Qhov ntau thiab tsawg yog los ntawm 0 KB txog 16 KB. · Tua tawm cov lus qhia cache thaum loj yog 0 KB.

Peripheral Region A thiab B

Loj

· Qhia qhov loj ntawm thaj tsam peripheral.
· Qhov ntau thiab tsawg yog los ntawm 64 KB txog 2 gigabytes (GB), lossis Tsis muaj. Xaiv Tsis Muaj lov tes taw cheeb tsam peripheral.

Chaw Nyob

· Qhia qhov chaw nyob hauv cheeb tsam peripheral tom qab koj xaiv qhov loj me.
· Txhua qhov chaw nyob hauv cheeb tsam peripheral tsim cov ntaub ntawv nkag tsis tau.
· Peripheral cheeb tsam hauv paus chaw nyob yuav tsum tau ua raws li cov cheeb tsam peripheral loj.

Tightly Coupled Memories

Loj

· Qhia qhov loj ntawm lub cim xeeb nruj. - Qhov ntau thiab tsawg yog los ntawm 0 MB txog 512 MB.

Base Chaw Nyob Initialization File

· Qhia qhov chaw nyob hauv paus ntawm lub cim xeeb nruj. · Qhia qhov pib file rau nruj-coupled nco.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 21

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Nco tseg:

Hauv Nios V processor system nrog cache enabled, koj yuav tsum tso qhov system peripherals nyob rau hauv ib cheeb tsam peripheral. Koj tuaj yeem siv cov cheeb tsam peripheral los txhais cov kev lag luam uas tsis yog cacheable rau cov khoom siv xws li UART, PIO, DMA, thiab lwm yam.

2.1.1.3.7 ib. ECC Tab

Table 18. ECC Tab
ECC Pab kom paub qhov yuam kev thiab qhia txog xwm txheej
Pab kom ib qho kho me ntsis

Kev piav qhia
· Pab kom qhov kev xaiv no siv ECC feature rau Nios V processor nrog RAM blocks. · ECC nta kuaj tau txog li 2-ntsis yuam kev thiab ua raws li tus cwj pwm hauv qab no:
- Yog tias nws yog qhov kho tau ib qho kev ua yuam kev me ntsis thiab Qhib Kev Kho Ib Leeg raug muab tua, tus txheej txheem txuas ntxiv ua haujlwm tom qab kho qhov yuam kev hauv cov raj xa dej. Txawm li cas los xij, qhov kev kho tsis raug cuam tshuam los ntawm qhov chaw nco.
- Yog tias nws yog qhov kho tau ib qho kev ua yuam kev me ntsis thiab Qhib Kev Kho Ib Leeg Ib Leeg tau qhib, tus txheej txheem txuas ntxiv ua haujlwm tom qab kho qhov yuam kev hauv cov raj xa hluav taws xob thiab cov chaw nco.
- Yog tias nws yog qhov ua yuam kev tsis raug, tus processor nres nws txoj haujlwm.
Qhib ib qho kev kho me ntsis ntawm embedded nco blocks hauv cov tub ntxhais.

2.1.1.3.8. Custom Instruction Tab

Nco tseg:

Cov tab no tsuas yog muaj rau Nios V/g processor core.

Custom Instruction Nios V Custom Instruction Hardware Interface Table
Nios V Custom Instruction Software Macro Table

Kev piav qhia
· Nios V processor siv cov lus no los txheeb xyuas nws cov kev cai qhia kev sib tham.
· Txhais tau hais tias kev cai tus thawj tswj xyuas interfaces yog cim encoded los ntawm ib tug Opcode (CUSTOM0-3) thiab 3 khoom ntawm funct7[6:4].
· Koj tuaj yeem txhais tau tag nrho ntawm 32 tus neeg saib xyuas kev cai qhia kev cuam tshuam.
· Nios V processor siv cov lus no yog siv los txheeb xyuas cov kev qhia kev cai software encodings rau cov kev cai qhia kev cai tswj kev cuam tshuam.
· Rau txhua qhov kev cai qhia kev cai software encoding, Opcode (CUSTOM0-3) thiab 3 cov khoom ntawm funct7[6:4] encoding yuav tsum sib raug rau cov kev cai qhia kev cai tswj xyuas interface encoding hauv Custom Instruction Hardware Interface Table.
· Koj tuaj yeem siv funct7[6:4], funct7[3:0], thiab funct3[2:0] los txhais cov encoding ntxiv rau cov lus qhia kev cai, lossis teev ua Xs kom dhau los ua cov lus qhia ntxiv.
· Nios V processor muab kev cai qhia kev cai software encodings raws li generated C-macros nyob rau hauv system.h, thiab ua raws li R-type RISC-V kev qhia hom ntawv.
· Mnemonics yuav raug siv los txhais cov npe kev cai rau: — C-Macros generated hauv system.h.
- Lub generated GDB debug mnemonics hauv custom_instruction_debug.xml.

Cov ntaub ntawv ntsig txog
AN 977: Nios V Processor Custom Instruction Xav paub ntau ntxiv txog cov lus qhia kev cai uas tso cai rau koj los hloov kho Nios® V processor kom tau raws li qhov xav tau ntawm ib daim ntawv thov tshwj xeeb.

Nios® V Embedded Processor Design Phau Ntawv 22

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
2.1.2. Defining System Component Design
Siv lub Platform Designer los txhais cov yam ntxwv kho vajtse ntawm Nios V processor system thiab ntxiv rau hauv cov khoom xav tau. Daim duab hauv qab no qhia txog qhov yooj yim Nios V processor system tsim nrog cov khoom hauv qab no: · Nios V processor core · On-Chip Memory · JTAG UART · Interval Timer (yeem)(1)
Thaum lub On-Chip Memory tshiab ntxiv rau lub Platform Designer system, ua Sync System Infos kom muaj kev cuam tshuam cov cim xeeb ntxiv hauv kev pib dua. Xwb, koj tuaj yeem ua kom Auto Sync hauv Platform Designer kom tau txais kev cuam tshuam cov kev hloov pauv tam sim no
Daim duab 11. Example kev sib txuas ntawm Nios V processor nrog rau lwm yam khoom siv hauv Platform Designer

(1) Koj muaj kev xaiv los siv Nios V Internal Timer nta los hloov lub sijhawm ncua sij hawm sab nraud hauv Platform Designer.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 23

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
Koj yuav tsum tau txhais cov haujlwm pins kom xa tawm raws li cov kav dej hauv koj lub Platform Designer system. Rau example, daim ntawv teev npe FPGA kev ua haujlwm tus pin raug txhais raws li hauv qab no tab sis tsis txwv rau:
· moos
· Rov pib dua
· I/O signals
2.1.3. Qhia qhov chaw nyob hauv paus thiab cuam tshuam kev thov ua ntej
Txhawm rau txheeb xyuas seb cov khoom sib txuas ntxiv li cas hauv kev tsim kev sib cuam tshuam los tsim ib qho system, koj yuav tsum tau muab cov chaw nyob hauv paus rau txhua tus neeg sawv cev tivthaiv thiab muab kev cuam tshuam kev thov (IRQ) qhov tseem ceeb rau JTAG UART thiab lub sijhawm ncua sijhawm. Lub Platform Designer muab cov lus txib - Assign Base Addresses - uas cia li muab cov chaw nyob hauv paus rau txhua yam hauv ib qho system. Txawm li cas los xij, koj tuaj yeem kho qhov chaw nyob raws li koj xav tau.
Cov hauv qab no yog qee cov lus qhia rau kev muab cov chaw nyob hauv paus:
· Nios V processor core muaj 32-ntsis chaw nyob ncua. Txhawm rau nkag mus rau tus neeg sawv cev cov khoom, lawv qhov chaw nyob yuav tsum nyob nruab nrab ntawm 0x00000000 thiab 0xFFFFFFFF.
· Nios V cov kev pab cuam siv cov cim tsis tu ncua kom xa mus rau qhov chaw nyob. Koj tsis tas yuav xaiv qhov chaw nyob uas yooj yim rau nco qab.
· Chaw nyob qhov tseem ceeb uas sib txawv cov khoom nrog tsuas yog ib qho chaw nyob qhov sib txawv tsim cov khoom siv tau zoo dua. Koj tsis tas yuav compact txhua qhov chaw nyob rau hauv qhov chaw nyob tsawg tshaj plaws vim tias compacting tuaj yeem tsim cov khoom siv tsawg dua.
· Platform Designer tsis sim ua kom haum cov cim xeeb cais nyob rau hauv ib qho kev nco sib txuas. Rau example, yog tias koj xav tau ntau yam On-Chip Memory Cheebtsam nyob raws li ib qho kev nco sib txuas, koj yuav tsum qhia meej qhov chaw nyob.
Platform Designer kuj tseem muab cov lus txib automation - Muab Tus lej cuam tshuam uas txuas IRQ cov cim los tsim cov khoom siv tau zoo. Txawm li cas los xij, kev muab IRQs ua tau zoo yuav tsum muaj kev nkag siab ntawm tag nrho cov txheej txheem teb tus cwj pwm. Platform Designer tsis tuaj yeem ua rau kev kawm kwv yees txog qhov zoo tshaj plaws IRQ txoj haujlwm.
Tus nqi qis tshaj IRQ muaj qhov tseem ceeb tshaj plaws. Nyob rau hauv ib qho zoo tagnrho system, Altera pom zoo kom lub timer tivthaiv kom muaj qhov tseem ceeb tshaj plaws IRQ, piv txwv li, tus nqi qis tshaj, kom muaj qhov tseeb ntawm lub kaw lus moos zuam.
Qee zaum, koj tuaj yeem muab qhov tseem ceeb dua rau cov khoom siv hauv lub sijhawm tiag tiag (xws li cov tswj hwm video), uas xav tau kev cuam tshuam ntau dua li cov khoom siv sijhawm.
Cov ntaub ntawv ntsig txog
Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Cov ntaub ntawv ntau ntxiv txog kev tsim Cov Txheej Txheem nrog Platform Designer.

Nios® V Embedded Processor Design Phau Ntawv 24

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
2.2. Integrating Platform Designer System rau hauv Quartus Prime Project
Tom qab tsim Nios V system tsim hauv Platform Designer, ua cov haujlwm hauv qab no los koom ua ke Nios V system module rau hauv Quartus Prime FPGA tsim qhov project. · Instantiate Nios V system module nyob rau hauv lub Quartus Prime project · Txuas cov teeb liab los ntawm Nios V system module rau lwm cov teeb liab nyob rau hauv lub FPGA logic · Muab lub cev pins qhov chaw · txwv FPGA tsim
2.2.1. Instantiating Nios V Processor System Module hauv Quartus Prime Project
Platform Designer tsim ib qhov system module tsim qhov chaw uas koj tuaj yeem instantiate hauv Quartus Prime. Yuav ua li cas koj instantiate lub system module nyob ntawm tus tsim nkag txoj kev rau tag nrho Quartus Prime project. Rau example, yog tias koj tau siv Verilog HDL rau kev tsim nkag, instantiate Verilog raws li qhov system module. Yog tias koj xav siv daim duab thaiv txoj hauv kev rau kev tsim nkag, instantiate ib qho system module cim .bdf file.
2.2.2. Txuas cov teeb liab thiab muab lub cev Pin qhov chaw
Txhawm rau txuas koj tus qauv Altera FPGA rau koj tus qauv tsim qauv, ua cov haujlwm hauv qab no: · Txheeb xyuas cov theem saum toj kawg nkaus file rau koj tus qauv tsim thiab cov teeb liab txuas rau sab nraud Altera
FPGA ntaus ntawv pins. · Nkag siab tus pins twg los txuas los ntawm koj lub rooj tsavxwm tsim qauv siv phau ntawv lossis
schematics. · Muab cov cim qhia hauv cov qauv tsim sab saum toj rau cov chaw nres nkoj ntawm koj lub Altera FPGA ntaus ntawv nrog tus pin
cov cuab yeej ua haujlwm.
Koj lub Platform Designer system tuaj yeem yog tus tsim qib siab tshaj plaws. Txawm li cas los xij, Altera FPGA tseem tuaj yeem suav nrog cov logic ntxiv raws li koj xav tau thiab yog li qhia txog kev cai sab saum toj-theem file. Cov theem sab saum toj file txuas Nios V processor system module teeb liab mus rau lwm yam Altera FPGA tsim logic.
Cov ntaub ntawv ntsig txog Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Tsim Kev Txwv
2.2.3. Constraining Altera FPGA Tsim
Qhov tsim nyog Altera FPGA system tsim suav nrog cov qauv tsim kom ntseeg tau tias tus qauv tsim muaj raws li lub sijhawm kaw thiab lwm yam kev txwv kev txwv. Koj yuav tsum txwv koj tus qauv Altera FPGA kom ua tau raws li cov kev cai no kom meej meej siv cov cuab yeej muab hauv Quartus Prime software lossis lwm tus neeg muab kev pabcuam EDA. Quartus Prime software siv cov kev txwv muab thaum lub sij hawm muab tso ua ke kom tau txais qhov zoo tshaj plaws qhov kev tso kawm.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 25

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
Cov ntaub ntawv cuam tshuam · Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Tsim Kev Txwv · Third-tog EDA Partners · Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Timing Analyzer
2.3. Tsim Nios V Processor Memory System
Tshooj lus no piav qhia txog cov kev coj ua zoo tshaj plaws rau kev xaiv cov cuab yeej nco hauv Platform Designer embedded system nrog Nios V processor thiab ua tiav qhov kev ua tau zoo. Cov cuab yeej nco ua lub luag haujlwm tseem ceeb hauv kev txhim kho tag nrho cov kev ua tau zoo ntawm lub kaw lus embedded. Embedded system nco khaws cov lus qhia thiab cov ntaub ntawv.
2.3.1. Volatile Nco
Ib qho tseem ceeb sib txawv hauv hom nco yog volatility. Volatile nco tsuas tuav nws cov ntsiab lus thaum koj muab lub zog rau lub cim xeeb ntaus ntawv. Thaum koj tshem tawm lub hwj chim, lub cim xeeb poob nws cov ntsiab lus.
Examples ntawm volatile nco yog RAM, cache, thiab sau npe. Cov no yog hom kev nco ceev uas ua rau kev ua haujlwm tau zoo. Altera xav kom koj thauj khoom thiab ua tiav cov lus qhia Nios V processor hauv RAM thiab khub Nios V IP core nrog On-Chip Memory IP lossis Sab Nraud Memory Interface IP rau kev ua haujlwm zoo.
Txhawm rau txhim kho kev ua tau zoo, koj tuaj yeem tshem tawm cov kev hloov pauv ntawm Platform Designer ntxiv los ntawm kev sib piv Nios V processor data manager interface hom lossis dav nrog khau raj RAM. Rau example, koj tuaj yeem teeb tsa On-Chip Memory II nrog 32-ntsis AXI-4 interface, uas phim Nios V cov ntaub ntawv tus thawj tswj interface.
Cov ntaub ntawv cuam tshuam · Sab Nraud Memory Interfaces IP Support Center · On-Chip Memory (RAM lossis ROM) Altera FPGA IP · On-Chip Memory II (RAM lossis ROM) Altera FPGA IP · Nios V Cov Txheej Txheem Daim Ntawv Thov Ua Haujlwm-hauv-Pib los ntawm OCRAM ntawm nplooj 54
2.3.1.1 ib. On-Chip Memory Configuration RAM lossis ROM
Koj tuaj yeem teeb tsa Altera FPGA On-Chip Memory IPs li RAM lossis ROM. · RAM muab kev nyeem ntawv thiab sau ntawv muaj peev xwm thiab muaj qhov tsis zoo. Yog koj yog
booting Nios V processor los ntawm On-Chip RAM, koj yuav tsum xyuas kom meej tias cov ntsiab lus khau raj tau khaws cia thiab tsis raug cuam tshuam thaum lub sijhawm rov pib dua. · Yog tias Nios V processor tab tom booting los ntawm ROM, ib qho software kab mob ntawm Nios V processor tsis tuaj yeem erroneously overwrite cov ntsiab lus ntawm On-Chip Nco. Yog li, txo qhov kev pheej hmoo ntawm khau raj software kev noj nyiaj txiag.
Cov ntaub ntawv cuam tshuam · On-Chip Memory (RAM lossis ROM) Altera FPGA IP · On-Chip Memory II (RAM lossis ROM) Altera FPGA IP · Nios V Cov Txheej Txheem Daim Ntawv Thov Ua Haujlwm-hauv-Chaw los ntawm OCRAM ntawm nplooj 54

Nios® V Embedded Processor Design Phau Ntawv 26

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
2.3.1.2. Caches
On-chip nco feem ntau yog siv los siv lub cache functionality vim lawv tsis tshua muaj latency. Nios V processor siv on-chip nco rau nws cov lus qhia thiab cov ntaub ntawv caches. Lub peev xwm tsawg ntawm on-chip nco feem ntau tsis yog qhov teeb meem rau caches vim lawv feem ntau me me.
Caches feem ntau siv raws li hauv qab no:
· Lub cim xeeb tsis tu ncua yog nyob ntawm lub nti tawm thiab muaj lub sijhawm nkag mus ntev dua li lub cim xeeb ntawm lub cim xeeb.
· Cov ntu tseem ceeb ntawm cov software code tuaj yeem haum rau hauv cov lus qhia cache, txhim kho kev ua haujlwm.
· Cov kev ua tau zoo-tseem ceeb, feem ntau siv cov ntaub ntawv tuaj yeem haum rau hauv cov ntaub ntawv cache, txhim kho kev ua haujlwm.
Enabling caches hauv Nios V processor tsim lub cim xeeb hierarchy, uas txo lub sijhawm nkag mus rau lub cim xeeb tsawg.
2.3.1.2.1. Peripheral cheeb tsam
Txhua qhov chaw txuas IP, xws li UART, I2C, thiab SPI yuav tsum tsis txhob cached. Cache tau pom zoo rau cov kev nco sab nraud uas cuam tshuam los ntawm lub sijhawm nkag mus ntev, thaum lub cim xeeb sab hauv on-chip tuaj yeem raug cais tawm vim lawv lub sijhawm siv luv. Koj yuav tsum tsis txhob cache ib qho embedded peripheral IPs, xws li UART, I2C, thiab SPI, tshwj tsis yog rau nco. Qhov no yog qhov tseem ceeb vim tias cov xwm txheej los ntawm cov khoom siv sab nraud, xws li tus neeg sawv cev cov cuab yeej hloov kho cov IPs mos, tsis raug ntes los ntawm processor cache, tig tsis tau los ntawm processor. Raws li qhov tshwm sim, cov xwm txheej no tuaj yeem tsis paub txog kom txog thaum koj yaug lub cache, uas tuaj yeem ua rau tus cwj pwm tsis zoo hauv koj lub cev. Hauv cov ntsiab lus, lub cim xeeb-mapped cheeb tsam ntawm embedded peripheral IPs yog uncacheable thiab yuav tsum nyob rau hauv lub processor lub peripheral cheeb tsam.
Txhawm rau teeb tsa thaj chaw peripheral, ua raws li cov kauj ruam no:
1. Qhib qhov system daim ntawv qhia chaw nyob hauv lub Platform Designer.
2. Nkag mus rau hauv daim ntawv qhia chaw nyob ntawm tus processor's Instruction Manager thiab Data Manager.
3. Txheeb xyuas cov peripheral thiab nco hauv koj lub cev.
Daim duab 12. Example ntawm Address Map

Lus Cim: Cov xub xiav yog taw rau kev nco. 4. Pab pawg neeg peripherals:
ib. Nco li cacheable b. Peripherals li uncacheable

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 27

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Table 19. Cacheable thiab Uncacheable Region

Subordinate

Daim Ntawv Qhia Chaw Nyob

xwm txheej

Peripheral Region

Loj

Chaw Nyob

user_application_mem.s1

0x 0 x0f

Cacheable

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 bytes N/A

0x40000 N / A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 bytes (min loj yog 65536 bytes)

0 x 54000

sysid_qsys_0.control_slave

0x54080 : 0x54087

Uncacheable

uart.avalon_jtag_ qhev

0x54088 - 0x5408f

Uncacheable

5. Kho cov cheeb tsam peripheral nrog lawv qhov loj me:
· Rau example, yog tias qhov loj me yog 65536 bytes, nws sib raug rau 0x10000 bytes. Yog li, qhov chaw nyob hauv paus yuav tsum yog ntau yam ntawm 0x10000.
· CPU.dm_agent siv lub hauv paus chaw nyob ntawm 0x40000, uas yog ntau yam ntawm 0x10000. Yog li ntawd, Peripheral Region A, nrog qhov loj ntawm 65536 bytes thiab qhov chaw nyob hauv paus ntawm 0x40000, ua tau raws li qhov yuav tsum tau ua.
· Lub hauv paus chaw nyob ntawm kev sau ntawm cov cheeb tsam uas tsis tuaj yeem ntawm 0x54000 tsis yog ntau yam ntawm 0x10000. Koj yuav tsum rov muab lawv rau 0x60000 lossis lwm yam ntau ntawm 0x10000. Yog li, Peripheral Region B, uas muaj qhov loj me ntawm 65536 bytes thiab qhov chaw nyob hauv paus ntawm 0x60000, txaus siab rau cov qauv.

Table 20. Cacheable thiab Uncacheable Region nrog Reassignment

Subordinate

Daim Ntawv Qhia Chaw Nyob

xwm txheej

Peripheral Region

Loj

Chaw Nyob

user_application_mem.s1

0x 0 x0f

Cacheable

N/A

cpu.dm_agent

0x 40000 x0f

Uncacheable 65536 bytes

0 x 40000

bootcopier_rom.s1

0x50000 ~ 0x517 ff

Cacheable

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Cacheable Uncacheable Uncacheable Uncacheable

144 bytes (min loj yog 65536 bytes)

0 x 60000

uart.avalon_jtag_ qhev

0x60088 - 0x6008f

Uncacheable

2.3.1.3. Tightly Coupled Nco
Tightly coupled nco (TCMs) yog siv los siv lub cim xeeb ntawm lub cim xeeb raws li lawv qhov latency qis ua rau lawv zoo haum rau txoj haujlwm. TCMs yog cov cim nco tau nyob rau hauv qhov chaw nyob ib txwm tab sis muaj kev sib koom siab rau microprocessor thiab muaj cov khoom ua haujlwm siab, qis-latency ntawm cache nco. TCM kuj tseem muab ib qho kev cuam tshuam rau tus tswv tsev sab nraud. Tus processor thiab tus tswv tsev sab nraud muaj tib qib kev tso cai los tswj TCM.

Nios® V Embedded Processor Design Phau Ntawv 28

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Nco tseg:

Thaum TCM subordinate chaw nres nkoj txuas nrog tus tswv tsev sab nraud, nws yuav raug tso tawm nrog qhov chaw nyob txawv dua li qhov chaw nyob hauv paus tau muab rau hauv cov tub ntxhais processor. Altera pom zoo kom muab ob qho chaw nyob rau tib tus nqi.

2.3.1.4 ib. Sab nraud Memory Interface (EMIF)
EMIF (External Memory Interface) ua haujlwm zoo ib yam li SRAM (Static Random Access Memory), tab sis nws yog qhov muaj zog thiab yuav tsum tau ua kom lub sijhawm ua kom nws cov ntsiab lus. Lub dynamic nco hlwb hauv EMIF muaj tsawg dua li cov cim xeeb zoo li qub hauv SRAM, uas ua rau muaj peev xwm ntau dua thiab qis dua cov khoom siv nco.
Ntxiv nrog rau qhov yuav tsum tau ua kom tshiab, EMIF muaj cov kev xav tau tshwj xeeb uas feem ntau xav tau tshwj xeeb cov khoom siv kho vajtse. Tsis zoo li SRAM, uas muaj cov kab nyob ruaj khov, EMIF teeb tsa nws qhov chaw nco mus rau hauv tsev txhab nyiaj, kab, thiab kab. Hloov ntawm cov tsev txhab nyiaj thiab cov kab qhia txog qee qhov nyiaj siv ua haujlwm, yog li koj yuav tsum ua tib zoo xaj kev nco nkag mus siv EMIF kom zoo. EMIF kuj multiplexes kab thiab kab nyob rau tib kab chaw nyob, txo tus naj npawb ntawm cov pins xav tau rau qhov muab EMIF loj.
Cov kev ua haujlwm siab dua ntawm EMIF, xws li DDR, DDR2, DDR3, DDR4, thiab DDR5, tsim cov teeb liab nruj nruj uas cov neeg tsim qauv PCB yuav tsum xav txog.
EMIF cov khoom siv nyob rau ntawm cov nqi zoo tshaj plaws thiab muaj peev xwm RAM hom muaj, ua rau lawv muaj kev xaiv nrov. Ib qho tseem ceeb ntawm EMIF interface yog EMIF IP, uas tswj cov haujlwm ntsig txog qhov chaw nyob multiplexing, refreshing, thiab hloov ntawm kab thiab cov tsev txhab nyiaj. Qhov kev tsim no tso cai rau tus so ntawm lub kaw lus nkag mus rau EMIF yam tsis tas yuav nkag siab nws cov qauv hauv tsev.

Cov ntaub ntawv ntsig txog Sab Nraud Memory Interfaces IP Support Center

2.3.1.4.1. Chaw Nyob Span Extender IP
Qhov Chaw Nyob Span Extender Altera FPGA IP tso cai rau lub cim xeeb-mapped host interfaces nkag mus rau daim ntawv qhia chaw nyob loj dua lossis me dua qhov dav ntawm lawv qhov chaw nyob cov cim tso cai. Qhov Chaw Nyob Span Extender IP faib qhov chaw nyob rau hauv ntau lub qhov rais cais kom tus tswv tsev tuaj yeem nkag mus rau qhov tsim nyog ntawm lub cim xeeb los ntawm lub qhov rais.
Qhov Chaw Nyob Span Extender tsis txwv tus tswv tsev thiab tus neeg sawv cev dav rau 32-ntsis thiab 64-ntsis teeb tsa. Koj tuaj yeem siv qhov Chaw Nyob Span Extender nrog 1-64 qhov chaw nyob qhov rais.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 29

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Daim duab 13. Chaw Nyob Span Extender Altera FPGA IP
Agent Word Chaw Nyob

Chaw Nyob Span Extender

Daim Ntawv Qhia
Tswj Chaw nres nkoj A

…

Tswj Sau Npe 0 Tswj Sau Npe Z-1

Expanded Host Chaw Nyob H

Cov ntaub ntawv ntsig txog
Quartus® Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Platform Designer Xa mus rau lub ncauj lus Chaw Nyob Span Extender Intel® FPGA IP kom paub ntau ntxiv.

2.3.1.4.2. Siv Chaw Nyob Span Extender IP nrog Nios V Processor
32-ntsis Nios V processor tuaj yeem hais txog 4 GB ntawm qhov chaw nyob. Yog tias EMIF muaj ntau dua 4GB ntawm lub cim xeeb, nws tshaj qhov siab tshaj plaws qhov chaw nyob, ua rau Platform Designer system ua yuam kev. Qhov Chaw Nyob Span Extender IP yuav tsum tau daws qhov teeb meem no los ntawm kev faib ib qho chaw nyob EMIF rau ntau lub qhov rais me.
Altera xav kom koj xav txog cov kev txwv hauv qab no.

Table 21. Chaw Nyob Span Extender Parameters

Parameter

Pom zoo Chaw

Datapath Dav
Expanded Master Byte Chaw Nyob Dav

Xaiv 32-ntsis, uas corelates rau 32-ntsis processor. Nyob ntawm EMIF lub cim xeeb loj.

Slave Word Address Width Burstcount Width

Xaiv 2 GB lossis tsawg dua. Ntxiv qhov chaw nyob ncua sij hawm ntawm Nios V processor yog tshwj tseg rau lwm cov embedded mos IPs.
Pib nrog 1 thiab maj mam nce tus nqi no los txhim kho kev ua haujlwm.

Tus naj npawb ntawm sub-windows

Xaiv 1 sub-window yog tias koj txuas EMIF rau Nios V processor raws li kev qhia thiab cov ntaub ntawv nco, lossis ob qho tib si. Hloov ntawm ntau lub qhov rais me me thaum Nios V processor tab tom ua los ntawm EMIF yog qhov txaus ntshai.

Qhib Slave Control Chaw nres nkoj

Tshem tawm qhov chaw nres nkoj tswj qhev yog tias koj txuas EMIF rau Nios V processor raws li kev qhia thiab / lossis cov ntaub ntawv nco. Tib yam kev txhawj xeeb raws li Tus naj npawb ntawm sub-windows.

Kev nyeem ntawv siab kawg

Pib nrog 1 thiab maj mam nce tus nqi no los txhim kho kev ua haujlwm.

Nios® V Embedded Processor Design Phau Ntawv 30

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
Daim duab 14. Txuas Kev Qhia thiab Tus Thawj Saib Xyuas Cov Ntaub Ntawv rau Chaw Nyob Span Extender

Daim duab 15. Daim Ntawv Qhia Chaw Nyob

Daim ntawv ceeb toom tias Chaw Nyob Span Extender tuaj yeem nkag mus rau tag nrho 8GB nco qhov chaw ntawm EMIF. Txawm li cas los xij, los ntawm Chaw Nyob Span Extender, Nios V processor tuaj yeem nkag tau tsuas yog thawj 1GB qhov chaw nco ntawm EMIF.

Daim duab 16. Simplified Block Diagram

Platform Designer System

Tseem tshuav 3 GB

Nios V processor address

span yog rau embedded

NNioos sVV PProrocecsesosor r
M

soft IPs nyob rau hauv tib lub system.
1 GB qhov rais

Chaw nyob Span

Extender

Tsuas yog thawj 1 GB

ntawm EMIF nco yog txuas nrog Nios V

EMIF

processor.

8 GB ua
S

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 31

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
2.3.1.4.3. Txhais qhov chaw nyob Span Extender Linker Memory Device 1. Txhais qhov chaw nyob Span Extender (EMIF) raws li qhov pib dua vector. Xwb, koj tuaj yeem muab Nios V processor rov pib dua vector rau lwm yam nco, xws li OCRAM lossis flash devices.
Daim duab 17. Ntau yam kev xaiv raws li Reset Vector
Txawm li cas los xij, Board Support Package (BSP) Editor tsis tuaj yeem tso npe rau Chaw Nyob Span Extender (EMIF) ua lub cim xeeb siv tau. Nyob ntawm qhov koj xaiv, koj pom ob qhov xwm txheej sib txawv raws li qhia hauv cov duab hauv qab no. Daim duab 18. BSP yuam kev thaum Defining Chaw Nyob Span Extender (EMIF) raws li Reset Vector

Nios® V Embedded Processor Design Phau Ntawv 32

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
Daim duab 19. Nthuav EMIF thaum txhais Lwm Yam Nco Ntsoov li Rov Pib Vector

2. Koj yuav tsum manually ntxiv qhov Chaw Nyob Span Extender (EMIF) siv Ntxiv Memory Device, Ntxiv Linker Memory Region, thiab Ntxiv Linker Section Mappings hauv BSP Linker Script tab.
3. Ua raws li cov kauj ruam no:
ib. Txiav txim siab qhov chaw nyob ntawm qhov Chaw Nyob Span Extender siv Daim Ntawv Qhia Memory (Example hauv daim duab hauv qab no siv Chaw Nyob Span Extender ntau ntawm 0x0 txog 0x3fff_ffff).
Daim duab 20. Memory Map

b. Nyem Ntxiv Memory Device, thiab sau nyob rau hauv raws li cov ntaub ntawv nyob rau hauv koj tus tsim lub cim xeeb daim ntawv qhia: i. Ntaus lub npe: emif_ddr4. Nco tseg: Xyuas kom koj luam tib lub npe los ntawm Memory Map. ii. Base Chaw Nyob: 0x0 iii. Loj: 0x40000000
c. Nyem Ntxiv txhawm rau ntxiv qhov txuas tshiab txuas ntxiv thaj chaw nco:

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 33

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Table 22. Ntxiv Linker Memory Region

Cov kauj ruam

Rov pib dua Vector

emif_ddr 4

Lwm yam nco

Ntxiv qhov Linker Memory Region tshiab hu ua rov pib dua. Ntxiv qhov Linker Memory Region tshiab rau lub

· Lub npe cheeb tsam: pib dua

emif_ddr 4.

· Thaj Chaw: 0x20

· Lub npe cheeb tsam: emif_ddr4

· Memory Device: emif_ddr4

· Thaj Chaw: 0x40000000

· Nco Offset: 0x0

· Memory Device: emif_ddr4

· Nco Offset: 0x0

Ntxiv qhov Linker Memory Region tshiab rau lub

tshuav emif_ddr4.

· Lub npe cheeb tsam: emif_ddr4

· Thaj Chaw Loj: 0x3ffffff0

· Memory Device: emif_ddr4

· Nco Offset: 0x20

Daim duab 21. Linker Region thaum Defining Address Span Extender (EMIF) as Reset Vector

Daim duab 22. Linker Region thaum txhais lwm yam kev nco li rov pib Vector
d. Thaum lub emif_ddr4 ntxiv rau BSP, koj tuaj yeem xaiv nws rau txhua ntu Linker.
Daim duab 23. Ntxiv Chaw Nyob Span Extender (EMIF) Ua tiav

e. Tsis quav ntsej cov lus ceeb toom txog Memory ntaus ntawv emif_ddr4 tsis pom hauv SOPC tsim.
f. Txuas mus tsim BSP.
Related Information Introduction to Nios V Processor Booting Methods ntawm nplooj 51

Nios® V Embedded Processor Design Phau Ntawv 34

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
2.3.2. Tsis-Volatile Memory
Tsis-volatile nco khaws nws cov ntsiab lus thaum lub hwj chim switches tawm, ua rau nws yog ib tug zoo xaiv rau khaws cia cov ntaub ntawv uas lub system yuav tsum tau retrieve tom qab ib tug system fais fab mov. Lub cim xeeb uas tsis yog-volatile feem ntau khaws cov txheej txheem khau raj-code, cov ntawv thov tsis tu ncua, thiab Altera FPGA cov ntaub ntawv teeb tsa. Txawm tias tsis-volatile nco muaj lub advantage ntawm khaws cia nws cov ntaub ntawv thaum koj tshem tawm lub hwj chim, nws yog qeeb qeeb piv rau qhov tsis muaj zog nco, thiab feem ntau muaj ntau txoj kev sau ntawv thiab tshem tawm cov txheej txheem. Tsis yog-volatile nco kuj feem ntau tsuas yog lav tias yuav tshem tau ib lub sijhawm, tom qab ntawd nws yuav ua tsis tiav.
Examples ntawm tsis-volatile nco suav nrog txhua hom flash, EPROM, thiab EEPROM. Altera xav kom koj khaws Altera FPGA bitstreams thiab Nios V qhov kev pab cuam cov duab hauv lub cim xeeb uas tsis hloov pauv, thiab siv serial flash ua lub khau raj rau Nios V processors.
Cov ntaub ntawv ntsig txog
· Generic Serial Flash Interface Altera FPGA IP Tus Neeg Siv Qhia
· Mailbox Client Altera FPGA IP User Guide · MAX® 10 User Flash Memory User Guide: On-Chip Flash Altera FPGA IP Core
2.4. Clocks thiab rov kho cov kev coj ua zoo tshaj plaws
Kev nkag siab yuav ua li cas Nios V processor moos thiab rov pib dua kev sib cuam tshuam nrog txhua qhov peripheral nws txuas nrog yog qhov tseem ceeb. Ib qho yooj yim Nios V processor system pib nrog ib lub moos sau, thiab nws tuaj yeem nyuaj nrog ntau lub moos sau npe thaum lub moos ceev ceev sib tsoo nrog lub moos qeeb. Koj yuav tsum tau sau tseg thiab nkag siab tias qhov sib txawv ntawm cov npe no li cas los ntawm kev pib dua thiab xyuas kom meej tias tsis muaj teeb meem hloov maj mam.
Rau kev xyaum zoo tshaj plaws, Altera pom zoo kom tso Nios V processor thiab khau raj nco hauv tib lub moos. Tsis txhob tso Nios V processor los ntawm kev pib dua hauv lub moos ceev ceev thaum nws khau raj los ntawm lub cim xeeb uas nyob hauv lub moos qeeb heev, uas yuav ua rau muaj kev qhia yuam kev. Koj tuaj yeem xav tau qee qhov kev qhia ua ntu zus dhau qhov Platform Designer muab los ntawm lub neej ntawd, thiab npaj tawm rov pib dua tso tawm topology raws li koj qhov kev siv. Yog tias koj xav rov pib dua koj lub kaw lus tom qab nws los txog thiab khiav ib ntus, siv tib qhov kev txiav txim siab rau qhov system rov pib ua ntu zus thiab tom qab rov pib pib qhov yuav tsum tau ua.
2.4.1. System JTAG moos
Kev qhia txog lub moos txwv nyob rau hauv txhua lub Nios V processor system yog ib qho tseem ceeb ntawm cov txheej txheem tsim kev txiav txim siab thiab yuav tsum tau ua kom raug thiab txiav txim siab tus cwj pwm. Lub Quartus Prime Timing Analyzer ua qhov kev soj ntsuam lub sijhawm zoo li qub los txheeb xyuas lub sijhawm ua haujlwm ntawm txhua qhov kev xav hauv koj tus qauv siv kev lag luam-tus qauv txwv, kev tshuaj xyuas, thiab kev tshaj tawm txoj hauv kev.
Example 1. Basic 100 MHz Clock nrog 50/50 Duty Cycle thiab 16 MHz JTAG moos
#********************************************************************** # Tsim 100MHz moos #***************************************************************** create_clock -name {clk} -period 10 [get_ports {clk}] #****************************** Tsim 16MHz JTAG Clock #******************************

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 35

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Related Information Quartus Prime Timing Analyzer Cookbook
2.4.2. Pib dua thov Interface
Nios V processor suav nrog kev xaiv rov pib dua qhov chaw thov. Qhov chaw thov rov pib dua muaj xws li reset_req thiab reset_req_ack signals.
Txhawm rau qhib qhov kev thov rov pib dua hauv Platform Designer: 1. Tua tawm Nios V Processor IP Parameter Editor. 2. Nyob rau ntawm Kev Siv Reset Request setting, qhib qhov Add Reset Request Interface
kev xaiv.
Daim duab 24. Pab kom Nios V Processor Reset Request
Lub teeb liab reset_req ua zoo li cuam tshuam. Thaum koj lees paub qhov reset_req, koj tab tom thov kom rov pib dua rau lub hauv paus. Lub hauv paus tseem tos rau txhua qhov kev lag luam tsheb npav ua tiav kom tiav nws txoj haujlwm. Rau example, yog tias muaj qhov tseem tos kev nkag mus rau kev hloov pauv, cov tub ntxhais tseem tos kom teb tiav. Ib yam li ntawd, cov tub ntxhais kawm lees txais cov lus qhia tseem tab sis tsis muab daim ntawv thov kev qhia tom qab tau txais lub teeb liab reset_req.
Kev rov pib ua haujlwm muaj xws li cov nram qab no: 1. Ua kom tiav tag nrho cov haujlwm tseem tos 2. Flush lub kav dej sab hauv 3. Teem lub Program Counter rau qhov rov pib vector 4. Rov pib dua lub hauv paus Lub sijhawm pib dua tag nrho yuav siv ob peb lub voj voog. Lub reset_req yuav tsum nyob twj ywm kom txog rau thaum reset_req_ack tau lees paub qhia tias cov haujlwm tseem ceeb rov pib dua tau ua tiav. Tsis ua li ntawd ua rau cov tub ntxhais lub xeev tsis yog kev txiav txim siab.

Nios® V Embedded Processor Design Phau Ntawv 36

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
2.4.2.1. Cov Kev Siv Ib txwm siv
· Koj tuaj yeem lees paub lub teeb liab reset_req los ntawm lub hwj chim-on los tiv thaiv Nios V processor core los ntawm kev pib ua haujlwm ua haujlwm los ntawm nws rov pib vector kom txog rau thaum lwm tus FPGA hosts hauv lub kaw lus pib Nios V processor boot nco. Nyob rau hauv cov ntaub ntawv no, tag nrho cov subsystem yuav muaj ib tug huv si hardware reset. Nios V processor tau tuav tsis tu ncua nyob rau hauv qhov kev thov rov pib dua lub xeev kom txog rau thaum lwm tus FPGA tus tswv pib pib lub processor nco nco.
· Nyob rau hauv ib qho system uas koj yuav tsum rov pib dua Nios V processor core yam tsis muaj kev cuam tshuam rau qhov seem ntawm lub system, koj tuaj yeem lees paub lub teeb liab reset_req kom huv si nres qhov kev ua haujlwm tam sim no ntawm cov tub ntxhais thiab rov pib lub processor los ntawm rov pib vector thaum lub kaw lus tso tawm reset_req_ack teeb liab.
· Tus tswv tsev sab nraud tuaj yeem siv qhov kev thov rov pib dua interface kom yooj yim rau kev siv cov haujlwm hauv qab no:
- Tso tseg Nios V processor program tam sim no.
- Thawb ib qho kev pab cuam tshiab rau hauv Nios V processor boot nco.
- Cia tus processor pib ua qhov program tshiab.
Altera xav kom koj siv lub sijhawm ua haujlwm los saib xyuas lub xeev ntawm reset_req_ack teeb liab. Yog hais tias Nios V processor core poob mus rau hauv lub xeev tos tsis kawg thiab stalls rau ib qho laj thawj tsis paub, reset_req_ack tsis tuaj yeem lees paub tas li. Lub timeout mechanism enables koj mus:
· Txhais lub sij hawm rov qab los thiab ua cov txheej txheem rov qab nrog cov txheej txheem pib dua.
· Ua ib tug hardware theem pib dua.
2.4.3. Pib dua Release IP
Altera SDM-raws li cov cuab yeej siv ib qho kev sib txuas, ua haujlwm raws li kev tsim qauv uas faib cov ntaub ntawv tseem ceeb thoob plaws ntau qhov chaw. Altera pom zoo kom koj siv Reset Release Altera FPGA IP raws li ib qho ntawm thawj qhov kev nkag mus rau qhov rov pib dua. Intel® SDMbased li suav nrog Stratix® 10, thiab AgilexTM li. Tswj-thaiv raws li cov cuab yeej tsis cuam tshuam los ntawm qhov yuav tsum tau ua.
Cov ntaub ntawv ntsig txog
AN 891: Siv qhov Rov Pib Tawm Tawm Altera FPGA IP
2.5. Muab Tus Neeg Saib Xyuas Default
Platform Designer tso cai rau koj los qhia txog tus neeg sawv cev ua ntej uas ua raws li tus neeg sawv cev yuam kev. Tus neeg sawv cev ua ntej koj xaiv muab qhov kev ua yuam kev teb rau cov tswv uas sim tsis tau txiav txim siab nkag mus rau hauv daim ntawv qhia chaw nyob.
Cov xwm txheej hauv qab no ua rau muaj qhov tshwm sim tsis tau txiav txim:
· tsheb npav kev ruaj ntseg xeev ua txhaum cai
· Kev nkag mus rau thaj chaw nco tsis tau txhais
· Exception event thiab lwm yam.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 37

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Tus neeg sawv cev ua ntej yuav tsum raug xa mus los tswj cov xwm txheej zoo li no, qhov kev hloov pauv tsis tau hloov pauv mus rau tus neeg sawv cev ua ntej thiab tom qab ntawd teb rau Nios V processor nrog cov lus teb yuam kev.
Cov ntaub ntawv ntsig txog
· Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Platform Designer. Tsim Tus Neeg Ua Haujlwm Default
· Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv: Platform Designer. Yuam kev teb qhev Altera FPGA IP
· Github – Ntxiv Reset Cheebtsam rau Qsys

2.6. Muab tus neeg sawv cev UART rau kev luam ntawv
Kev luam ntawv muaj txiaj ntsig zoo rau kev debugging daim ntawv thov software, nrog rau kev saib xyuas cov xwm txheej ntawm koj lub cev. Altera pom zoo luam tawm cov ntaub ntawv yooj yim xws li cov lus pib, lus yuam kev, thiab kev ua tiav ntawm daim ntawv thov software.
Tsis txhob siv lub tsev qiv ntawv printf() ua haujlwm raws li cov xwm txheej hauv qab no: · Lub tsev qiv ntawv printf() ua rau daim ntawv thov raug kaw yog tias tsis muaj tus tswv tsev nyeem ntawv.
Qhov no muaj feem xyuam rau JTAG UART nkaus xwb. · Lub tsev qiv ntawv printf() siv ntau qhov kev pab cuam nco.

2.6.1. Tiv Thaiv Cov Tsev Muag Khoom los ntawm JTAG UART

Table 23. Qhov txawv ntawm Traditional UART thiab JTAG UART

UART Hom Traditional UART

Kev piav qhia
Xa cov ntaub ntawv serial tsis hais seb tus tswv tsev sab nraud puas mloog. Yog tias tsis muaj tus tswv tsev nyeem cov ntaub ntawv serial, cov ntaub ntawv ploj.

JTAG UART

Sau cov ntaub ntawv xa mus rau qhov tso zis tsis tawm thiab tso siab rau tus tswv tsev sab nraud los nyeem los ntawm qhov tsis tuaj yeem ua rau nws khoob.

Tus J.TAG UART tus neeg tsav tsheb tos thaum cov zis tsis puv puv. Cov JTAG UART tus neeg tsav tsheb tos rau tus tswv tsev sab nraud los nyeem los ntawm cov khoom tso tawm ua ntej sau cov ntaub ntawv xa mus ntxiv. Cov txheej txheem no tiv thaiv tsis tau cov ntaub ntawv xa mus.
Txawm li cas los xij, thaum tsis muaj qhov kev debugging tsis tas yuav tsum tau, xws li thaum lub sijhawm tsim khoom, embedded systems yog deployed yam tsis muaj tus tswv PC txuas nrog J.TAG UART. Yog tias qhov system xaiv JTAG UART ua tus neeg sawv cev UART, nws tuaj yeem ua rau lub kaw lus kaw vim tsis muaj tus tswv tsev sab nraud txuas nrog.
Txhawm rau tiv thaiv kev stalling los ntawm JTAG UART, siv cov kev xaiv hauv qab no:

Nios® V Embedded Processor Design Phau Ntawv 38

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib

Table 24. Kev Tiv Thaiv Kev Cuam Tshuam los ntawm JTAG UART

Kev xaiv
Tsis muaj UART interface thiab tus tsav tsheb tam sim no
Siv lwm UART interface thiab tsav tsheb
Khaws JTAG UART interface (tsis muaj tsav tsheb)

Thaum Lub Sij Hawm Txhim Kho Kho vajtse (hauv Platform Designer)

Thaum lub sij hawm txhim kho Software (hauv Board Support Package Editor)

Tshem tawm JTAG UART los ntawm qhov system

Configure hal.stdin, hal.stdout thiab hal.stderr li Tsis muaj.

Hloov JTAG UART nrog rau lwm yam mos Configure hal.stdin, hal.stdout thiab hal.stderr

UAS IP

nrog rau lwm yam mos UART IP.

Khaws JTAG UART hauv qhov system

· Configure hal.stdin, hal.stdout thiab hal.stderr li Tsis muaj nyob rau hauv Pawg Neeg Txhawb Pab Pawg Editor.
· Disable JTAG UART tsav tsheb hauv BSP Tsav tab.

2.7. JTAG Teeb liab
Nios V processor debug module siv JTAG interface rau software ELF rub tawm thiab software debugging. Thaum koj debug koj tus tsim nrog JTAG interface, JTAG Cov teeb liab TCK, TMS, TDI, thiab TDO yog siv los ua ib feem ntawm kev tsim. Specification ntawm JTAG teeb liab txwv nyob rau hauv txhua qhov Nios V processor system yog ib qho tseem ceeb ntawm kev tsim qauv kev txiav txim siab thiab yuav tsum tau ua kom raug thiab txiav txim siab tus cwj pwm.
Altera pom zoo tias txhua tus qauv tsim lub moos zaus yog tsawg kawg yog plaub zaug JTAG moos zaus los xyuas kom meej tias cov cuab yeej siv rau hauv-chip (OCI) core ua haujlwm zoo.
Cov ntaub ntawv cuam tshuam · Quartus® Prime Timing Analyzer Cookbook: JTAG Teeb liab
Yog xav paub ntxiv txog JTAG cov txheej txheem kev txwv lub sijhawm. · KDB: Vim li cas niosv-download ua tsis tiav nrog cov uas tsis yog-pipelined Nios® V / m processor ntawm
JTAG zaus 24MHz lossis 16Mhz?
2.8. Optimizing Platform Designer System Kev ua tau zoo
Platform Designer muab cov cuab yeej rau optimizing qhov kev ua tau zoo ntawm qhov system interconnect rau Altera FPGA tsim.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 39

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer
726952 Nws 2025.07.16 ib
Daim duab 25. Optimization Examples

Cov example qhia hauv daim duab qhia cov kauj ruam hauv qab no:
1. Ntxiv Pipeline Choj kom txo tau txoj hauv kev tseem ceeb los ntawm kev tso nws: a. Nruab nrab ntawm Tus Thawj Saib Xyuas Kev Qhia thiab nws cov neeg sawv cev b. Nruab nrab ntawm Tus Thawj Tswj Cov Ntaub Ntawv thiab nws cov neeg sawv cev
2. Siv True Dual chaw nres nkoj On-Chip RAM, nrog rau txhua qhov chaw nres nkoj nplooj siab rau Tus Thawj Tswj Kev Qhia thiab Tus Thawj Tswj Cov Ntaub Ntawv raws li

Nios® V Embedded Processor Design Phau Ntawv 40

Xa lus tawm tswv yim

2. Nios V Processor Hardware System Tsim nrog Quartus Prime Software thiab Platform Designer 726952 | 2025.07.16
Xa mus rau cov kev sib txuas hauv qab no, uas nthuav tawm cov txheej txheem rau leveraging cov cuab yeej muaj thiab kev lag luam tawm ntawm txhua qhov kev siv.
Cov ntaub ntawv ntsig txog · Quartus® Prime Pro Edition Cov Neeg Siv Khoom Qhia: Platform Designer
Xa mus rau lub npe Optimizing Platform Designer System Performance kom paub ntau ntxiv. · Quartus® Prime Standard Edition User Guide: Platform Designer Xa mus rau lub ntsiab lus Optimizing Platform Designer System Performance kom paub ntau ntxiv.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 41

726952 | 2025.07.16 Xa lus tawm tswv yim

3. Nios V Processor Software System Design
Tshooj no piav qhia txog Nios V processor software txhim kho ntws thiab cov cuab yeej software uas koj tuaj yeem siv los tsim koj qhov kev tsim qauv tsim. Cov ntsiab lus ua haujlwm dhauview ua ntej tsim Nios V processor software system.
Daim duab 26. Software Design Flow
Pib

Tsim BSP hauv Platform Designer Siv BSP Editor

Tsim lub BSP Siv Nios V Command Plhaub
Tsim daim ntawv thov CMake Tsim File Siv Nios V Command Plhaub

Nco tseg:

Ntshuam BSP thiab Daim Ntawv Thov CMake Tsim File
Tsim Nios V Processor Application siv lub
RiscFree IDE rau Intel FPGA

Tsim Nios V Processor daim ntawv thov siv ib qho twg
command-line source code editor, CMake, thiab Ua
lus txib
Xaus

Altera pom zoo kom koj siv Altera FPGA cov khoom siv txhim kho lossis cov qauv kev cai rau kev txhim kho software thiab kev debugging. Ntau yam khoom siv thiab cov txheej txheem-theem muaj tsuas yog thaum koj software khiav ntawm lub rooj tsav xwm tiag tiag.

© Altera Corporation. Altera, Altera logo, 'a' logo, thiab lwm yam Altera cov cim yog cov cim lag luam ntawm Altera Corporation. Altera muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Altera xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, khoom, lossis kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo los ntawm kev sau ntawv los ntawm Altera. Altera cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

3. Nios V Processor Software System Design 726952 | 2025.07.16
3.1. Nios V Processor Software Development Flow
3.1.1. Board Support Package Project
Nios V Board Support Package (BSP) qhov project yog ib lub tsev qiv ntawv tshwj xeeb uas muaj cov cai tshwj xeeb txhawb nqa. BSP muab cov software khiav haujlwm ib puag ncig hloov kho rau ib tus processor hauv Nios V processor hardware system.
Quartus Prime software muab Nios V Board Support Package Editor thiab niosv-bsp cov cuab yeej siv hluav taws xob los hloov kho qhov chaw uas tswj tus cwj pwm ntawm BSP.
A BSP muaj cov hauv qab no: · Hardware abstraction layer · Device drivers · Optional software packages · Optional real-time operating system
3.1.2. Daim ntawv thov Project
Nios VC/C++ daim ntawv thov qhov project muaj cov yam ntxwv hauv qab no: · Muaj cov ntawv sau los ntawm qhov chaws thiab CMakeLists.txt.
- Lub CMakeLists.txt suav nrog cov cai thiab txuas nws nrog BSP thiab ib lossis ntau lub tsev qiv ntawv xaiv, los tsim ib qho .elf file
· Ib qhov chaw files muaj nuj nqi main(). · suav nrog cov lej uas hu ua haujlwm hauv cov tsev qiv ntawv thiab BSPs.
Altera muab niosv-app cov cuab yeej siv hluav taws xob hauv Quartus Prime software cov cuab yeej siv hluav taws xob los tsim Daim Ntawv Thov CMakeLists.txt, thiab RiscFree IDE rau Altera FPGAs los hloov kho cov cai hauv ib puag ncig dab noj hnub.
3.2. Altera FPGA Embedded Development Tools
Nios V processor txhawb nqa cov cuab yeej hauv qab no rau kev txhim kho software: · Graphical User Interface (GUI) - Graphical development tools uas muaj nyob rau hauv
Windows* thiab Linux* Operating Systems (OS). - Nios V Board Support Package Editor (Nios V BSP Editor) - Ashling RiscFree IDE for Altera FPGAs · Command-Line Tools (CLI) - Cov cuab yeej tsim kho uas tau pib los ntawm Nios V Command Plhaub. Txhua lub cuab yeej muab nws cov ntaub ntawv nyob rau hauv daim ntawv ntawm kev pab nkag tau los ntawm kab hais kom ua. Qhib Nios V Command Shell thiab ntaus cov lus txib hauv qab no: - pab rau view cov ntawv qhia pab. — Nios V Utilities Tools — File Hom Hloov Cov Cuab Yeej - Lwm Cov Cuab Yeej Siv Hluav Taws Xob

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 43

3. Nios V Processor Software System Design 726952 | 2025.07.16

Table 25. GUI Cov Cuab Yeej thiab Cov Cuab Yeej Command-line Tasks Summary

Ua haujlwm

GUI Tool

Command-line Tool

Tsim BSP

Nios V BSP Editor

· Hauv Quartus Prime Pro Edition software: niosv-bsp -c -s=<.qsys file> -t= [Xov Xwm] settings.bsp
· Hauv Quartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t= [Xov Xwm] settings.bsp

Tsim ib tug BSP siv .bsp file
Hloov kho BSP

Nios V BSP Editor Nios V BSP Editor

niosv-bsp -g [OPTIONS] settings.bsp niosv-bsp -u [OPTIONS] settings.bsp

Tshawb xyuas BSP

Nios V BSP Editor

niosv-bsp -q -E= [Xov Xwm] settings.bsp

Tsim ib daim ntawv thov

niosv-app -a = -b= -s = files directory> [OPTIONS]

Tsim ib lub tsev qiv ntawv siv

niosv-app -l= -s = files directory> -p= [Xav tau]

Hloov daim ntawv thov Hloov kho cov neeg siv tsev qiv ntawv Tsim ib daim ntawv thov

RiscFree IDE rau Altera FPGAs
RiscFree IDE rau Altera FPGAs
RiscFree IDE rau Altera FPGAs

Ib qho kev hais kom ua kab qhov chaw editor
Ib qho kev hais kom ua kab qhov chaw editor
· ua · ua

Tsim ib lub tsev qiv ntawv siv

RiscFree IDE rau Altera FPGAs

· ua · ua

Downloading ib daim ntawv thov ELF
Hloov ua lwm yam .elf file

RiscFree IDE rau Altera FPGAs
-

niosv-download
· elf2flash · elf2hex

Cov ntaub ntawv ntsig txog
Ashling RiscFree Integrated Development Ib puag ncig (IDE) rau Altera FPGAs Tus Neeg Siv Qhia

3.2.1. Nios V Processor Board Support Package Editor
Koj tuaj yeem siv Nios V processor BSP Editor los ua cov haujlwm hauv qab no: · Tsim lossis hloov kho Nios V processor BSP project · Kho cov chaw, txuas cov cheeb tsam, thiab cov ntawv qhia ntu · Xaiv cov pob software thiab cov tsav tsheb.
Lub peev xwm ntawm BSP Editor suav nrog cov peev txheej ntawm cov khoom siv niosv-bsp. Txhua qhov project tsim hauv BSP Editor tuaj yeem tsim los siv cov khoom siv kab hais kom ua.

Nios® V Embedded Processor Design Phau Ntawv 44

Xa lus tawm tswv yim

3. Nios V Processor Software System Design 726952 | 2025.07.16

Nco tseg:

Rau Quartus Prime Standard Edition software, xa mus rau AN 980: Nios V Processor Quartus Prime Software Txhawb nqa rau cov kauj ruam los hu rau BSP Editor GUI.

Txhawm rau qhib BSP Editor, ua raws li cov kauj ruam no: 1. Qhib Platform Designer, thiab mus rau qhov File zaub mov.
ib. Txhawm rau qhib qhov chaw BSP uas twb muaj lawm file, nyem Qhib… b. Txhawm rau tsim BSP tshiab, nyem New BSP… 2. Xaiv lub BSP Editor tab thiab muab cov ntsiab lus tsim nyog.

Daim duab 27. Tua tawm BSP Editor

Cov ntaub ntawv ntsig txog AN 980: Nios V Processor Quartus Prime Software Support
3.2.2. RiscFree IDE rau Altera FPGAs
RiscFree IDE rau Altera FPGAs yog Eclipse-based IDE rau Nios V processor. Altera pom zoo kom koj tsim Nios V processor software hauv IDE no rau cov laj thawj hauv qab no: · Cov yam ntxwv tau tsim thiab txheeb xyuas kom haum rau Nios V
processor tsim flow. · Nruab nrog tag nrho cov cuab yeej tsim nyog thiab cov cuab yeej txhawb nqa uas ua rau koj
kom yooj yim pib Nios V processor txhim kho.
Cov ntaub ntawv ntsig txog Ashling RiscFree Integrated Development Environment (IDE) rau Altera FPGAs Tus Neeg Siv Qhia
3.2.3. Nios V Utilities Tools
Koj tuaj yeem tsim, hloov kho, thiab tsim Nios V cov kev pabcuam nrog cov lus txib ntaus ntawm kab hais kom ua lossis kos rau hauv tsab ntawv. Nios V cov cuab yeej hais kom ua kab tau piav qhia hauv ntu no yog nyob rau hauv /niosv/bin directory.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 45

3. Nios V Processor Software System Design 726952 | 2025.07.16

Table 26. Nios V Utilities Tools

Cov cuab yeej hais kom ua kab

Cov ntsiab lus

niosv-app niosv-bsp niosv-download niosv-plhaub niosv-stack-report

Tsim thiab configure ib daim ntawv thov project.
Txhawm rau tsim lossis hloov kho BSP nqis file thiab tsim BSP files. Txhawm rau rub tawm ELF file rau Nios® V processor.
Txhawm rau qhib Nios V Command Plhaub. Txhawm rau qhia koj txog qhov chaw nco seem tshuav muaj rau koj daim ntawv thov .elf rau pawg lossis siv heap.

3.2.4. File Hom Hloov Cov Cuab Yeej

File hom kev hloov dua siab tshiab yog qee zaum tsim nyog thaum dhau cov ntaub ntawv los ntawm ib qho khoom siv mus rau lwm qhov. Cov file hom ntawv conversion cuab yeej yog nyob rau hauv lub
software installation directory> / niosv/bin directory.

Table 27. File Hom Hloov Cov Cuab Yeej

Command-Line Tools elf2flash elf2hex

Summary Kom txhais lub .elf file rau .srec hom ntawv rau flash nco programming. Txhais cov .elf file rau .hex hom ntawv rau kev nco pib.

3.2.5. Lwm cov cuab yeej siv hluav taws xob

Tej zaum koj yuav xav tau cov cuab yeej hauv qab no thaum tsim Nios V processor raws li qhov system. Cov cuab yeej hais kom ua kab no yog muab los ntawm Intel hauv /quartus/bin los yog tau los ntawm
cov cuab yeej qhib.

Table 28. Lwm cov cuab yeej hais kom ua kab

Cov cuab yeej hais kom ua kab

Hom

Cov ntsiab lus

juart-terminal

Intel muab

Txhawm rau saib xyuas stdout thiab stderr, thiab muab tswv yim rau Nios® V processor
subsystem los ntawm stdin. Cov cuab yeej no tsuas yog siv rau JTAG UART IP thaum nws txuas nrog Nios® V processor.

openocd

Intel tau muab los ua OpenOCD.

openocd-cfg-gen

Intel-provided · Los tsim cov kev teeb tsa OpenOCD file. · Mus saib JTAG chain device index.

Nios® V Embedded Processor Design Phau Ntawv 46

Xa lus tawm tswv yim

726952 | 2025.07.16 Xa lus tawm tswv yim
4. Nios V Processor Configuration thiab Booting Solutions
Koj tuaj yeem teeb tsa Nios V processor kom khau raj thiab tua software los ntawm ntau qhov chaw nco. Lub cim xeeb khau raj yog Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), lossis Tightly Coupled Memory (TCM).
Cov ntaub ntawv ntsig txog · Fais fab-Up Trigger tej yam kev mob ntawm nplooj 193 · Fais fab-Up Triggers
Yog xav paub ntxiv txog lub zog-up triggers.
4.1. Taw qhia
Nios V processor txhawb nqa ob hom txheej txheem khau raj: · Execute-in-Place (XIP) siv alt_load() muaj nuj nqi · Program luam rau RAM siv khau raj tshuab luam ntawv. Nios V embedded cov kev pab cuam kev txhim kho yog raws li hardware abstraction txheej (HAL). HAL muab cov kev pabcuam khau raj me me (tseem hu ua khau raj tshuab luam ntawv) uas luam cov ntu txuas txuas ntawm lub cim xeeb khau raj rau lawv lub sijhawm ua haujlwm ntawm lub sijhawm khau raj. Koj tuaj yeem qhia meej txog qhov kev zov me nyuam thiab cov ntaub ntawv lub cim xeeb khiav lub sijhawm los ntawm kev tswj hwm Pawg Pabcuam Txhawb Pab Pawg (BSP) Editor nqis. Ntu no piav qhia txog: · Nios V processor khau raj tshuab luam ntawv uas khau raj koj Nios V processor system raws li
kev xaiv khau raj lub cim xeeb · Nios V processor booting xaiv thiab dav dav · Nios V programming daws rau cov xaiv khau raj nco
4.2. Txuas daim ntawv thov
Thaum koj tsim Nios V processor project, BSP Editor tsim ob qhov txuas txuas files: · linker.x: linker command file uas generated daim ntawv thov uafile siv
los tsim .elf binary file. · linker.h: Muaj cov ntaub ntawv hais txog qhov linker nco layout. Txhua qhov txuas txuas qhov kev hloov kho koj ua rau BSP qhov project cuam tshuam rau cov ntsiab lus ntawm ob qhov txuas txuas files. Txhua daim ntawv thov Nios V processor muaj cov txuas txuas hauv qab no:
© Altera Corporation. Altera, Altera logo, 'a' logo, thiab lwm yam Altera cov cim yog cov cim lag luam ntawm Altera Corporation. Altera muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Altera xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, khoom, lossis kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo los ntawm kev sau ntawv los ntawm Altera. Altera cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Table 29. Linker Sections

. ntawv

Linker Sections

.rodata

.rwdata

.bss

.khob

. pawg

Cov lus piav qhia Executable code. Txhua cov ntaub ntawv nyeem nkaus xwb siv hauv kev ua tiav ntawm qhov program. Khaws cov ntaub ntawv nyeem-sau siv hauv kev ua tiav ntawm qhov program. Muaj cov ntaub ntawv zoo li qub uas tsis tsim nyog. Muaj dynamically faib lub cim xeeb. Khaws cov khoom ua haujlwm-hu tsis siv thiab lwm cov ntaub ntawv ib ntus.

Koj tuaj yeem ntxiv cov txuas txuas ntxiv rau .elf file tuav cov cai thiab cov ntaub ntawv. Cov kab txuas txuas no tau muab tso rau hauv lub npe hu ua cheeb tsam nco, txhais kom sib haum nrog lub cev nco thiab chaw nyob. Los ntawm lub neej ntawd, BSP Editor cia li tsim cov kab txuas txuas no. Txawm li cas los xij, koj tuaj yeem tswj cov kab txuas txuas rau ib daim ntawv thov tshwj xeeb.

4.2.1. Txuas Cwj Pwm
Tshooj lus no piav qhia txog BSP Editor default linking behaviour thiab yuav ua li cas tswj tus cwj pwm txuas.

4.2.1.1. Default BSP Linking
Thaum lub sij hawm BSP configuration, cov cuab yeej ua cov kauj ruam hauv qab no tau txais:
1. Muab cov npe hauv cheeb tsam nco: Muab ib lub npe rau txhua qhov system nco thiab ntxiv txhua lub npe rau tus txuas file ua ib cheeb tsam nco.
2. Nrhiav lub cim xeeb loj tshaj plaws: Qhia qhov loj tshaj plaws nyeem-thiab-sau cheeb tsam hauv lub cim xeeb txuas file.
3. Muab cov kab txuas txuas: Muab cov seem txuas txuas (.text, .rodata, .rwdata, .bss, .heap, thiab .stack) hauv thaj tsam nco tau txheeb xyuas hauv cov kauj ruam dhau los.
4. Sau files: Sau cov linker.x thiab linker.h files.
Feem ntau, qhov txuas txuas txuas faib cov phiaj xwm ua haujlwm thaum lub sijhawm txhim kho software vim tias daim ntawv thov tau lees paub ua haujlwm yog tias lub cim xeeb loj txaus.
Cov kev cai rau kev sib txuas tus cwj pwm yog muaj nyob rau hauv Altera-tsim Tcl scripts bsp-set-defaults.tcl thiab bsp-linker-utils.tcl pom nyob rau hauv /niosv/scripts/bsp-defaults directory. Cov lus txib niosv-bsp hu cov ntawv no. Tsis txhob hloov cov ntawv sau ncaj qha.

Nios® V Embedded Processor Design Phau Ntawv 48

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

4.2.1.2. Configurable BSP Txuas
Koj tuaj yeem tswj hwm tus cwj pwm sib txuas ua ntej hauv Linker Script tab ntawm BSP Editor. Manipulate tus linker tsab ntawv siv cov hauv qab no: · Ntxiv ib cheeb tsam nco: Maps lub cim xeeb cheeb tsam lub npe mus rau lub cev lub cim xeeb ntaus ntawv. · Ntxiv daim ntawv qhia seem: Qhia cov npe ntu rau thaj tsam nco. Lub BSP
Editor tso cai rau koj mus view daim ntawv qhia nco ua ntej thiab tom qab hloov.

4.3. Nios V Processor Booting Methods

Muaj ob peb txoj hauv kev los khau raj Nios V processor hauv Altera FPGA li. Cov txheej txheem rau khau raj Nios V processor sib txawv raws li kev xaiv flash nco thiab tsev neeg ntaus ntawv.

Table 30. Txhawb Flash Memories nrog Respective Boot Options

Txhawb Boot Memories

Ntaus ntawv

On-Chip Flash (rau Internal configuration)

Max 10 li tsuas yog (nrog On-Chip Flash IP)

Lub Hom Phiaj QSPI Flash (rau cov neeg siv cov ntaub ntawv nkaus xwb)

Tag nrho cov txhawb FPGA li (nrog Generic Serial Flash Interface FPGA IP)

Configuration QSPI Flash (rau Active Serial configuration)

Tswj thaiv-raws li
cov khoom siv (nrog Generic
Serial Flash Interface Intel FPGA IP) (2)

Nios V Processor Booting Methods

Application Runtime Location

Khau raj tshuab luam ntawv

Nios V processor application executein-place from On-Chip Flash

On-Chip Flash (XIP) + OCRAM / Sab nraud RAM (rau cov ntaub ntawv sau tau)

alt_load() muaj nuj nqi

Nios V processor tau theej los ntawm On-Chip Flash rau RAM siv khau raj theej

OCRAM / Sab nraud RAM

Rov qab siv Bootloader ntawm GSFI

Nios V processor application executein-place from general purpose QSPI flash

Lub hom phiaj dav dav QSPI flash (XIP) + OCRAM / Sab nraud RAM (rau cov ntaub ntawv sau tau)

alt_load() muaj nuj nqi

Nios V processor daim ntawv thov theej los ntawm lub hom phiaj dav dav QSPI flash rau RAM siv khau raj tshuab luam ntawv

OCRAM / Sab nraud RAM

Bootloader ntawm GSFI

Nios V processor application executein-place from configuration QSPI flash

Configuration QSPI flash (XIP) + OCRAM / Sab nraud RAM (rau cov ntaub ntawv sau tau)

alt_load() muaj nuj nqi

Nios V processor daim ntawv thov theej los ntawm kev teeb tsa QSPI flash rau RAM siv khau raj tshuab luam ntawv

OCRAM / Sab nraud RAM Bootloader ntawm GSFI txuas ntxiv…

(2) Xa mus rau AN 980: Nios V Processor Quartus Prime Software Txhawb nqa rau cov npe ntaus ntawv.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 49

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Txhawb Boot Memories
On-chip Memory (OCRAM) Tightly Coupled Memory (TCM)

Ntaus ntawv
SDM-based khoom siv (nrog Mailbox Client Intel FPGA IP). (2)
Txhua qhov txhawb Altera FPGA li (2)
Txhua qhov txhawb Altera FPGA li (2)

Nios V Processor Booting Methods
Nios V processor daim ntawv thov theej los ntawm kev teeb tsa QSPI flash rau RAM siv khau raj tshuab luam ntawv
Nios V processor application executein-place from OCRAM
Nios V processor application executein-place from TCM

Application Runtime Location

Khau raj tshuab luam ntawv

OCRAM / Sab nraud RAM Bootloader ntawm SDM

OCRAM

alt_load() muaj nuj nqi

Kev qhia TCM (XIP) Tsis muaj + Cov Ntaub Ntawv TCM (rau cov ntaub ntawv sau tau)

Daim duab 28. Nios V Processor Boot Flow

Rov pib dua

Processor dhia mus pib dua vector (boot code pib)

Daim ntawv thov code yuav raug theej rau lwm qhov chaw nco (nyob ntawm kev xaiv khau raj)
Boot code pib lub processor

Nyob ntawm kev xaiv khau raj, khau raj code tuaj yeem luam thawj qhov tseem ceeb rau cov ntaub ntawv / chaws rau lwm qhov chaw nco (alt_load)
Boot code pib ua daim ntawv thov code thiab cov ntaub ntawv nco qhov chaw
Boot code pib tag nrho cov kab ke peripherals nrog HAL tsav tsheb (alt_main)
Nkag mus rau lub ntsiab
Cov ntaub ntawv ntsig txog · Generic Serial Flash Interface Altera FPGA IP Tus Neeg Siv Qhia
Nios® V Embedded Processor Design Phau Ntawv 50

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
· Mailbox Client Altera FPGA IP User Guide · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Taw qhia rau Nios V Processor Booting Methods
Nios V processor systems xav tau cov duab software kom teeb tsa hauv lub cim xeeb ua ntej lub processor tuaj yeem pib ua tiav daim ntawv thov kev pab cuam. Xa mus rau Linker Sections rau cov seem txuas txuas.
BSP Editor tsim cov ntawv txuas uas ua haujlwm hauv qab no: · Xyuas kom meej tias cov software software txuas nrog raws li qhov txuas txuas
ntawm BSP editor thiab txiav txim siab qhov twg software nyob hauv nco. · Tso lub processor lub code cheeb tsam nyob rau hauv lub cim xeeb tivthaiv raws li lub
muab lub cim xeeb.
Cov ntu hauv qab no piav qhia luv luv txog Nios V processor booting txoj kev.
4.4.1. Nios V Processor Application Execute-In-Place from Boot Flash
Altera tsim cov flash controllers xws li khau raj flash chaw nyob tam sim ntawd nkag mus rau Nios V processor thaum lub kaw lus rov pib dua, tsis tas yuav pib lub cim xeeb tswj lossis cov khoom siv nco. Qhov no ua rau Nios V processor los ua cov ntawv thov code khaws cia ntawm cov khoom siv khau raj ncaj qha yam tsis siv lub tshuab luam ntawv khau raj los luam cov lej rau lwm hom nco. Cov maub los flash yog: · On-Chip Flash nrog On-Chip Flash IP (tsuas yog hauv MAX® 10 ntaus ntawv) · Lub hom phiaj QSPI flash nrog Generic Serial Flash Interface IP · Configuration QSPI flash nrog Generic Serial Flash Interface IP (tshwj tsis yog MAX 10
pab kiag li lawm)
Thaum daim ntawv thov Nios V processor ua-nyob rau hauv-qhov chaw los ntawm khau raj flash, BSP Editor ua cov haujlwm hauv qab no: · Teem cov .text linker seem rau khau raj flash nco cheeb tsam. · Teem lub .bss, .rodata, .rwdata, .stack thiab .heap linker seem rau RAM
cheeb tsam nco. Koj yuav tsum ua kom lub alt_load() ua haujlwm hauv BSP Chaw kom luam cov ntaub ntawv ntu (.rodata, .rwdata,, .exceptions) rau RAM thaum lub kaw lus rov pib dua. Tshooj cai (.text) tseem nyob hauv cheeb tsam khau raj flash nco.
Cov ntaub ntawv cuam tshuam · Generic Serial Flash Interface Altera FPGA IP Tus Neeg Siv Phau Ntawv Qhia · Altera MAX 10 Cov Neeg Siv Flash Memory Cov Lus Qhia
4.4.1.1. alt_load()
Koj tuaj yeem ua kom lub alt_load() ua haujlwm hauv HAL code siv BSP Editor.
Thaum siv hauv kev ua haujlwm-hauv-qhov chaw khau raj khiav, alt_load() muaj nuj nqi ua cov haujlwm hauv qab no:

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 51

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

· Ua haujlwm raws li lub tshuab luam ntawv me me uas luam cov ntu nco rau RAM raws li BSP nqis.
· Luam cov ntaub ntawv seem (.rodata, .rwdata, .exceptions) rau RAM tab sis tsis yog cov code seem (.text).Cov kab lus (.text) seem yog ib tug nyeem nkaus xwb thiab tseem nyob rau hauv lub booting flash nco cheeb tsam. Qhov kev faib tawm no yuav pab txo qis kev siv RAM tab sis tuaj yeem txwv cov lej ua haujlwm vim tias kev nkag mus rau lub cim xeeb flash qeeb dua li nkag mus rau ntawm lub cim xeeb RAM.

Cov lus hauv qab no teev BSP Editor nqis thiab ua haujlwm:

Table 31. BSP Editor Chaw
BSP Editor Teeb tsa hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Function Enables alt_load() muaj nuj nqi. alt_load() luam .rodata seem rau RAM. alt_load() luam .rwdata seem rau RAM. alt_load() luam .exceptions seem rau RAM.

4.4.2. Nios V Processor Daim ntawv thov theej los ntawm khau raj flash rau RAM siv khau raj tshuab luam ntawv
Nios V processor thiab HAL suav nrog lub tshuab luam ntawv khau raj uas muab kev ua haujlwm txaus rau feem ntau Nios V processor applications thiab yooj yim rau kev siv nrog Nios V software txhim kho ntws.
Thaum daim ntawv thov siv lub tshuab luam ntawv khau raj, nws teev tag nrho cov txuas txuas (.text, .heap, .rwdata, .rodata, .bss, .stack) rau ib qho RAM sab hauv lossis sab nraud. Siv lub tshuab luam ntawv khau raj los luam daim ntawv thov Nios V processor los ntawm khau raj flash mus rau sab hauv lossis sab nraud RAM rau kev ua haujlwm pab txhim kho kev ua tiav.
Rau qhov kev xaiv khau raj no, Nios V processor pib executing khau raj tshuab luam ntawv software thaum lub kaw lus pib dua. Lub software luam theej daim ntawv thov los ntawm khau raj flash mus rau sab hauv lossis sab nraud RAM. Thaum cov txheej txheem tiav lawm, Nios V processor hloov cov kev tswj hwm mus rau daim ntawv thov.

Nco tseg:

Yog tias lub tshuab luam ntawv khau raj yog nyob rau hauv flash, ces alt_load() ua haujlwm tsis tas yuav raug hu vim tias lawv ob leeg ua haujlwm tib lub hom phiaj.

4.4.2.1. Nios V Processor Bootloader ntawm Generic Serial Flash Interface
Lub Bootloader ntawm GSFI yog Nios V processor khau raj tshuab luam ntawv uas txhawb QSPI flash nco hauv kev tswj hwm cov khoom siv. Lub Bootloader ntawm GSFI suav nrog cov yam ntxwv hauv qab no:
· Nrhiav cov ntawv thov software hauv lub cim xeeb tsis hloov pauv.
· Unpacks thiab theej daim ntawv thov software duab rau RAM.
· Hloov pauv cov txheej txheem ua tiav rau daim ntawv thov code hauv RAM tom qab luam tiav.

Nios® V Embedded Processor Design Phau Ntawv 52

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Cov duab khau raj yog nyob tom qab lub tshuab luam ntawv khau raj. Koj yuav tsum xyuas kom meej Nios V processor pib dua cov ntsiab lus offset rau qhov pib ntawm lub tshuab luam ntawv khau raj. Daim duab: Daim ntawv qhia nco rau QSPI Flash nrog Bootloader ntawm GSFI nco daim ntawv qhia rau QSPI Flash nrog Bootloader ntawm GSFI qhia lub cim xeeb daim ntawv qhia rau QSPI flash thaum siv khau raj tshuab luam ntawv. Daim ntawv qhia kev nco no xav tias lub cim xeeb flash khaws cov duab FPGA thiab daim ntawv thov software.

Table 32. Bootloader ntawm GSFI rau Nios V Processor Core

Nios V Processor Core
Nios V/m processor

Bootloader ntawm GSFI File Qhov chaw
/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/components/bootloader/ niosv_g_bootloader.srec

Daim duab 29. Daim ntawv qhia nco rau QSPI Flash nrog Bootloader ntawm GSFI

Cov ntaub ntawv neeg siv khoom (*.hex)

Daim ntawv thov Code

Nco tseg:

Pib dua Vector Offset

Khau raj tshuab luam ntawv

0 x01e00000

FPGA Duab (*.sof)

0 x 00000000

1. Thaum pib ntawm daim ntawv qhia nco yog FPGA duab ua raws li koj cov ntaub ntawv, uas muaj cov tshuab luam ntawv khau raj thiab daim ntawv thov code.
2. Koj yuav tsum teeb tsa Nios V processor pib dua offset hauv Platform Designer thiab taw tes rau qhov pib ntawm lub tshuab luam ntawv khau raj.
3. Qhov loj ntawm cov duab FPGA tsis paub.Koj tsuas tuaj yeem paub qhov loj me tom qab Quartus Prime qhov project muab tso ua ke. Koj yuav tsum tau txiav txim siab ib sab sauv rau qhov loj ntawm Altera FPGA duab. Rau example, yog tias qhov luaj li cas ntawm FPGA duab kwv yees tsawg dua 0x01E00000, teeb tsa Reset Offset rau 0x01E00000 hauv Platform Designer, uas kuj yog qhov pib ntawm lub tshuab luam ntawv khau raj.
4. Kev coj ua zoo tsim muaj qhov teeb tsa rov pib dua vector offset ntawm ib thaj tsam flash kom tsis txhob muaj ib feem ntawm cov duab FPGA tshwm sim yog tias daim ntawv thov software hloov kho.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 53

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

4.4.2.2. Nios V Processor Bootloader ntawm Secure Device Manager
Lub Bootloader ntawm Secure Device Manager (SDM) yog HAL daim ntawv thov code siv Mailbox Client Altera FPGA IP HAL tsav tsheb rau processor booting. Altera pom zoo rau daim ntawv thov bootloader no thaum siv lub teeb tsa QSPI flash hauv SDM-based li txhawm rau khau raj Nios V processor.
Thaum lub kaw lus rov pib dua, Nios V processor thawj zaug khau raj Bootloader ntawm SDM los ntawm lub cim xeeb me me ntawm lub cim xeeb thiab ua tiav lub Bootloader ntawm SDM los sib txuas lus nrog lub teeb tsa QSPI flash siv Mailbox Client IP.
Lub Bootloader ntawm SDM ua cov haujlwm hauv qab no: · Nrhiav Nios V software hauv kev teeb tsa QSPI flash. · Luam the Nios V software rau hauv-chip RAM lossis lwm RAM. · Hloov cov txheej txheem ua tiav rau Nios V software nyob rau hauv-chip RAM lossis
sab nraud RAM.
Thaum cov txheej txheem tiav lawm, Bootloader ntawm SDM hloov chaw tswj hwm rau cov neeg siv daim ntawv thov. Altera pom zoo lub koom haum nco raws li tau teev tseg hauv Lub Koom Haum Memory rau Bootloader ntawm SDM.
Daim duab 30. Bootloader ntawm SDM Process Flow

Kev teeb tsa

Flash

Nios V Software

SDM

SDM-raws li FPGA Device

Mailbox Client IP

FPGA Logic Nios V

4 Sab nraud RAM
Nios V Software

On-Chip 4

EMIF

RAM

On-Chip Nco

Nios V

Software

Bootloader ntawm SDM

1. Nios V processor khiav lub Bootloader ntawm SDM los ntawm on-chip nco.
2. Bootloader ntawm SDM sib txuas lus nrog cov teeb tsa flash thiab nrhiav cov software Nios V.
3. Bootloader ntawm SDM luam theej Nios V software los ntawm Configuration Flash rau hauv-chip RAM / sab nraud RAM.
4. Bootloader ntawm SDM hloov Nios V processor tua rau Nios V software hauv on-chip RAM / sab nraud RAM.

4.4.3. Nios V Processor Application Execute-In-Place from OCRAM
Nyob rau hauv txoj kev no, Nios V processor reset chaw nyob yog teem rau lub hauv paus chaw nyob ntawm on-chip nco (OCRAM). Daim ntawv thov binary (.hex) file yog loaded rau hauv OCRAM thaum FPGA teeb tsa, tom qab kho vajtse tsim tau muab tso ua ke hauv Quartus Prime software. Thaum Nios V processor rov pib dua, daim ntawv thov pib ua haujlwm thiab ceg mus rau qhov chaw nkag.

Nios® V Embedded Processor Design Phau Ntawv 54

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Nco tseg:

· Execute-In-Place los ntawm OCRAM tsis tas yuav khau raj tshuab luam ntawv vim Nios V processor daim ntawv thov twb nyob rau hauv qhov chaw ntawm qhov system pib dua.
· Altera pom zoo kom ua kom alt_load() rau txoj kev booting no kom cov software embedded coj zoo ib yam thaum pib dua yam tsis tau teeb tsa FPGA cov duab.
· Koj yuav tsum ua kom lub alt_load() muaj nuj nqi hauv BSP Chaw kom luam cov ntu .rwdata raws li qhov system rov pib dua. Nyob rau hauv txoj kev no, thawj qhov tseem ceeb rau qhov pib hloov pauv tau muab cais los ntawm cov sib txawv sib xws kom tsis txhob sau overwriting ntawm kev ua haujlwm.

4.4.4 ib. Nios V Processor Application Execute-In-Place from TCM
Txoj kev ua-nyob rau hauv-qhov chaw teeb tsa Nios V processor reset chaw nyob rau lub hauv paus chaw nyob ntawm lub cim xeeb nruj (TCM). Daim ntawv thov binary (.hex) file yog loaded rau hauv TCM thaum koj configure FPGA tom qab koj sau cov kho vajtse tsim nyob rau hauv lub Quartus Prime software. Thaum Nios V processor rov pib dua, daim ntawv thov pib ua haujlwm thiab ceg mus rau qhov chaw nkag.

Nco tseg:

Execute-In-Place los ntawm TCM tsis tas yuav khau raj tshuab luam ntawv vim Nios V processor daim ntawv thov twb nyob rau hauv qhov chaw ntawm qhov system pib dua.

4.5. Nios V Processor Booting los ntawm On-Chip Flash (UFM)

Nios V processor booting thiab executing software los ntawm on-chip flash (UFM) muaj nyob rau hauv MAX 10 FPGA li. Nios V processor txhawb nqa ob qho kev xaiv khau raj hauv qab no siv On-Chip Flash hauv Internal Configuration hom:
· Nios V processor application executes in-place from On-Chip Flash.
· Nios V processor daim ntawv thov yog theej los ntawm On-Chip Flash rau RAM siv khau raj tshuab luam ntawv.

Table 33. Txhawb Flash Memories nrog rau khau raj xaiv

Txhawb Boot Memories

Nios V Booting Methods

Application Runtime Location

Khau raj tshuab luam ntawv

MAX 10 li tsuas yog (nrog OnChip Flash IP)

Nios V processor application executein-place from On-Chip Flash
Nios V processor tau theej los ntawm On-Chip Flash rau RAM siv khau raj theej

On-Chip Flash (XIP) + OCRAM / Sab nraud RAM (rau cov ntaub ntawv sau tau)

alt_load() muaj nuj nqi

OCRAM / Sab nraud RAM

Rov qab siv Bootloader ntawm GSFI

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 55

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Daim duab 31.

Design, Configuration, thiab Booting Flow
Tsim · Tsim koj Nios V Processor raws li qhov project siv Platform Designer. · Xyuas kom meej tias muaj cov RAM sab nraud lossis on-chip RAM hauv qhov system tsim.

FPGA Configuration thiab Compilation
· Teem ib hom kev teeb tsa sab hauv hauv On-chip Flash IP hauv Platform Designer thiab Quartus Prime software. · Teem Nios V processor pib dua tus neeg sawv cev rau On-chip Flash. · Xaiv koj txoj kev pib UFM uas koj nyiam. · Tsim koj tus qauv tsim hauv Platform Designer. · Sau koj qhov project hauv Quartus Prime software.

Tus neeg siv daim ntawv thov BSP Project · Tsim Nios V processor HAL BSP raws li .sopcinfo file tsim los ntawm Platform Designer. · Kho Nios V processor BSP nqis thiab Linker Script hauv BSP Editor. · Tsim BSP project.
Tus neeg siv daim ntawv thov APP Project · Tsim Nios V processor daim ntawv thov code. · Compile Nios V processor application thiab tsim Nios V processor application (.hex) file. · Recompile koj qhov project hauv Quartus Prime software yog tias koj tshawb xyuas Initialize nco cov ntsiab lus xaiv hauv Intel FPGA On-Chip Flash IP.

Programming Files Hloov, Download thiab khiav · Tsim lub On-Chip Flash .pof file siv Convert Programming Files feature hauv Quartus Prime software.
· Program .pof file rau hauv koj MAX 10 ntaus ntawv. · Fais fab voj voog koj kho vajtse.
4.5.1. MAX 10 FPGA On-Chip Flash Description
MAX 10 FPGA cov cuab yeej muaj nyob rau hauv-chip flash uas yog segmented ua ob ntu: · Configuration Flash Memory (CFM) - khaws cov ntaub ntawv kho vajtse rau
MAX 10 FPGAs. · Tus Neeg Siv Flash Memory (UFM) — khaws cov ntaub ntawv tus neeg siv lossis cov ntawv thov software.
UFM architecture ntawm MAX 10 ntaus ntawv yog kev sib txuas ntawm cov mos mos thiab tawv IPs. Koj tsuas tuaj yeem nkag mus rau UFM siv On-Chip Flash IP Core hauv Quartus Prime software.
Lub On-chip Flash IP core txhawb cov yam ntxwv hauv qab no: · Nyeem lossis sau nkag mus rau UFM thiab CFM (yog tias qhib rau hauv Platform Designer) cov haujlwm
siv Avalon MM cov ntaub ntawv thiab tswj qhev interface. · Txhawb cov nplooj ntawv erase, sector erase thiab sector sau. · Simulation qauv rau UFM nyeem / sau nkag siv ntau yam EDA simulation cuab yeej.

Nios® V Embedded Processor Design Phau Ntawv 56

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Table 34. On-chip Flash Regions hauv MAX 10 FPGA Devices

Flash Regions

Kev ua haujlwm

Configuration Flash Memory (sectors CFM0-2)

FPGA configuration file khaws cia

Tus neeg siv Flash Memory (sectors UFM0-1)

Nios V processor application thiab user data

MAX 10 FPGA cov cuab yeej txhawb nqa ntau hom kev teeb tsa thiab qee yam ntawm cov qauv no tso cai rau CFM1 thiab CFM2 siv los ua thaj tsam UFM ntxiv. Cov lus hauv qab no qhia qhov chaw cia ntawm FPGA teeb tsa cov duab raws li MAX 10 FPGA cov qauv teeb tsa.

Table 35. Cia qhov chaw ntawm FPGA Configuration Images

Configuration Hom Dual compressed duab

CFM2 Compressed Duab 2

SIB 1

CFM0 Compressed Duab 1

Ib daim duab uncompressed

Virtual UFM

Uncompressed duab

Ib daim duab uncompressed nrog Memory Initialization

Uncompressed duab (nrog pre-initialized on-chip nco cov ntsiab lus)

Ib daim duab compressed nrog Memory Initialization Compressed duab (nrog pre-initialized on-chip nco cov ntsiab lus)

Ib daim duab compressed

Virtual UFM

Compressed duab

Koj yuav tsum siv On-chip Flash IP core kom nkag mus rau lub cim xeeb flash hauv MAX 10 FPGAs. Koj tuaj yeem instantiate thiab txuas On-chip Flash IP rau Quartus Prime software. Nios V soft core processor siv Platform Designer interconnects los sib txuas lus nrog On-chip Flash IP.
Daim duab 32. Kev sib txuas ntawm On-chip Flash IP thiab Nios V Processor

Nco tseg:

Xyuas kom tseeb tias On-chip Flash csr chaw nres nkoj txuas nrog Nios V processor data_manager kom lub processor tswj kev sau ntawv thiab tshem tawm cov haujlwm.
Lub On-chip Flash IP core tuaj yeem muab kev nkag mus rau tsib qhov chaw flash - UFM0, UFM1, CFM0, CFM1, thiab CFM2.
Cov ntaub ntawv tseem ceeb hais txog UFM thiab CFM sectors.: · CFM sectors yog npaj rau configuration (bitstream) cov ntaub ntawv (*.pof) cia.
· Cov neeg siv cov ntaub ntawv tuaj yeem muab khaws cia rau hauv UFM cov haujlwm thiab yuav raug muab zais, yog tias qhov chaw raug xaiv raug xaiv hauv Platform Designer tool.
· Tej yam khoom siv tsis muaj UFM1 sector. Koj tuaj yeem xa mus rau lub rooj: UFM thiab CFM Sector Loj rau cov haujlwm muaj nyob hauv txhua tus neeg MAX 10 FPGA ntaus ntawv.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 57

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

· Koj tuaj yeem teeb tsa CFM2 raws li UFM virtual los ntawm kev xaiv ib hom kev teeb tsa Cov Duab Tsis Txaus Siab.
· Koj tuaj yeem teeb tsa CFM2 thiab CFM1 ua lub UFM virtual los ntawm kev xaiv ib hom kev teeb tsa uas tsis muaj duab.
· Qhov loj ntawm txhua qhov chaw sib txawv nrog cov xaiv MAX 10 FPGA li.

Table 36.

UFM thiab CFM Sector Size
Cov lus no teev qhov ntev ntawm UFM thiab CFM arrays.

Ntaus ntawv

Pages per Sector

UFM1 UFM0 CFM2 CFM1 CFM0

Nplooj ntawv loj (Kbit)

Cov neeg siv siab tshaj plaws
Flash Memory Loj (Kbit) (3)

Tag Nrho Configuration Memory Size (Kbit)

10m02 3

544

10m04 0

41 29

1248

2240

10m08 8

41 29

1376

2240

10m16 4

38 28

2368

4224

10m25 4

52 40

3200

5888

10m40 4

48 36

5888

10752

10m50 4

48 36

5888

10752

OCRAM Loj (Kbit)
108 189 378 549 675 1260 1638

Related Information · MAX 10 FPGA Configuration User Guide · Altera MAX 10 User Flash Memory User Guide

4.5.2 ib. Nios V Processor Application Execute-In-Place from UFM

Lub Execute-In-Place los ntawm UFM kev daws teeb meem yog tsim rau Nios V processor daim ntaub ntawv uas yuav tsum tau txwv nyob rau hauv-chip nco siv. Lub alt_load() muaj nuj nqi ua haujlwm raws li lub tshuab luam ntawv me me uas luam cov ntaub ntawv ntu (.rodata, .rwdata, lossis .exceptions) los ntawm khau raj nco rau RAM raws li BSP nqis. Tshooj cai (.text),
uas yog ib qho kev nyeem nkaus xwb, tseem nyob hauv MAX 10 On-chip Flash nco cheeb tsam. Qhov kev teeb tsa no txo qis kev siv RAM tab sis tuaj yeem txwv qhov kev ua tiav kev ua tiav raws li kev nkag mus rau lub cim xeeb flash qeeb dua li ntawm RAM.

Daim ntawv thov Nios V processor yog programmed rau hauv UFM sector. Nios V processor's reset vector point rau UFM puag chaw nyob kom ua tiav cov cai los ntawm UFM tom qab lub kaw lus rov pib dua.

Yog tias koj tab tom siv lub hauv paus-theem debugger los kho koj daim ntawv thov, koj yuav tsum siv hardware breakpoint. Qhov no yog vim UFM tsis txhawb kev nkag mus rau lub cim xeeb, uas yog qhov tsim nyog rau kev kho qhov muag tsis zoo.

Nco tseg:

Koj tsis tuaj yeem lwv lossis sau UFM thaum ua haujlwm-hauv-qhov chaw hauv MAX 10. Hloov mus rau khau raj tshuab luam ntawv yog tias koj xav tau lwv lossis sau UFM.

(3) Tus nqi siab tshaj plaws, uas yog nyob ntawm hom kev teeb tsa koj xaiv.

Nios® V Embedded Processor Design Phau Ntawv 58

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Daim duab 33. Nios V Processor Application XIP los ntawm UFM

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

On-Chip Flash

CFM

Nios V Hardware

UFM

Nios V Software

Sab hauv Configuration

On-Chip Flash IP

FPGA Logic
Nios V Processor

On-Chip RAM

Sab nraud

RAM

EMIF

4.5.2.1. Hardware Design Flow
Cov lus hauv qab no piav qhia txog cov txheej txheem ib ntus rau kev tsim lub tshuab bootable rau Nios V processor thov los ntawm On-Chip Flash. Cov example hauv qab no yog tsim los siv MAX 10 ntaus ntawv.
IP Component Settings
1. Tsim koj qhov project Nios V processor siv Quartus Prime thiab Platform Designer. 2. Nco ntsoov tias sab nraud RAM lossis On-Chip Memory (OCRAM) ntxiv rau koj lub Platform
Designer system.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 59

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
Daim duab 34. Example IP Kev Sib Txuas hauv Platform Designer rau Booting Nios V los ntawm OnChip Flash (UFM)

3. Nyob rau hauv On-Chip Flash IP parameter editor, teem lub Configuration hom mus rau ib qho ntawm cov nram qab no, raws li koj nyiam tsim: · Ib leeg Uncompressed duab · Ib tug Compressed duab · Ib tug Uncompressed Duab nrog Nco Initialization · Tib Compressed Duab nrog Nco Initialization
Yog xav paub ntxiv txog Dual Compressed Dluab, xa mus rau MAX 10 FPGA Configuration User Guide – Remote System Upgrade.

Nco tseg:

Koj yuav tsum muab Hidden Access rau txhua thaj tsam CFM hauv On-Chip Flash IP.

Daim duab 35. Configuration Mode Xaiv nyob rau hauv On-Chip Flash Parameter Editor

On-Chip Flash IP Chaw - UFM Initialization Koj tuaj yeem xaiv ib qho ntawm cov hauv qab no raws li koj nyiam:

Nios® V Embedded Processor Design Phau Ntawv 60

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Nco tseg:

Cov kauj ruam hauv cov tshooj tom ntej (Software Design Flow thiab Programming) nyob ntawm qhov kev xaiv koj ua ntawm no.

· Txoj Kev 1: Pib UFM cov ntaub ntawv hauv SOF thaum muab tso ua ke
Quartus Prime suav nrog UFM cov ntaub ntawv pib pib hauv SOF thaum muab tso ua ke. SOF recompilation yog xav tau yog tias muaj kev hloov pauv hauv UFM cov ntaub ntawv.
1. Tshawb xyuas Initialize flash cov ntsiab lus thiab Pab kom tsis yog qhov pib pib file.

Daim duab 36. Initialize Flash Cov Ntsiab Lus thiab Pab Kom Tsis Ua Haujlwm Initialization File

2. Qhia txoj hauv kev ntawm generated .hex file (los ntawm elf2hex hais kom ua) hauv Tus Neeg Siv tsim hex lossis mif file.
Daim duab 37. Ntxiv cov .hex File Txoj kev

· Txoj Kev 2: Muab UFM cov ntaub ntawv nrog SOF muab tso ua ke thaum lub sijhawm POF tiam
UFM cov ntaub ntawv yog ua ke nrog cov SOF compiled thaum converting programming files. Koj tsis tas yuav rov ua dua SOF, txawm tias UFM cov ntaub ntawv hloov pauv. Thaum lub sij hawm kev loj hlob, koj tsis tas yuav recompile SOF files rau kev hloov hauv daim ntawv thov. Alterarecommends txoj kev no rau daim ntawv thov developers.
1. Uncheck Initialize flash cov ntsiab lus..
Daim duab 38. Initialize Flash Cov ntsiab lus nrog Non-default Initialization File

Pib dua Tus Neeg Saib Xyuas Chaw rau Nios V Processor Ua-hauv-Place Method
1. Nyob rau hauv lub Nios V processor parameter editor, teem lub Reset Agent rau On-Chip Flash.
Daim duab 39. Nios V Processor Parameter Editor Chaw nrog Reset Agent Teem rau On-Chip Flash

2. Nyem Generate HDL thaum lub Generation dialog box tshwm. 3. Qhia cov zis file tiam xaiv thiab nias Tsim.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 61

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
Quartus Prime Software Settings 1. Hauv Quartus Prime software, nyem Assignments Device thiab Pin
Kev xaiv Configuration. Teem lub Configuration hom raws li qhov chaw hauv On-Chip Flash IP. Daim duab 40. Configuration Mode Xaiv nyob rau hauv Quartus Prime Software

2. Nyem OK kom tawm ntawm lub cuab yeej thiab Pin Options qhov rai,
3. Nyem OK kom tawm ntawm lub qhov rais ntaus ntawv.
4. Nyem Processing Start Compilation los sau koj qhov project thiab tsim cov .sof file.

Nco tseg:

Yog tias qhov kev teeb tsa hom teeb tsa hauv Quartus Prime software thiab Platform Designer parameter editor txawv, Quartus Prime project tsis ua tiav nrog cov lus yuam kev hauv qab no.

Daim duab 41.

Message yuam kev rau txawv Configuration Mode Teeb Meem yuam kev (14740): Configuration hom ntawm atom “q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block.” tsis phim. Hloov kho thiab rov tsim dua Qsys system kom phim qhov project teeb tsa.

Cov ntaub ntawv ntsig txog MAX 10 FPGA Configuration User Guide

4.5.2.2. Software Design Flow
Tshooj lus no muab cov qauv tsim los tsim thiab tsim Nios V processor software project. Txhawm rau txhawm rau txhim kho kev khiav dej num, koj raug txhawb kom tsim cov ntoo zoo sib xws hauv koj qhov project tsim. Cov software tsim tawm hauv qab no yog ua raws li cov npe ntoo no.
Txhawm rau tsim cov software project directory tsob ntoo, ua raws li cov kauj ruam no: 1. Nyob rau hauv koj tus tsim project folder, tsim ib tug folder hu ua software. 2. Hauv daim nplaub tshev software, tsim ob lub folders hu ua hal_app thiab hal_bsp.
Daim duab 42. Software Project Directory Tree

Nios® V Embedded Processor Design Phau Ntawv 62

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
Tsim Daim Ntawv Thov BSP Project
Txhawm rau tso tawm BSP Editor, ua raws cov kauj ruam no: 1. Nkag mus rau Nios V Command Plhaub. 2. Hu rau BSP Editor nrog niosv-bsp-editor hais kom ua. 3. Hauv BSP Editor, nyem File Tshiab BSP los pib koj qhov project BSP. 4. Configure cov chaw hauv qab no:
· SOPC Information File Lub npe: Muab SOPCINFO file (.sopcinfo). · CPU lub npe: Xaiv Nios V processor. · Kev khiav hauj lwm qhov system: Xaiv lub operating system ntawm Nios V processor. · Version: Cia li default. · BSP lub hom phiaj directory: Xaiv cov directory txoj kev ntawm BSP project. Koj ua tau
pre-set nws /software/hal_bsp los ntawm enabling Siv qhov chaw nyob. · BSP Chaw File lub npe: Ntaus lub npe ntawm BSP Chaw File. · Cov ntawv Tcl Ntxiv: Muab ib tsab ntawv BSP Tcl los ntawm kev ua kom Enable Ntxiv Tcl tsab ntawv. 5. Nyem OK.
Daim duab 43. Configure BSP tshiab

Configuring BSP Editor thiab tsim BSP Project
Koj tuaj yeem txhais lub processor qhov tshwj xeeb vector hauv On-Chip Memory (OCRAM) lossis On-Chip Flash raws li koj nyiam tsim. Kev teeb tsa qhov tshwj xeeb vector cim xeeb rau OCRAM / Sab Nraud RAM yog pom zoo kom ua rau kev cuam tshuam sai dua. 1. Mus rau Main Chaw Advanced hal.linker. 2. Yog tias koj xaiv On-Chip Flash raws li kev zam vector,
a. Qhib cov kev teeb tsa hauv qab no:

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 63

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Daim duab 44. Advanced.hal.linker Chaw

b. Nyem rau ntawm Linker Script tab hauv BSP Editor. c. Teem lub .exceptions thiab .text regions hauv Linker Section Name rau
On-Chip Flash. d. Teem cov seem ntawm thaj chaw hauv Linker Tshooj Npe npe rau On-Chip
Nco (OCRAM) lossis lwm RAM.
Daim duab 45. Linker Thaj Chaw Chaw (Tsuas Vector Memory: On-Chip Flash)

3. Yog tias koj xaiv OCRAM/Sternal RAM raws li kev zam vector, a. Qhib cov chaw hauv qab no: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Daim duab 46. Linker Thaj Chaw Chaw (Tsuas Vector Memory: OCRAM/External RAM)

b. Nyem rau ntawm Linker Script tab hauv BSP Editor.
c. Teem the.text regions hauv Linker Section Name rau On-Chip Flash.
d. Teem cov seem ntawm thaj chaw hauv Linker Tshooj Npe npe rau On-Chip Memory (OCRAM) lossis lwm RAM.

Nios® V Embedded Processor Design Phau Ntawv 64

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
Daim duab 47. Linker Thaj Chaw Chaw (Tshwj tsis yog Vector Memory: OCRAM)
4. Nyem Tsim los tsim qhov project BSP. Tsim tus neeg siv daim ntawv thov Project File 1. Nkag mus rau software / hal_app nplaub tshev thiab tsim koj qhov chaw thov
code. 2. Tua tawm Nios V Command Plhaub. 3. Ua raws li cov lus txib hauv qab no los tsim daim ntawv thov CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/
Tsim Tus Neeg Siv Daim Ntawv Thov Txoj Haujlwm Koj tuaj yeem xaiv los tsim tus neeg siv daim ntawv thov qhov project siv Ashling RiscFree IDE rau Altera FPGAs lossis los ntawm cov kab hais kom ua (CLI). Yog tias koj nyiam siv CLI, koj tuaj yeem tsim tus neeg siv daim ntawv thov siv cov lus txib hauv qab no: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
Daim ntawv thov (.elf) file yog tsim nyob rau hauv software/hal_app/build folder. Generating HEX File Koj yuav tsum tsim ib .hex file los ntawm koj daim ntawv thov .elf file, yog li koj tuaj yeem tsim .pof file haum rau programming cov cuab yeej. 1. Tua tawm Nios V Command Plhaub. 2. Rau Nios V processor thov khau raj ntawm On-Chip Flash, siv cov hauv qab no
kab hais kom hloov ELF rau HEX rau koj daim ntawv thov. Cov lus txib no tsim cov neeg siv daim ntawv thov (onchip_flash.hex) file. elf2hex software/hal_app/build/ .elf -o onchip_flash.hex
-b -w 8 e 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Txoj Kev 1). Qhov no yog suav nrog cov ntaub ntawv software (.HEX) hauv SOF file.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 65

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
4.5.2.3. Programming 1. Hauv Quartus Prime, nyem File Hloov Programming Files. 2. Nyob rau hauv cov zis programming file, xaiv Programmer Object File (.pof) as Programming file hom. 3. Teem hom rau Internal Configuration.
Daim duab 48. Hloov Programming File Chaw
4. Nyem Options/Boot info…, MAX 10 Device Options window tshwm. 5. Raws li Initialize flash cov ntsiab lus teeb tsa hauv On-chip Flash IP, ua
ib qho ntawm cov kauj ruam hauv qab no: · Yog tias Initialize flash cov ntsiab lus raug kuaj xyuas (Txoj Kev 1), UFM cov ntaub ntawv pib
tau suav nrog hauv SOF thaum lub sijhawm Quartus Prime muab tso ua ke. - Xaiv Page_0 rau UFM qhov chaw: kev xaiv. Nyem OK thiab mus rau qhov chaw
tom ntej no. Daim duab 49. Teem Page_0 rau UFM Source yog Initialize Flash Cov ntsiab lus raug kuaj xyuas

Nios® V Embedded Processor Design Phau Ntawv 66

Xa lus tawm tswv yim

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16
· Yog tias Initialize flash cov ntsiab lus tsis raug kuaj (Txoj Kev 2), xaiv Load nco file rau UFM qhov kev xaiv. Xauj rau qhov tsim tawm On-chip Flash HEX file (onchip_flash.hex) hauv lub File path: thiab nias OK. Cov kauj ruam no ntxiv UFM cov ntaub ntawv cais rau SOF file thaum lub programming file hloov dua siab tshiab.
Daim duab 50. Teeb Load Memory File rau UFM Source yog Initialize Flash Cov ntsiab lus tsis tau kuaj xyuas

6. Nyob rau hauv Hloov Programming File dialog box, ntawm Input files los hloov seem, nyem Ntxiv File… thiab taw tes rau lub generated Quartus Prime .sof file.
Daim duab 51. Input Files rau Hloov hauv Convert Programming Files rau tib hom duab

7. Nyem Tsim los tsim cov .pof file. 8. Program .pof file rau hauv koj lub MAX 10 ntaus ntawv. 9. Fais fab lub voj voog koj kho vajtse.

4.5.3. Nios V Processor Application Copyed from UFM to RAM using Boot Copyer

Altera pom zoo qhov kev daws teeb meem no rau MAX 10 FPGA Nios V processor system tsim qhov twg ntau qhov kev hloov pauv ntawm daim ntawv thov software txhim kho thiab kev ua haujlwm siab yuav tsum tau ua. Lub tshuab luam ntawv khau raj yog nyob hauv UFM ntawm qhov offset uas yog tib qhov chaw nyob raws li rov pib dua vector. Daim ntawv thov Nios V nyob ib sab ntawm lub tshuab luam ntawv khau raj.

Rau qhov kev xaiv khau raj no, Nios V processor pib ua cov tshuab luam ntawv khau raj thaum lub kaw lus rov pib dua los luam daim ntawv thov los ntawm UFM sector mus rau OCRAM lossis lwm RAM. Thaum luam tawm tiav, Nios V processor hloov cov kev tswj hwm mus rau daim ntawv thov.

Nco tseg:

Daim ntawv thov khau raj yog tib yam li Bootloader ntawm GSFI.

Xa lus tawm tswv yim

Nios® V Embedded Processor Design Phau Ntawv 67

4. Nios V Processor Configuration thiab Booting Solutions 726952 | 2025.07.16

Daim duab 52. Nios V Daim Ntawv Thov Luam ntawm UFM rau RAM siv khau raj tshuab luam ntawv

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

Sab nraud RAM
Nios V Software

On-Chip Flash

CFM

Nios V Hardwa

Cov ntaub ntawv / Cov ntaub ntawv

altera Nios V Embedded Processor [ua pdf] Cov neeg siv phau ntawv qhia
Nios V, Nios Vm, Nios Vg, Nios Vc, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

Cov ntaub ntawv

Cov neeg siv phau ntawv

altera Nios V Embedded Processor

Specifications

Nios V Processor Hardware System Design

Nios V Processor Software System Design

Nios V Processor Configuration thiab Booting Solutions

Cov ntaub ntawv / Cov ntaub ntawv

Cov ntaub ntawv

Cia ib saib

Ncua tseg teb