Nios V Embedded Processor

Product Information

Specifications

Product Name: Nios V Processor

Software Compatibility: Quartus Prime Software and Platform
Designer
Processor Type: Altera FPGA

Memory System: Volatile and Non-Volatile Memory
Communication Interface: UART Agent

Product Usage Instructions

1. Nios V Processor Hardware System Design

To design the Nios V Processor hardware system, follow these
steps:

Create Nios V Processor system design using Platform
Designer.

Integrate the system into Quartus Prime project.
Design memory system including volatile and non-volatile
memory.

Implement clocks and resets best practices.
Assign default and UART agents for efficient operation.

2. Nios V Processor Software System Design

To design the software system for Nios V Processor:

Follow the software development flow for Nios V Processor.

Create Board Support Package Project and Application
Project.

3. Nios V Processor Configuration and Booting Solutions

For configuring and booting the Nios V Processor:

Understand the introduction to configuration and booting
solutions.
Link applications for seamless operation.

Frequently Asked Questions (FAQ)

Q: What software is compatible with the Nios V Processor?

A: The Nios V Processor is compatible with Quartus Prime
Software and Platform Designer for system design.

Q: What type of memories does the Nios V Processor
support?

A: The processor supports both volatile and non-volatile memory
systems for data storage.

Q: How can I optimize the performance of the Platform Designer
system?

A: To optimize performance, follow best practices for clocks,
resets, and agent assignments as outlined in the user manual.

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Contents

Contents
1. About the Nios® V Embedded Processor………………………………………………………………..6 1.1. Altera® FPGA and Embedded Processors Overview…………………………………………….. 6 1.2. Quartus® Prime Software Support………………………………………………………………….7 1.3. Nios V Processor Licensing………………………………………………………………………….. 7 1.4. Embedded System Design………………………………………………………………………….. 8
2. Nios V Processor Hardware System Design with Quartus Prime Software and Platform Designer……………………………………………………………………………………….10
2.1. Creating Nios V Processor System Design with Platform Designer ………………………… 10 2.1.1. Instantiating Nios V Processor Altera FPGA IP………………………………………. 11 2.1.2. Defining System Component Design………………………………………………….. 23 2.1.3. Specifying Base Addresses and Interrupt Request Priorities ………………………24
2.2. Integrating Platform Designer System into the Quartus Prime Project……………………. 25 2.2.1. Instantiating the Nios V Processor System Module in the Quartus Prime Project……………………………………………………………………………………… 25 2.2.2. Connecting Signals and Assigning Physical Pin Locations…………………………. 25 2.2.3. Constraining the Altera FPGA Design…………………………………………………..25
2.3. Designing a Nios V Processor Memory System ……………………………………………….. 26 2.3.1. Volatile Memory…………………………………………………………………………… 26 2.3.2. Non-Volatile Memory…………………………………………………………………….. 35
2.4. Clocks and Resets Best Practices………………………………………………………………….35 2.4.1. System JTAG Clock………………………………………………………………………..35 2.4.2. Reset Request Interface…………………………………………………………………. 36 2.4.3. Reset Release IP………………………………………………………………………….. 37
2.5. Assigning a Default Agent…………………………………………………………………………. 37 2.6. Assigning a UART Agent for Printing…………………………………………………………….. 38
2.6.1. Preventing Stalls by the JTAG UART…………………………………………………… 38 2.7. JTAG Signals…………………………………………………………………………………………. 39 2.8. Optimizing Platform Designer System Performance……………………………………………39
3. Nios V Processor Software System Design………………………………………………………….. 42
3.1. Nios V Processor Software Development Flow…………………………………………………. 43 3.1.1. Board Support Package Project………………………………………………………… 43 3.1.2. Application Project……………………………………………………………………….. 43
3.2. Altera FPGA Embedded Development Tools…………………………………………………….. 43 3.2.1. Nios V Processor Board Support Package Editor……………………………………..44 3.2.2. RiscFree IDE for Altera FPGAs………………………………………………………….. 45 3.2.3. Nios V Utilities Tools……………………………………………………………………… 45 3.2.4. File Format Conversion Tools…………………………………………………………… 46 3.2.5. Other Utilities Tools………………………………………………………………………. 46
4. Nios V Processor Configuration and Booting Solutions…………………………………………..47
4.1. Introduction………………………………………………………………………………………….. 47 4.2. Linking Applications………………………………………………………………………………… 47
4.2.1. Linking Behavior………………………………………………………………………….. 48 4.3. Nios V Processor Booting Methods……………………………………………………………….. 49 4.4. Introduction to Nios V Processor Booting Methods……………………………………………. 51
4.4.1. Nios V Processor Application Execute-In-Place from Boot Flash…………………..51

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4.4.2. Nios V Processor Application Copied from Boot Flash to RAM Using Boot Copier………………………………………………………………………………………. 52
4.4.3. Nios V Processor Application Execute-In-Place from OCRAM……………………… 54 4.4.4. Nios V Processor Application Execute-In-Place from TCM…………………………. 55 4.5. Nios V Processor Booting from On-Chip Flash (UFM)…………………………………………. 55 4.5.1. MAX 10 FPGA On-Chip Flash Description…………………………………………….. 56 4.5.2. Nios V Processor Application Execute-In-Place from UFM…………………………. 58 4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier……… 67 4.6. Nios V Processor Booting from General Purpose QSPI Flash………………………………… 76 4.6.1. Nios V Processor Application Executes-In-Place from General Purpose QSPI
Flash………………………………………………………………………………………… 77 4.6.2. Nios V Processor Application Copied from General Purpose QSPI Flash to
RAM Using Boot Copier (Bootloader via GSFI)………………………………………. 86 4.7. Nios V Processor Booting from Configuration QSPI Flash……………………………………..94
4.7.1. Nios V Processor Application Executes-In-Place from Configuration QSPI Flash………………………………………………………………………………………… 95
4.7.2. Nios V Processor Design, Configuration and Boot Flow (Control Blockbased Device)…………………………………………………………………………….106
4.7.3. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices).. 119 4.8. Nios V Processor Booting from On-Chip Memory (OCRAM)………………………………… 140
4.8.1. Nios V Processor Application Executes in-place from OCRAM…………………… 140 4.9. Nios V Processor Booting from Tightly Coupled Memory (TCM)…………………………… 147
4.9.1. Nios V Processor Application Executes in-place from TCM………………………..147 4.10. Summary of Nios V Processor Vector Configuration and BSP Settings…………………. 154 4.11. Reducing Nios V Processor Booting Time……………………………………………………..156
4.11.1. Boot Methods……………………………………………………………………………156 4.11.2. Boot devices……………………………………………………………………………. 156 4.11.3. Peripheral Initialization………………………………………………………………..156 4.11.4. Caches……………………………………………………………………………………156 4.11.5. System Speed…………………………………………………………………………..157
5. Nios V Processor – Using the MicroC/TCP-IP Stack…………………………………………….. 158
5.1. Introduction………………………………………………………………………………………… 158 5.2. Software Architecture…………………………………………………………………………….. 158 5.3. Support and Licensing……………………………………………………………………………. 159 5.4. MicroC/TCP-IP Example Designs………………………………………………………………… 159
5.4.1. Hardware and Software Requirements……………………………………………….159 5.4.2. Overview…………………………………………………………………………………. 160 5.4.3. Acquiring the Example Design Files…………………………………………………..162 5.4.4. Hardware Design Files…………………………………………………………………. 163 5.4.5. Software Design Files………………………………………………………………….. 164 5.5. Development Flow………………………………………………………………………………….165 5.5.1. Hardware Development Flow…………………………………………………………. 165 5.5.2. Software Development Flow………………………………………………………….. 167 5.5.3. Device Programming…………………………………………………………………….170 5.6. Operating the Example Designs………………………………………………………………….171 5.6.1. Operating the MicroC/TCP-IP IPerf…………………………………………………… 171 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server……………………………….173 5.7. Optional Configuration……………………………………………………………………………. 176 5.7.1. Configuring Hardware Name………………………………………………………….. 176 5.7.2. Configuring MAC and IP Addresses………………………………………………….. 177 5.7.3. Configuring MicroC/TCP-IP Initialization……………………………………………..177

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5.7.4. Configuring iPerf Server Auto-Initialization………………………………………….180 5.8. MicroC/TCP-IP Simple Socket Server Concepts………………………………………………. 181
5.8.1. MicroC/OS-II Resources ………………………………………………………………. 181 5.8.2. Error Handling…………………………………………………………………………… 182 5.8.3. MicroC/TCP-IP Stack Default Configuration………………………………………… 182
6. Nios V Processor Debugging, Verifying, and Simulating………………………………………. 183
6.1. Debugging Nios V/c Processor …………………………………………………………………..183 6.1.1. Pilot System with Non-pipelined Nios V/m Processor…………………………….. 183 6.1.2. printf() Debugging…………………………………………………………………..185
6.2. Debugging Nios V Processor Hardware Designs……………………………………………… 186 6.2.1. JTAG Server……………………………………………………………………………… 186 6.2.2. System Console…………………………………………………………………………. 187 6.2.3. Signal Tap Logic Analyzer……………………………………………………………… 189 6.2.4. In-System Sources and Probes………………………………………………………..198
6.3. Debugging Nios V Processor Software Designs………………………………………………. 199 6.3.1. Ashling RiscFree IDE for Altera FPGAs………………………………………………. 199 6.3.2. Ashling Visual Studio Code Extension for Altera FPGAs………………………….. 200 6.3.3. OpenOCD………………………………………………………………………………….200 6.3.4. Objdump File…………………………………………………………………………….. 200 6.3.5. Show Make Commands………………………………………………………………… 200
6.4. Debugging Tools…………………………………………………………………………………… 201 6.5. Additional Embedded Design Considerations…………………………………………………. 201
6.5.1. JTAG Signal Integrity…………………………………………………………………… 201 6.5.2. Additional Memory Space for System Prototyping………………………………… 201 6.6. Simulating Nios V Processor Designs……………………………………………………………201 6.6.1. Prerequisites…………………………………………………………………………….. 202 6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 202 6.6.3. Creating Nios V Processor Software…………………………………………………. 203 6.6.4. Generating Memory Initialization File……………………………………………….. 204 6.6.5. Generating System Simulation Files…………………………………………………. 204 6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line……….. 205
7. Nios V Processor — Remote System Update………………………………………………………. 207
7.1. Overview……………………………………………………………………………………………. 207 7.2. Quartus Prime Pro Edition Software and Tool Support……………………………………….208
7.2.1. Quartus Prime Pro Edition Software…………………………………………………. 208 7.2.2. Programming File Generator………………………………………………………….. 210 7.3. Nios V Processor RSU Quick Start Guide in SDM-based Devices………………………….. 212 7.3.1. Individual Factory, Application, and Update Images……………………………….213 7.3.2. Hardware Design Flow…………………………………………………………………. 213 7.3.3. Software Design Flow………………………………………………………………….. 216 7.3.4. Individual Images Generation………………………………………………………… 221 7.3.5. Remote System Update Image Files Generation……………………………………221 7.3.6. QSPI Flash Programming……………………………………………………………….228 7.3.7. Operating the RSU Client API…………………………………………………………. 230
8. Nios V Processor — Using Custom Instruction…………………………………………………….234
8.1. Introduction………………………………………………………………………………………… 234 8.2. Unimplemented Instruction Example Design…………………………………………………. 234
8.2.1. Hardware and Software Requirements……………………………………………….234 8.2.2. Overview…………………………………………………………………………………. 235

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8.2.3. Acquiring the Example Design File…………………………………………………… 235 8.2.4. Hardware Design Files…………………………………………………………………. 235 8.2.5. Software Design Files………………………………………………………………….. 237 8.2.6. Development Flow……………………………………………………………………….237 8.2.7. Operating the Example Design……………………………………………………….. 238 8.3. Hardware Acceleration Example Design……………………………………………………….. 240 8.3.1. Hardware and Software Requirements……………………………………………….241 8.3.2. Overview…………………………………………………………………………………. 241 8.3.3. Acquiring the Example Design File…………………………………………………… 241 8.3.4. Hardware Design Files…………………………………………………………………. 242 8.3.5. Software Design Files………………………………………………………………….. 242 8.3.6. Development Flow……………………………………………………………………….243 8.3.7. Operating the Example Design……………………………………………………….. 244
9. Nios V Embedded Processor Design Handbook Archives……………………………………… 246
10. Document Revision History for the Nios V Embedded Processor Design Handbook… 247

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1. About the Nios® V Embedded Processor
1.1. Altera® FPGA and Embedded Processors Overview
Altera FPGA devices can implement logic that functions as a complete microprocessor while providing many options.
An important difference between discrete microprocessors and Altera FPGA is that Altera FPGA fabric contains no logic when it powers up. The Nios® V processor is a soft intellectual property (IP) processor based on the RISC-V specification. Before you run software on a Nios V processor based system, you must configure the Altera FPGA device with a hardware design that contains a Nios V processor. You can place the Nios V processor anywhere on the Altera FPGA, depending on the requirements of the design.
To enable your Altera® FPGA IP-based embedded system to behave as a discrete microprocessor-based system, your system should include the following: · A JTAG interface to support Altera FPGA configuration, hardware and software
debugging · A power-up Altera FPGA configuration mechanism
If your system has these capabilities, you can begin refining your design from a pretested hardware design loaded in the Altera FPGA. Using an Altera FPGA also allows you to modify your design quickly to address problems or to add new functionality. You can test these new hardware designs easily by reconfiguring the Altera FPGA using your system’s JTAG interface.
The JTAG interface supports hardware and software development. You can perform the following tasks using the JTAG interface: · Configure the Altera FPGA · Download and debug software · Communicate with the Altera FPGA through a UART-like interface (JTAG UART
terminal) · Debug hardware (with the Signal Tap embedded logic analyzer) · Program flash memory
After you configure the Altera FPGA with a Nios V processor-based design, the software development flow is similar to the flow for discrete microcontroller designs.
Related Information · AN 985: Nios V Processor Tutorial
A quick start guide about creating a simple Nios V processor system and running the Hello World application.
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

1. About the Nios® V Embedded Processor 726952 | 2025.07.16
· Nios V Processor Reference Manual Provides information about the Nios V processor performance benchmarks, processor architecture, the programming model, and the core implementation.
· Embedded Peripherals IP User Guide · Nios V Processor Software Developer Handbook
Describes the Nios V processor software development environment, the tools that are available, and the process to build software to run on Nios V processor. · Ashling* RiscFree* Integrated Development Environment (IDE) for Altera FPGAs User Guide Describes the RiscFree* integrated development environment (IDE) for Altera FPGAs Arm*-based HPS and Nios V core processor. · Nios V Processor Altera FPGA IP Release Notes
1.2. Quartus® Prime Software Support
Nios V processor build flow is different for Quartus® Prime Pro Edition software and Quartus Prime Standard Edition software. Refer to AN 980: Nios V Processor Quartus Prime Software Support for more information about the differences.
Related Information AN 980: Nios V Processor Quartus Prime Software Support
1.3. Nios V Processor Licensing
Each Nios V processor variant has its license key. Once you acquire the license key, you can use the same license key for all Nios V processor projects until the expiration date. You can acquire the Nios V Processor Altera FPGA IP licenses at zero cost.
The Nios V processor license key list is available in the Altera FPGA Self-Service Licensing Center. Click the Sign up for Evaluation or Free License tab, and select the corresponding options to make the request.
Figure 1. Altera FPGA Self-Service Licensing Center

With the license keys, you can:
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· Implement a Nios V processor within your system. · Simulate the behavior of a Nios V processor system. · Verify the functionality of the design, such as size and speed. · Generate device programming files. · Program a device and verify the design in hardware.
You do not need a license to develop software in the Ashling* RiscFree* IDE for Altera FPGAs.
Related Information · Altera FPGA Self-Service Licensing Center
For more information about obtaining the Nios V Processor Altera FPGA IP license keys. · Altera FPGA Software Installation and Licensing For more information about licensing the Altera FPGA software and setting up a fixed license and network license server.
1.4. Embedded System Design
The following figure illustrates a simplified Nios V processor based system design flow, including both hardware and software development.

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Figure 2.

Nios V Processor System Design Flow
System Concept

Analyze System Requirements

Nios® V
Processor Cores and Standard Components

Define and Generate System in
Platform Designer

Hardware Flow: Integrate and Compile Intel Quartus Prime Project

Software Flow: Develop and Build Nios V Proposal Software

Hardware Flow: Download FPGA Design
to Target Board

Software Flow: Test and Debug Nios V Processor Software

Software No Meets Spec?
Yes
Hardware No Meets Spec? Yes
System Complete

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2. Nios V Processor Hardware System Design with Quartus Prime Software and Platform Designer

Figure 3.

The following diagram illustrates a typical Nios V processor hardware design. Nios V Processor System Hardware Design Flow

Start

Nios V Cores and Standard Components

Use Platform Designer to Design a Nios V Based System
Generate Platform Designer Design

Integrate Platform Designer System with Intel Quartus Prime Project
Assign Pin Locations, Timing Requirements, and other Design Constraints
Compile Hardware for Target Device in Intel Quartus Prime

Ready to Download
2.1. Creating Nios V Processor System Design with Platform Designer
The Quartus Prime software includes the Platform Designer system integration tool that simplifies the task of defining and integrating Nios V processor IP core and other IPs into an Altera FPGA system design. The Platform Designer automatically creates interconnect logic from the specified high-level connectivity. The interconnect automation eliminates the time-consuming task of specifying system-level HDL connections.
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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After analyzing the system hardware requirements, you use Quartus Prime to specify the Nios V processor core, memory, and other components your system requires. The Platform Designer automatically generates the interconnect logic to integrate the components in the hardware system.

2.1.1. Instantiating Nios V Processor Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

The IP core of each processor supports different configuration options based on its unique architecture. You can define these configurations to better suit your design needs.

Table 1.

Configuration Options Across Core Variants

Configuration Options

Nios V/c Processor

Nios V/m Processor

Debug Use Reset Request

—

Traps, Exceptions, and Interrupts

CPU Architecture

ECC

Caches, Peripheral Regions and TCMs

—

Custom Instructions

—

Lockstep

—

Nios V/g Processor

2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Figure 4. Nios V/c Compact Microcontroller Altera FPGA IP

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2.1.1.1.1. CPU Architecture Tab

Table 2.

CPU Architecture Tab

Feature

Description

Enable Avalon® Interface Enables Avalon Interface for instruction manager and data manager. If disabled, the system uses AXI4-Lite interface.

mhartid CSR value

· Invalid IP option. · Do not use mhartid CSR value in Nios V/c processor.

2.1.1.1.2. Use Reset Request Tab

Table 3.

Use Reset Request Tab Parameter

Use Reset Request Tab

Description

Add Reset Request Interface

· Enable this option to expose local reset ports where a local master can use it to trigger the Nios V processor to reset without affecting other components in a Nios V processor system.
· The reset interface consists of an input resetreq signal and an output ack signal.
· You can request a reset to the Nios V processor core by asserting the resetreq signal.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

2.1.1.1.3. Traps, Exceptions, and Interrupts Tab

Table 4.

Traps, Exceptions, and Interrupts Tab Parameters

Traps, Exceptions, and Interrupts

Description

Reset Agent

Reset Offset

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.

Note:

Platform Designer provides an Absolute option, which allows you to specify an absolute address in Reset Offset. Use this option when the memory storing the reset vector is located outside the processor system and subsystems.

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2.1.1.1.4. ECC Tab

Table 5.

ECC Tab

ECC

Enable Error Detection and Status Reporting

Description
· Enable this option to apply ECC feature for Nios V processor internal RAM blocks. · ECC features detect up to 2-bits errors and react based on the following behavior:
— If it is a correctable error 1-bit, the processor continues to operate after correcting the error in the processor pipeline. However, the correction is not reflected in the source memories.
— If the error is uncorrectable, the processor continues to operate without correcting it in the processor pipeline and source memories, which might cause the processor to enter a nondeterministic state.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Figure 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Debug Tab

Table 6.

Debug Tab Parameters

Debug Tab

Description

Enable Debug
Enable Reset from Debug Module

· Enable this option to add the JTAG target connection module to the Nios V processor. · The JTAG target connection module allows connecting to the Nios V processor through the
JTAG interface pins of the FPGA. · The connection provides the following basic capabilities:
— Start and stop the Nios V processor — Examine and edit registers and memory. — Download the Nios V application .elf file to the processor memory at runtime via
niosv-download. — Debug the application running on the Nios V processor · Connect dm_agent port to the processor instruction and data bus. Ensure the base address between both buses are the same.
· Enable this option to expose dbg_reset_out and ndm_reset_in ports. · JTAG debugger or niosv-download -r command trigger the dbg_reset_out, which
allows the Nios V processor to reset system peripherals connecting to this port. · You must connect the dbg_reset_out interface to ndm_reset_in instead of reset
interface to trigger reset to processor core and timer module. You must not connect dbg_reset_out interface to reset interface to prevent indeterminate behavior.

2.1.1.2.2. Use Reset Request Tab

Table 7.

Use Reset Request Tab Parameter

Use Reset Request Tab

Description

Add Reset Request Interface

· Enable this option to expose local reset ports where a local master can use it to trigger the Nios V processor to reset without affecting other components in a Nios V processor system.
· The reset interface consists of an input resetreq signal and an output ack signal.
· You can request a reset to the Nios V processor core by asserting the resetreq signal.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· Assertion of the resetreq signal in debug mode has no effect on the processor’s state.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

2.1.1.2.3. Traps, Exceptions, and Interrupts Tab

Table 8.

Traps, Exceptions, and Interrupts Tab

Description

Reset Agent

Reset Offset Interrupt Mode

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.
Specific the type of interrupt controller either Direct or Vectored. Note: The Nios V/m non-pipelined processor does not support Vectored interrupts.
Therefore, avoid using the Vectored interrupt mode when the processor is in Nonpipelined mode.

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Note:

2.1.1.2.4. CPU Architecture

Table 9.

CPU Architecture Tab Parameters

CPU Architecture

Description

Enable Pipelining in CPU

· Enable this option to instantiate pipelined Nios V/m processor. — IPC is higher at the cost of higher logic area and lower Fmax frequency.
· Disable this option to instantiate non-pipelined Nios V/m processor. — Has similar core performance as the Nios V/c processor. — Supports debugging and interrupt capability — Lower logic area and higher Fmax frequency at the cost of lower IPC.

Enable Avalon Interface

Enables Avalon Interface for instruction manager and data manager. If disabled, the system uses AXI4-Lite interface.

mhartid CSR value

· Hart ID register (mhartid) value is 0 at default. · Assign a value between 0 and 4094. · Compatible with Altera FPGA Avalon Mutex Core HAL API.

Related Information Embedded Peripheral IP User Guide – Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Tab
Table 10. ECC Tab
ECC Enable Error Detection and Status Reporting

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2.1.1.3. Instantiating Nios V/g General Purpose Processor Altera FPGA IP
Figure 6. Nios V/g General Purpose Processor Altera FPGA IP – Part 1

Figure 7.

Nios V/g General Purpose Processor Altera FPGA IP – Part 2 (Turn Off Enable Core Level Interrupt Controller)

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Figure 8.

Nios V/g General Purpose Processor Altera FPGA IP – Part 2 (Turn On Enable Core Level Interrupt Controller)

Figure 9. Nios V/g General Purpose Processor Altera FPGA IP – Part 3

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Figure 10. Nios V/g General Purpose Processor Altera FPGA IP – Part 4

2.1.1.3.1. CPU Architecture

Table 11. CPU Architecture Parameters

CPU Architecture Tab Enable Floating Point Unit

Description Enable this option to add the floating-point unit (“F” extension) in the processor core.

Enable Branch Prediction

Enable static branch prediction (Backward Taken and Forward Not Taken) for branch instructions.

mhartid CSR value

· Hart ID register (mhartid) value is 0 at default. · Assign a value between 0 and 4094. · Compatible with Altera FPGA Avalon Mutex Core HAL API.

Disable FSQRT & FDIV instructions for FPU

· Remove floating-point square root (FSQRT) and floating-point division (FDIV) operations in FPU.
· Apply software emulation on both instructions during runtime.

Related Information Embedded Peripheral IP User Guide – Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. Debug Tab

Table 12. Debug Tab Parameters

Debug Tab

Description

Enable Debug
Enable Reset from Debug Module

2.1.1.3.3. Lockstep Tab Table 13. Lockstep Tab
Parameters Enable Lockstep Default Timeout Period Enable Extended Reset Interface

Description · Enable the dual core Lockstep system. · Default value of programmable timeout on reset exit (between 0 and 255). · Enable the optional Extended Reset Interface for Extended Reset Control. · When disabled, the fRSmartComp implements Basic Reset Control.

2.1.1.3.4. Use Reset Request Tab

Table 14. Use Reset Request Tab Parameter

Use Reset Request Tab

Description

Add Reset Request Interface

· Enable this option to expose local reset ports where a local master can use it to trigger the Nios V processor to reset without affecting other components in a Nios V processor system.
· The reset interface consists of an input resetreq signal and an output ack signal.
· You can request a reset to the Nios V processor core by asserting the resetreq signal.
· The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
· Assertion of the resetreq signal in debug mode has no effect on the processor’s state.
· The Nios V processor responds that the reset is successful by asserting the ack signal.
· After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.

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2.1.1.3.5. Traps, Exceptions, and Interrupts Tab

Table 15.

Traps, Exceptions, and Interrupts Tab when Enable Core Level Interrupt Controller is Turned Off

Traps, Exceptions, and Interrupts Tab
Reset Agent

Description
· The memory hosting the reset vector (the Nios V processor reset address) where the reset code resides.
· You can select any memory module connected to the Nios V processor instruction master and supported by a Nios V processor boot flow as the reset agent.

Reset Offset

· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.

Enable Core Level Interrupt Controller (CLIC)

· Enable CLIC to support pre-emptive interrupts and configurable interrupt trigger condition.
· When enabled, you can configure the number of platform interrupts, set trigger conditions, and designate some of the interrupts as pre-emptive.

Interrupt Mode Shadow Register Files

Specify the interrupt types as Direct, or Vectored Enable shadow register to reduce context switching upon interrupt.

Table 16.

Traps, Exceptions and Interrupts when Enable Core Level Interrupt Controller is Turned On

Traps, Exceptions, and Interrupts

Descriptions

Reset Agent
Reset Offset
Enable Core Level Interrupt Controller (CLIC)

· The memory hosting the reset vector (the Nios V processor reset address) where the reset code resides.
· You can select any memory module connected to the Nios V processor instruction master and supported by a Nios V processor boot flow as the reset agent.
· Specifies the offset of the reset vector relative to the chosen reset agent’s base address. · Platform Designer automatically provides a default value for the reset offset.
· Enable CLIC to support pre-emptive interrupts and configurable interrupt trigger condition. · When enabled, you can configure the number of platform interrupts, set trigger conditions,
and designate some of the interrupts as pre-emptive.

Interrupt Mode

· Specify the interrupt types as Direct, Vectored, or CLIC.

Shadow Register Files

· Enable shadow register to reduce context switching upon interrupt.
· Offers two approaches:
— Number of CLIC interrupt levels
— Number of CLIC interrupt levels – 1: This option is useful when you want the number of register file copies to fit in an exact number of M20K or M9K blocks.
· Enable the Nios V processor to use shadow register files which reduce context switching overhead upon interrupt.
For more information about shadow register files, refer to the Nios V Processor Reference Manual.

Number of Platform interrupt sources

· Specifies the number of platform interrupt between 16 to 2048.
Note: CLIC supports up to 2064 interrupt inputs, and the first 16 interrupt inputs are also connected to the basic interrupt controller.

CLIC Vector Table Alignment

· Automatically determined based on the number of platform interrupt sources. · If you use an alignment that is below the recommended value, the CLIC increases logic
complexity by adding an extra adder to perform vectoring calculations. · If you use an alignment that is below the recommended value, this results in increased
logic complexity in the CLIC.
continued…

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Traps, Exceptions, and Interrupts
Number of Interrupt Levels
Number of Interrupt Priorities per level
Configurable interrupt polarity Support edge triggered interrupts

Descriptions
· Specifies the number of interrupt levels with an additional level 0 for application code. Interrupts of a higher level can interrupt (pre-empt) a running handler for a lower-level interrupt.
· With non-zero interrupt levels as the only options for interrupts, the application code is always at the lowest level 0. Note: Run-time configuration of an interrupt’s level and priority is done in a single 8-bit register. If the number of interrupt levels is 256, it is not possible to configure the interrupt priority at run-time. Otherwise, the maximum number of configurable priorities is 256 / (number of interrupt levels – 1).
· Specifies the number of interrupt priorities, which the CLIC uses to determine the order in which non pre-empting interrupt handlers are called. Note: Concatenation of binary values of the selected interrupt level and selected interrupt priority must be less than 8 bits.
· Allows you to configure interrupt polarity during runtime. · Default polarity is positive polarity.
· Allows you to configure interrupt trigger condition during runtime, i.e. high-level triggered or positive-edge triggered (when interrupt polarity is positive in Configurable interrupt polarity).
· Default trigger condition is level triggered interrupt.

Note:

Related Information Nios® V Processor Reference Manual

2.1.1.3.6. Memory Configurations Tab

Table 17. Memory Configuration Tab Parameters

Category

Memory Configuration Tab

Description

Caches

Data Cache Size

· Specifies the size of the data cache. · Valid sizes are from 0 kilobytes (KB) to 16 KB. · Turn off data cache when size is 0 KB.

Instruction Cache Size

· Specifies the size of the instruction cache. · Valid sizes are from 0 KB to 16 KB. · Turn off instruction cache when size is 0 KB.

Peripheral Region A and B

Size

· Specifies the size of the peripheral region.
· Valid sizes are from 64 KB to 2 gigabytes (GB), or None. Choosing None disables the peripheral region.

Base Address

· Specifies the base address of peripheral region after you select the size.
· All addresses in the peripheral region produce uncacheable data accesses.
· Peripheral region base address must be aligned to the peripheral region size.

Tightly Coupled Memories

Size

· Specifies the size of the tightly-coupled memory. — Valid sizes are from 0 MB to 512 MB.

Base Address Initialization File

· Specifies the base address of tightly-coupled memory. · Specifies the initialization file for tightly-coupled memory.

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Note:

In a Nios V processor system with cache enabled, you must place system peripherals within a peripheral region. You can use peripheral regions to define a non-cacheable transaction for peripherals such as UART, PIO, DMA, and others.

2.1.1.3.7. ECC Tab

Table 18. ECC Tab
ECC Enable Error Detection and Status Reporting
Enable Single Bit Correction

Description
· Enable this option to apply ECC feature for Nios V processor internal RAM blocks. · ECC features detect up to 2-bits errors and react based on the following behavior:
— If it is a correctable single bit error and Enable Single Bit Correction is turned off, the processor continues to operate after correcting the error in the processor pipeline. However, the correction is not reflected in the source memories.
— If it is a correctable single bit error and Enable Single Bit Correction is turned on, the processor continues to operate after correcting the error in the processor pipeline and the source memories.
— If it is an uncorrectable error, the processor halts its operation.
Enable single bit correction on embedded memory blocks in the core.

2.1.1.3.8. Custom Instruction Tab

Note:

This tab is only available for the Nios V/g processor core.

Custom Instruction Nios V Custom Instruction Hardware Interface Table
Nios V Custom Instruction Software Macro Table

Description
· Nios V processor uses this table to define its custom instruction manager interfaces.
· Defined custom instruction manager interfaces are uniquely encoded by an Opcode (CUSTOM0-3) and 3 bits of funct7[6:4].
· You can define up to a total of 32 individual custom instruction manager interfaces.
· Nios V processor uses this table is used to define custom instruction software encodings for defined custom instruction manager interfaces.
· For each defined custom instruction software encoding, the Opcode (CUSTOM0-3) and 3 bits of funct7[6:4] encoding must correlate to a defined custom instruction manager interface encoding in the Custom Instruction Hardware Interface Table.
· You can use funct7[6:4], funct7[3:0], and funct3[2:0] to define additional encoding for a given custom instruction, or specified as Xs to be passed in as additional instruction arguments.
· Nios V processor provides defined custom instruction software encodings as generated C-macros in system.h, and follow the R-type RISC-V instruction format.
· Mnemonics may be used to define custom names for: — The generated C-Macros in system.h.
— The generated GDB debug mnemonics in custom_instruction_debug.xml.

Related Information
AN 977: Nios V Processor Custom Instruction For more information about custom instructions that allow you to customize the Nios® V processor to meet the needs of a particular application.

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2.1.2. Defining System Component Design
Use the Platform Designer to define the hardware characteristics of the Nios V processor system and add in the desired components. The following diagram demonstrates a basic Nios V processor system design with the following components: · Nios V processor core · On-Chip Memory · JTAG UART · Interval Timer (optional)(1)
When a new On-Chip Memory is added to a Platform Designer system, perform Sync System Infos to reflect the added memory components in reset. Alternatively, you can enable Auto Sync in Platform Designer to automatically reflect the latest component changes
Figure 11. Example connection of Nios V processor with other peripherals in Platform Designer

(1) You have the option to use the Nios V Internal Timer features to replace the external Interval Timer in Platform Designer.

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You must also define operation pins to export as conduit in your Platform Designer system. For example, a proper FPGA system operation pin list is defined as below but not limited to:
· Clock
· Reset
· I/O signals
2.1.3. Specifying Base Addresses and Interrupt Request Priorities
To specify how the components added in the design interact to form a system, you need to assign base addresses for each agent component and assign interrupt request (IRQ) priorities for the JTAG UART and the interval timer. The Platform Designer provides a command – Assign Base Addresses – which automatically assigns proper base addresses to all components in a system. However, you can adjust the base addresses based on your needs.
The following are some guidelines for assigning base addresses:
· Nios V processor core has a 32-bit address span. To access agent components, their base address must range between 0x00000000 and 0xFFFFFFFF.
· Nios V programs use symbolic constants to refer to addresses. You do not have to choose address values that are easy to remember.
· Address values that differentiate components with only a one-bit address difference produce more efficient hardware. You do not have to compact all base addresses into the smallest possible address range because compacting can create less efficient hardware.
· Platform Designer does not attempt to align separate memory components in a contiguous memory range. For example, if you want multiple On-Chip Memory components addressable as one contiguous memory range, you must explicitly assign base addresses.
Platform Designer also provides an automation command – Assign Interrupt Numbers which connects IRQ signals to produce valid hardware results. However, assigning IRQs effectively requires an understanding of the overall system response behavior. Platform Designer cannot make educated guesses about the best IRQ assignment.
The lowest IRQ value has the highest priority. In an ideal system, Altera recommends that the timer component to have the highest priority IRQ, i.e., the lowest value, to maintain the accuracy of the system clock tick.
In some cases, you might assign a higher priority to real time peripherals (such as video controllers), which demands a higher interrupt rate than timer components.
Related Information
Quartus Prime Pro Edition User Guide: More information about creating a System with Platform Designer.

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2.2. Integrating Platform Designer System into the Quartus Prime Project
After generating the Nios V system design in Platform Designer, perform the following tasks to integrate the Nios V system module into the Quartus Prime FPGA design project. · Instantiate the Nios V system module in the Quartus Prime project · Connect signals from Nios V system module to other signals in the FPGA logic · Assign physical pins location · Constrain the FPGA design
2.2.1. Instantiating the Nios V Processor System Module in the Quartus Prime Project
Platform Designer generates a system module design entity which you can instantiate in Quartus Prime. How you instantiate the system module depends on the design entry method for the overall Quartus Prime project. For example, if you were using Verilog HDL for design entry, instantiate the Verilog based system module. If you prefer to use the block diagram method for design entry, instantiate a system module symbol .bdf file.
2.2.2. Connecting Signals and Assigning Physical Pin Locations
To connect your Altera FPGA design to your board-level design, perform the following tasks: · Identify the top-level file for your design and signals to connect to external Altera
FPGA device pins. · Understand which pins to connect through your board-level design user guide or
schematics. · Assign signals in the top-level design to ports on your Altera FPGA device with pin
assignment tools.
Your Platform Designer system can be the top level design. However, the Altera FPGA can also include additional logic based on your needs and thus introduces a custom top-level file. The top-level file connects the Nios V processor system module signals to other Altera FPGA design logic.
Related Information Quartus Prime Pro Edition User Guide: Design Constraints
2.2.3. Constraining the Altera FPGA Design
A proper Altera FPGA system design includes design constraints to ensure the design meets timing closure and other logic constraint requirements. You must constrain your Altera FPGA design to meet these requirements explicitly using tools provided in the Quartus Prime software or third-party EDA providers. The Quartus Prime software uses the provided constraints during the compilation phase to get the optimum placement results.

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Related Information · Quartus Prime Pro Edition User Guide: Design Constraints · Third-party EDA Partners · Quartus Prime Pro Edition User Guide: Timing Analyzer
2.3. Designing a Nios V Processor Memory System
This section describes the best practices for selecting memory devices in a Platform Designer embedded system with a Nios V processor and achieving optimum performance. Memory devices play a critical role in improving the overall performance of an embedded system. Embedded system memory stores the program instructions and data.
2.3.1. Volatile Memory
A primary distinction in a memory type is volatility. Volatile memory only holds its contents while you supply power to the memory device. As soon as you remove the power, the memory loses its contents.
Examples of volatile memory are RAM, cache, and registers. These are fast memory types that increases running performance. Altera recommends you load and execute Nios V processor instructions in RAM and pair Nios V IP core with On-Chip Memory IP or External Memory Interface IP for optimum performance.
To improve performance, you can eliminate additional Platform Designer adaptation components by matching Nios V processor data manager interface type or width with boot RAM. For example, you can configure On-Chip Memory II with a 32-bits AXI-4 interface, which matches the Nios V data manager interface.
Related Information · External Memory Interfaces IP Support Center · On-Chip Memory (RAM or ROM) Altera FPGA IP · On-Chip Memory II (RAM or ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place from OCRAM on page 54
2.3.1.1. On-Chip Memory Configuration RAM or ROM
You can configure Altera FPGA On-Chip Memory IPs as RAM or ROM. · RAM provides read and write capability and has a volatile nature. If you are
booting the Nios V processor from an On-Chip RAM, you must make sure boot content is preserved and not corrupted in the event of a reset during run time. · If a Nios V processor is booting from ROM, any software bug on the Nios V processor cannot erroneously overwrite the contents of On-Chip Memory. Thus, reducing the risk of boot software corruption.
Related Information · On-Chip Memory (RAM or ROM) Altera FPGA IP · On-Chip Memory II (RAM or ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place from OCRAM on page 54

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2.3.1.2. Caches
On-chip memories are commonly used to implement the cache functionality because of their low latency. The Nios V processor uses on-chip memory for its instruction and data caches. The limited capacity of on-chip memory is usually not an issue for caches because they are typically small.
Caches are commonly used under the following conditions:
· Regular memory is located off-chip and has a longer access time than on-chip memory.
· The performance-critical sections of the software code can fit in the instruction cache, improving system performance.
· The performance-critical, most frequently used section of the data can fit in the data cache, improving system performance.
Enabling caches in Nios V processor creates a memory hierarchy, which minimize the memory access time.
2.3.1.2.1. Peripheral region
Any embedded peripherals IP, such as UART, I2C, and SPI must not be cached. Cache is highly recommended for external memories which are affected by long access time, while internal on-chip memories may be excluded due to their short access time. You must not cache any embedded peripheral IPs, such as UART, I2C, and SPI, except for memories. This is important because events from external devices, such as agent devices updating the soft IPs, are not captured by the processor cache, in turn not received by the processor. As a result, these events can go unnoticed until you flush the cache, which can lead to unintended behavior in your system. In summary, the memory-mapped region of embedded peripheral IPs is uncacheable and must reside within the processor’s peripheral regions.
To set a peripheral region, follow these steps:
1. Open the system’s Address Map in the Platform Designer.
2. Navigate to the address map of the processor’s Instruction Manager and Data Manager.
3. Identify the peripherals and memories in your system.
Figure 12. Example of Address Map

Note: The blue arrows are pointing to memories. 4. Group the peripherals:
a. Memory as cacheable b. Peripherals as uncacheable

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Table 19. Cacheable and Uncacheable Region

Subordinate

Address Map

Status

Peripheral Region

Size

Base Address

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 bytes N/A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 bytes (min size is 65536 bytes)

0x54000

sysid_qsys_0.control_slave

0x54080 ~ 0x54087

Uncacheable

uart.avalon_jtag_slave

0x54088 ~ 0x5408f

Uncacheable

5. Align the peripheral regions with their specific sizes:
· For example, if the size is 65536 bytes, it corresponds to 0x10000 bytes. Therefore, the allowed base address must be a multiple of 0x10000.
· The CPU.dm_agent uses a base address of 0x40000, which is a multiple of 0x10000. As a result, Peripheral Region A, with a size of 65536 bytes and a base address of 0x40000, meets the requirements.
· The base address of the collection of uncacheable regions at 0x54000 is not a multiple of 0x10000. You must reassign them to 0x60000 or other multiple of 0x10000. Thus, Peripheral Region B, which has a size of 65536 bytes and a base address of 0x60000, satisfies the criteria.

Table 20. Cacheable and Uncacheable Region with Reassignment

Subordinate

Address Map

Status

Peripheral Region

Size

Base Address

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

Uncacheable 65536 bytes

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Cacheable

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Cacheable Uncacheable Uncacheable Uncacheable

144 bytes (min size is 65536 bytes)

0x60000

uart.avalon_jtag_slave

0x60088 ~ 0x6008f

Uncacheable

2.3.1.3. Tightly Coupled Memory
Tightly coupled memories (TCMs) are implemented using on-chip memory as their low latency makes them well suited to the task. TCMs are memories mapped in the typical address space but have a dedicated interface to the microprocessor and possess the high-performance, low-latency properties of cache memory. TCM also provides a subordinate interface for the external host. The processor and external host have the same permission level to handle the TCM.

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Note:

When the TCM subordinate port is connected to an external host, it may be displayed with a different base address than the base address assigned in the processor core. Altera recommends to align both addresses to the same value.

2.3.1.4. External Memory Interface (EMIF)
EMIF (External Memory Interface) functions similarly to SRAM (Static Random Access Memory), but it is dynamic and requires periodic refreshing to maintain its content. The dynamic memory cells in EMIF are much smaller than the static memory cells in SRAM, which results in higher capacity and lower-cost memory devices.
In addition to the refresh requirement, EMIF has specific interface requirements that often necessitate specialized controller hardware. Unlike SRAM, which has a fixed set of address lines, EMIF organizes its memory space into banks, rows, and columns. Switching between banks and rows introduces some overhead, so you must carefully order memory accesses to use EMIF efficiently. EMIF also multiplexes row and column addresses over the same address lines, reducing the number of pins required for a given EMIF size.
Higher-speed versions of EMIF, such as DDR, DDR2, DDR3, DDR4, and DDR5, impose strict signal integrity requirements that PCB designers must consider.
EMIF devices rank among the most cost-effective and high-capacity RAM types available, making them a popular option. A key component of an EMIF interface is the EMIF IP, which manages tasks related to address multiplexing, refreshing, and switching between rows and banks. This design allows the rest of the system to access EMIF without needing to understand its internal architecture.

Related Information External Memory Interfaces IP Support Center

2.3.1.4.1. Address Span Extender IP
The Address Span Extender Altera FPGA IP allows memory-mapped host interfaces to access a larger or smaller address map than the width of their address signals allows. The Address Span Extender IP splits the addressable space into multiple separate windows so that the host can access the appropriate part of the memory through the window.
The Address Span Extender does not limit host and agent widths to a 32-bit and 64bit configuration. You can use the Address Span Extender with 1-64 bit address windows.

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Figure 13. Address Span Extender Altera FPGA IP
Agent Word Address

Address Span Extender

Mapping Table
Control Port A

…

Control Register 0 Control Register Z-1

Expanded Host Address H

Related Information
Quartus® Prime Pro Edition User Guide: Platform Designer Refer to the topic Address Span Extender Intel® FPGA IP for more information.

2.3.1.4.2. Using Address Span Extender IP with Nios V Processor
The 32-bit Nios V processor can address up to 4 GB of an address span. If the EMIF contains more than 4GB of memory, it exceeds the maximum supported address span, rendering the Platform Designer system as erroneous. An Address Span Extender IP is required to resolve this issue by dividing a single EMIF address space into multiple smaller windows.
Altera recommends that you consider the following parameters.

Table 21. Address Span Extender Parameters

Parameter

Recommended Settings

Datapath Width
Expanded Master Byte Address Width

Select 32-bits, which corelates to the 32-bit processor. Depends on the EMIF memory size.

Slave Word Address Width Burstcount Width

Select 2 GB or less. Remaining address span of Nios V processor is reserved for other embedded soft IPs.
Start with 1 and gradually increase this value to improve performance.

Number of sub-windows

Select 1 sub-window if you are connecting EMIF to the Nios V processor as instruction and data memory, or both. Switching between multiple sub-windows while Nios V processor is executing from EMIF is hazardous.

Enable Slave Control Port

Disable the slave control port if you are connecting EMIF to the Nios V processor as instruction and/or data memory. Same concerns as Number of sub-windows.

Maximum Pending Reads

Start with 1 and gradually increase this value to improve performance.

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Figure 14. Connecting Instruction and Data Manager to Address Span Extender

Figure 15. Address Mapping

Notice that the Address Span Extender can access the whole 8GB memory space of the EMIF. However, via the Address Span Extender, the Nios V processor can access only the first 1GB memory space of the EMIF.

Figure 16. Simplified Block Diagram

Platform Designer System

Remaining 3 GB

Nios V processor address

span is for embedded

NNioios sVV PProrocecsesosor r
M

soft IPs in the same system.
1 GB window

Address Span

Extender

Only the first 1 GB

of EMIF memory is connected to Nios V

EMIF

processor.

8 GB
S

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2.3.1.4.3. Defining Address Span Extender Linker Memory Device 1. Define the Address Span Extender (EMIF) as the reset vector. Alternatively, you can assign the Nios V processor reset vector to other memories, such as OCRAM or flash devices.
Figure 17. Multiple Options as Reset Vector
However, the Board Support Package (BSP) Editor cannot automatically register the Address Span Extender (EMIF) as a valid memory. Depending on the choice you made, you see two different situations as shown in the following figures. Figure 18. BSP Error when Defining Address Span Extender (EMIF) as Reset Vector

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Figure 19. Missing EMIF when Defining Other Memories as Reset Vector

2. You must manually add the Address Span Extender (EMIF) using Add Memory Device, Add Linker Memory Region, and Add Linker Section Mappings in the BSP Linker Script tab.
3. Follow these steps:
a. Determine the address span of the Address Span Extender using the Memory Map (The example in the following figure uses Address Span Extender range from 0x0 to 0x3fff_ffff).
Figure 20. Memory Map

b. Click Add Memory Device, and fill in based on the information in your design’s Memory Map: i. Device Name: emif_ddr4. Note: Ensure you copy the same name from Memory Map. ii. Base Address: 0x0 iii. Size: 0x40000000
c. Click Add to add a new linker memory region:

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Table 22. Adding Linker Memory Region

Steps

Reset Vector

emif_ddr4

Other memories

Add a new Linker Memory Region called reset. Add a new Linker Memory Region for the

· Region Name: reset

emif_ddr4.

· Region Size: 0x20

· Region Name: emif_ddr4

· Memory Device: emif_ddr4

· Region Size: 0x40000000

· Memory Offset: 0x0

· Memory Device: emif_ddr4

· Memory Offset: 0x0

Add a new Linker Memory Region for the

remaining emif_ddr4.

· Region Name: emif_ddr4

· Region Size: 0x3fffffe0

· Memory Device: emif_ddr4

· Memory Offset: 0x20

Figure 21. Linker Region when Defining Address Span Extender (EMIF) as Reset Vector

Figure 22. Linker Region when Defining Other Memories as Reset Vector
d. Once the emif_ddr4 is added to the BSP, you can select it for any Linker Section.
Figure 23. Added Address Span Extender (EMIF) Successfully

e. Ignore the warning about Memory device emif_ddr4 is not visible in the SOPC design.
f. Proceed to Generate BSP.
Related Information Introduction to Nios V Processor Booting Methods on page 51

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2.3.2. Non-Volatile Memory
Non-volatile memory retains its contents when the power switches off, making it a good choice for storing information that the system must retrieve after a system power cycle. Non-volatile memory commonly stores processor boot-code, persistent application settings, and Altera FPGA configuration data. Although non-volatile memory has the advantage of retaining its data when you remove the power, it is much slower compare to volatile memory, and often has more complex writing and erasing procedures. Non-volatile memory is also usually only guaranteed to be erasable a given number of times, after which it may fail.
Examples of non-volatile memory include all types of flash, EPROM, and EEPROM. Altera recommends you to store Altera FPGA bitstreams and Nios V program images in a non-volatile memory, and use serial flash as the boot device for Nios V processors.
Related Information
· Generic Serial Flash Interface Altera FPGA IP User Guide
· Mailbox Client Altera FPGA IP User Guide · MAX® 10 User Flash Memory User Guide: On-Chip Flash Altera FPGA IP Core
2.4. Clocks and Resets Best Practices
Understanding how the Nios V processor clock and reset domain interacts with every peripheral it connects to is important. A simple Nios V processor system starts with a single clock domain, and it can get complicated with a multi-clock domain system when a fast clock domain collides with a slow clock domain. You need to take note and understand how these different domains sequence out of reset and make sure there aren’t any subtle problems.
For best practice, Altera recommends placing the Nios V processor and boot memory in the same clock domain. Do not release the Nios V processor from reset in a fast clock domain when it boots from a memory that resides in a very slow clock domain, which may cause an instruction fetch error. You may require some manual sequencing beyond what Platform Designer provides by default, and plan out reset release topology accordingly based on your use case. If you want to reset your system after it comes up and runs for a while, apply the same considerations to system reset sequencing and post reset initialization requirement.
2.4.1. System JTAG Clock
Specifying the clock constraints in every Nios V processor system is an important system design consideration and is required for correctness and deterministic behavior. The Quartus Prime Timing Analyzer performs static timing analysis to validate the timing performance of all logic in your design using industry-standard constraint, analysis, and reporting methodology.
Example 1. Basic 100 MHz Clock with 50/50 Duty Cycle and 16 MHz JTAG Clock
#************************************************************** # Create 100MHz Clock #************************************************************** create_clock -name {clk} -period 10 [get_ports {clk}] #************************ Create 16MHz JTAG Clock #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Related Information Quartus Prime Timing Analyzer Cookbook
2.4.2. Reset Request Interface
Nios V processor includes an optional reset request facility. The reset request facility consists of reset_req and reset_req_ack signals.
To enable the reset request in Platform Designer: 1. Launch the Nios V Processor IP Parameter Editor. 2. On the Use Reset Request setting, turn on the Add Reset Request Interface
option.
Figure 24. Enable Nios V Processor Reset Request
The reset_req signal acts like an interrupt. When you assert the reset_req, you are requesting to reset to the core. The core waits for any outstanding bus transaction to complete its operation. For example, if there is a pending memory access transaction, the core waits for a complete response. Similarly, the core accepts any pending instruction response but does not issue an instruction request after receiving the reset_req signal.
The reset operation consists of the following flow: 1. Complete all pending operations 2. Flush the internal pipeline 3. Set the Program Counter to the reset vector 4. Reset the core The whole reset operation takes a few clock cycles. The reset_req must remain asserted until reset_req_ack is asserted indicating core reset operation has successfully completed. Failure to do so results in core’s state being non-deterministic.

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2.4.2.1. Typical Use Cases
· You can assert the reset_req signal from power-on to prevent the Nios V processor core from starting program execution from its reset vector until other FPGA hosts in the system initialize the Nios V processor boot memory. In this case, the entire subsystem can experience a clean hardware reset. The Nios V processor is held indefinitely in a reset request state until the other FPGA hosts initialize the processor boot memory.
· In a system where you must reset the Nios V processor core without disrupting the rest of the system, you can assert the reset_req signal to cleanly halt the current operation of the core and restart the processor from the reset vector once the system releases the reset_req_ack signal.
· An external host can use the reset request interface to ease the implementations of the following tasks:
— Halt the current Nios V processor program.
— Load a new program into the Nios V processor boot memory.
— Allow the processor to begin executing the new program.
Altera recommends you to implement a timeout mechanism to monitor the state of reset_req_ack signal. If the Nios V processor core falls into an infinite wait state condition and stalls for an unknown reason, reset_req_ack cannot assert indefinitely. The timeout mechanism enables you to:
· Define a recovery timeout period and perform system recovery with system level reset.
· Perform a hardware level reset.
2.4.3. Reset Release IP
Altera SDM-based devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Altera recommends you to use the Reset Release Altera FPGA IP as one of the initial inputs to the reset circuit. Intel® SDMbased devices includes Stratix® 10, and AgilexTM devices. Control-block based devices are not affected by this requirement.
Related Information
AN 891: Using the Reset Release Altera FPGA IP
2.5. Assigning a Default Agent
Platform Designer allows you to specify a default agent which acts as the error response default agent. The default agent you designate provides an error response service for hosts that attempt non-decoded accesses into the address map.
The following scenarios trigger a non decoded event:
· Bus transaction security state violation
· Transaction access to undefined memory region
· Exception event and etc.

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A default agent should be assigned to handle such events, where undefined transaction is rerouted to the default agent and subsequently responds to Nios V processor with an error response.
Related Information
· Quartus Prime Pro Edition User Guide: Platform Designer. Designating a Default Agent
· Quartus Prime Pro Edition User Guide: Platform Designer. Error Response Slave Altera FPGA IP
· Github – Supplemental Reset Components for Qsys

2.6. Assigning a UART Agent for Printing
Printing is useful for debugging the software application, as well as for monitoring the status of your system. Altera recommends printing basic information such as a startup message, error message, and execution progress of the software application.
Avoid using the printf() library function under the following circumstances: · The printf() library causes the application to stall if no host is reading output.
This is applicable to the JTAG UART only. · The printf() library consumes large amounts of program memory.

2.6.1. Preventing Stalls by the JTAG UART

Table 23. Differences between Traditional UART and JTAG UART

UART Type Traditional UART

Description
Transmits serial data regardless of whether an external host is listening. If no host reads the serial data, the data is lost.

JTAG UART

Writes the transmitted data to an output buffer and relies on an external host to read from the buffer to empty it.

The JTAG UART driver waits when the output buffer is full. The JTAG UART driver waits for an external host to read from the output buffer before writing more transmit data. This process prevents the loss of transmit data.
However, when system debugging is not required, such as during production, embedded systems are deployed without a host PC connected to JTAG UART. If the system selected the JTAG UART as the UART agent, it could cause stalling system because no external host is connected.
To prevent stalling by JTAG UART, apply of the following options:

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Table 24. Prevention on Stalling by JTAG UART

Options
No UART interface and driver present
Use other UART interface and driver
Preserve JTAG UART interface (without driver)

During Hardware Development (in Platform Designer)

During Software Development (in Board Support Package Editor)

Remove JTAG UART from the system

Configure hal.stdin, hal.stdout and hal.stderr as None.

Replace JTAG UART with other soft Configure hal.stdin, hal.stdout and hal.stderr

UART IP

with other soft UART IP.

Preserve JTAG UART in the system

· Configure hal.stdin, hal.stdout and hal.stderr as None in the Board Support Package Editor.
· Disable JTAG UART driver in BSP Driver tab.

2.7. JTAG Signals
The Nios V processor debug module uses the JTAG interface for software ELF download and software debugging. When you debug your design with the JTAG interface, the JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design. Specifying the JTAG signal constraints in every Nios V processor system is an important system design consideration and is required for correctness and deterministic behavior.
Altera recommends that any design’s system clock frequency be at least four times the JTAG clock frequency to ensure that the on-chip instrumentation (OCI) core functions properly.
Related Information · Quartus® Prime Timing Analyzer Cookbook: JTAG Signals
For more information about JTAG timing constraints guidelines. · KDB: Why does niosv-download fail with a non-pipelined Nios® V/m processor at
JTAG frequency 24MHz or 16Mhz?
2.8. Optimizing Platform Designer System Performance
Platform Designer provides tools for optimizing the performance of the system interconnect for Altera FPGA designs.

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Figure 25. Optimization Examples

The example shown in the figure demonstrates the following steps:
1. Adds Pipeline Bridge to alleviate critical paths by placing it: a. Between the Instruction Manager and its agents b. Between the Data Manager and its agents
2. Apply True Dual port On-Chip RAM, with each port dedicated to the Instruction Manager and the Data Manager respectively

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Refer to the following related links below, which present techniques for leveraging the available tools and the trade-offs of each implementation.
Related Information · Quartus® Prime Pro Edition User Guide: Platform Designer
Refer to the topic Optimizing Platform Designer System Performance for more information. · Quartus® Prime Standard Edition User Guide: Platform Designer Refer to the topic Optimizing Platform Designer System Performance for more information.

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3. Nios V Processor Software System Design
This chapter describes the Nios V processor software development flow and the software tools that you can use in developing your embedded design system. The content serves as an overview before developing a Nios V processor software system.
Figure 26. Software Design Flow
Start

Generate the BSP in the Platform Designer Using the BSP Editor

Generate the BSP Using the Nios V Command Shell
Generate the Application CMake Build File Using the Nios V Command Shell

Note:

Import the BSP and Application CMake Build File
Build the Nios V Processor Application using the
RiscFree IDE for Intel FPGA

Build the Nios V Processor application using any
command-line source code editor, CMake, and Make
commands
End

Altera recommends that you use an Altera FPGA development kit or a custom prototype board for software development and debugging. Many peripherals and system-level features are available only when your software runs on an actual board.

© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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3.1. Nios V Processor Software Development Flow
3.1.1. Board Support Package Project
A Nios V Board Support Package (BSP) project is a specialized library containing system-specific support code. A BSP provides a software runtime environment customized for one processor in a Nios V processor hardware system.
The Quartus Prime software provides Nios V Board Support Package Editor and niosv-bsp utility tools to modify settings that control the behavior of the BSP.
A BSP contains the following elements: · Hardware abstraction layer · Device drivers · Optional software packages · Optional real-time operating system
3.1.2. Application Project
A Nios V C/C++ application project has the following features: · Consists of a collection of source code and a CMakeLists.txt.
— The CMakeLists.txt compiles the source code and links it with a BSP and one or more optional libraries, to create one .elf file
· One of the source files contains function main(). · Includes code that calls functions in libraries and BSPs.
Altera provides niosv-app utility tool in the Quartus Prime software utility tools to create the Application CMakeLists.txt, and RiscFree IDE for Altera FPGAs to modify the source code in an Eclipse-based environment.
3.2. Altera FPGA Embedded Development Tools
The Nios V processor supports the following tools for software development: · Graphical User Interface (GUI) – Graphical development tools that are available in
both Windows* and Linux* Operating Systems (OS). — Nios V Board Support Package Editor (Nios V BSP Editor) — Ashling RiscFree IDE for Altera FPGAs · Command-Line Tools (CLI) – Development tools that are initiated from the Nios V Command Shell. Each tool provides its own documentation in the form of help accessible from the command line. Open the Nios V Command Shell and type the following command: <name of tool> –help to view the Help menu. — Nios V Utilities Tools — File Format Conversion Tools — Other Utilities Tools

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Table 25. GUI Tools and Command-line Tools Tasks Summary

Task

GUI Tool

Command-line Tool

Creating a BSP

Nios V BSP Editor

· In Quartus Prime Pro Edition software: niosv-bsp -c -s=<.qsys file> -t=<bsp type> [OPTIONS] settings.bsp
· In Quartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t=<bsp type>[OPTIONS] settings.bsp

Generating a BSP using existing .bsp file
Updating a BSP

Nios V BSP Editor Nios V BSP Editor

niosv-bsp -g [OPTIONS] settings.bsp niosv-bsp -u [OPTIONS] settings.bsp

Examining a BSP

Nios V BSP Editor

niosv-bsp -q -E=<tcl script> [OPTIONS] settings.bsp

Creating an application

–

niosv-app -a=<application directory> -b=<bsp directory> -s=<source files directory> [OPTIONS]

Creating a user library

–

niosv-app -l=<library directory> -s=<source files directory> -p=<public includes directory> [OPTIONS]

Modifying an application Modifying a user library Building an application

RiscFree IDE for Altera FPGAs
RiscFree IDE for Altera FPGAs
RiscFree IDE for Altera FPGAs

Any command-line source editor
Any command-line source editor
· make · cmake

Building a user library

RiscFree IDE for Altera FPGAs

· make · cmake

Downloading an application ELF
Converting the .elf file

RiscFree IDE for Altera FPGAs
–

niosv-download
· elf2flash · elf2hex

Related Information
Ashling RiscFree Integrated Development Environment (IDE) for Altera FPGAs User Guide

3.2.1. Nios V Processor Board Support Package Editor
You can use the Nios V processor BSP Editor to perform the following tasks: · Create or modify a Nios V processor BSP project · Edit settings, linker regions, and section mappings · Select software packages and device drivers.
The capabilities of the BSP Editor include the capabilities of the niosv-bsp utilities. Any project created in the BSP Editor can also be created using the command-line utilities.

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Note:

For Quartus Prime Standard Edition software, refer to AN 980: Nios V Processor Quartus Prime Software Support for the steps to invoke the BSP Editor GUI.

To launch the BSP Editor, follow these steps: 1. Open Platform Designer, and navigate to the File menu.
a. To open an existing BSP setting file, click Open… b. To create a new BSP, click New BSP… 2. Select the BSP Editor tab and provide the appropriate details.

Figure 27. Launch BSP Editor

Related Information AN 980: Nios V Processor Quartus Prime Software Support
3.2.2. RiscFree IDE for Altera FPGAs
The RiscFree IDE for Altera FPGAs is an Eclipse-based IDE for the Nios V processor. Altera recommends that you develop the Nios V processor software in this IDE for the following reasons: · The features are developed and verified to be compatible with the Nios V
processor build flow. · Equipped with all the necessary toolchains and supporting tools which enables you
to easily start Nios V processor development.
Related Information Ashling RiscFree Integrated Development Environment (IDE) for Altera FPGAs User Guide
3.2.3. Nios V Utilities Tools
You can create, modify, and build Nios V programs with commands typed at a command line or embedded in a script. The Nios V command-line tools described in this section are in the <Intel Quartus Prime software installation directory>/niosv/bin directory.

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Table 26. Nios V Utilities Tools

Command-Line Tools

Summary

niosv-app niosv-bsp niosv-download niosv-shell niosv-stack-report

To generate and configure an application project.
To create or update a BSP settings file and create the BSP files. To download the ELF file to a Nios® V processor.
To open the Nios V Command Shell. To inform you of the left-over memory space available to your application .elf for stack or heap usage.

3.2.4. File Format Conversion Tools

File format conversion is sometimes necessary when passing data from one utility to another. The file format conversion tools are in the <Intel Quartus Prime
software installation directory>/niosv/bin directory.

Table 27. File Format Conversion Tools

Command-Line Tools elf2flash elf2hex

Summary To translate the .elf file to .srec format for flash memory programming. To translate the .elf file to .hex format for memory initialization.

3.2.5. Other Utilities Tools

You might require the following command-line tools when building a Nios V processor based system. These command-line tools are either provided by Intel in <Intel Quartus Prime installation directory>/quartus/bin or acquired from
open-source tools.

Table 28. Other Command-Line Tools

Command-Line Tools

Type

Summary

juart-terminal

Intel-provided

To monitor stdout and stderr, and to provide input to a Nios® V processor
subsystem through stdin. This tool only applies to the JTAG UART IP when it is connected to the Nios® V processor.

openocd

Intel-provided To execute OpenOCD.

openocd-cfg-gen

Intel-provided · To generate the OpenOCD configuration file. · To display JTAG chain device index.

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4. Nios V Processor Configuration and Booting Solutions
You can configure the Nios V processor to boot and execute software from different memory locations. The boot memory is the Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), or Tightly Coupled Memory (TCM).
Related Information · Power-Up Trigger Conditions on page 193 · Power-Up Triggers
For more information about power-up triggers.
4.1. Introduction
The Nios V processor supports two types of boot processes: · Execute-in-Place (XIP) using alt_load() function · Program copied to RAM using boot copier. The Nios V embedded programs development is based on the hardware abstraction layer (HAL). The HAL provides a small boot loader program (also known as boot copier) that copies relevant linker sections from the boot memory to their run time location at boot time. You can specify the program and data memory run time locations by manipulating the Board Support Package (BSP) Editor settings. This section describes: · Nios V processor boot copier that boots your Nios V processor system according to
the boot memory selection · Nios V processor booting options and general flow · Nios V programming solutions for the selected boot memory
4.2. Linking Applications
When you generate the Nios V processor project, the BSP Editor generates two linker related files: · linker.x: The linker command file that the generated application’s makefile uses
to create the .elf binary file. · linker.h: Contains information about the linker memory layout. All linker setting modifications you make to the BSP project affect the contents of these two linker files. Every Nios V processor application contains the following linker sections:
© Altera Corporation. Altera, the Altera logo, the `a’ logo, and other Altera marks are trademarks of Altera Corporation. Altera reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Table 29. Linker Sections

.text

Linker Sections

.rodata

.rwdata

.bss

.heap

.stack

Descriptions Executable code. Any read-only data used in the execution of the program. Stores read-write data used in the execution of the program. Contains uninitialized static data. Contains dynamically allocated memory. Stores function-call parameters and other temporary data.

You can add additional linker sections to the .elf file to hold custom code and data. These linker sections are placed in named memory regions, defined to correspond with physical memory devices and addresses. By default, BSP Editor automatically generates these linker sections. However, you can control the linker sections for a particular application.

4.2.1. Linking Behavior
This section describes the BSP Editor default linking behavior and how to control the linking behavior.

4.2.1.1. Default BSP Linking
During BSP configuration, the tools perform the following steps automatically:
1. Assign memory region names: Assign a name to each system memory device and add each name to the linker file as a memory region.
2. Find largest memory: Identify the largest read-and-write memory region in the linker file.
3. Assign linker sections: Place the default linker sections (.text, .rodata, .rwdata, .bss, .heap, and .stack) in the memory region identified in the previous step.
4. Write files: Write the linker.x and linker.h files.
Typically, the linker section allocation scheme works during the software development process because the application is guaranteed to function if the memory is large enough.
The rules for the default linking behavior are contained in the Altera-generated Tcl scripts bsp-set-defaults.tcl and bsp-linker-utils.tcl found in the <Intel Quartus Prime installation directory>/niosv/scripts/bsp-defaults directory. The niosv-bsp command invokes these scripts. Do not modify these scripts directly.

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4.2.1.2. Configurable BSP Linking
You can manage the default linking behavior in the Linker Script tab of the BSP Editor. Manipulate the linker script using the following methods: · Add a memory region: Maps a memory region name to a physical memory device. · Add a section mapping: Maps a section name to a memory region. The BSP
Editor allows you to view the memory map before and after making changes.

4.3. Nios V Processor Booting Methods

There are a few methods to boot up the Nios V processor in Altera FPGA devices. The methods to boot up Nios V processor vary according to the flash memory selection and device families.

Table 30. Supported Flash Memories with Respective Boot Options

Supported Boot Memories

Device

On-Chip Flash (for Internal configuration)

Max 10 devices only (with On-Chip Flash IP)

General Purpose QSPI Flash (for user data only)

All supported FPGA devices (with Generic Serial Flash Interface FPGA IP)

Configuration QSPI Flash (for Active Serial configuration)

Control block-based
devices (with Generic
Serial Flash Interface Intel FPGA IP)(2)

Nios V Processor Booting Methods

Application Runtime Location

Boot Copier

Nios V processor application executein-place from On-Chip Flash

On-Chip Flash (XIP) + OCRAM/ External RAM (for writable data sections)

alt_load() function

Nios V processor application copied from On-Chip Flash to RAM using boot copier

OCRAM/External RAM

Reusing Bootloader via GSFI

Nios V processor application executein-place from general purpose QSPI flash

General purpose QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections)

alt_load() function

Nios V processor application copied from general purpose QSPI flash to RAM using boot copier

OCRAM/External RAM

Bootloader via GSFI

Nios V processor application executein-place from configuration QSPI flash

Configuration QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections)

alt_load() function

Nios V processor application copied from configuration QSPI flash to RAM using boot copier

OCRAM/ External RAM Bootloader via GSFI continued…

(2) Refer to AN 980: Nios V Processor Quartus Prime Software Support for the device list.

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Supported Boot Memories
On-chip Memory (OCRAM) Tightly Coupled Memory (TCM)

Device
SDM-based devices (with Mailbox Client Intel FPGA IP). (2)
All supported Altera FPGA devices (2)
All supported Altera FPGA devices(2)

Nios V Processor Booting Methods
Nios V processor application copied from configuration QSPI flash to RAM using boot copier
Nios V processor application executein-place from OCRAM
Nios V processor application executein-place from TCM

Application Runtime Location

Boot Copier

OCRAM/ External RAM Bootloader via SDM

OCRAM

alt_load() function

Instruction TCM (XIP) None + Data TCM (for writable data sections)

Figure 28. Nios V Processor Boot Flow

Reset

Processor jumps to reset vector (boot code start)

Application code may be copied to another memory location (depending on boot options)
Boot code initializes the processor

Depending on boot options, the boot code may copy initial values for data/code to another memory space (alt_load)
Boot code initializes the application code and data memory space
Boot code initializes all the system peripherals with HAL drivers (alt_main)
Entry to main
Related Information · Generic Serial Flash Interface Altera FPGA IP User Guide
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· Mailbox Client Altera FPGA IP User Guide · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Introduction to Nios V Processor Booting Methods
Nios V processor systems require the software images to be configured in system memory before the processor can begin executing the application program. Refer to Linker Sections for the default linker sections.
The BSP Editor generates a linker script that performs the following functions: · Ensures that the processor software is linked in accordance with the linker settings
of the BSP editor and determines where the software resides in memory. · Positions the processor’s code region in the memory component according to the
assigned memory components.
The following section briefly describes the available Nios V processor booting methods.
4.4.1. Nios V Processor Application Execute-In-Place from Boot Flash
Altera designed the flash controllers such that the boot flash address space is immediately accessible to the Nios V processor upon system reset, without the need to initialize the memory controller or memory devices. This enables the Nios V processor to execute application code stored on the boot devices directly without using a boot copier to copy the code to another memory type. The flash controllers are: · On-Chip Flash with On-Chip Flash IP (only in MAX® 10 device) · General purpose QSPI flash with Generic Serial Flash Interface IP · Configuration QSPI flash with Generic Serial Flash Interface IP (except MAX 10
devices)
When the Nios V processor application execute-in-place from boot flash, the BSP Editor performs the following functions: · Sets the .text linker sections to the boot flash memory region. · Sets the .bss,.rodata, .rwdata, .stack and .heap linker sections to the RAM
memory region. You must enable the alt_load() function in the BSP Settings to copy the data sections (.rodata, .rwdata,, .exceptions) to the RAM upon system reset. The code section (.text) remains in the boot flash memory region.
Related Information · Generic Serial Flash Interface Altera FPGA IP User Guide · Altera MAX 10 User Flash Memory User Guide
4.4.1.1. alt_load()
You can enable the alt_load() function in the HAL code using the BSP Editor.
When used in the execute-in-place boot flow, the alt_load() function performs the following tasks:

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· Operates as a mini boot copier that copies the memory sections to RAM based on the BSP settings.
· Copies data sections (.rodata, .rwdata, .exceptions) to RAM but not the code sections (.text).The code section (.text) section is a read-only section and remains in the booting flash memory region. This partitioning helps to minimize the RAM usage but may limit the code execution performance because accesses to flash memory are slower than accesses to the on-chip RAM.

The following table lists the BSP Editor settings and functions:

Table 31. BSP Editor Settings
BSP Editor Setting hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Function Enables alt_load() function. alt_load() copies .rodata section to RAM. alt_load() copies .rwdata section to RAM. alt_load() copies .exceptions section to RAM.

4.4.2. Nios V Processor Application Copied from Boot Flash to RAM Using Boot Copier
The Nios V processor and HAL include a boot copier that provides sufficient functionality for most Nios V processor applications and is convenient to implement with the Nios V software development flow.
When the application uses a boot copier, it sets all linker sections ( .text, .heap , .rwdata, .rodata , .bss, .stack) to an internal or external RAM. Using the boot copier to copy a Nios V processor application from the boot flash to the internal or external RAM for execution helps to improve the execution performance.
For this boot option, the Nios V processor starts executing the boot copier software upon system reset. The software copies the application from the boot flash to the internal or external RAM. Once the process is complete, the Nios V processor transfers the program control over to the application.

Note:

If the boot copier is in flash, then the alt_load() function does not need to be called because they both serve the same purpose.

4.4.2.1. Nios V Processor Bootloader via Generic Serial Flash Interface
The Bootloader via GSFI is the Nios V processor boot copier that supports QSPI flash memory in control block-based devices. The Bootloader via GSFI includes the following features:
· Locates the software application in non-volatile memory.
· Unpacks and copies the software application image to RAM.
· Automatically switches processor execution to application code in RAM after copy completes.

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The boot image is located right after the boot copier. You need to ensure the Nios V processor reset offset points to the start of the boot copier. The Figure: Memory Map for QSPI Flash with Bootloader via GSFI memory map for QSPI Flash with Bootloader via GSFI shows the flash memory map for QSPI flash when using a boot copier. This memory map assumes the flash memory memory stores the FPGA image and the application software.

Table 32. Bootloader via GSFI for Nios V Processor Core

Nios V Processor Core
Nios V/m processor

Bootloader via GSFI File Location
<Intel Quartus Installation Directory>/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

<Intel Quartus Installation Directory>/niosv/components/bootloader/ niosv_g_bootloader.srec

Figure 29. Memory Map for QSPI Flash with Bootloader via GSFI

Customer Data (*.hex)

Application Code

Note:

Reset Vector Offset

Boot Copier

0x01E00000

FPGA Image (*.sof)

0x00000000

1. At the start of the memory map is the FPGA image followed by your data, which consists of boot copier and application code.
2. You must set the Nios V processor reset offset in Platform Designer and point it to the start of the boot copier.
3. The size of the FPGA image is unknown.You can only know the exact size after the Quartus Prime project compilation. You must determine an upper bound for the size of the Altera FPGA image. For example, if the size of the FPGA image is estimated to be less than 0x01E00000, set the Reset Offset to 0x01E00000 in Platform Designer, which is also the start of the boot copier.
4. A good design practice consists of setting the reset vector offset at a flash sector boundary to ensure no partial erase of the FPGA image occurs in case the software application is updated.

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4.4.2.2. Nios V Processor Bootloader via Secure Device Manager
The Bootloader via Secure Device Manager (SDM) is a HAL application code utilizing the Mailbox Client Altera FPGA IP HAL driver for processor booting. Altera recommends this bootloader application when using the configuration QSPI flash in SDM-based devices to boot the Nios V processor.
Upon system reset, the Nios V processor first boots the Bootloader via SDM from a tiny on-chip memory and executes the Bootloader via SDM to communicate with the configuration QSPI flash using the Mailbox Client IP.
The Bootloader via SDM performs the following tasks: · Locates the Nios V software in the configuration QSPI flash. · Copies the Nios V software into the on-chip RAM or external RAM. · Switches the processor execution to the Nios V software within the on-chip RAM or
external RAM.
Once the process is complete, the Bootloader via SDM transfers program control over to the user application. Altera recommends the memory organization as outlined in Memory Organization for Bootloader via SDM.
Figure 30. Bootloader via SDM Process Flow

Configuration

Flash

Nios V Software

SDM

SDM-Based FPGA Device

Mailbox Client IP

FPGA Logic Nios V

4 External RAM
Nios V Software

On-Chip 4

EMIF

RAM

On-Chip Memory

Nios V

Software

Bootloader via SDM

1. Nios V processor runs the Bootloader via SDM from the on-chip memory.
2. Bootloader via SDM communicates with the configuration flash and locates the Nios V software.
3. Bootloader via SDM copies the Nios V software from the Configuration Flash into on-chip RAM / external RAM.
4. Bootloader via SDM switches the Nios V processor execution to the Nios V software in the on-chip RAM / external RAM.

4.4.3. Nios V Processor Application Execute-In-Place from OCRAM
In this method, the Nios V processor reset address is set to the base address of the on-chip memory (OCRAM). The application binary (.hex) file is loaded into the OCRAM when the FPGA is configured, after the hardware design is compiled in the Quartus Prime software. Once the Nios V processor resets, the application begins executing and branches to the entry point.

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Note:

· Execute-In-Place from OCRAM does not require boot copier because Nios V processor application is already in place at system reset.
· Altera recommends enabling alt_load() for this booting method so that the embedded software behaves identically when reset without reconfiguring the FPGA device image.
· You must enable the alt_load() function in the BSP Settings to copy the .rwdata section upon system reset. In this method, the initial values for initialized variables are stored separately from the corresponding variables to avoid overwriting on program execution.

4.4.4. Nios V Processor Application Execute-In-Place from TCM
The execute-in-place method sets the Nios V processor reset address to the base address of the tightly coupled memory (TCM). The application binary (.hex) file is loaded into the TCM when you configure the FPGA after you compile the hardware design in the Quartus Prime software. Once the Nios V processor resets, the application begins executing and branches to the entry point.

Note:

Execute-In-Place from TCM does not require boot copier because Nios V processor application is already in place at system reset.

4.5. Nios V Processor Booting from On-Chip Flash (UFM)

Nios V processor booting and executing software from on-chip flash (UFM) is available in MAX 10 FPGA devices. The Nios V processor supports the following two boot options using On-Chip Flash under Internal Configuration mode:
· Nios V processor application executes in-place from On-Chip Flash.
· Nios V processor application is copied from On-Chip Flash to RAM using boot copier.

Table 33. Supported Flash Memories with respective Boot Options

Supported Boot Memories

Nios V Booting Methods

Application Runtime Location

Boot Copier

MAX 10 devices only (with OnChip Flash IP)

Nios V processor application executein-place from On-Chip Flash
Nios V processor application copied from On-Chip Flash to RAM using boot copier

On-Chip Flash (XIP) + OCRAM/ External RAM (for writable data sections)

alt_load() function

OCRAM/ External RAM

Reusing Bootloader via GSFI

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Figure 31.

Design, Configuration, and Booting Flow
Design · Create your Nios V Processor based project using Platform Designer. · Ensure that there is external RAM or on-chip RAM in the system design.

FPGA Configuration and Compilation
· Set the same internal configuration mode in On-chip Flash IP in Platform Designer and Quartus Prime software. · Set Nios V processor reset agent to On-chip Flash. · Choose your preferred UFM initialization method. · Generate your design in Platform Designer. · Compile your project in Quartus Prime software.

User Application BSP Project · Create Nios V processor HAL BSP based on .sopcinfo file created by Platform Designer. · Edit Nios V processor BSP settings and Linker Script in BSP Editor. · Generate BSP project.
User Application APP Project · Develop Nios V processor application code. · Compile Nios V processor application and generate Nios V processor application (.hex) file. · Recompile your project in Quartus Prime software if you check Initialize memory content option in Intel FPGA On-Chip Flash IP.

Programming Files Conversion, Download and Run · Generate the On-Chip Flash .pof file using Convert Programming Files feature in Quartus Prime software.
· Program the .pof file into your MAX 10 device. · Power cycle your hardware.
4.5.1. MAX 10 FPGA On-Chip Flash Description
MAX 10 FPGA devices contain on-chip flash that is segmented into two parts: · Configuration Flash Memory (CFM) — stores the hardware configuration data for
MAX 10 FPGAs. · User Flash Memory (UFM) — stores the user data or software applications.
The UFM architecture of MAX 10 device is a combination of soft and hard IPs. You can only access the UFM using the On-Chip Flash IP Core in the Quartus Prime software.
The On-chip Flash IP core supports the following features: · Read or write accesses to UFM and CFM (if enabled in Platform Designer) sectors
using the Avalon MM data and control slave interface. · Supports page erase, sector erase and sector write. · Simulation model for UFM read/write accesses using various EDA simulation tools.

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Table 34. On-chip Flash Regions in MAX 10 FPGA Devices

Flash Regions

Functionality

Configuration Flash Memory (sectors CFM0-2)

FPGA configuration file storage

User Flash Memory (sectors UFM0-1)

Nios V processor application and user data

MAX 10 FPGA devices support several configuration modes and some of these modes allow CFM1 and CFM2 to be used as an additional UFM region. The following table shows the storage location of the FPGA configuration images based on the MAX 10 FPGA’s configuration modes.

Table 35. Storage Location of FPGA Configuration Images

Configuration Mode Dual compressed images

CFM2 Compressed Image 2

CFM1

CFM0 Compressed Image 1

Single uncompressed image

Virtual UFM

Uncompressed image

Single uncompressed image with Memory Initialization

Uncompressed image (with pre-initialized on-chip memory content)

Single compressed image with Memory Initialization Compressed image (with pre-initialized on-chip memory content)

Single compressed image

Virtual UFM

Compressed Image

You must use the On-chip Flash IP core to access to the flash memory in MAX 10 FPGAs. You can instantiate and connect the On-chip Flash IP to the Quartus Prime software. The Nios V soft core processor uses the Platform Designer interconnects to communicate with the On-chip Flash IP.
Figure 32. Connection between On-chip Flash IP and Nios V Processor

Note:

Ensure the On-chip Flash csr port is connected to the Nios V processor data_manager to enable the processor to control write and erase operations.
The On-chip Flash IP core can provide access to five flash sectors – UFM0, UFM1, CFM0, CFM1, and CFM2.
Important information about the UFM and CFM sectors.: · CFM sectors are intended for configuration (bitstream) data (*.pof) storage.
· User data can be stored in the UFM sectors and may be hidden, if the correct settings are selected in the Platform Designer tool.
· Certain devices do not have a UFM1 sector. You can refer to the table: UFM and CFM Sector Size for available sectors in each individual MAX 10 FPGA device.

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· You can configure CFM2 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
· You can configure CFM2 and CFM1 as a virtual UFM by selecting Single Uncompressed Image configuration mode.
· The size of each sector varies with the selected MAX 10 FPGA devices.

Table 36.

UFM and CFM Sector Size
This table lists the dimensions of the UFM and CFM arrays.

Device

Pages per Sector

UFM1 UFM0 CFM2 CFM1 CFM0

Page Size (Kbit)

Maximum User
Flash Memory Size (Kbit) (3)

Total Configuration Memory Size (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

OCRAM Size (Kbit)
108 189 378 549 675 1260 1638

Related Information · MAX 10 FPGA Configuration User Guide · Altera MAX 10 User Flash Memory User Guide

4.5.2. Nios V Processor Application Execute-In-Place from UFM

The Execute-In-Place from UFM solution is suitable for Nios V processor applications which require limited on-chip memory usage. The alt_load() function operates as a mini boot copier that copies the data sections (.rodata, .rwdata, or .exceptions) from boot memory to RAM based on the BSP settings. The code section (.text),
which is a read only section, remains in the MAX 10 On-chip Flash memory region. This setup minimizes the RAM usage but may limit the code execution performance as access to the flash memory is slower than the on-chip RAM.

The Nios V processor application is programmed into the UFM sector. The Nios V processor’s reset vector points to the UFM base address to execute code from the UFM after the system resets.

If you are using the source-level debugger to debug your application, you must use a hardware breakpoint. This is because the UFM does not support random memory access, which is necessary for soft breakpoint debugging.

Note:

You cannot erase or write UFM while performing execute-in-place in the MAX 10. Sswitch to boot copier approach if you need to erase or write the UFM.

(3) The maximum possible value, which is dependent on the configuration mode you select.

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Figure 33. Nios V Processor Application XIP from UFM

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

On-Chip Flash

CFM

Nios V Hardware

UFM

Nios V Software

Internal Configuration

On-Chip Flash IP

FPGA Logic
Nios V Processor

On-Chip RAM

External

RAM

EMIF

4.5.2.1. Hardware Design Flow
The following section describes a step-by-step method for building a bootable system for a Nios V processor application from On-Chip Flash. The example below is built using MAX 10 device.
IP Component Settings
1. Create your Nios V processor project using Quartus Prime and Platform Designer. 2. Make sure external RAM or On-Chip Memory (OCRAM) is added to your Platform
Designer system.

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Figure 34. Example IP Connections in Platform Designer for Booting Nios V from OnChip Flash (UFM)

3. In the On-Chip Flash IP parameter editor, set the Configuration Mode to one of the following, according to your design preference: · Single Uncompressed Image · Single Compressed Image · Single Uncompressed Image with Memory Initialization · Single Compressed Image with Memory Initialization
For more information about Dual Compressed Images, refer to the MAX 10 FPGA Configuration User Guide – Remote System Upgrade.

Note:

You must assign Hidden Access to every CFM regions in the On-Chip Flash IP.

Figure 35. Configuration Mode Selection in On-Chip Flash Parameter Editor

On-Chip Flash IP Settings – UFM Initialization You can choose one of the following methods according to your preference:

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Note:

The steps in the subsequent subchapters (Software Design Flow and Programming) depend on the selection you make here.

· Method 1: Initialize the UFM data in the SOF during compilation
Quartus Prime includes the UFM initialization data in the SOF during compilation. SOF recompilation is needed if there are changes in the UFM data.
1. Check Initialize flash content and Enable non-default initialization file.

Figure 36. Initialize Flash Contents and Enable Non-default Initialization File

2. Specify the path of the generated .hex file (from the elf2hex command) in the User created hex or mif file.
Figure 37. Adding the .hex File Path

· Method 2: Combine UFM data with a compiled SOF during POF generation
UFM data is combined with the compiled SOF when converting programming files. You do not need to recompile the SOF, even if the UFM data changes. During development, you do not have to recompile SOF files for changes in the application. Alterarecommends this method for application developers.
1. Uncheck Initialize flash content..
Figure 38. Initialize Flash Content with Non-default Initialization File

Reset Agent Settings for Nios V Processor Execute-In-Place Method
1. In the Nios V processor parameter editor, set the Reset Agent to On-Chip Flash.
Figure 39. Nios V Processor Parameter Editor Settings with Reset Agent Set to On-Chip Flash

2. Click Generate HDL when the Generation dialog box appears. 3. Specify output file generation options and click Generate.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Click OK to exit the Device and Pin Options window,
3. Click OK to exit the Device window.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Note:

If the configuration mode setting in Quartus Prime software and Platform Designer parameter editor is different, the Quartus Prime project fails with the following error message.

Figure 41.

Error Message for Different Configuration Mode Setting Error (14740): Configuration mode on atom “q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block|ufm_block” does not match the project setting. Update and regenerate the Qsys system to match the project setting.

Related Information MAX 10 FPGA Configuration User Guide

4.5.2.2. Software Design Flow
This section provides the design flow to generate and build the Nios V processor software project. To ensure a streamlined build flow, you are encouraged to create a similar directory tree in your design project. The following software design flow is based on this directory tree.
To create the software project directory tree, follow these steps: 1. In your design project folder, create a folder called software. 2. In the software folder, create two folders called hal_app and hal_bsp.
Figure 42. Software Project Directory Tree

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Creating the Application BSP Project
To launch the BSP Editor, follow these steps: 1. Enter the Nios V Command Shell. 2. Invoke the BSP Editor with niosv-bsp-editor command. 3. In the BSP Editor, click File New BSP to start your BSP project. 4. Configure the following settings:
· SOPC Information File name: Provide the SOPCINFO file (.sopcinfo). · CPU name: Select Nios V processor. · Operating system: Select the operating system of the Nios V processor. · Version: Leave as default. · BSP target directory: Select the directory path of the BSP project. You can
pre-set it at <Project directory>/software/hal_bsp by enabling Use default locations. · BSP Settings File name: Type the name of the BSP Settings File. · Additional Tcl scripts: Provide a BSP Tcl script by enabling Enable Additional Tcl script. 5. Click OK.
Figure 43. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Convert Programming Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Settings
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file conversion.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Note:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Max 10 Device

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

External RAM
Nios V Software

On-Chip Flash

CFM

Nios V Hardwa

Documents / Resources

altera Nios V Embedded Processor [pdf] User Guide
Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

References

User Manual

altera Nios V Embedded Processor User Guide

Nios V Embedded Processor

Product Information

Specifications

Product Usage Instructions

1. Nios V Processor Hardware System Design

2. Nios V Processor Software System Design

3. Nios V Processor Configuration and Booting Solutions

Frequently Asked Questions (FAQ)

Q: What software is compatible with the Nios V Processor?

Q: What type of memories does the Nios V Processor
support?

Q: How can I optimize the performance of the Platform Designer
system?

Documents / Resources

References

Leave a comment

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Nios V Embedded Processor

Product Information

Specifications

Product Usage Instructions

1. Nios V Processor Hardware System Design

2. Nios V Processor Software System Design

3. Nios V Processor Configuration and Booting Solutions

Frequently Asked Questions (FAQ)

Q: What software is compatible with the Nios V Processor?

Q: What type of memories does the Nios V Processor support?

Q: How can I optimize the performance of the Platform Designer system?

Documents / Resources

References

Leave a comment

Cancel reply

Q: What type of memories does the Nios V Processor
support?

Q: How can I optimize the performance of the Platform Designer
system?