Altera Nios V Jagorar Mai Amfani Mai Haɗawa

Abubuwan da ke ciki boye

1 altera Nios V Embedded Processor

2 Ƙayyadaddun bayanai

3 Nios V Processor Hardware System Design

4 Nios V Processor Software System Design

5 Nios V Processor Configuration and Booting Solutions

6 Takardu / Albarkatu

6.1 Magana

altera Nios V Embedded Processor

Ƙayyadaddun bayanai

Sunan samfur: Nios V Processor
Software Compatibility: Quartus Prime Software and Platform Designer

Nau'in Mai sarrafawa: Altera FPGA
Tsarin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa) da Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa

Sadarwar Sadarwa: Wakilin UART

Nios V Processor Hardware System Design

To design the Nios V Processor hardware system, follow these steps:

Create Nios V Processor system design using Platform Designer.
Haɗa tsarin cikin aikin Quartus Prime.

Design memory system including volatile and non-volatile memory.
Aiwatar da agogo da sake saita mafi kyawun ayyuka.

Sanya tsoffin wakilai da UART don ingantaccen aiki.

Nios V Processor Software System Design

Don tsara tsarin software don Nios V Processor:

Bi tsarin haɓaka software don Nios V Processor.
Create Board Support Package Project and Application Project.

Nios V Processor Configuration and Booting Solutions

Don daidaitawa da booting da Nios V Processor:

Understand the introduction to configuration and booting solutions.

Aikace-aikacen haɗin yanar gizo don aiki mara kyau.

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About the Nios® V Embedded Processor
1.1. Altera® FPGA da Haɗe-haɗen Processors Overview
Na'urorin Altera FPGA na iya aiwatar da dabaru waɗanda ke aiki azaman cikakken microprocessor yayin samar da zaɓuɓɓuka da yawa.
Bambanci mai mahimmanci tsakanin masu sarrafa microprocessors da Altera FPGA shine cewa masana'anta na Altera FPGA ba su ƙunshe da dabaru yayin da yake tashi. Nios® V na'ura mai sarrafawa ne mai taushin kayan fasaha (IP) bisa ƙayyadaddun RISC-V. Kafin kayi amfani da software akan tsarin tushen Nios V, dole ne ka saita na'urar Altera FPGA tare da ƙirar kayan masarufi wanda ya ƙunshi na'ura mai sarrafa Nios V. Kuna iya sanya injin Nios V a ko'ina akan Altera FPGA, dangane da buƙatun ƙira.

Don ba da damar tsarin shigar da tushen IP na Altera® FPGA don yin aiki azaman tsarin tushen microprocessor mai hankali, tsarinku yakamata ya haɗa da masu zuwa: · AJ.TAG dubawa don tallafawa saitin Altera FPGA, hardware da software
gyara matsala · Tsarin daidaitawar Altera FPGA mai ƙarfi
Idan tsarin ku yana da waɗannan damar, zaku iya fara tace ƙirar ku daga ƙirar kayan aikin da aka riga aka ɗora a cikin Altera FPGA. Amfani da Altera FPGA kuma yana ba ku damar canza ƙirar ku da sauri don magance matsaloli ko ƙara sabbin ayyuka. Kuna iya gwada waɗannan sabbin ƙirar kayan masarufi cikin sauƙi ta hanyar sake saita Altera FPGA ta amfani da tsarin ku na JTAG dubawa.
A JTAG dubawa yana goyan bayan haɓaka kayan masarufi da software. Kuna iya aiwatar da ayyuka masu zuwa ta amfani da JTAG Interature: · Sanya Altera FPGA · Zazzagewa da cire software · Sadarwa tare da Altera FPGA ta hanyar sadarwa mai kama da UART (J)TAG UART
Terminal) · Kayan aikin gyara kuskure (tare da siginar Tap mai ƙididdige ƙididdiga) · Ƙwaƙwalwar walƙiya na shirin
Bayan kun saita Altera FPGA tare da ƙira na tushen Nios V, haɓakar haɓaka software yayi kama da kwarara don ƙirar ƙira mai hankali.

Bayani mai alaƙa · AN 985: Nios V Processor Tutorial
Jagorar farawa mai sauri game da ƙirƙirar tsarin sarrafa Nios V mai sauƙi da gudanar da aikace-aikacen Hello World.
© Altera Corporation. Altera, tambarin Altera, tambarin `a', da sauran alamomin Altera alamun kasuwanci ne na Kamfanin Altera. Altera yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Altera ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka bayyana a nan sai dai kamar yadda Altera ya yarda da shi a rubuce. Ana shawarci abokan cinikin Altera su sami sabon sigar ƙayyadaddun na'urar kafin dogaro da kowane bayanan da aka buga kuma kafin yin oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

1. Game da Nios® V Embedded Processor 726952 | 2025.07.16
Manual Reference Processor Nios V Yana ba da bayanai game da ma'auni na aikin Nios V, tsarin gine-gine, ƙirar shirye-shirye, da ainihin aiwatarwa.
Haɗe-haɗe-haɗe-haɗen Jagorar Mai amfanin IP · Nios V Littafin Jagorar Haɓaka Software

Yana bayyana yanayin haɓaka software na Nios V, kayan aikin da ake da su, da kuma tsarin gina software don aiki akan processor na Nios V. Ashling* RiscFree* Haɗin Haɗin Ci gaban Muhalli (IDE) don Altera FPGAs Jagorar Mai Amfani Yana Siffanta RiscFree* hadedde raya muhalli (IDE) don Altera FPGAs Arm* na tushen HPS da Nios V core processor. Nios V Mai sarrafawa Altera FPGA Bayanan Sakin IP
1.2. Taimakon Software na Quartus® Prime
Nios V na aikin ginawa ya bambanta don software na Quartus® Prime Pro Edition da software na Quartus Prime Standard Edition. Koma zuwa AN 980: Nios V Processor Quartus Prime Software Support don ƙarin bayani game da bambance-bambance.
Bayani mai alaƙa AN 980: Nios V Processor Quartus Prime Support Software
1.3. Nios V Mai sarrafawa lasisi
Kowane bambance-bambancen processor na Nios V yana da maɓallin lasisinsa. Da zarar kun sami maɓallin lasisi, zaku iya amfani da maɓallin lasisi iri ɗaya don duk ayyukan sarrafa Nios V har zuwa ranar karewa. Kuna iya samun lasisin Nios V Processor Altera FPGA IP akan sifili.
Akwai jerin maɓallin lasisin mai sarrafa Nios V a cikin Altera FPGA Cibiyar Lasisi na Sabis na Kai. Danna maballin Yi rijista don kimantawa ko shafin lasisin Kyauta, kuma zaɓi zaɓuɓɓukan da suka dace don yin buƙatar.
Hoto 1. Cibiyar Ba da Lasisi ta Sabis ta Altera FPGA

Tare da maɓallin lasisi, zaku iya:
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Aiwatar da Nios V processor a cikin tsarin ku. Kwaikwayi halin tsarin sarrafa Nios V. · Tabbatar da aikin ƙira, kamar girma da sauri. · Ƙirƙirar shirye-shiryen na'ura files. · Shirya na'ura kuma tabbatar da ƙira a cikin kayan aiki.
Ba kwa buƙatar lasisi don haɓaka software a cikin Ashling* RiscFree* IDE don Altera FPGAs.
Bayani mai dangantaka · Altera FPGA Cibiyar ba da lasisin Sabis na Kai
Don ƙarin bayani game da samun maɓallan lasisin IP na Nios V Processor Altera FPGA. Altera FPGA Software Shigarwa da Lasisi Don ƙarin bayani game da lasisin Altera FPGA software da kafa kafaffen lasisi da uwar garken lasisin cibiyar sadarwa.
1.4. Ƙirƙirar Tsarin Tsarin
Hoto mai zuwa yana misalta sauƙaƙan tsarin ƙirar ƙirar Nios V, gami da haɓaka kayan masarufi da software.

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Hoto na 2.

Nios V Tsarin Tsarin Tsarin Tsarin Gudanarwa
Tsarin Tsarin

Yi nazarin Bukatun Tsarin

Nios® V
Cores Processor da Madaidaitan Kayan Aiki

Ƙayyade kuma Ƙirƙirar Tsarin a ciki
Dandali Mai Zane

Hardware Flow: Haɗa da Haɗa Intel Quartus Prime Project

Gudun Software: Haɓaka da Gina Nios V Proposal Software

Gudun Hardware: Zazzage Tsarin FPGA
zuwa Target Board

Gudun Software: Gwaji da Gyara Nios V Software Processor

Software Babu Haɗuwa Takaice?
Ee
Hardware Babu Haɗuwa Takaice? Ee
Tsarin Kammala

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Hoto na 3.

Zane mai zuwa yana kwatanta ƙirar kayan aikin Nios V na yau da kullun. Nios V Tsarin Tsarin Tsarin Hardware Flow

Fara

Nios V Cores da Daidaitattun Kayan Aiki

Yi amfani da Mai Zane Platform don Zana Tsarin Tsarin Nios V
Ƙirƙirar Zane-zanen Platform

Haɗa Tsarin Tsarin Platform tare da Intel Quartus Prime Project
Sanya Wuraren Pin, Bukatun Lokaci, da sauran Matsalolin ƙira
Haɗa Hardware don Na'urar Target a cikin Intel Quartus Prime

Shirye don saukewa
2.1. Ƙirƙirar Tsarin Tsarin Nios V Processor tare da Mai tsara Platform
Software na Quartus Prime ya haɗa da kayan aikin haɗin gwiwar tsarin Platform Designer wanda ke sauƙaƙe aikin ma'ana da haɗa Nios V processor IP core da sauran IPs a cikin ƙirar tsarin Altera FPGA. Zane Platform ta atomatik yana ƙirƙira dabarun haɗin kai ta atomatik daga ƙayyadadden haɗin haɗin matakin matakin. Haɗin haɗin kai ta atomatik yana kawar da aikin ɗaukar lokaci na ƙididdige haɗin tsarin matakin HDL.
© Altera Corporation. Altera, tambarin Altera, tambarin `a', da sauran alamomin Altera alamun kasuwanci ne na Kamfanin Altera. Altera yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Altera ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka bayyana a nan sai dai kamar yadda Altera ya yarda da shi a rubuce. Ana shawarci abokan cinikin Altera su sami sabon sigar ƙayyadaddun na'urar kafin dogaro da kowane bayanan da aka buga kuma kafin yin oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

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Bayan nazarin abubuwan buƙatun kayan masarufi na tsarin, kuna amfani da Quartus Prime don ƙididdige ainihin abin sarrafawa na Nios V, ƙwaƙwalwar ajiya, da sauran abubuwan da tsarin ku ke buƙata. Mai Zane Platform ta atomatik yana haifar da dabarun haɗin kai don haɗa abubuwan da ke cikin tsarin hardware.

2.1.1. Mai Haɓakawa Nios V Mai sarrafawa Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

Tushen IP na kowane mai sarrafawa yana goyan bayan zaɓuɓɓukan sanyi daban-daban dangane da keɓaɓɓen gine-ginensa. Kuna iya ayyana waɗannan saitunan don dacewa da buƙatun ƙirar ku.

Tebur 1.

Zaɓuɓɓukan Kanfigareshan Tsakanin Bambancin Mahimmanci

Zaɓuɓɓukan Kanfigareshan

Nios V/c Processor

Nios V/m Mai sarrafawa

Buƙatar Buƙatun Sake saitin Amfani

—

Tarko, Keɓancewa, da Katsewa

CPU Architecture

ECC

Caches, Yankunan Wuta da TCMs

—

Umarnin Musamman

—

Makulli

—

Nios V/g Processor

2.1.1.1. Instantiating Nios V/c Karamin Microcontroller Altera FPGA IP Hoto 4. Nios V/c Karamin Microcontroller Altera FPGA IP

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2.1.1.1.1. CPU Architecture Tab

Tebur 2.

CPU Architecture Tab

Siffar

Bayani

Kunna Interface Avalon® Yana kunna Avalon Interface don manajan koyarwa da manajan bayanai. Idan an kashe, tsarin yana amfani da AXI4-Lite interface.

darajar CSR

· Zaɓin IP mara inganci. Kar a yi amfani da ƙimar mhartid CSR a cikin Nios V/c processor.

2.1.1.1.2. Yi amfani da Sake saitin Neman Tab

Tebur 3.

Yi amfani da Siginar Sake saitin Tab

Yi amfani da Tab ɗin Buƙatun Sake saitin

Bayani

Ƙara Interface Buƙatar Sake saitin

Ba da damar wannan zaɓi don fallasa tashoshin sake saiti na gida inda maigidan gida zai iya amfani da shi don kunna na'urar sarrafa Nios V don sake saitawa ba tare da shafar sauran abubuwan da ke cikin na'urar sarrafa Nios V ba.
Sake saitin dubawa ya ƙunshi siginar sake saiti na shigarwa da siginar ack na fitarwa.
Kuna iya buƙatar sake saiti zuwa Nios V processor core ta tabbatar da siginar sake saitawa.
Dole ne siginar sake saitawa ya ci gaba da tabbatarwa har sai mai sarrafawa ya tabbatar da sigina. Rashin ci gaba da tabbatar da siginar na iya haifar da na'ura mai sarrafa ya kasance cikin yanayin da ba a tantancewa ba.
· Mai sarrafa Nios V ya amsa cewa sake saitin ya yi nasara ta hanyar tabbatar da siginar ack.
Bayan an sami nasarar sake saita na'ura mai sarrafawa, tabbatar da siginar ack na iya faruwa sau da yawa lokaci-lokaci har sai an cire siginar sake saitawa.

2.1.1.1.3. Tarko, Keɓancewa, da Tab ɗin Katsewa

Tebur 4.

Tarko, Keɓancewa, da Katse Ma'aunin Tab

Tarko, Keɓancewa, da Katsewa

Bayani

Sake saitin Wakili

Sake saitin Kayyade

· Yana ƙayyadad da diyya na sake saiti vector dangane da zaɓaɓɓen adireshin tushe na wakilin sake saiti. Zane Platform ta atomatik yana ba da ƙimar da ta dace don sake saiti.

Lura:

Platform Designer yana ba da cikakken zaɓi, wanda ke ba ka damar ƙididdige adireshi cikakke a Sake saiti. Yi amfani da wannan zaɓin lokacin da ƙwaƙwalwar ajiyar ƙwaƙwalwar ajiya ta sake saiti vector tana wajen tsarin sarrafawa da ƙananan tsarin.

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2.1.1.1.4. ECC Tab

Tebur 5.

ECC Tab

ECC

Kunna Gano Kuskure da Rahoton Hali

Bayani
Ba da damar wannan zaɓi don amfani da fasalin ECC don Nios V processor na RAM tubalan. Siffofin ECC suna gano kurakurai har zuwa 2-bits kuma suna mayar da martani dangane da halaye masu zuwa:
- Idan kuskuren 1-bit ne wanda za'a iya gyarawa, mai sarrafa na'urar yana ci gaba da aiki bayan gyara kuskuren a cikin bututun mai sarrafawa. Duk da haka, gyara ba ya bayyana a cikin tunanin tushen.
- Idan kuskuren ba a iya gyara shi ba, mai sarrafa na'ura ya ci gaba da aiki ba tare da gyara shi ba a cikin bututun mai sarrafawa da kuma abubuwan tunawa, wanda zai iya sa mai sarrafawa ya shiga yanayin da ba a tantance ba.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Hoto 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Gyara Tab

Tebur 6.

Gyara Matsalolin Tab

Gyara Tab

Bayani

Kunna gyara kuskure
Kunna Sake saitin daga Module na gyara kuskure

Kunna wannan zaɓi don ƙara JTAG module dangane da manufa zuwa processor Nios V. · JTAG Maƙasudin haɗin haɗin kai yana ba da damar haɗi zuwa mai sarrafa Nios V ta hanyar
JTAG Interface fil na FPGA. Haɗin yana ba da damar iyakoki masu zuwa:
- Fara da dakatar da Nios V processor - Bincika kuma gyara rajista da ƙwaƙwalwar ajiya. - Zazzage aikace-aikacen Nios V .elf file zuwa memory processor a runtime via
niosv-zazzagewa. - Kashe aikace-aikacen da ke gudana akan na'urar sarrafa Nios V · Haɗa tashar dm_agent zuwa umarni na sarrafawa da bas ɗin bayanai. Tabbatar da adireshin tushe tsakanin duka motocin bas iri ɗaya ne.
Ba da damar wannan zaɓi don buɗe tashar dbg_reset_out da ndm_reset_in. · JTAG debugger ko umarni na niosv-download -r yana haifar da dbg_reset_out, wanda
yana ba da damar mai sarrafa Nios V don sake saita na'urori masu alaƙa da wannan tashar jiragen ruwa. Dole ne ku haɗa haɗin dbg_reset_out zuwa ndm_reset_in maimakon sake saiti
dubawa don kunna sake saiti zuwa processor core da timer module. Ba dole ba ne ka haɗa haɗin dbg_reset_out don sake saita dubawa don hana hali mara iyaka.

2.1.1.2.2. Yi amfani da Sake saitin Neman Tab

Tebur 7.

Yi amfani da Siginar Sake saitin Tab

Yi amfani da Tab ɗin Buƙatun Sake saitin

Bayani

Ƙara Interface Buƙatar Sake saitin

Ba da damar wannan zaɓi don fallasa tashoshin sake saiti na gida inda maigidan gida zai iya amfani da shi don kunna na'urar sarrafa Nios V don sake saitawa ba tare da shafar sauran abubuwan da ke cikin na'urar sarrafa Nios V ba.
Sake saitin dubawa ya ƙunshi siginar sake saiti na shigarwa da siginar ack na fitarwa.
Kuna iya buƙatar sake saiti zuwa Nios V processor core ta tabbatar da siginar sake saitawa.
Dole ne siginar sake saitawa ya ci gaba da tabbatarwa har sai mai sarrafawa ya tabbatar da sigina. Rashin ci gaba da tabbatar da siginar na iya haifar da na'ura mai sarrafa ya kasance cikin yanayin da ba a tantancewa ba.
Tabbatar da siginar sake saitawa a yanayin gyara kuskure ba shi da wani tasiri akan yanayin mai sarrafawa.
· Mai sarrafa Nios V ya amsa cewa sake saitin ya yi nasara ta hanyar tabbatar da siginar ack.
Bayan an sami nasarar sake saita na'ura mai sarrafawa, tabbatar da siginar ack na iya faruwa sau da yawa lokaci-lokaci har sai an cire siginar sake saitawa.

2.1.1.2.3. Tarko, Keɓancewa, da Tab ɗin Katsewa

Tebur 8.

Tarko, Keɓancewa, da Tab ɗin Katsewa

Bayani

Sake saitin Wakili

Sake saitin Katse Yanayin Katsewa

· Yana ƙayyadad da diyya na sake saiti vector dangane da zaɓaɓɓen adireshin tushe na wakilin sake saiti. Zane Platform ta atomatik yana ba da ƙimar da ta dace don sake saiti.
Ƙayyadaddun nau'in mai sarrafa katse kai tsaye ko Vectored. Lura: Nios V/m mai sarrafawa mara bututu baya goyan bayan katsewar Vectored.
Don haka, guje wa amfani da yanayin katsewar Vectored lokacin da mai sarrafa ke cikin Yanayin Mara bututu.

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Lura:

2.1.1.2.4. CPU Architecture

Tebur 9.

CPU Architecture Tab Parameters

CPU Architecture

Bayani

Kunna bututun mai a cikin CPU

Ba da damar wannan zaɓi don kunna mai sarrafa bututun Nios V/m. - IPC ya fi girma a farashin mafi girman yankin tunani da ƙananan mitar Fmax.
· Kashe wannan zaɓin don aiwatar da aikin Nios V/m mara bututu. - Yana da aiki mai kama da na Nios V/c processor. - Yana goyan bayan ƙaddamarwa da iyawar katsewa - Ƙananan yanki na dabaru da mafi girma Fmax a farashin ƙananan IPC.

Kunna Interface Avalon

Yana kunna Interface Avalon don manajan koyarwa da manajan bayanai. Idan an kashe, tsarin yana amfani da AXI4-Lite interface.

darajar CSR

· Rijistar Hart ID (mhartid) darajar ita ce 0 a tsohuwa. · Sanya ƙima tsakanin 0 da 4094. · Mai dacewa da Altera FPGA Avalon Mutex Core HAL API.

Bayani mai alaƙa Haɗe-haɗe na Jagorar Mai amfani da IP - Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Tab
Tebur 10. ECC Tab
ECC Kunna Gano Kuskure da Rahoton Hali

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2.1.1.3. Haɓaka Nios V/g Babban Maƙasudin Manufa Altera FPGA IP
Hoto 6. Nios V/g Babban Maƙasudin Manufa Altera FPGA IP - Sashe na 1

Hoto na 7.

Nios V/g Babban Maƙasudin Manufa Altera FPGA IP - Kashi na 2 (Kashe Mai Kula da Matakin Katsewa)

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Hoto na 8.

Nios V/g Babban Maƙasudin Manufa Altera FPGA IP - Kashi na 2 (Kuna Kunna Mai Kula da Matakin Tsage-tsare)

Hoto 9. Nios V/g Babban Maƙasudin Manufa Altera FPGA IP - Sashe na 3

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Hoto 10. Nios V/g Babban Maƙasudin Manufa Altera FPGA IP - Sashe na 4

2.1.1.3.1. CPU Architecture

Table 11. CPU Architecture Parameters

Tabbun Gine-gine na CPU Kunna Rukunin Ma'anar iyo

Bayanin Ƙaddamar da wannan zaɓi don ƙara naúrar mai iyo ("F" tsawo) a cikin core processor.

Kunna Hasashen Reshe

Kunna tsinkayar reshe a tsaye (An ɗauki Baya da Gaba ba a ɗauka) don umarnin reshe.

darajar CSR

· Rijistar Hart ID (mhartid) darajar ita ce 0 a tsohuwa. · Sanya ƙima tsakanin 0 da 4094. · Mai dacewa da Altera FPGA Avalon Mutex Core HAL API.

Kashe umarnin FSQRT & FDIV don FPU

Cire tushen murabba'i mai iyo (FSQRT) da ayyukan rarraba-maki (FDIV) a cikin FPU.
· Aiwatar da kwaikwayi software akan umarni biyu yayin lokacin aiki.

Bayani mai alaƙa Haɗe-haɗe na Jagorar Mai amfani da IP - Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. Gyara Tab

Tebura 12. Gyara Matsalolin Tab

Gyara Tab

Bayani

Kunna gyara kuskure
Kunna Sake saitin daga Module na gyara kuskure

2.1.1.3.3. Teburin Makulli 13. Makulli Tab
Sigogi Kunna Tsohuwar Makulli Lokacin Kashe Lokacin Ƙaddamar da Ƙarfin Sake saitin Interface

Bayani · Kunna tsarin kulle-kulle mai dual core. Ƙimar ƙayyadaddun ƙayyadaddun lokaci na shirye-shirye akan sake saitin fita (tsakanin 0 da 255). • Kunna madaidaicin Sake saitin na zaɓi don Ƙarfin Sake saitin Ikon. · Lokacin da aka kashe, fRSmartComp yana aiwatar da Ikon Sake saitin Ainihin.

2.1.1.3.4. Yi amfani da Sake saitin Neman Tab

Tebura 14. Yi Amfani da Siginar Sake saitin Tab

Yi amfani da Tab ɗin Buƙatun Sake saitin

Bayani

Ƙara Interface Buƙatar Sake saitin

Ba da damar wannan zaɓi don fallasa tashoshin sake saiti na gida inda maigidan gida zai iya amfani da shi don kunna na'urar sarrafa Nios V don sake saitawa ba tare da shafar sauran abubuwan da ke cikin na'urar sarrafa Nios V ba.
Sake saitin dubawa ya ƙunshi siginar sake saiti na shigarwa da siginar ack na fitarwa.
Kuna iya buƙatar sake saiti zuwa Nios V processor core ta tabbatar da siginar sake saitawa.
Dole ne siginar sake saitawa ya ci gaba da tabbatarwa har sai mai sarrafawa ya tabbatar da sigina. Rashin ci gaba da tabbatar da siginar na iya haifar da na'ura mai sarrafa ya kasance cikin yanayin da ba a tantancewa ba.
Tabbatar da siginar sake saitawa a yanayin gyara kuskure ba shi da wani tasiri akan yanayin mai sarrafawa.
· Mai sarrafa Nios V ya amsa cewa sake saitin ya yi nasara ta hanyar tabbatar da siginar ack.
Bayan an sami nasarar sake saita na'ura mai sarrafawa, tabbatar da siginar ack na iya faruwa sau da yawa lokaci-lokaci har sai an cire siginar sake saitawa.

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2.1.1.3.5. Tarko, Keɓancewa, da Tab ɗin Katsewa

Tebur 15.

Tarko, Keɓancewa, da Tab ɗin Katsewa lokacin da An Kashe Mai Kula da Matakin Tsagewar Matsayi

Tarko, Keɓancewa, da Tab ɗin Katsewa
Sake saitin Wakili

Bayani
· Ƙwaƙwalwar ajiya mai karɓar reset vector (adreshin sake saiti na processor Nios V) inda lambar sake saiti take.
Za ka iya zaɓar kowane ƙirar ƙwaƙwalwar ajiya da aka haɗa zuwa mai sarrafa na'ura na Nios V kuma yana goyan bayan kwararar boot ɗin processor na Nios V azaman wakili na sake saiti.

Sake saitin Kayyade

· Yana ƙayyadad da diyya na sake saiti vector dangane da zaɓaɓɓen adireshin tushe na wakilin sake saiti. Zane Platform ta atomatik yana ba da ƙimar da ta dace don sake saiti.

Kunna Mai Kula da Matakin Tsage-Tsare (CLIC)

Ba da damar CLIC don tallafawa katsewa da wuri da kuma daidaita yanayin faɗakarwa.
· Lokacin da aka kunna, zaku iya saita adadin masu katsewar dandamali, saita yanayin faɗakarwa, da sanya wasu daga cikin katsewar azaman riga-kafi.

Katse Yanayin Inuwa Rajista Files

Ƙayyade nau'ikan katsewa azaman Kai tsaye, ko Vectored Kunna rajistar inuwa don rage canjin mahallin akan katsewa.

Tebur 16.

Tarko, Keɓancewa da Katsewa lokacin Kunna Mai Kula da Katse Matsayin Babban Matsayi

Tarko, Keɓancewa, da Katsewa

Bayani

Sake saitin Wakili
Sake saitin Kayyade
Kunna Mai Kula da Matakin Tsage-Tsare (CLIC)

· Ƙwaƙwalwar ajiya mai karɓar reset vector (adreshin sake saiti na processor Nios V) inda lambar sake saiti take.
Za ka iya zaɓar kowane ƙirar ƙwaƙwalwar ajiya da aka haɗa zuwa mai sarrafa na'ura na Nios V kuma yana goyan bayan kwararar boot ɗin processor na Nios V azaman wakili na sake saiti.
· Yana ƙayyadad da diyya na sake saiti vector dangane da zaɓaɓɓen adireshin tushe na wakilin sake saiti. Zane Platform ta atomatik yana ba da ƙimar da ta dace don sake saiti.
Ba da damar CLIC don tallafawa katsewa da wuri da kuma daidaita yanayin faɗakarwa. · Lokacin da aka kunna, zaku iya saita adadin masu katsewar dandamali, saita yanayin faɗakarwa,
da kuma sanya wasu daga cikin katsewa a matsayin riga-kafi.

Yanayin Katsewa

Ƙayyade nau'ikan katsewa azaman Direct, Vectored, ko CLIC.

Inuwa Rajista Files

• Kunna rajistar inuwa don rage sauyawar mahallin bayan katsewa.
· Yana ba da hanyoyi guda biyu:
- Adadin matakan katsewar CLIC
- Adadin matakan katsewar CLIC - 1: Wannan zaɓin yana da amfani lokacin da kuke son adadin rajista file kwafi don dacewa da ainihin adadin M20K ko M9K tubalan.
Kunna mai sarrafa Nios V don amfani da rajistar inuwa files wanda ke rage jujjuyawar mahallin sama a kan katsewa.
Don ƙarin bayani game da rajistar inuwa files, koma zuwa Nios V Reference Manual.

Adadin hanyoyin katse hanyoyin dandamali

· Yana ƙayyade adadin katsewar dandamali tsakanin 16 zuwa 2048.
Lura: CLIC tana goyan bayan shigarwar katsewa har zuwa 2064, kuma abubuwan shigarwa na katsewa guda 16 na farko suma an haɗa su zuwa ainihin mai sarrafa katsewa.

Daidaita Tebur Vector CLIC

· Ƙaddamarwa ta atomatik bisa adadin hanyoyin katsewar dandamali. · Idan kun yi amfani da jeri da ke ƙasa da ƙimar da aka ba da shawarar, CLIC yana ƙaruwa da hankali
hadaddun ta hanyar ƙara ƙarin ƙara don yin lissafin vectoring. · Idan kun yi amfani da jeri da ke ƙasa da ƙimar da aka ba da shawarar, wannan yana haifar da haɓaka
hadaddun dabaru a cikin CLIC.
ci gaba…

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Tarko, Keɓancewa, da Katsewa
Adadin Matakan Katsewa
Adadin Abubuwan Farko na Farko kowane mataki
Ƙaddamar da katsewar polarity Taimako gefen goyan baya ya jawo katsewa

Bayani
· Yana ƙayyade adadin matakan katsewa tare da ƙarin matakin 0 don lambar aikace-aikace. Katsewa na matsayi mafi girma na iya katse (pre-empty) mai gudanar da aiki don katsewar matakin ƙasa.
· Tare da matakan katse marasa sifili a matsayin zaɓin kawai don katsewa, lambar aikace-aikacen koyaushe tana kan matakin mafi ƙanƙanta 0. Lura: Tsayawa lokacin gudu na matakin katsewa kuma ana yin fifiko a cikin rijistar 8-bit guda ɗaya. Idan adadin matakan katsewa shine 256, ba zai yiwu a daidaita fifikon katsewa a lokacin gudu ba. In ba haka ba, matsakaicin adadin abubuwan abubuwan da za a iya daidaita su shine 256 / (yawan matakan katsewa - 1).
· Yana ƙayyadaddun adadin abubuwan da aka fi dacewa da katsewa, waɗanda CLIC ke amfani da su don tantance tsarin da ake kiran masu kula da katsewa. Lura: Haɗin ƙimar binaryar matakin katse da aka zaɓa da zaɓin fifikon katsewa dole ne ya zama ƙasa da rago 8.
· Yana ba ku damar saita polarity ta katse yayin lokacin aiki. · Default polarity tabbatacce polarity.
Yana ba ku damar saita yanayin faɗakarwa yayin lokacin aiki, watau babban matakin jawo ko tabbataccen baki (lokacin da katse polarity yana da inganci a cikin Ƙaƙwalwar katsewar polarity).
· Yanayin faɗakarwa na asali yana haifar da katsewa.

Lura:

Bayani mai alaƙa Nios® V Manual Reference Manual

2.1.1.3.6. Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa Tab

Tebur 17. Ma'auni na Kanfigareshan Ƙwaƙwalwar Ƙwaƙwalwa

Kashi

Tab ɗin Kanfigareshan Ƙwaƙwalwa

Bayani

Caches

Girman Cache Data

· Yana ƙayyade girman cache ɗin bayanai. Girma masu inganci daga 0 kilobytes (KB) zuwa 16 KB. Kashe cache na bayanai idan girman ya kai 0 KB.

Girman Cache Umarni

· Yana ƙayyade girman cache na umarni. Girma masu inganci daga 0 KB zuwa 16 KB. Kashe cache na umarni lokacin da girman ya kai 0 KB.

Yankin Yanki A da B

Girman

· Ƙayyadaddun girman yanki na gefe.
Girma masu inganci daga 64 KB zuwa 2 gigabytes (GB), ko Babu. Zaɓin Babu ɗaya yana kashe yanki na gefe.

Adireshin tushe

· Ƙayyadaddun adireshin tushe na yanki na gefe bayan kun zaɓi girman.
Duk adiresoshin da ke cikin yanki suna samar da hanyar shiga bayanan da ba za a iya ganowa ba.
Adireshin tushe na yanki dole ne ya daidaita zuwa girman yanki.

Abubuwan Tunawa da Haɗaɗɗen Tattara

Girman

· Yana ƙayyadaddun girman ƙwaƙwalwar haɗe-haɗe. - Ingantattun masu girma dabam daga 0 MB zuwa 512 MB.

Ƙaddamar da Adireshin tushe File

· Ƙayyadaddun adireshin tushe na ƙwaƙwalwar haɗe-haɗe. · Yana ƙayyade ƙaddamarwa file don ƙwaƙwalwar haɗe-haɗe.

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Lura:

A cikin tsarin sarrafa Nios V tare da kunna cache, dole ne ku sanya abubuwan da ke kewaye da tsarin a cikin yanki na gefe. Kuna iya amfani da yankuna na gefe don ayyana ma'amalar da ba za a iya adanawa ba don abubuwan da ke gefe kamar UART, PIO, DMA, da sauransu.

2.1.1.3.7. ECC Tab

Tebur 18. ECC Tab
ECC Kunna Gano Kuskure da Rahoton Hali
Kunna Gyara Guda Daya

Bayani
Ba da damar wannan zaɓi don amfani da fasalin ECC don Nios V processor na RAM tubalan. Siffofin ECC suna gano kurakurai har zuwa 2-bits kuma suna mayar da martani dangane da halaye masu zuwa:
- Idan kuskuren bit guda ne wanda za'a iya gyarawa kuma An kashe Gyaran Single Bit, mai sarrafa na'ura yana ci gaba da aiki bayan ya gyara kuskuren a cikin bututun mai sarrafawa. Duk da haka, gyara ba ya bayyana a cikin tunanin tushen.
- Idan kuskuren bit guda ne wanda za'a iya daidaitawa kuma an kunna Gyara Single Bit Correction, mai sarrafa na'ura yana ci gaba da aiki bayan ya gyara kuskuren a cikin bututun na'ura da abubuwan tunawa.
- Idan kuskure ne wanda ba a iya gyarawa, mai sarrafa na'urar yana dakatar da aikinsa.
Kunna gyaran bit guda ɗaya akan tubalan ƙwaƙwalwar ajiya a cikin ainihin.

2.1.1.3.8. Tab ɗin Umarni na Musamman

Lura:

Wannan shafin yana samuwa ne kawai don Nios V/g processor core.

Umarni na Musamman Nios V Tebur Interface Interface Umarni na Musamman na Hardware
Nios V Custom Koyarwar Software Macro Tebura

Bayani
· Nios V processor yana amfani da wannan tebur don ayyana musaya ɗin sarrafa umarni na al'ada.
Ƙayyadaddun musaya na manajan umarni na al'ada an tsara su ta musamman ta Opcode (CUSTOM0-3) da 3 ragowa na aikin7[6:4].
Za ka iya ayyana har zuwa jimillar musaya mai sarrafa koyarwa na al'ada guda 32.
· Nios V processor yana amfani da wannan tebur ana amfani da shi don ayyana ɓoyayyun software na koyarwa na al'ada don ƙayyadaddun musaya masu sarrafa koyarwa na al'ada.
Ga kowane ƙayyadaddun tsarin ɓoye software na koyarwa na al'ada, Opcode (CUSTOM0-3) da 3 bits na ayyuka7[6:4] dole ne su daidaita da ƙayyadadden ƙirar manajan umarni na al'ada da ke ɓoye a cikin Teburin Interface Interface Instruction Hardware.
Za ka iya amfani da funct7[6:4], funct7[3:0], da kuma funct3[2:0] don ayyana ƙarin rikodi don koyarwar al'ada da aka bayar, ko ƙayyadaddun azaman Xs da za'a shigar dasu azaman ƙarin hujjojin koyarwa.
Nios V processor yana ba da ƙayyadaddun bayanan software na koyarwa na al'ada kamar yadda aka samar da C-macro a cikin system.h, kuma bi tsarin koyarwa na nau'in R-RISC-V.
Za a iya amfani da ma'anar mnemonics don ayyana sunaye na al'ada don: - C-Macros da aka samar a cikin tsarin.h.
- GDB da aka haifar da gyara kuskuren mnemonics a cikin custom_instruction_debug.xml.

Bayanai masu alaƙa
AN 977: Umarnin Custom na Nios V Processor Don ƙarin bayani game da umarnin al'ada waɗanda ke ba ku damar keɓance na'urar sarrafa Nios® V don saduwa da buƙatun takamaiman aikace-aikacen.

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2.1.2. Ma'anar Ƙirar Tsarin Tsarin
Yi amfani da Platform Designer don ayyana halayen kayan masarufi na tsarin sarrafa Nios V kuma ƙara cikin abubuwan da ake so. Zane mai zuwa yana nuna ainihin ƙirar ƙirar Nios V tare da abubuwa masu zuwa: · Nios V processor core · On-Chip Memory · JTAG UART · Lokacin Tazara (na zaɓi) (1)
Lokacin da aka ƙara sabon Ƙwaƙwalwar Kan-Chip zuwa tsarin Platform Designer, yi Bayanan Tsarin Aiki tare don nuna ƙarin abubuwan ƙwaƙwalwar ajiya a sake saiti. A madadin, zaku iya kunna Aiki tare ta atomatik a cikin Platform Designer don nuna sabbin canje-canje ta atomatik ta atomatik
Hoto 11. ExampHaɗin na'ura mai sarrafa Nios V tare da sauran kayan aiki a cikin Platform Designer

(1) Kuna da zaɓi don amfani da fasalulluka na Nios V na ciki don maye gurbin lokaci tazara ta waje a cikin Mai tsara Platform.

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Dole ne ku kuma ayyana fil ɗin aiki don fitarwa azaman magudanar ruwa a cikin tsarin Tsarin Platform ɗin ku. Don misaliampHar ila yau, an ayyana madaidaicin lissafin aikin tsarin FPGA kamar yadda ke ƙasa amma ba'a iyakance ga:
· Agogo
· Sake saita
· Alamomin I/O
2.1.3. Ƙayyadaddun adiresoshin Tushe da Abubuwan da ake buƙata na Katsewa
Don ƙayyade yadda abubuwan da aka ƙara a cikin ƙirar ke hulɗa don samar da tsari, kuna buƙatar sanya adiresoshin tushe ga kowane ɓangaren wakili kuma sanya buƙatun katsewa (IRQ) fifiko ga J.TAG UART da lokacin tazara. Mai tsara Platform yana ba da umarni - Sanya Adireshin Base - wanda ke ba da adiresoshin tushe masu dacewa ta atomatik zuwa duk abubuwan da ke cikin tsarin. Koyaya, zaku iya daidaita adiresoshin tushe bisa ga bukatun ku.
Waɗannan su ne wasu jagororin sanya adireshin tushe:
Nios V processor core yana da tsawon adireshi 32-bit. Don samun dama ga abubuwan da aka haɗa, adireshin tushe dole ne ya kasance tsakanin 0x00000000 da 0xFFFFFFFF.
· Shirye-shiryen Nios V suna amfani da madaukai na alama don komawa zuwa adireshi. Ba lallai ne ku zaɓi ƙimar adireshi waɗanda ke da sauƙin tunawa ba.
· Ƙimar adireshi waɗanda ke bambanta sassa tare da bambancin adireshi-biti ɗaya kawai suna samar da ingantaccen kayan aiki. Ba dole ba ne ka haɗa dukkan adiresoshin tushe zuwa mafi ƙanƙancin iyawar adireshi saboda ƙaddamarwa na iya haifar da ƙarancin ingantaccen kayan aiki.
Zane Platform baya ƙoƙarin daidaita abubuwan žwažwalwar ajiya daban a cikin kewayon žwažwalwar ajiya. Don misaliampDon haka, idan kuna son abubuwan žwažwalwar ajiyar On-Chip da yawa waɗanda za'a iya magance su azaman kewayon ƙwaƙwalwar ajiya guda ɗaya, dole ne ku sanya adiresoshin tushe a sarari.
Platform Designer kuma yana ba da umarnin aiki da kai - Sanya Lambobin Katsewa waɗanda ke haɗa siginar IRQ don samar da ingantaccen sakamako na hardware. Duk da haka, sanya IRQs yadda ya kamata yana buƙatar fahimtar yanayin amsawar tsarin gaba ɗaya. Platform Designer ba zai iya yin hasashen ilimi game da mafi kyawun aikin IRQ ba.
Mafi ƙarancin ƙimar IRQ yana da fifiko mafi girma. A cikin kyakkyawan tsari, Altera yana ba da shawarar cewa ɓangaren mai ƙidayar lokaci ya sami fifiko mafi girma na IRQ, watau, mafi ƙarancin ƙima, don kiyaye daidaiton agogon tsarin.
A wasu lokuta, kuna iya ba da fifiko mafi girma ga abubuwan haɗin lokaci na ainihi (kamar masu sarrafa bidiyo), waɗanda ke buƙatar ƙimar katsewa mafi girma fiye da abubuwan haɗin lokaci.
Bayanai masu alaƙa
Jagorar Mai Amfani na Quartus Prime Pro Edition: Ƙarin bayani game da ƙirƙira Tsari tare da Mai tsara Platform.

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2.2. Haɗa Tsarin Tsarin Tsarin Platform cikin Aikin Quartus Prime Project
Bayan samar da ƙirar tsarin Nios V a cikin Platform Designer, yi ayyuka masu zuwa don haɗa tsarin Nios V a cikin aikin ƙirar Quartus Prime FPGA. Ƙaddamar da tsarin Nios V a cikin aikin Quartus Prime · Haɗa sigina daga tsarin Nios V zuwa wasu sigina a cikin ma'anar FPGA · Sanya wurin fil na zahiri · Ƙuntata ƙirar FPGA
2.2.1. Ƙaddamar da Tsarin Tsarin Nios V a cikin Quartus Prime Project
Platform Designer yana haifar da mahallin ƙirar tsarin tsarin wanda zaku iya ɗauka a cikin Quartus Prime. Yadda kuke hanzarta tsarin tsarin ya dogara da hanyar shigar da ƙira don aikin Quartus Prime gabaɗaya. Domin misaliampto, idan kuna amfani da Verilog HDL don shigarwar ƙira, zazzage tsarin tushen tsarin Verilog. Idan kun fi son yin amfani da hanyar zanen toshe don shigarwar ƙira, sanya alamar tsarin tsarin .bdf file.
2.2.2. Haɗin Sigina da Sanya Wuraren Fil na Jiki
Don haɗa ƙirar Altera FPGA ɗinku zuwa ƙirar matakin allo, yi ayyuka masu zuwa: · Gano babban matakin. file don ƙirar ku da sigina don haɗawa zuwa Altera na waje
FPGA na'urar fil. · Fahimtar nau'ikan fil don haɗawa ta hanyar jagorar mai amfani da ƙirar matakin allo ko
makirci. · Sanya sigina a cikin babban matakin ƙira zuwa tashar jiragen ruwa akan na'urar FPGA ta Altera tare da fil
kayan aikin aiki.
Tsarin Platform Designer ɗin ku na iya zama ƙirar matakin saman. Koyaya, Altera FPGA kuma na iya haɗawa da ƙarin dabaru dangane da bukatunku kuma don haka gabatar da babban matakin al'ada. file. Babban matakin file yana haɗa siginar tsarin ƙirar Nios V zuwa wasu dabaru na ƙira na Altera FPGA.
Bayani mai alaƙa da Quartus Prime Pro Jagorar Mai amfani: Matsalolin ƙira
2.2.3. Ƙuntata Tsarin Altera FPGA
Kyakkyawan ƙirar tsarin Altera FPGA ya haɗa da ƙayyadaddun ƙira don tabbatar da ƙira ya cika ƙulli lokaci da sauran buƙatun ƙuntata hankali. Dole ne ku takura ƙirar Altera FPGA ɗin ku don biyan waɗannan buƙatun a sarari ta amfani da kayan aikin da aka bayar a cikin software na Quartus Prime ko masu samar da EDA na ɓangare na uku. Software na Quartus Prime yana amfani da ƙayyadaddun ƙayyadaddun ƙayyadaddun lokacin tattarawa don samun ingantacciyar sakamakon jeri.

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Bayani mai dangantaka · Quartus Prime Pro Jagorar Mai amfani: Matsalolin ƙira · Abokan hulɗa na EDA na ɓangare na uku · Jagoran Mai Amfani na Quartus Prime Pro: Mai nazarin lokaci
2.3. Ƙirƙirar Tsarin Ƙwaƙwalwar Ƙwaƙwalwar Nios V
Wannan sashe yana bayyana mafi kyawun ayyuka don zaɓar na'urorin ƙwaƙwalwar ajiya a cikin Tsarin Platform Designer tare da na'ura mai sarrafa Nios V da samun ingantaccen aiki. Na'urorin ƙwaƙwalwar ajiya suna taka muhimmiyar rawa wajen haɓaka aikin gaba ɗaya na tsarin da aka saka. Ƙwaƙwalwar tsarin ƙwaƙwalwar ajiya tana adana umarnin shirin da bayanai.
2.3.1. Ƙwaƙwalwar Ƙwaƙwalwa
Babban bambanci a nau'in ƙwaƙwalwar ajiya shine rashin ƙarfi. Ƙwaƙwalwar ƙwaƙwalwar ajiya tana riƙe da abinda ke ciki kawai yayin da kuke ba da wuta ga na'urar ƙwaƙwalwa. Da zaran ka cire wutar, ƙwaƙwalwar ajiyar tana rasa abinda ke ciki.
ExampƘwaƙwalwar ƙwaƙwalwar ajiya mara ƙarfi shine RAM, cache, da rajista. Waɗannan nau'ikan ƙwaƙwalwar ajiya ne masu sauri waɗanda ke haɓaka aikin gudu. Altera yana ba da shawarar ku lodawa da aiwatar da umarnin processor Nios V a cikin RAM kuma ku haɗa Nios V IP core tare da On-Chip Memory IP ko Interface Interface IP don ingantaccen aiki.
Don haɓaka aiki, zaku iya kawar da ƙarin abubuwan daidaitawa na Platform Designer ta hanyar daidaita nau'in mai sarrafa bayanan processor na Nios V ko nisa tare da taya RAM. Don misaliampHar ila yau, za ku iya saita Ƙwaƙwalwar On-Chip II tare da 32-bits AXI-4 interface, wanda ya dace da aikin sarrafa bayanai na Nios V.
Bayani mai Ma'ana · Interfaces na Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar IP · Ƙwaƙwalwar Kan Chip (RAM ko ROM) Altera FPGA IP · On-Chip Memory II (RAM ko ROM) Altera FPGA IP · Nios V Aikace-aikacen Mai aiwatarwa Cika-In- Wuri daga OCRAM a shafi na 54
2.3.1.1. Kan-Chip Memory Kanfigareshan RAM ko ROM
Kuna iya saita Altera FPGA On-Chip Memory IPs azaman RAM ko ROM. RAM yana ba da damar karantawa da rubutawa kuma yana da yanayi mara ƙarfi. Idan kun kasance
booting da Nios V processor daga na'urar On-Chip RAM, dole ne ka tabbata an adana abun cikin taya kuma ba a lalatar da shi ba a yanayin sake saiti yayin lokacin gudu. Idan mai sarrafa Nios V yana tashi daga ROM, duk wani kwaro na software akan na'ura mai sarrafa Nios V ba zai iya yin kuskure a sake rubuta abin da ke cikin ƙwaƙwalwar On-Chip ba. Don haka, rage haɗarin lalata software na boot.
Bayani mai Ma'ana · Ƙwaƙwalwar Kan Chip (RAM ko ROM) Altera FPGA IP · Ƙwaƙwalwar Kan Chip II (RAM ko ROM) Altera FPGA IP · Nios V Aikace-aikacen Mai aiwatar da aiwatar da Wuri daga OCRAM a shafi na 54

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2.3.1.2. Caches
Ana amfani da ƙwaƙwalwar kan-chip don aiwatar da aikin cache saboda ƙarancin jinkirin su. Mai sarrafa Nios V yana amfani da ƙwaƙwalwar kan-chip don koyarwa da caches ɗin bayanai. Iyakantaccen ƙarfin ƙwaƙwalwar ajiya akan guntu yawanci ba batun caches bane saboda yawanci ƙanana ne.
Ana yawan amfani da caches a ƙarƙashin yanayi masu zuwa:
· Ƙwaƙwalwar ajiya ta yau da kullun tana wurin kashe guntu kuma tana da tsawon lokacin samun dama fiye da ƙwaƙwalwar kan-chip.
· Sassan ayyuka masu mahimmanci na lambar software na iya dacewa da cache na koyarwa, inganta aikin tsarin.
· Mahimmanci-mahimmanci, mafi yawan amfani da sashin bayanan na iya dacewa da ma'ajin bayanan, inganta aikin tsarin.
Ba da damar caches a cikin na'ura mai sarrafa Nios V yana haifar da matsayi na ƙwaƙwalwar ajiya, wanda ke rage lokacin samun damar ƙwaƙwalwar ajiya.
2.3.1.2.1. Yankin yanki
Duk wani abin da aka haɗa IP, kamar UART, I2C, da SPI dole ne a adana su. Ana ba da shawarar cache sosai don abubuwan ƙwaƙwalwar waje waɗanda dogon lokacin samun dama ya shafa, yayin da za'a iya keɓance ƙwaƙwalwar guntu na ciki saboda ɗan gajeren lokacin shiga su. Ba dole ba ne ka adana kowane nau'in IP na gefe, kamar UART, I2C, da SPI, sai dai abubuwan tunawa. Wannan yana da mahimmanci saboda abubuwan da suka faru daga na'urori na waje, kamar na'urorin wakilai masu sabunta IPs masu laushi, ba a kama su ta hanyar cache mai sarrafawa ba, bi da bi ba a karɓa ta hanyar sarrafawa ba. Sakamakon haka, waɗannan abubuwan da suka faru na iya wucewa ba a san su ba har sai kun goge cache, wanda zai haifar da halayen da ba a yi niyya ba a cikin tsarin ku. A taƙaice, yankin da aka yi taswirar ƙwaƙwalwar ajiya na IPs na gefe ba za a iya ɓoyewa ba kuma dole ne ya zauna a cikin yankunan na'ura mai sarrafawa.
Don saita yanki na gefe, bi waɗannan matakan:
1. Bude Taswirar Adireshin tsarin a cikin Mai tsara Platform.
2. Kewaya zuwa taswirar adireshin Manajan Umarni da Mai sarrafa bayanai.
3. Gano abubuwan da ke kewaye da abubuwan tunawa a cikin tsarin ku.
Hoto 12. Examptaswirar adireshin

Lura: Kibiyoyi masu shuɗi suna nuna abubuwan tunawa. 4. Rukunin abubuwan da ke kewaye:
a. Ƙwaƙwalwar ajiya azaman cacheable b. Abubuwan da ba a iya ganowa ba

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Tebur 19. Yankin da ba a iya ganowa da kuma wanda ba a iya ganowa

Ƙarƙashin ma'aikata

Taswirar adireshi

Matsayi

Yankin Yanki

Girman

Adireshin tushe

mai amfani_application_mem.s1

0x0 ~ 0x3

Mai iya cache

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Ba za a iya cacheable ba

65536 bytes N/A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Ba za a iya cache wanda ba a iya ganowa

144 bytes (girman min shine 65536 bytes)

0 x54000

sysid_qsys_0.control_bawa

0x54080 ~ 0x54087

Ba a iya ganowa

uart.avalon_jtag_bawa

0x54088 ~ 0x5408f

Ba a iya ganowa

5. Daidaita yankuna na gefe tare da takamaiman girmansu:
· Domin misaliample, idan girman shine 65536 bytes, yayi daidai da 0x10000 bytes. Don haka, adireshin tushe da aka yarda dole ne ya zama mahara na 0x10000.
· CPU.dm_agent yana amfani da adireshin tushe na 0x40000, wanda shine madaidaicin 0x10000. Sakamakon haka, Yankin A, tare da girman 65536 bytes da adireshin tushe na 0x40000, ya cika buƙatun.
Adireshin tushe na tarin yankunan da ba a iya ganowa a 0x54000 ba mahara na 0x10000 ba ne. Dole ne ku sake sanya su zuwa 0x60000 ko wasu mahara na 0x10000. Don haka, Yankin Yankin B, wanda ke da girman 65536 bytes da adireshin tushe na 0x60000, ya cika ka'idodin.

Tebur 20. Yankin da ba za a iya ɓoyewa ba tare da sake sanyawa

Ƙarƙashin ma'aikata

Taswirar adireshi

Matsayi

Yankin Yanki

Girman

Adireshin tushe

mai amfani_application_mem.s1

0x0 ~ 0x3

Mai iya cache

N/A

cpu.dm_agent

0x40000 ~ 0x4

65536 bytes ba a iya ganowa

0 x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Mai iya cache

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Ba za a iya yin cache wanda ba a iya ganowa

144 bytes (girman min shine 65536 bytes)

0 x60000

uart.avalon_jtag_bawa

0x60088 ~ 0x6008f

Ba a iya ganowa

2.3.1.3. Ƙwaƙwalwar Ƙwaƙwalwar Haɗaɗɗiyar Tattara
Ana aiwatar da ƙwaƙwalwar haɗe-haɗe (TCMs) ta amfani da ƙwaƙwalwar kan-chip saboda ƙarancin jinkirin su ya sa su dace da aikin. TCMs sune abubuwan da aka tsara taswira a cikin sararin adireshi na yau da kullun amma suna da keɓancewar keɓancewa ga microprocessor kuma suna da babban aiki, ƙananan kaddarorin ƙwaƙwalwar ajiyar cache. TCM kuma yana ba da hanyar sadarwa ta ƙasa don mai masaukin waje. Mai sarrafawa da mai masaukin baki na waje suna da matakin izini iri ɗaya don sarrafa TCM.

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Lura:

Lokacin da aka haɗa tashar tashar TCM da ke ƙarƙashin maƙiyi na waje, ana iya nuna ta tare da wani adireshin tushe daban fiye da adireshin tushe da aka sanya a cikin core processor. Altera yana ba da shawarar daidaita adiresoshin biyu zuwa ƙima ɗaya.

2.3.1.4. Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Waje (EMIF)
EMIF (External Memory Interface) yana aiki iri ɗaya da SRAM (Static Random Access Memory), amma yana da ƙarfi kuma yana buƙatar wartsakewa lokaci-lokaci don kiyaye abun ciki. Ƙwayoyin ƙwaƙwalwar ajiya masu ƙarfi a cikin EMIF sun fi ƙanƙanta da ƙananan ƙwayoyin ƙwaƙwalwar ajiya a cikin SRAM, wanda ke haifar da ƙarfin aiki da ƙananan na'urorin ƙwaƙwalwar ajiya.
Baya ga buƙatun wartsakewa, EMIF tana da ƙayyadaddun buƙatun mu'amala waɗanda galibi ke buƙatar na'urar sarrafawa ta musamman. Ba kamar SRAM ba, wanda ke da kafaffen layin adireshi, EMIF tana tsara sararin ƙwaƙwalwar ajiyarta zuwa bankuna, layuka, da ginshiƙai. Canjawa tsakanin bankuna da layuka yana gabatar da wasu sama-sama, don haka dole ne ku yi oda a hankali don amfani da ƙwaƙwalwar ajiya don amfani da EMIF da kyau. EMIF kuma tana ninka adiresoshin jere da shafi akan layin adireshi iri ɗaya, yana rage adadin fil ɗin da ake buƙata don girman EMIF.
Siffofin EMIF mafi girma, kamar DDR, DDR2, DDR3, DDR4, da DDR5, suna ba da ƙaƙƙarfan buƙatun amincin sigina waɗanda masu zanen PCB su yi la'akari da su.
Na'urorin EMIF suna matsayi a cikin mafi tsadar farashi da nau'ikan RAM masu ƙarfi da ake da su, wanda ya sa su zama sanannen zaɓi. Babban abin da ke tattare da keɓancewa na EMIF shine EMIF IP, wanda ke gudanar da ayyuka masu alaƙa da magance yawan haɓakawa, shakatawa, da sauyawa tsakanin layuka da bankuna. Wannan zane yana ba da damar sauran tsarin don samun damar EMIF ba tare da buƙatar fahimtar gine-ginen ciki ba.

Bayanin Mahimman Bayanai na Wuta na Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar IP

2.3.1.4.1. Adireshin Span Extender IP
Adireshin Span Extender Altera FPGA IP yana ba da damar mu'amalar mai amfani da taswirar ƙwaƙwalwar ajiya don samun damar babban taswirar adireshi fiye da faɗin siginar adireshin su ya ƙyale. Adireshin Span Extender IP yana raba sararin da za a iya magana da shi zuwa manyan windows daban-daban domin mai watsa shiri ya iya samun dama ga sashin da ya dace na ƙwaƙwalwar ajiya ta taga.
Adireshin Span Extender baya iyakance mai watsa shiri da nisa na wakili zuwa tsarin 32-bit da 64bit. Kuna iya amfani da Address Span Extender tare da windows 1-64 bit address.

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Hoto 13. Adireshin Span Extender Altera FPGA IP
Adireshin Kalma na Wakili

Adireshin Span Extender

Teburin Taswira
Control Port A

…

Rijistar Sarrafa 0 Rijistar Sarrafa Z-1

Fadada Adireshin Mai watsa shiri H

Bayanai masu alaƙa
Jagorar Mai Amfani na Quartus® Prime Pro Edition: Mai Zane Platform Koma zuwa taken Adireshin Span Extender Intel® FPGA IP don ƙarin bayani.

2.3.1.4.2. Amfani da Address Span Extender IP tare da Nios V Processor
Mai sarrafa Nios V mai 32-bit na iya yin magana har zuwa 4 GB na tsawon adireshi. Idan EMIF ya ƙunshi fiye da 4GB na ƙwaƙwalwar ajiya, ya zarce iyakar adadin adireshi mai goyan baya, yana mai da tsarin Platform Designer a matsayin kuskure. Ana buƙatar Address Span Extender IP don warware wannan batu ta hanyar rarraba sararin adireshin EMIF guda ɗaya zuwa ƙananan windows masu yawa.
Altera ya ba da shawarar cewa kayi la'akari da sigogi masu zuwa.

Tebura 21. Adireshin Tsaftace Ma'auni

Siga

Nagari Saituna

Faɗin Hanyar Data
Fadada Babban Faɗin Adireshin Byte

Zaɓi 32-bits, wanda ke da alaƙa da processor 32-bit. Ya dogara da girman ƙwaƙwalwar EMIF.

Adreshin Kalma Bawa Fasa Fasa Ƙididdigar Nisa

Zaɓi 2 GB ko ƙasa da haka. Ragowar tazarar adireshin processor na Nios V an tanada don sauran saƙon IP masu taushi.
Fara da 1 kuma a hankali ƙara wannan ƙimar don inganta aiki.

Adadin ƙananan windows

Zaɓi ƙaramin taga 1 idan kuna haɗa EMIF zuwa mai sarrafa Nios V azaman umarni da ƙwaƙwalwar ajiyar bayanai, ko duka biyun. Canjawa tsakanin manyan windows yayin da Nios V processor ke aiwatarwa daga EMIF yana da haɗari.

Kunna tashar Ikon Bayi

Kashe tashar sarrafa bawa idan kana haɗa EMIF zuwa mai sarrafa Nios V azaman umarni da/ko ƙwaƙwalwar ajiya. Damuwa iri ɗaya kamar Yawan ƙananan windows.

Matsakaicin Karatun da ake jira

Fara da 1 kuma a hankali ƙara wannan ƙimar don inganta aiki.

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Hoto 14. Haɗa Umarni da Mai sarrafa bayanai zuwa Address Span Extender

Hoto 15. Taswirar adireshin

Yi la'akari da cewa Address Span Extender na iya samun dama ga sararin ƙwaƙwalwar ajiyar 8GB na EMIF. Koyaya, ta hanyar Address Span Extender, mai sarrafa Nios V na iya samun damar sararin ƙwaƙwalwar ajiyar 1GB na farko kawai na EMIF.

Hoto 16. Zane Mai Sauƙaƙe

Tsarin Mawallafin Dandali

Saura 3 GB

Nios V Processor address

span ne don haɗawa

NNioios sVV PProrocecsesosor r
M

IPs masu laushi a cikin wannan tsarin.
1 GB taga

Takaitaccen adireshin

Extender

Kawai 1 GB na farko

na EMIF ƙwaƙwalwar ajiya an haɗa shi zuwa Nios V

EMIF

mai sarrafawa.

8 GB
S

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2.3.1.4.3. Ƙayyadaddun Adireshin Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙaddamarwa 1. Ƙayyata Adireshin Span Extender (EMIF) a matsayin reset vector. A madadin, zaku iya sanya Nios V processor reset vector zuwa wasu abubuwan tunawa, kamar OCRAM ko na'urorin filasha.
Hoto 17. Zabuka da yawa azaman Sake saitin Vector
Koyaya, Editan Kunshin Tallafi na Board (BSP) ba zai iya yin rijistar Adireshin Tsare-tsare (EMIF) ta atomatik azaman ingantaccen ƙwaƙwalwar ajiya ba. Dangane da zaɓin da kuka yi, kuna ganin yanayi daban-daban guda biyu kamar yadda aka nuna a cikin waɗannan alkaluma. Hoto 18. Kuskuren BSP lokacin da aka Bayyana Adreshin Tsare Tsare (EMIF) azaman Sake saitin Vector

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Hoto 19. Bacewar EMIF lokacin Fayyace Wasu Memories azaman Sake saitin Vector

2. Dole ne ku ƙara Address Span Extender (EMIF) da hannu ta amfani da Ƙara Ƙwaƙwalwar Na'ura, Ƙara Linker Memory Region, da Ƙara Taswirar Sashe na Linker a cikin BSP Linker Script tab.
3. Bi waɗannan matakan:
a. Ƙayyade tazarar adireshi na Address Span Extender ta amfani da taswirar ƙwaƙwalwa (Example a cikin adadi mai zuwa yana amfani da kewayon Address Span Extender daga 0x0 zuwa 0x3fff_ffff).
Hoto 20. Taswirar ƙwaƙwalwa

b. Danna Ƙara Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙirƙiri na Ƙirƙiri na Ƙirƙiri na Ƙirƙiri na Ƙirƙiri na Ƙirƙiri na Ƙirƙirar Ƙirar Ƙirƙira na Ƙirar Ƙirƙirar Ƙirƙira na Ƙirar Ƙirar Ƙirƙira na Ƙirar Ƙirƙirar Ƙirar ku: i. Sunan na'ura: emif_ddr4. Lura: Tabbatar kun kwafi suna ɗaya daga Taswirar Ƙwaƙwalwar ajiya. ii. Adireshin tushe: 0x0 iii. Girman: 0x40000000
c. Danna Ƙara don ƙara sabon yankin ƙwaƙwalwar mahaɗi:

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Table 22. Ƙara Linker Memory Region

Matakai

Sake saita Vector

emif_ddr4

Sauran abubuwan tunawa

Ƙara sabon Yankin Ƙwaƙwalwar Mai haɗawa da ake kira sake saiti. Ƙara sabon Yankin Ƙwaƙwalwar Ƙwaƙwalwa na Linker don

Sunan yanki: sake saiti

emif_ddr4.

Girman Yanki: 0x20

Sunan yanki: emif_ddr4

Na'urar ƙwaƙwalwar ajiya: emif_ddr4

Girman Yanki: 0x40000000

· Ƙwaƙwalwar ajiya: 0x0

Na'urar ƙwaƙwalwar ajiya: emif_ddr4

· Ƙwaƙwalwar ajiya: 0x0

Ƙara sabon Yankin Ƙwaƙwalwar Ƙwaƙwalwa na Linker don

saura emif_ddr4.

Sunan yanki: emif_ddr4

Girman Yanki: 0x3ffffffe0

Na'urar ƙwaƙwalwar ajiya: emif_ddr4

· Ƙwaƙwalwar ajiya: 0x20

Hoto 21. Yanki na Linker lokacin da ake ayyana Adreshin Span Extender (EMIF) azaman Sake saitin Vector

Hoto 22. Yankin Linker lokacin Bayyana Wasu Memories azaman Sake saitin Vector
d. Da zarar an ƙara emif_ddr4 zuwa BSP, zaku iya zaɓar shi don kowane Sashe na Linker.
Hoto 23. Ƙara Address Span Extender (EMIF) Nasara

e. Yi watsi da gargaɗin game da na'urar ƙwaƙwalwar ajiya emif_ddr4 ba a iya gani a ƙirar SOPC.
f. Ci gaba don Samar da BSP.
Bayani mai alaƙa Gabatarwa zuwa Hanyoyin Booting na Nios V a shafi na 51

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2.3.2. Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa
Ƙwaƙwalwar ajiyar da ba ta da ƙarfi tana riƙe abin da ke ciki lokacin da wutar lantarki ta kashe, yana mai da shi kyakkyawan zaɓi don adana bayanan da tsarin dole ne ya dawo da su bayan zagayowar wutar lantarki. Ƙwaƙwalwar ajiyar da ba ta da ƙarfi yawanci tana adana lambar boot-processor, saitunan aikace-aikacen dagewa, da bayanan daidaitawar Altera FPGA. Ko da yake ba maras canzawa memory yana da advantage na riƙe da bayanan sa lokacin da kuka cire wutar lantarki, yana da hankali sosai idan aka kwatanta da ƙwaƙwalwar ƙwaƙwalwa, kuma sau da yawa yana da ƙarin hadaddun hanyoyin rubutu da gogewa. Ƙwaƙwalwar ajiyar da ba ta da ƙarfi kuma yawanci ana ba da garantin gogewa ne kawai adadin da aka bayar, bayan haka yana iya gazawa.
ExampƘwaƙwalwar ƙwaƙwalwar da ba ta da ƙarfi ta haɗa da kowane nau'in walƙiya, EPROM, da EEPROM. Altera yana ba ku shawarar adana raƙuman raƙuman ruwa na Altera FPGA da hotunan shirin Nios V a cikin ƙwaƙwalwar ajiyar da ba ta da ƙarfi, kuma ku yi amfani da serial flash azaman na'urar taya don masu sarrafa Nios V.
Bayanai masu alaƙa
Gabaɗaya Serial Flash Interface Altera FPGA IP Jagorar mai amfani
Abokin ciniki na Akwatin Wasiƙa Altera FPGA IP Jagorar Mai Amfani · MAX® 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwar Filasha: On-Chip Flash Altera FPGA IP Core
2.4. Agogo da Sake saitin Mafi kyawun Ayyuka
Fahimtar yadda agogon processor na Nios V da yankin sake saiti ke hulɗa tare da kowane yanki da yake haɗawa da shi yana da mahimmanci. Tsarin Nios V mai sauƙi yana farawa da yanki na agogo ɗaya, kuma yana iya yin rikitarwa tare da tsarin yanki mai yawan agogo lokacin da yankin agogo mai sauri ya yi karo da yankin agogon jinkirin. Kuna buƙatar yin bayanin kula kuma ku fahimci yadda waɗannan yankuna daban-daban ke fita daga sake saiti kuma tabbatar da cewa babu wata matsala ta dabara.
Don mafi kyawun aiki, Altera yana ba da shawarar sanya na'ura mai sarrafa Nios V da ƙwaƙwalwar taya a cikin yankin agogo ɗaya. Kar a saki na'ura mai sarrafa Nios V daga sake saiti a cikin yankin agogo mai sauri lokacin da ya tashi daga ƙwaƙwalwar ajiyar da ke zaune a cikin yankin agogon jinkirin, wanda zai iya haifar da kuskuren ɗauko umarni. Kuna iya buƙatar wasu jeri na hannu fiye da abin da Platform Designer ke bayarwa ta tsohuwa, da kuma tsara fitar da sake saitin topology daidai da yanayin amfanin ku. Idan kuna son sake saita tsarin ku bayan ya fito yana aiki na ɗan lokaci, yi amfani da la'akari iri ɗaya zuwa tsarin sake saitin tsarin da buƙatun sake saitin farawa.
2.4.1. Tsarin JTAG Agogo
Ƙayyadaddun ƙayyadaddun ƙayyadaddun agogo a cikin kowane tsarin aikin Nios V shine muhimmin la'akari da ƙirƙira tsarin kuma ana buƙata don daidaito da ƙayyadaddun halaye. Mai Analyzer Prime Prime Time Analyzer yana aiwatar da bincike akan lokaci don tabbatar da aikin lokaci na duk dabaru a cikin ƙirar ku ta amfani da ƙayyadaddun ƙayyadaddun masana'antu, bincike, da hanyoyin bayar da rahoto.
Example 1. Basic 100 MHz Clock tare da 50/50 Duty Cycle da 16 MHz JTAG Agogo
************************************************************* * Createirƙiri agogon 100MHz #************************************ ƙirƙirar agogo -name {clk} -lokaci 10 [samun_tashar jiragen ruwa {clk}] #************************ Create 16MHz JTAG Agogo #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Bayani mai dangantaka Quartus Prime Time Analyzer Kitbook
2.4.2. Sake saita Interface Interface
Nios V processor ya haɗa da wurin buƙatar sake saitin zaɓi na zaɓi. Wurin sake saitin buƙatun ya ƙunshi reset_req da siginonin reset_req_ack.
Don kunna buƙatun sake saitin a Platform Designer: 1. Kaddamar da Nios V Processor IP Parameter Edita. 2. A kan Saitin Buƙatun Sake saitin Amfani, kunna Interface Buƙatar Sake saitin
zaɓi.
Hoto 24. Kunna Neman Sake saitin Processor Nios V
Siginar reset_req yana aiki kamar katsewa. Lokacin da kuka tabbatar da reset_req, kuna buƙatar sake saitawa zuwa ainihin. Matsakaicin yana jiran duk wani fitaccen ma'amalar bas don kammala aikinsa. Don misaliampto, idan akwai ma'amalar samun damar ƙwaƙwalwar ajiya mai jiran aiki, ainihin yana jiran cikakkiyar amsa. Hakazalika, jigon yana karɓar duk wani martanin umarni amma baya bayar da buƙatar umarni bayan karɓar siginar reset_req.
Aiki na sake saiti ya ƙunshi gudana mai zuwa: 1. Kammala duk ayyukan da ke jiran aiki 2. Flush bututun ciki 3. Saita Counter ɗin Shirin zuwa na'urar sake saiti 4. Sake saita ainihin gabaɗayan aikin sake saiti yana ɗaukar ƴan zagayowar agogo. Dole ne a ci gaba da tabbatar da reset_req har sai an tabbatar da reset_req_ack wanda ke nuna ainihin aikin sake saitin ya yi nasara. Rashin yin haka yana haifar da asalin jihar da ba ta da iyaka.

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2.4.2.1. Abubuwan Amfani Na Musamman
Kuna iya tabbatar da siginar reset_req daga kunnawa don hana Nios V processor core fara aiwatar da aiwatar da shirin daga sake saitin vector har sai sauran rundunonin FPGA a cikin tsarin sun fara ƙwaƙwalwar ƙwaƙwalwar na'ura ta Nios V. A wannan yanayin, tsarin tsarin gabaɗayan zai iya samun ingantaccen sake saitin kayan masarufi. Ana gudanar da na'ura mai sarrafa Nios V har abada a cikin yanayin buƙatar sake saiti har sai sauran rundunonin FPGA sun fara ƙaddamar da ƙwaƙwalwar taya na processor.
A cikin tsarin da dole ne ka sake saita Nios V processor core ba tare da rushe sauran tsarin ba, za ka iya tabbatar da siginar reset_req don dakatar da aiki na yanzu da tsabta kuma sake kunna processor daga reset vector da zarar tsarin ya saki siginar reset_req_ack.
· Mai masaukin baki na waje zai iya amfani da tsarin sake saitin buƙatun don sauƙaƙe aiwatar da ayyuka masu zuwa:
- Dakatar da shirin Nios V na yanzu.
- Load da wani sabon shiri a cikin Nios V processor boot memory.
- Bada izinin sarrafawa don fara aiwatar da sabon shirin.
Altera yana ba ku shawarar aiwatar da tsarin ƙarewar lokaci don saka idanu yanayin siginar reset_req_ack. Idan Nios V processor core ya faɗi cikin yanayin jira mara iyaka kuma ya tsaya saboda wani dalili da ba a sani ba, reset_req_ack ba zai iya faɗi ba har abada. Tsarin lokacin ƙarewa yana ba ku damar:
· Ƙayyade lokacin ƙarewar dawowa kuma aiwatar da dawo da tsarin tare da sake saitin matakin tsarin.
Yi sake saitin matakin hardware.
2.4.3. Sake saita Sakin IP
Na'urori masu tushen Altera SDM suna amfani da layi daya, tsarin gine-gine na yanki wanda ke rarraba ainihin masana'anta a cikin sassa da yawa. Altera yana ba ku shawarar amfani da Sake saitin Sakin Altera FPGA IP azaman ɗaya daga cikin abubuwan da aka fara farawa zuwa da'irar sake saiti. Na'urorin Intel® SDM sun haɗa da Stratix® 10, da na'urorin AgilexTM. Wannan buƙatu ba ta shafi tushen na'urorin toshewar sarrafawa.
Bayanai masu alaƙa
AN 891: Amfani da Sake saitin Sakin Altera FPGA IP
2.5. Sanya Wakilin Default
Platform Designer yana ba ku damar ƙididdige tsohuwar wakili wanda ke aiki azaman wakili na tsoho na amsa kuskure. Tsohuwar wakili da kuka zaɓa yana ba da sabis na amsa kuskure ga runduna waɗanda ba su canza hanyar shiga taswirar adireshin ba.
Abubuwan da ke biyowa suna haifar da taron da ba a canza lambar ba:
· Rashin tsaro na mu'amalar bas
· Samun damar ma'amala zuwa yankin ƙwaƙwalwar da ba a bayyana ba
· Bangaren taron da sauransu.

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Ya kamata a sanya wakili na asali don gudanar da irin waɗannan abubuwan, inda aka mayar da ma'amalar da ba a bayyana ba zuwa ga tsohuwar wakili kuma daga baya ta amsa ga mai sarrafa Nios V tare da amsa kuskure.
Bayanai masu alaƙa
Jagoran Mai Amfani na Quartus Prime Pro Edition: Mai tsara dandamali. Zayyana Default Agent
Jagoran Mai Amfani na Quartus Prime Pro Edition: Mai tsara dandamali. Amsa Kuskure Bawa Altera FPGA IP
Github - Ƙarin Abubuwan Sake saitin don Qsys

2.6. Sanya Wakilin UART don Bugawa
Buga yana da amfani don gyara aikace-aikacen software, da kuma lura da yanayin tsarin ku. Altera yana ba da shawarar buga mahimman bayanai kamar saƙon farawa, saƙon kuskure, da ci gaban aiwatar da aikace-aikacen software.
Guji yin amfani da aikin laburare na printf () a ƙarƙashin yanayi masu zuwa: · Laburaren printf() yana sa aikace-aikacen ya tsaya tsayin daka idan babu mai watsa shiri da yake karantawa.
Wannan ya shafi JTAG UART kawai. Laburaren printf() yana cinye ɗimbin ƙwaƙwalwar ajiyar shirin.

2.6.1. Hana Shafukan da JTAG UART

Tebur 23. Bambance-bambance tsakanin UART na Gargajiya da JTAG UART

UART Nau'in Gargajiya UART

Bayani
Yana watsa bayanan serial ko da kuwa mai watsa shiri na waje yana sauraro. Idan babu mai watsa shiri ya karanta bayanan serial, bayanan sun ɓace.

JTAG UART

Yana rubuta bayanan da aka watsa zuwa mabuɗin fitarwa kuma ya dogara ga mai watsa shiri na waje don karantawa daga buffer don komai.

A JTAG Direban UART yana jira lokacin da buffer ɗin fitarwa ya cika. A JTAG Direban UART yana jira mai masaukin waje don karantawa daga ma'ajin fitarwa kafin rubuta ƙarin bayanan watsawa. Wannan tsari yana hana asarar bayanan watsawa.
Koyaya, lokacin da ba a buƙatar gyara tsarin ba, kamar lokacin samarwa, ana tura tsarin da aka haɗa ba tare da PC mai watsa shiri da aka haɗa da J ba.TAG UART. Idan tsarin ya zaɓi JTAG UART a matsayin wakili na UART, zai iya haifar da tsarin dakatarwa saboda babu wani mai watsa shiri na waje da aka haɗa.
Don hana tsayawa ta hanyar JTAG UART, yi amfani da waɗannan zaɓuɓɓuka masu zuwa:

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Table 24. Rigakafin Tsayawa ta JTAG UART

Zabuka
Babu UART dubawa da direba ba
Yi amfani da sauran UART dubawa da direba
Tsare JTAG UART dubawa (ba tare da direba ba)

Yayin Haɓaka Hardware (a cikin Mai tsara Platform)

Yayin Ci gaban Software (a cikin Editan Kunshin Tallafi)

Cire JTAG UART daga tsarin

Sanya hal.stdin, hal.stdout da hal.stderr azaman Babu.

Sauya JTAG UART tare da sauran taushi Sanya hal.stdin, hal.stdout da hal.stderr

UART IP

tare da sauran taushi UART IP.

Tsare JTAG UART a cikin tsarin

· Sanya hal.stdin, hal.stdout da hal.stderr a matsayin Babu kowa a cikin Editan Kunshin Tallafi na Hukumar.
A kashe JTAG Direban UART a cikin BSP Driver tab.

2.7. JTAG Sigina
Nios V processor debug module yana amfani da JTAG dubawa don software na ELF zazzagewa da gyara software. Lokacin da kuka gyara ƙirar ku tare da JTAG Interface, da JTAG Ana aiwatar da siginar TCK, TMS, TDI, da TDO azaman ɓangaren ƙira. Bayanin JTAG Matsakaicin sigina a cikin kowane tsarin sarrafa Nios V shine muhimmin la'akari da ƙirar tsarin kuma ana buƙata don daidaitawa da ƙayyadaddun halaye.
Altera yana ba da shawarar cewa kowane mitar agogon tsarin ƙira ya zama aƙalla sau huɗu na JTAG Mitar agogo don tabbatar da cewa kayan aikin on-chip (OCI) core yana aiki da kyau.
Bayani mai alaƙa · Quartus® Firayim Mai Nazari na Lokaci Littafin dafa abinci: JTAG Sigina
Don ƙarin bayani game da JTAG jagororin ƙayyadaddun lokaci. KDB: Me yasa niosv-zazzagewa ta gaza tare da na'urar sarrafa Nios® V/m mara bututu a
JTAG mitar 24MHz ko 16Mhz?
2.8. Haɓaka Ayyukan Tsare-Tsaren Mawallafin Platform
Platform Designer yana ba da kayan aiki don haɓaka aikin haɗin gwiwar tsarin don ƙirar Altera FPGA.

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Hoto 25. Inganta Examples

The example da aka nuna a cikin adadi yana nuna matakai masu zuwa:
1. Yana ƙara gadar Pipeline don rage mahimman hanyoyi ta sanya shi: a. Tsakanin Manajan Umarni da wakilansa b. Tsakanin Data Manager da wakilansa
2. Aiwatar da True Dual Port On-Chip RAM, tare da kowane tashar jiragen ruwa da aka keɓe ga Manajan Umarni da Mai sarrafa bayanai bi da bi.

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Koma zuwa hanyoyin haɗin yanar gizo masu alaƙa da ke ƙasa, waɗanda ke ba da dabarun yin amfani da kayan aikin da ake da su da cinikin kowane aiwatarwa.
Bayani mai dangantaka · Quartus® Prime Pro Edition Jagorar mai amfani: Mai tsara dandamali
Koma zuwa taken Inganta Ayyukan Tsare-tsare Tsare-tsare don ƙarin bayani. Jagoran Mai Amfani na Quartus® Prime Standard Edition: Mai Zane Platform Koma kan batun Inganta Ayyukan Tsarin Tsarin Platform don ƙarin bayani.

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3. Nios V Processor Software System Design
Wannan babin yana bayyana kwararar haɓaka software na Nios V da kayan aikin software waɗanda zaku iya amfani da su wajen haɓaka tsarin ƙirar ku. Abubuwan da ke ciki suna aiki azaman ƙarewaview kafin haɓaka tsarin software na Nios V.
Hoto 26. Tsarin Tsarin Software
Fara

Ƙirƙirar BSP a cikin Mawallafin Platform Amfani da Editan BSP

Ƙirƙirar BSP Amfani da Nios V Command Shell
Ƙirƙirar Aikace-aikacen CMake Gina File Amfani da Nios V Command Shell

Lura:

Shigo da BSP da Aikace-aikacen CMake Gina File
Gina Nios V Processor Application ta amfani da
RiscFree IDE don Intel FPGA

Gina aikace-aikacen Nios V Processor ta amfani da kowane
Editan lambar tushen umarni, CMake, da Make
umarni
Ƙarshe

Altera yana ba da shawarar cewa kayi amfani da kayan haɓakawa na Altera FPGA ko allon ƙirar al'ada don haɓaka software da gyara kuskure. Yawancin abubuwan gefe da fasalulluka na tsarin suna samuwa ne kawai lokacin da software ɗinku ke gudana akan ainihin allo.

© Altera Corporation. Altera, tambarin Altera, tambarin `a', da sauran alamomin Altera alamun kasuwanci ne na Kamfanin Altera. Altera yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Altera ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka bayyana a nan sai dai kamar yadda Altera ya yarda da shi a rubuce. Ana shawarci abokan cinikin Altera su sami sabon sigar ƙayyadaddun na'urar kafin dogaro da kowane bayanan da aka buga kuma kafin yin oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

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3.1. Nios V Processor Rarraba Haɓaka Software
3.1.1. Aikin Kunshin Tallafi na Hukumar
Aikin Kunshin Tallafi na Board na Nios V (BSP) babban ɗakin karatu ne na musamman wanda ke ɗauke da takamaiman lambar tallafi na tsarin. BSP yana ba da yanayin lokacin aiki na software wanda aka keɓance don mai sarrafawa ɗaya a cikin tsarin kayan aikin Nios V.
Software na Quartus Prime yana ba da Editan Kunshin Tallafi na Nios V da kayan aikin niosv-bsp don gyara saitunan da ke sarrafa halayen BSP.
BSP yana ƙunshe da abubuwa masu zuwa: · Hardware abstraction Layer · Direban na'ura · Fakitin software na zaɓi · Tsarin aiki na ainihin lokaci na zaɓi
3.1.2. Aikace-aikace Project
Aikin aikace-aikacen Nios VC/C++ yana da fa'idodi masu zuwa: · Ya ƙunshi tarin lambar tushe da CMakeLists.txt.
- CMakeLists.txt yana tattara lambar tushe kuma yana haɗa shi tare da BSP da ɗaya ko fiye da ɗakunan karatu na zaɓi, don ƙirƙirar .elf ɗaya. file
· Daya daga cikin tushen files ya ƙunshi babban aiki (). · Ya haɗa da lambar da ke kiran ayyuka a ɗakunan karatu da BSPs.
Altera yana ba da kayan aikin niosv-app a cikin kayan aikin amfani da software na Quartus Prime don ƙirƙirar Aikace-aikacen CMakeLists.txt, da RiscFree IDE don Altera FPGAs don canza lambar tushe a cikin yanayin tushen Eclipse.
3.2. Altera FPGA Abubuwan Haɓakawa
Mai sarrafa Nios V yana goyan bayan waɗannan kayan aikin haɓaka software: · Interface mai amfani da zane (GUI) - Kayan aikin haɓaka zane waɗanda ke samuwa a ciki
duka Windows* da Linux* Operating Systems (OS). - Editan Kunshin Tallafi na Hukumar Nios V (Editan Nios V BSP) - Ashling RiscFree IDE don Altera FPGAs · Kayan Aikin Layi (CLI) - Kayan aikin haɓakawa waɗanda aka fara daga Nios V Command Shell. Kowane kayan aiki yana ba da takaddun kansa a cikin nau'in taimako da ake samu daga layin umarni. Bude Nios V Command Shell kuma buga umarni mai zuwa: -taimako ga view menu na Taimako. - Nios V Utilities Tools - File Kayayyakin Juya Tsarin Tsara - Sauran Kayan Aiki

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Table 25. GUI Tools da Command-line Tools Summary

Aiki

GUI Tool

Kayan aiki-layin umarni

Ƙirƙirar BSP

Nios V BSP Editan

A cikin software na Quartus Prime Pro Edition: niosv-bsp -c -s=<.qsys file> -t= [ZABI] saituna.bsp
A cikin software na Quartus Prime Standard Edition: niosv-bsp -c -s=<.sopcinfo file> -t= [ZABI] saituna.bsp

Samar da BSP ta amfani da data kasance .bsp file
Ana sabunta BSP

Nios V BSP Editan Nios V BSP Editan

niosv-bsp -g [ZABI] saituna.bsp niosv-bsp -u [ZABI] saituna.bsp

Binciken BSP

Nios V BSP Editan

niosv-bsp -q -E= [ZABI] saituna.bsp

Ƙirƙirar aikace-aikace

–

niosv-app -a= -b= -s= files directory> [OPTIONS]

Ƙirƙirar ɗakin karatu mai amfani

–

niosv-app -l= -s= files directory> -p= [ZABI]

Gyara aikace-aikace Gyara ɗakin karatu na mai amfani Gina aikace-aikace

RiscFree IDE don Altera FPGAs
RiscFree IDE don Altera FPGAs
RiscFree IDE don Altera FPGAs

Duk wani editan tushen layin umarni
Duk wani editan tushen layin umarni
· yi · cika

Gina ɗakin karatu mai amfani

RiscFree IDE don Altera FPGAs

· yi · cika

Zazzage aikace-aikacen ELF
Maida .elf file

RiscFree IDE don Altera FPGAs
–

niosv-zazzagewa
· elf2flash · elf2hex

Bayanai masu alaƙa
Ashling RiscFree Integrated Development Environment (IDE) don Altera FPGAs Jagorar Mai Amfani

3.2.1. Editan Kunshin Tallafi na Nios V Processor Board
Kuna iya amfani da Editan BSP na Nios V don aiwatar da ayyuka masu zuwa: · Ƙirƙiri ko gyaggyara aikin Nios V processor BSP · Gyara saitunan, yankuna masu haɗawa, da taswirar sashe · Zaɓi fakitin software da direbobin na'ura.
Ƙwararrun Editan BSP sun haɗa da damar abubuwan amfani na niosv-bsp. Duk wani aikin da aka ƙirƙira a cikin Editan BSP kuma ana iya ƙirƙira shi ta amfani da kayan aikin layin umarni.

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Lura:

Don software na Quartus Prime Standard Edition, koma zuwa AN 980: Nios V Processor Quartus Prime Software Support don matakan kiran GUI Editan BSP.

Don ƙaddamar da Editan BSP, bi waɗannan matakan: 1. Buɗe Platform Designer, kuma kewaya zuwa File menu.
a. Don buɗe saitin BSP na yanzu file, danna Buɗe… b. Don ƙirƙirar sabon BSP, danna Sabon BSP… 2. Zaɓi shafin Editan BSP kuma samar da bayanan da suka dace.

Hoto 27. Kaddamar da Editan BSP

Bayani mai alaƙa AN 980: Nios V Processor Quartus Prime Support Software
3.2.2. RiscFree IDE don Altera FPGAs
RiscFree IDE don Altera FPGAs IDE ne na tushen Eclipse don mai sarrafa Nios V. Altera ya ba da shawarar cewa ku haɓaka software na Nios V a cikin wannan IDE saboda dalilai masu zuwa: · An haɓaka fasalin kuma an tabbatar da su dacewa da Nios V.
processor gina kwarara. · An sanye shi da duk kayan aiki masu mahimmanci da kayan aikin tallafi waɗanda ke ba ku damar
don fara ci gaban Nios V cikin sauƙi.
Bayanai masu dangantaka Ashling RiscFree Integrated Development Environment (IDE) don Altera FPGAs Jagorar Mai Amfani
3.2.3. Nios V Utilities Tools
Kuna iya ƙirƙira, gyara, da gina shirye-shiryen Nios V tare da umarni da aka buga a layin umarni ko saka a cikin rubutun. Kayan aikin layin umarni na Nios V da aka bayyana a wannan sashe suna cikin /niosv/bin directory.

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Table 26. Nios V Utilities Tools

Kayan aikin Umurnin-Layin

Takaitawa

niosv-app niosv-bsp niosv-zazzage rahoton niosv-shell niosv-tari-rahoton

Don ƙirƙira da daidaita aikin aikace-aikacen.
Don ƙirƙira ko sabunta saitunan BSP file kuma ƙirƙirar BSP files. Don saukar da ELF file zuwa Nios® V processor.
Don buɗe Nios V Command Shell. Don sanar da ku sararin ƙwaƙwalwar ajiyar hagu da ke akwai ga aikace-aikacenku .elf don amfani ko tari.

3.2.4. File Tsarin Kayan Aikin Juyawa

File Canjin tsarin wani lokaci yakan zama dole lokacin aika bayanai daga wannan mai amfani zuwa wani. The file kayan aikin canza tsarin suna cikin
directory shigarwa software>/niosv/bin directory.

Tebur 27. File Tsarin Kayan Aikin Juyawa

Kayan aikin Umurnin-Layin elf2flash elf2hex

Takaitawa Don fassara .elf file zuwa tsarin .srec don shirye-shiryen ƙwaƙwalwar ajiyar filasha. Don fassara .elf file zuwa tsarin hex don ƙaddamar da ƙwaƙwalwar ajiya.

3.2.5. Sauran Kayan Aiki

Kuna iya buƙatar kayan aikin layin umarni masu zuwa lokacin gina tsarin tushen Nios V. Waɗannan kayan aikin layin umarni ko dai Intel ne ke bayarwa /quartus/bin ko aka samo daga
kayan aikin buɗaɗɗen tushe.

Tebur 28. Sauran Kayan Aikin-Layin Umarni

Kayan aikin Umurnin-Layin

Nau'in

Takaitawa

juart-terminal

Intel-sabar

Don saka idanu stdout da stderr, da kuma samar da shigarwa zuwa na'urar sarrafa Nios® V
subsystem ta hanyar stdin. Wannan kayan aikin yana aiki ne kawai ga JTAG UART IP lokacin da aka haɗa ta zuwa mai sarrafa Nios® V.

budeocd

An samar da Intel Don aiwatar da OpenOCD.

budeocd-cfg-gen

An samar da Intel · Don samar da daidaitawar OpenOCD file. · Nuna JTAG index na'urar sarkar.

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4. Nios V Kanfigareshan Processor da Booting Solutions
Kuna iya saita mai sarrafa Nios V don taya da aiwatar da software daga wurare daban-daban na ƙwaƙwalwar ajiya. Ƙwaƙwalwar taya shine filasha Quad Serial Peripheral Interface (QSPI), Ƙwaƙwalwar Kan Chip (OCRAM), ko Ƙwaƙwalwar Haɗe-haɗe (TCM).
Bayani mai alaƙa · Yanayin Ƙarfafa Ƙarfafawa a shafi na 193 · Ƙarfafa Ƙarfafawa
Don ƙarin bayani game da abubuwan kunna wutar lantarki.
4.1. Gabatarwa
Nios V processor yana goyan bayan nau'ikan tafiyar matakai guda biyu: · Execute-in-Place (XIP) ta amfani da aikin alt_load() · Shirin da aka kwafi zuwa RAM ta amfani da na'urar kwafi. Ci gaban shirye-shirye na Nios V ya dogara ne akan Layer abstraction Layer (HAL). HAL tana ba da ƙaramin shirin ɗaukar kaya (wanda kuma aka sani da boot copier) wanda ke kwafin sassan mahaɗan da suka dace daga ƙwaƙwalwar taya zuwa wurin lokacin gudu a lokacin taya. Kuna iya ƙididdige shirin da wuraren žwažwalwar ajiyar bayanai da ke gudana lokacin ta hanyar sarrafa saitunan Editan Kunshin Tallafi (BSP). Wannan sashe yana bayyana: · Nios V processor boot copier wanda ke yin booting tsarin aikin Nios V na ku bisa ga
Zaɓin ƙwaƙwalwar ajiyar taya · Nios V zaɓuɓɓukan booting na processor da kwarara gabaɗaya · Nios V shirye-shiryen mafita don ƙwaƙwalwar taya da aka zaɓa
4.2. Aikace-aikace masu haɗawa
Lokacin da kuka samar da aikin mai sarrafa Nios V, Editan BSP yana haifar da alaƙa guda biyu masu alaƙa files: · linker.x: Umurnin mai haɗawa file wanda aikace-aikacen da aka ƙirƙira ya yifile amfani
don ƙirƙirar .elf binary file. linker.h: Ya ƙunshi bayani game da shimfidar ƙwaƙwalwar mahaɗin mahaɗin. Duk gyare-gyaren saitin mahaɗar da kuka yi ga aikin BSP yana shafar abubuwan da ke cikin waɗannan mahaɗan guda biyu files. Kowane aikace-aikacen processor na Nios V ya ƙunshi sassan mahaɗan masu zuwa:
© Altera Corporation. Altera, tambarin Altera, tambarin `a', da sauran alamomin Altera alamun kasuwanci ne na Kamfanin Altera. Altera yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Altera ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka bayyana a nan sai dai kamar yadda Altera ya yarda da shi a rubuce. Ana shawarci abokan cinikin Altera su sami sabon sigar ƙayyadaddun na'urar kafin dogaro da kowane bayanan da aka buga kuma kafin yin oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

4. Nios V Kanfigareshan Mai sarrafawa da Booting Solutions 726952 | 2025.07.16

Tebur 29. Sashe na Linker

.rubutu

Sassan Linker

.rodata

rwdata

.bss

. tsiri

.tari

Bayanin lambar da za a iya aiwatarwa. Duk bayanan karantawa kawai da aka yi amfani da su wajen aiwatar da shirin. Ana adana bayanan karanta-rubutu da aka yi amfani da su wajen aiwatar da shirin. Ya ƙunshi bayanan da ba a buɗe ba. Ya ƙunshi ƙayyadaddun ƙwaƙwalwar ajiya mai ƙarfi. Adana sigogin aikin-kiran da sauran bayanan wucin gadi.

Kuna iya ƙara ƙarin sassan mahaɗa zuwa .elf file don riƙe al'ada code da bayanai. Ana sanya waɗannan ɓangarorin masu haɗin kai a cikin yankunan ƙwaƙwalwar ajiya mai suna, waɗanda aka ayyana don dacewa da na'urorin ƙwaƙwalwar ajiya na zahiri da adireshi. Ta hanyar tsoho, Editan BSP yana haifar da waɗannan sassan haɗin kai ta atomatik. Koyaya, zaku iya sarrafa sassan mahaɗin don takamaiman aikace-aikacen.

4.2.1. Haɗin Haɓakawa
Wannan sashe yana bayyana halin haɗin kai na Editan BSP da yadda ake sarrafa halayen haɗin kai.

4.2.1.1. Tsohuwar Haɗin BSP
A lokacin daidaitawar BSP, kayan aikin suna aiwatar da matakai masu zuwa ta atomatik:
1. Sanya sunayen yankin ƙwaƙwalwar ajiya: Sanya suna ga kowace na'urar ƙwaƙwalwar ajiyar tsarin kuma ƙara kowane suna zuwa mahaɗin file a matsayin yankin ƙwaƙwalwar ajiya.
2. Nemo mafi girman ƙwaƙwalwar ajiya: Gano mafi girman yankin ƙwaƙwalwar karatu da rubutu a cikin mahaɗin file.
3. Sanya sassan mahaɗa: Sanya sassan mahaɗan tsoho (.rubutu, .rodata, .rwdata, .bss, .heap, da .stack) a cikin yankin ƙwaƙwalwar ajiya da aka gano a mataki na baya.
4. Rubuta files: Rubuta linker.x da linker.h files.
Yawanci, tsarin rarraba sashin mahaɗin yana aiki yayin aikin haɓaka software saboda aikace-aikacen yana da tabbacin yin aiki idan ƙwaƙwalwar ajiya ta isa.
Dokokin halayen haɗin kai na asali suna ƙunshe a cikin Altera-generated Tcl scripts bsp-set-defaults.tcl da bsp-linker-utils.tcl da aka samu a cikin /niosv/scripts/bsp-defaults directory. Umurnin niosv-bsp yana kiran waɗannan rubutun. Kar a gyara waɗannan rubutun kai tsaye.

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4.2.1.2. Haɗin BSP mai daidaitawa
Kuna iya sarrafa dabi'un haɗin kai na asali a cikin shafin Linker Script na Editan BSP. Sarrafa rubutun mahaɗin ta amfani da hanyoyi masu zuwa: · Ƙara yankin ƙwaƙwalwar ajiya: Taswirar sunan yankin ƙwaƙwalwar ajiya zuwa na'urar ƙwaƙwalwar ajiya ta zahiri. Ƙara taswirar sashe: Taswirar sunan sashe zuwa yankin ƙwaƙwalwar ajiya. Farashin BSP
Edita yana ba ku damar view taswirar ƙwaƙwalwar ajiya kafin da bayan yin canje-canje.

4.3. Hanyoyin Booting na Nios V Processor

Akwai 'yan hanyoyin da za a tayar da Nios V processor a cikin na'urorin Altera FPGA. Hanyoyin taya Nios V processor sun bambanta bisa ga zaɓin ƙwaƙwalwar filasha da iyalai na na'ura.

Tebur 30. Ƙwararrun Ƙwararrun Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙaƙwalwa

Abubuwan Tunawa da Boot Mai Goyan baya

Na'ura

Flash On-Chip (don Tsarin Ciki)

Max 10 na'urori kawai (tare da On-Chip Flash IP)

Babban Manufar QSPI Flash (don bayanan mai amfani kawai)

Duk na'urorin FPGA masu goyan bayan (tare da Generic Serial Flash Interface FPGA IP)

Kanfigareshan QSPI Flash (don Tsarin Serial Mai Aiki)

Sarrafa tushen toshe
na'urorin (tare da Generic
Serial Flash Interface Intel FPGA IP)(2)

Hanyoyin Booting na Nios V Processor

Wurin Gudun Aikace-aikacen

Boot Copier

Aikace-aikacen mai sarrafa Nios V yana aiwatarwa daga Wurin Kan-Chip Flash

Flash on-Chip (XIP) + OCRAM / RAM na waje (don sassan bayanan da za a iya rubutawa)

alt_load() aiki

Nios V processor aikace-aikacen da aka kwafi daga On-Chip Flash zuwa RAM ta amfani da na'urar kwafi

OCRAM/ RAM na waje

Sake amfani da Bootloader ta hanyar GSFI

Nios V processor aikace-aikacen aiwatarwa daga wurin gabaɗaya QSPI flash

Babban manufar QSPI flash (XIP) + OCRAM/ RAM na waje (don sassan bayanan da za a iya rubutawa)

alt_load() aiki

Aikace-aikacen processor na Nios V da aka kwafi daga babban manufa QSPI filashi zuwa RAM ta amfani da na'urar kwafi

OCRAM/ RAM na waje

Bootloader ta hanyar GSFI

Aikace-aikacen mai sarrafa Nios V yana aiwatarwa daga wurin saitin QSPI flash

Kanfigareshan QSPI flash (XIP) + OCRAM / RAM na waje (don sassan bayanan da za a iya rubutawa)

alt_load() aiki

Aikace-aikacen processor na Nios V da aka kwafi daga ƙirar QSPI flash zuwa RAM ta amfani da na'urar kwafin taya

OCRAM/ Bootloader na RAM na waje ta hanyar GSFI ya ci gaba…

(2) Koma zuwa AN 980: Nios V Processor Quartus Prime Software Support don lissafin na'urar.

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Abubuwan Tunawa da Boot Mai Goyan baya
Ƙwaƙwalwar Ƙwaƙwalwar Kan Chip (OCRAM) Ƙwaƙwalwar Haɗe-haɗe (TCM)

Na'ura
Na'urorin tushen SDM (tare da Abokin Wasiku na Intel FPGA IP). (2)
Duk na'urorin Altera FPGA masu goyan bayan (2)
Duk na'urorin Altera FPGA masu goyan baya(2)

Hanyoyin Booting na Nios V Processor
Aikace-aikacen processor na Nios V da aka kwafi daga ƙirar QSPI flash zuwa RAM ta amfani da na'urar kwafin taya
Nios V processor aikace-aikacen aiwatarwa daga OCRAM
Nios V processor aikace-aikacen aiwatarwa daga TCM

Wurin Gudun Aikace-aikacen

Boot Copier

OCRAM/ Bootloader na RAM na waje ta hanyar SDM

OCRAM

alt_load() aiki

Umarnin TCM (XIP) Babu + Data TCM (don sassan bayanan da za a iya rubutawa)

Hoto 28. Nios V Processor Boot Flow

Sake saiti

Mai sarrafawa yayi tsalle don sake saita vector (fara lambar boot)

Ana iya kwafi lambar aikace-aikacen zuwa wani wurin ƙwaƙwalwar ajiya (dangane da zaɓuɓɓukan taya)
Boot code yana fara aikin sarrafawa

Dangane da zaɓuɓɓukan taya, lambar taya na iya kwafin ƙimar farko don bayanai/ladi zuwa wani wurin ƙwaƙwalwar ajiya (alt_load)
Lambar Boot tana fara lambar aikace-aikacen da sarari ƙwaƙwalwar ajiya
Lambar Boot tana fara duk abubuwan da ke gefen tsarin tare da direbobi HAL (alt_main)
Shiga zuwa main
Bayani mai alaƙa · Gabaɗaya Serial Flash Interface Altera FPGA IP Jagorar mai amfani
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Abokin Akwatin Saƙo Altera FPGA IP Jagorar Mai Amfani · AN 980: Nios V Processor Quartus Prime Support Software
4.4. Gabatarwa zuwa Hanyoyin Booting na Nios V
Tsarin Nios V yana buƙatar a saita hotunan software a cikin ƙwaƙwalwar tsarin kafin mai sarrafawa ya fara aiwatar da shirin aikace-aikacen. Koma zuwa Sashe na Linker don tsoffin sassan mahaɗin.
Editan BSP yana haifar da rubutun haɗin gwiwa wanda ke aiwatar da ayyuka masu zuwa: · Yana tabbatar da cewa an haɗa software ɗin processor daidai da saitunan mahaɗan.
na editan BSP kuma yana ƙayyade inda software ke zaune a ƙwaƙwalwar ajiya. · Sanya yankin code na na'ura mai sarrafawa a cikin bangaren ƙwaƙwalwar ajiya bisa ga
Abubuwan da aka sanya wa ƙwaƙwalwar ajiya.
Sashe na gaba yana bayyana hanyoyin booting processor na Nios V a taƙaice.
4.4.1. Nios V Aikace-aikacen Mai aiwatarwa yana aiwatar da-In- Wuri daga Boot Flash
Altera ya ƙirƙira masu sarrafa filasha kamar yadda sararin adireshi filashin boot ke samun dama ga mai sarrafa Nios V akan sake saitin tsarin, ba tare da buƙatar fara mai sarrafa ƙwaƙwalwar ajiya ko na'urorin ƙwaƙwalwar ajiya ba. Wannan yana bawa mai sarrafa Nios V damar aiwatar da lambar aikace-aikacen da aka adana akan na'urorin taya kai tsaye ba tare da yin amfani da na'urar kwafi don kwafi lambar zuwa wani nau'in ƙwaƙwalwar ajiya ba. Masu sarrafa filasha sune: · On-Chip Flash tare da On-Chip Flash IP (kawai a cikin na'urar MAX® 10) · Gabaɗaya QSPI flash tare da Generic Serial Flash Interface IP · Tsare-tsare QSPI flash tare da Generic Serial Flash Interface IP (sai dai MAX 10).
na'urori)
Lokacin aiwatar da aikace-aikacen processor na Nios V daga boot flash, Editan BSP yana aiwatar da ayyuka masu zuwa: · Yana saita sassan mahaɗin rubutu zuwa yankin ƙwaƙwalwar filashin boot. · Yana saita sassan .bss,.rodata, .rwdata, .stack da .heap linker sassan zuwa RAM
yankin ƙwaƙwalwar ajiya. Dole ne ku kunna aikin alt_load() a cikin Saitunan BSP don kwafi sassan bayanan (.rodata, .rwdata,, .banda) zuwa RAM akan sake saitin tsarin. Sashin lambar (.rubu) ya kasance a cikin yankin ƙwaƙwalwar filasha ta boot.
Bayani mai alaƙa · Jigon Serial Flash Interface Altera FPGA IP Jagorar Mai amfani
4.4.1.1. alt_load()
Kuna iya kunna aikin alt_load() a cikin lambar HAL ta amfani da Editan BSP.
Lokacin da aka yi amfani da shi a cikin aiwatar da aikin boot-in-place, aikin alt_load() yana yin ayyuka masu zuwa:

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Yana aiki azaman ƙaramin kwafin boot wanda ke kwafin sassan ƙwaƙwalwar ajiya zuwa RAM dangane da saitunan BSP.
· Kwafi sassan bayanai (.rodata, .rwdata, .banda) zuwa RAM amma ba sassan code (.rubutu ba) Sashe na code (.rubutu) sashe ne na karantawa kawai kuma ya kasance a cikin yankin ƙwaƙwalwar filashin booting. Wannan rarrabuwa yana taimakawa rage yawan amfani da RAM amma yana iya iyakance aikin aiwatar da lambar saboda samun dama ga ƙwaƙwalwar filasha yana da hankali fiye da samun dama ga RAM akan guntu.

Tebur mai zuwa yana lissafin saitunan Editan BSP da ayyuka:

Table 31. BSP Editan Saituna
Saitin Editan BSP hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Aiki Yana kunna aikin alt_load(). alt_load() kwafin .rodata sashen zuwa RAM. alt_load() kwafi .rwdata sashen zuwa RAM. alt_load() kwafi .bangare na RAM.

4.4.2. Nios V Application An Kwafi daga Boot Flash zuwa RAM Ta Amfani da Boot Copier
Nios V processor da HAL sun haɗa da na'urar kwafin taya wanda ke ba da isassun ayyuka don yawancin aikace-aikacen sarrafa Nios V kuma ya dace don aiwatarwa tare da kwararar haɓaka software na Nios V.
Lokacin da aikace-aikacen yana amfani da na'urar kwafi, yana saita duk sassan mahaɗa (.rubutu, .heap, .rwdata, .rodata, .bss, .stack) zuwa RAM na ciki ko na waje. Yin amfani da kwafin taya don kwafi aikace-aikacen processor na Nios V daga filasha boot zuwa RAM na ciki ko na waje don aiwatarwa yana taimakawa wajen haɓaka aikin aiwatarwa.
Don wannan zaɓin taya, mai sarrafa Nios V yana fara aiwatar da software mai kwafin taya akan sake saitin tsarin. Software yana kwafin aikace-aikacen daga filasha boot zuwa RAM na ciki ko na waje. Da zarar aikin ya cika, na'urar sarrafa Nios V tana canja wurin sarrafa shirin zuwa aikace-aikacen.

Lura:

Idan boot copier yana cikin walƙiya, to aikin alt_load() baya buƙatar a kira shi saboda dukansu suna aiki iri ɗaya.

4.4.2.1. Nios V Mai sarrafa Bootloader ta hanyar Interface Serial Flash Interface
Bootloader ta hanyar GSFI shine Nios V processor boot copier wanda ke goyan bayan ƙwaƙwalwar filasha QSPI a cikin na'urori masu tushen toshewa. Bootloader ta hanyar GSFI ya haɗa da fasali masu zuwa:
· Nemo aikace-aikacen software a cikin ƙwaƙwalwar da ba ta da ƙarfi.
· Buɗe da kwafi hoton aikace-aikacen software zuwa RAM.
· Yana canza aikin sarrafawa ta atomatik zuwa lambar aikace-aikace a RAM bayan an gama kwafin.

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Hoton taya yana nan daidai bayan na'urar kwafin taya. Kuna buƙatar tabbatar da saitunan sake saitin processor na Nios V zuwa farkon na'urar kwafin taya. Hoton: Taswirar Ƙwaƙwalwa don QSPI Flash tare da Bootloader ta taswirar ƙwaƙwalwar ajiya na GSFI don QSPI Flash tare da Bootloader ta GSFI yana nuna taswirar ƙwaƙwalwar ajiyar filasha don filasha QSPI lokacin amfani da na'urar kwafi. Wannan taswirar žwažwalwar ajiya tana ɗauka cewa ƙwaƙwalwar ajiyar filasha tana adana hoton FPGA da software na aikace-aikacen.

Tebur 32. Bootloader ta GSFI don Nios V Processor Core

Nios V Processor Core
Nios V/m processor

Bootloader ta hanyar GSFI File Wuri
/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/components/bootloader/ niosv_g_bootloader.srec

Hoto 29. Taswirar ƙwaƙwalwa don QSPI Flash tare da Bootloader ta GSFI

Bayanan Abokin ciniki (*.hex)

Lambar Aikace-aikace

Lura:

Sake saitin Vector Offset

Boot Copier

0x01E00000 ku

Hoton FPGA (*.sof)

0 x00000000

1. A farkon taswirar ƙwaƙwalwar ajiya shine hoton FPGA wanda ke biye da bayanan ku, wanda ya ƙunshi boot copier da lambar aikace-aikace.
2. Dole ne ku saita sake saitin processor na Nios V a cikin Platform Designer kuma ku nuna shi zuwa farkon na'urar kwafi.
3. Girman hoton FPGA ba a san shi ba. Kuna iya sanin ainihin girman kawai bayan aikin Quartus Prime. Dole ne ku ƙayyade iyaka na sama don girman hoton Altera FPGA. Don misaliample, idan girman hoton FPGA ya yi kiyasin kasa da 0x01E00000, saita Reset Offset zuwa 0x01E00000 a Platform Designer, wanda kuma shine farkon na'urar kwafi.
4. Kyakkyawan aikin ƙira ya ƙunshi saita saiti na sake saiti a cikin iyakar ɓangaren walƙiya don tabbatar da cewa babu wani ɓangare na goge hoton FPGA idan an sabunta aikace-aikacen software.

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4.4.2.2. Nios V Mai sarrafa Bootloader ta Manajan Na'urar Amintaccen
Bootloader ta hanyar Manajan Na'ura mai aminci (SDM) lambar aikace-aikacen HAL ce ta amfani da Akwatin Wasiƙa Client Altera FPGA IP HAL direba don booting processor. Altera yana ba da shawarar wannan aikace-aikacen bootloader lokacin amfani da daidaitawar QSPI filashi a cikin na'urorin tushen SDM don kora na'urar Nios V.
Bayan sake saitin tsarin, mai sarrafa Nios V ya fara yin takalman Bootloader ta hanyar SDM daga ƙaramin ƙwaƙwalwar ajiya akan guntu kuma yana aiwatar da Bootloader ta hanyar SDM don sadarwa tare da daidaitawar filasha QSPI ta amfani da Abokin Ciniki na Akwatin Wasiku IP.
Bootloader ta hanyar SDM yana aiwatar da ayyuka masu zuwa: · Ya gano software na Nios V a cikin tsarin QSPI flash. · Kwafi software na Nios V zuwa cikin RAM akan guntu ko RAM na waje. Yana canza aikin processor zuwa software na Nios V a cikin RAM akan guntu ko
RAM na waje.
Da zarar aikin ya cika, Bootloader ta hanyar SDM yana canja wurin sarrafa shirin zuwa aikace-aikacen mai amfani. Altera yana ba da shawarar ƙungiyar ƙwaƙwalwar ajiya kamar yadda aka tsara a Ƙungiyar Ƙwaƙwalwar Ƙwaƙwalwar Bootloader ta hanyar SDM.
Hoto 30. Bootloader ta hanyar Tsarin Tsarin SDM

Kanfigareshan

Filashi

Nios V Software

SDM

Na'urar FPGA ta tushen SDM

Akwatin saƙon abokin ciniki IP

FPGA Logic Nios V

4 RAM na waje
Nios V Software

On-Chip 4

EMIF

RAM

Ƙwaƙwalwar Kan Chip

Nios V

Software

Bootloader ta hanyar SDM

1. Nios V processor yana gudanar da Bootloader ta hanyar SDM daga ƙwaƙwalwar kan-chip.
2. Bootloader ta hanyar SDM yana sadarwa tare da filashin daidaitawa kuma yana gano software na Nios V.
3. Bootloader ta hanyar SDM yana kwafin software na Nios V daga Filashin Kanfigareshan zuwa RAM akan guntu / RAM na waje.
4. Bootloader ta hanyar SDM yana canza aikin Nios V processor zuwa software na Nios V a cikin RAM akan guntu / RAM na waje.

4.4.3. Nios V Aikace-aikacen Mai aiwatarwa yana aiwatar da-In- Wuri daga OCRAM
A cikin wannan hanyar, an saita adireshin sake saitin processor na Nios V zuwa adireshin tushe na ƙwaƙwalwar kan-chip (OCRAM). Binaryar aikace-aikacen (.hex) file ana loda shi cikin OCRAM lokacin da aka saita FPGA, bayan an haɗa ƙirar kayan aikin a cikin software na Quartus Prime. Da zarar na'urar aikin Nios V ta sake saiti, aikace-aikacen ya fara aiwatarwa da rassa zuwa wurin shigarwa.

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Lura:

Execute-In-Place daga OCRAM baya buƙatar mai kwafin taya saboda Nios V processor aikace-aikacen ya riga ya kasance a wurin sake saitin tsarin.
Altera yana ba da shawarar ba da damar alt_load() don wannan hanyar booting ta yadda software ɗin da aka haɗa ta yi aiki iri ɗaya lokacin sake saitawa ba tare da sake saita hoton na'urar FPGA ba.
Dole ne ku kunna aikin alt_load() a cikin saitunan BSP don kwafi sashin .rwdata akan sake saitin tsarin. A cikin wannan hanyar, ana adana ƙimar farko don masu canji daban-daban daga madaidaitan ma'auni don guje wa sake rubutu akan aiwatar da shirin.

4.4.4. Nios V Aikace-aikacen Mai aiwatarwa yana aiwatar da-In- Wuri daga TCM
Hanyar aiwatar-in-wuri tana saita adireshin sake saitin processor na Nios V zuwa adireshin tushe na ƙwaƙwalwar haɗe-haɗe (TCM). Binaryar aikace-aikacen (.hex) file ana loda shi cikin TCM lokacin da kuka saita FPGA bayan kun haɗa ƙirar kayan aikin a cikin software na Quartus Prime. Da zarar na'urar aikin Nios V ta sake saiti, aikace-aikacen ya fara aiwatarwa da rassa zuwa wurin shigarwa.

Lura:

Execute-In-Place daga TCM baya buƙatar mai kwafin taya saboda Nios V processor aikace-aikacen ya riga ya kasance a wurin sake saitin tsarin.

4.5. Nios V Processor Booting daga On-Chip Flash (UFM)

Nios V processor booting da aiwatar da software daga kan-chip flash (UFM) ana samunsa a cikin na'urorin MAX 10 FPGA. Mai sarrafa Nios V yana goyan bayan zaɓuɓɓukan taya biyu masu zuwa ta amfani da On-Chip Flash a ƙarƙashin Yanayin Kanfigareshan Ciki:
Nios V processor aikace-aikace yana aiwatar da a-wuri daga On-Chip Flash.
Ana kwafin aikace-aikacen processor na Nios V daga On-Chip Flash zuwa RAM ta amfani da na'urar kwafi.

Tebura 33. Taimakon Ƙwayoyin Flash tare da Zaɓuɓɓukan Boot daban-daban

Abubuwan Tunawa da Boot Mai Goyan baya

Nios V Hanyoyin Booting

Wurin Gudun Aikace-aikacen

Boot Copier

Na'urori MAX 10 kawai (tare da OnChip Flash IP)

Aikace-aikacen mai sarrafa Nios V yana aiwatarwa daga Wurin Kan-Chip Flash
Nios V processor aikace-aikacen da aka kwafi daga On-Chip Flash zuwa RAM ta amfani da na'urar kwafi

Flash on-Chip (XIP) + OCRAM / RAM na waje (don sassan bayanan da za a iya rubutawa)

alt_load() aiki

OCRAM / RAM na waje

Sake amfani da Bootloader ta hanyar GSFI

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Hoto na 31.

Zane, Kanfigareshan, da Booting Gudun
Zane · Ƙirƙiri tushen aikin Nios V Processor ta amfani da Platform Designer. · Tabbatar cewa akwai RAM na waje ko na kan-chip RAM a cikin ƙirar tsarin.

Kanfigareshan da Tarin FPGA
Saita yanayin sanyi na ciki iri ɗaya a cikin On-chip Flash IP a cikin Mai tsara Platform da Quartus Prime software. Saita wakili na sake saiti na Nios V zuwa Flash On-chip. · Zaɓi hanyar farawa ta UFM da kuka fi so. · Ƙirƙirar ƙirar ku a cikin Platform Designer. · Haɗa aikin ku a cikin software na Quartus Prime.

Aikace-aikacen mai amfani BSP Project · Ƙirƙiri Nios V processor HAL BSP bisa .sopcinfo file Wanda Platform Designer ya kirkira. · Shirya saitunan Nios V mai sarrafawa na BSP da Rubutun Linker a cikin Editan BSP. · Ƙirƙirar aikin BSP.
Aikace-aikacen APP Project · Haɓaka lambar aikace-aikacen mai sarrafa Nios V. Haɗa aikace-aikacen processor na Nios V kuma ƙirƙirar aikace-aikacen sarrafa Nios V (.hex) file. Sake tattara aikinku a cikin software na Quartus Prime idan kun duba Fara zaɓin abun ciki na ƙwaƙwalwar ajiya a cikin Intel FPGA On-Chip Flash IP.

Shirye-shirye Files Juyawa, Zazzagewa da Gudu · Ƙirƙirar Filashin Kan Chip .pof file ta amfani da Convert Programming Files fasalin a cikin Quartus Prime software.
· Shirya .pof file cikin na'urarka ta MAX 10. · Zagayowar wutar lantarki kayan aikin ku.
4.5.1. Bayanin Filashin Kan Chip MAX 10 FPGA
Na'urorin MAX 10 FPGA sun ƙunshi walƙiya-kan-chip wanda aka kasu kashi biyu: · Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa (CFM) - tana adana bayanan daidaita kayan masarufi don
MAX 10 FPGAs. Ƙwaƙwalwar ajiya mai amfani (UFM) - tana adana bayanan mai amfani ko aikace-aikacen software.
Gine-ginen UFM na na'urar MAX 10 hade ne na IPs masu taushi da wuya. Kuna iya samun dama ga UFM kawai ta amfani da On-Chip Flash IP Core a cikin software na Quartus Prime.
On-chip Flash IP core yana goyan bayan fasalulluka masu zuwa: · Karanta ko rubuta hanyoyin shiga UFM da CFM (idan an kunna su a cikin Mai tsara Platform)
ta amfani da bayanan Avalon MM da kuma sarrafa ma'amalar bawa. · Yana goyan bayan shafe shafi, shafe sashe da rubuta sassan. Samfuran kwaikwaiyo don karantawa/rubutu damar shiga UFM ta amfani da kayan aikin kwaikwayo na EDA daban-daban.

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Tebur 34. Yankunan Filashin kan-chip a cikin na'urorin MAX 10 FPGA

Yankunan Flash

Ayyuka

Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙadda ) na CFM0-2 ) yayi

Tsarin FPGA file ajiya

Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Mai Amfani (bangar UFM0-1)

Nios V aikace-aikacen processor da bayanan mai amfani

Na'urorin MAX 10 FPGA suna goyan bayan yanayin sanyi da yawa kuma wasu daga cikin waɗannan hanyoyin suna ba da damar amfani da CFM1 da CFM2 azaman ƙarin yankin UFM. Tebu mai zuwa yana nuna wurin ajiya na hotunan daidaitawar FPGA bisa tsarin daidaitawa na MAX 10 FPGA.

Tebur 35. Wurin Ajiya na Hotunan Kanfigareshan FPGA

Yanayin Kanfigareshan hotuna Dual matsi

Hoton da aka matse CFM2

Saukewa: CFM1

Hoton da aka matse CFM0

Hoto daya tilo mara matsawa

UFM na zahiri

Hoton da ba a matsawa ba

Hoto daya tilo mara matsawa tare da Ƙaddamarwa Ƙwaƙwalwar ajiya

Hoton da ba a matsawa ba (tare da abun ciki na ƙwaƙwalwar ajiya da aka riga aka fara)

Hoto guda ɗaya da aka matsa tare da Ƙaddamar da Ƙwaƙwalwar Ƙwaƙwalwar Hoto (tare da abun cikin ƙwaƙwalwar da aka riga aka fara farawa)

Hoto guda ɗaya da aka matsa

UFM na zahiri

Hoton da aka matsa

Dole ne ku yi amfani da On-chip Flash core IP don samun damar zuwa ƙwaƙwalwar filasha a cikin MAX 10 FPGAs. Za ka iya nan take da haɗa Kan-chip Flash IP zuwa software na Quartus Prime. Nios V soft core processor yana amfani da haɗin haɗin kan Platform Designer don sadarwa tare da On-chip Flash IP.
Hoto 32. Haɗin kai tsakanin On-chip Flash IP da Nios V Processor

Lura:

Tabbatar cewa an haɗa tashar Csr On-chip Flash zuwa Nios V processor data_manager don baiwa mai sarrafawa damar sarrafa rubutu da goge ayyukan.
Kan-chip Flash core IP na iya ba da dama ga sassan filasha guda biyar - UFM0, UFM1, CFM0, CFM1, da CFM2.
Muhimman bayanai game da sassan UFM da CFM.: · An yi nufin sassan CFM don daidaitawa (bitstream) bayanai (* .pof) ajiya.
Za a iya adana bayanan mai amfani a cikin sassan UFM kuma ana iya ɓoye su, idan an zaɓi saitunan da suka dace a cikin kayan aikin Platform Designer.
Wasu na'urori ba su da sashin UFM1. Kuna iya komawa zuwa teburin: Girman Sashin UFM da CFM don samuwan sassa a cikin kowane ɗayan na'urar MAX 10 FPGA.

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Zaku iya saita CFM2 azaman UFM na kama-da-wane ta zaɓin yanayin daidaita hoto guda ɗaya wanda ba a matsawa ba.
Za ka iya saita CFM2 da CFM1 a matsayin kama-da-wane UFM ta zaɓar yanayin daidaita hoto guda ɗaya wanda ba a haɗa shi ba.
Girman kowane sashe ya bambanta da zaɓin na'urorin MAX 10 FPGA.

Tebur 36.

Girman Sashin UFM da CFM
Wannan tebur yana lissafin ma'auni na UFM da CFM.

Na'ura

Shafuka a kowane Sashe

UFM1 UFM0 CFM2 CFM1 CFM0

Girman Shafin (Kbit)

Mafi girman Mai amfani
Girman Ƙwaƙwalwar Filashi (Kbit) (3)

Jimlar Girman Ƙwaƙwalwar Ƙwaƙwalwa (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

Girman OCRAM (Kbit)
108 189 378 549 675 1260 1638

Bayani mai alaƙa · MAX 10 FPGA Jagorar Mai amfani na Kanfigareshan · Altera MAX 10 Jagorar Mai Amfani da Ƙwaƙwalwar Ƙwaƙwalwar Mai Amfani

4.5.2. Nios V Aikace-aikacen Mai aiwatarwa yana aiwatar da-In- Wuri daga UFM

The Execute-In-Place daga UFM bayani ya dace da aikace-aikacen mai sarrafa Nios V wanda ke buƙatar iyakanceccen amfani da ƙwaƙwalwar ajiya akan guntu. Aikin alt_load() yana aiki azaman ƙaramin kwafin taya wanda ke kwafin sassan bayanan (.rodata, .rwdata, ko .banda) daga ƙwaƙwalwar taya zuwa RAM dangane da saitunan BSP. Sashen lambar (.rubutu),
wanda yanki ne kawai karantawa, ya rage a cikin MAX 10 On-chip Flash memory area. Wannan saitin yana rage yawan amfani da RAM amma yana iya iyakance aikin aiwatar da lambar saboda samun damar ƙwaƙwalwar ajiyar filasha ta yi hankali fiye da RAM akan guntu.

An tsara aikace-aikacen processor na Nios V zuwa sashin UFM. Reset vector na Nios V processor yana nuni zuwa adireshin tushe na UFM don aiwatar da lamba daga UFM bayan tsarin ya sake saiti.

Idan kana amfani da madaidaicin matakin tushe don gyara aikace-aikacenka, dole ne ka yi amfani da wurin warwarewar kayan aiki. Wannan saboda UFM baya goyan bayan samun damar ƙwaƙwalwar ajiya bazuwar, wanda ya wajaba don gyara maɓalli mai laushi.

Lura:

Ba za ku iya gogewa ko rubuta UFM ba yayin aiwatar da aiwatarwa a cikin MAX 10. Canja zuwa tsarin taya na kwafin idan kuna buƙatar gogewa ko rubuta UFM.

(3) Matsakaicin ƙima mai yuwuwa, wanda ya dogara da yanayin sanyi da kuka zaɓa.

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Hoto 33. Nios V Application XIP daga UFM

Na'ura mafi girma 10

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Quartus Programmer

Akan-Chip Flash

Farashin CFM

Nios V Hardware

UFM

Nios V Software

Kanfigareshan Cikin Gida

Kan-Chip Flash IP

Farashin FPGA
Nios V Processor

A-Chip RAM

Na waje

RAM

EMIF

4.5.2.1. Tsarin Tsarin Hardware
Sashe na gaba yana bayyana hanyar mataki-mataki don gina tsarin bootable don aikace-aikacen processor na Nios V daga On-Chip Flash. The example kasa an gina ta ta amfani da na'urar MAX 10.
Saitunan Bangaren IP
1. Ƙirƙiri aikin Nios V ɗin ku ta amfani da Quartus Prime da Platform Designer. 2. Tabbatar an ƙara RAM na waje ko Ƙwaƙwalwar Kan Chip (OCRAM) zuwa Platform ɗin ku
Tsarin zane.

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Hoto 34. ExampHaɗin IP a cikin Mai tsara Platform don Booting Nios V daga OnChip Flash (UFM)

3. A cikin Editan IP na On-Chip Flash, saita yanayin Configuration zuwa ɗaya daga cikin masu zuwa, gwargwadon zaɓin ƙira: · Hoto Guda ɗaya da ba a matsawa ba · Hoto guda ɗaya da ba a danne shi ba tare da Ƙaddamar da ƙwaƙwalwar ajiya · Hoto guda ɗaya tare da ƙaddamar da ƙwaƙwalwar ajiya.
Don ƙarin bayani game da Dual Compressed Images, koma zuwa MAX 10 FPGA Kanfigareshan Jagorar Mai Amfani - Haɓaka Tsari Mai Nisa.

Lura:

Dole ne ku sanya Hidden Dama zuwa kowane yanki na CFM a cikin On-Chip Flash IP.

Hoto 35. Zaɓin Yanayin Kanfigareshan a Kan Chip Flash Parameter Editan

Saitunan IP na Filashin Kan-Chip – Ƙaddamarwar UFM Za ka iya zaɓar ɗaya daga cikin hanyoyin masu zuwa gwargwadon zaɓinka:

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Lura:

Matakan da ke cikin ɓangarorin da ke gaba (Flow Design Design da Programming) sun dogara da zaɓin da kuka yi a nan.

Hanyar 1: Fara bayanan UFM a cikin SOF yayin haɗawa
Quartus Prime ya haɗa da bayanan farawa na UFM a cikin SOF yayin haɗawa. Ana buƙatar sake tattara SOF idan akwai canje-canje a cikin bayanan UFM.
1. Bincika fara abun ciki na walƙiya kuma Kunna farawa mara tushe file.

Hoto 36. Fara abubuwan da ke cikin Filasha kuma Kunna Ƙaddamar da ba tsoho ba File

2. Ƙayyade hanyar da aka haifar da .hex file (daga umarnin elf2hex) a cikin Mai amfani ya ƙirƙira hex ko mif file.
Hoto 37. Ƙara .hex File Hanya

· Hanyar 2: Haɗa bayanan UFM tare da SOF da aka haɗa yayin tsara POF
Ana haɗe bayanan UFM tare da harhada SOF lokacin da ake canza shirye-shirye files. Ba kwa buƙatar sake tara SOF, koda bayanan UFM sun canza. Lokacin haɓakawa, ba lallai ne ku sake tara SOF ba files don canje-canje a cikin aikace-aikacen. Alterare yana yaba wannan hanyar don masu haɓaka aikace-aikacen.
1. Cire alamar Fara abun ciki na walƙiya.
Hoto 38. Fara abun ciki na Filashi tare da Ƙaddamarwar da ba ta asali ba File

Sake saita Saitunan Wakili don Nios V Processor Execute-In-Place Hanyar
1. A cikin editan sigar sigar processor na Nios V, saita Wakilin Sake saitin zuwa Flash On-Chip.
Hoto 39. Saitunan Editan Ma'auni na Nios V tare da Saitin Wakilin Sake saitin zuwa Filashin Kan-Chip

2. Danna Generate HDL lokacin da akwatin maganganu na Generation ya bayyana. 3. Saka fitarwa file zažužžukan tsara kuma danna Generate.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Danna Ok don fita daga Na'ura da Pin Options taga.
3. Danna Ok don fita daga Na'ura taga.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Lura:

Idan saitin yanayin sanyi a cikin Quartus Prime software da Platform Designer siga editan ya bambanta, aikin Quartus Prime ya gaza tare da saƙon kuskure mai zuwa.

Hoto na 41.

Saƙon Kuskure don Kuskuren Saita Yanayin Kanfigareshan Daban-daban (14740): Yanayin daidaitawa akan zarra "q_sys:q_sys_inst| Sabunta kuma sabunta tsarin Qsys don dacewa da saitin aikin.

Bayani mai alaƙa MAX 10 FPGA Jagorar Mai amfani Kanfigareshan

4.5.2.2. Tsarin Tsarin Software
Wannan sashe yana ba da kwararar ƙira don samarwa da gina aikin software na Nios V. Don tabbatar da ingantaccen tsarin gini, ana ƙarfafa ku don ƙirƙirar bishiyar adireshi iri ɗaya a cikin aikin ƙirar ku. Gudun ƙirar software mai zuwa yana dogara ne akan wannan bishiyar jagorar.
Don ƙirƙirar bishiyar directory na software, bi waɗannan matakan: 1. A cikin babban fayil ɗin aikin ƙira, ƙirƙiri babban fayil mai suna software. 2. A cikin babban fayil ɗin software, ƙirƙira manyan fayiloli guda biyu masu suna hal_app da hal_bsp.
Hoto 42. Bishiyar Jagoran Ayyukan Software

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Ƙirƙirar aikace-aikacen BSP Project
Don ƙaddamar da Editan BSP, bi waɗannan matakan: 1. Shigar da Nios V Command Shell. 2. Kira Editan BSP tare da umarnin edita niosv-bsp. 3. A cikin Editan BSP, danna File Sabon BSP don fara aikin BSP ɗin ku. 4. Sanya saitunan masu zuwa:
· Bayanin SOPC File suna: Samar da SOPINFO file (.sopcinfo). Sunan CPU: Zaɓi Nios V processor. Tsarin aiki: Zaɓi tsarin aiki na processor na Nios V. · Siga: Bar azaman tsoho. BSP manufa directory: Zaɓi hanyar shugabanci na aikin BSP. Za ka iya
kafin saita shi a /software/hal_bsp ta hanyar ba da damar Yi amfani da tsoffin wurare. · Saitunan BSP File suna: Rubuta sunan Saitunan BSP File. Ƙarin rubutun Tcl: Samar da rubutun BSP Tcl ta hanyar kunna Ƙarfafa rubutun Tcl. 5. Danna Ok.
Figure 43. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Maida Shirye-shirye Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Saituna
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file tuba.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Lura:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Na'ura mafi girma 10

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Quartus Programmer

RAM na waje
Nios V Software

Akan-Chip Flash

Farashin CFM

Nios V Hardwa

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Nios V Processor Configuration and Booting Solutions

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