Altera Nios V Ntuziaka onye ọrụ agbakwunyere

About the Nios® V Embedded Processor
1.1. Altera® FPGA na agbakwunyere Nhazi gafereview
Ngwa Altera FPGA nwere ike mejuputa mgbagha na-arụ ọrụ dị ka microprocessor zuru oke ma na-enye ọtụtụ nhọrọ.
Ọdịiche dị mkpa n'etiti microprocessors pụrụ iche na Altera FPGA bụ na akwa Altera FPGA enweghị mgbagha mgbe ọ na-agbali elu. Ihe nhazi Nios® V bụ ihe eji arụ ọrụ ọgụgụ isi dị nro (IP) dabere na nkọwapụta RISC-V. Tupu ị na-agba ọsọ sọftụwia na sistemụ Nios V, ị ga-ahazi ngwaọrụ Altera FPGA na ngwaike nwere ihe nrụpụta Nios V. Ị nwere ike idowe ihe nhazi Nios V ebe ọ bụla na Altera FPGA, dabere n'ihe achọrọ nke imewe.

Iji mee ka sistemu agbakwunyere Altera® FPGA IP gị na-akpa àgwà dị ka sistemụ microprocessor nwere uche, sistemụ gị kwesịrị ịgụnye ihe ndị a: · AJTAG interface iji kwado nhazi, ngwaike na ngwanrọ Altera FPGA
nbibi · Usoro nhazi nhazi nke Altera FPGA
Ọ bụrụ na sistemụ gị nwere ikike ndị a, ị nwere ike ịmalite imezi atụmatụ gị site na ngwaike elelegoro nke etinyere na Altera FPGA. Iji Altera FPGA na-enyekwa gị ohere ịgbanwe atụmatụ gị ngwa ngwa iji dozie nsogbu ma ọ bụ ịgbakwunye ọrụ ọhụrụ. Ị nwere ike ịnwale atụmatụ ngwaike ọhụrụ ndị a n'ụzọ dị mfe site na ịhazigharị Altera FPGA site na iji sistemụ JTAG interface.
Ihe JTAG interface na-akwado mmepe ngwaike na ngwanrọ. Ị nwere ike ịrụ ọrụ ndị a site na iji JTAG interface: · Hazie Altera FPGA · Budata na debug software · Kpọkọtanụ Altera FPGA site na interface yiri UART (J)TAG UART
ọnụ) · ngwa nbibi (ya na mgbanaka mgbanaka agbakwunyere mgbagha) · ebe nchekwa ihe mmemme
Mgbe ị mezichara Altera FPGA na nhazi dabere na Nios V, usoro mmepe sọftụwia yiri mgbaba maka atụmatụ microcontroller pụrụ iche.

Ozi metụtara · AN 985: Nios V Processor nkuzi
Ntuziaka mmalite ngwa ngwa gbasara ịmepụta usoro nhazi Nios V dị mfe ma na-agba ọsọ ngwa Hello World.
© Altera Corporation. Altera, akara Altera, akara 'a', na akara Altera ndị ọzọ bụ ụghalaahịa nke ụlọ ọrụ Altera. Altera nwere ikike ime mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Altera anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Altera kwenyesiri ike na ederede. A dụrụ ndị ahịa Altera ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

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Akwụkwọ ntuziaka Nios V Processor na-enye ozi gbasara akara arụmọrụ Nios V, nhazi nhazi, ụdị mmemme na mmejuputa isi.
Ntuziaka onye ọrụ IP agbakwunyere agbakwunyere · Nios V Akwụkwọ ntuziaka Onye Mmepụta Software

Na-akọwa gburugburu mmepe sọftụwia Nios V, ngwa ndị dị na usoro iji wuo ngwanrọ iji rụọ ọrụ na Nios V processor. Ashling* RiscFree* Integrated Development Environment (IDE) maka ntuziaka onye ọrụ Altera FPGA na-akọwa mpaghara mmepe agbakwunyere RiscFree* (IDE) maka Altera FPGAs Arm* dabere na HPS na Nios V core processor. Ihe ndetu mwepụta Nios V Altera FPGA IP
1.2. Nkwado ngwanrọ Quartus® Prime
Nios V ihe nrụpụta ihe nrụpụta dị iche maka sọftụwia Quartus® Prime Pro Edition yana sọftụwia Quartus Prime Standard Edition. Rụtụ aka na AN 980: Nios V Processor Quartus Prime Software Nkwado maka ozi ndị ọzọ gbasara ndịiche.
Ozi metụtara AN 980: Nios V Processor Quartus Prime Nkwado Software
1.3. Nios V Processor ikikere
Ụdị nhazi Nios V ọ bụla nwere igodo ikike ya. Ozugbo ị nwetara igodo ikike, ị nwere ike iji otu igodo ikike maka ọrụ nhazi Nios V niile ruo ụbọchị njedebe. Ị nwere ike nweta ikikere Nios V Processor Altera FPGA IP na efu efu.
Ndepụta igodo nhazi ihe nhazi Nios V dị na Altera FPGA Ụlọ ọrụ ikikere. Pịa debanye aha maka nyocha ma ọ bụ taabụ ikike efu, wee họrọ nhọrọ dabara adaba iji mee arịrịọ ahụ.
Onyonyo 1. Altera FPGA Center ikike inye ọrụ onwe

Iji igodo ikike, ị nwere ike:
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Tinye ihe nhazi Nios V n'ime sistemụ gị. Mee ka omume nke sistemụ nhazi Nios V. · Nyochaa arụmọrụ nke imewe, dị ka nha na ọsọ. · Mepụta mmemme ngwaọrụ files. · Hazie ngwaọrụ ma nyochaa imewe na ngwaike.
Ịchọghị ikike iji mepụta ngwanrọ na Ashling* RiscFree* IDE maka Altera FPGAs.
Ozi emetụtara · Altera FPGA Center ikikere ọrụ onwe
Maka ozi ndị ọzọ gbasara ịnweta igodo ikike IP Nios V Processor Altera FPGA. Nwụnye na ikikere Altera FPGA Software Maka ozi ndị ọzọ gbasara ịnye ikike ngwanrọ Altera FPGA yana ịtọlite ikike edobere na ihe nkesa ikike netwọkụ.
1.4. Nhazi Sistemu agbakwunyere
Ọnụọgụ na-esonụ na-egosi usoro nhazi usoro Nios V dị mfe, gụnyere ma ngwaike na mmepe ngwanrọ.

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Onyonyo 2.

Nios V Processor Sistemu Nrụpụta Efere
Echiche Sistemu

Nyochaa ihe achọrọ sistemu

Nios® V
Cores processor na Standard components

Kọwaa ma mepụta sistemu n'ime
Onye nrụpụta ikpo okwu

Ngwa ngwa ngwaike: jikọta ma chịkọta Intel Quartus Prime Project

Usoro ngwanrọ: Zụlite ma wulite ngwa ngwa Nios V Proposal

Ngwa ngwaike: Budata FPGA
na Target Board

Usọ sọftụwia: Nnwale na mebie ngwa Nios V Processor Software

Ngwanrọ Ọ nweghị ezute ụdịdị?
Ee
Akụrụngwa Ọ dịghị ezute ụdịdị? Ee
Sistemu zuru oke

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Onyonyo 3.

Eserese na-esonụ na-egosi ụdị ngwaike ngwaike Nios V. Nios V Processor Sistemu Ihe Nrụpụta Ngwa Ngwa

Malite

Nios V Cores na akụrụngwa ọkọlọtọ

Jiri Onye Mmebe Platform chepụta Sistemụ dabere na Nios V
Mepụta Platform Designer Design

Ejikọ sistemu onye nrụpụta Platform na Intel Quartus Prime Project
Kenye ebe Pin, chọrọ oge, yana mmachi imewe ndị ọzọ
Chịkọta ngwaike maka ngwaọrụ Target na Intel Quartus Prime

Dị njikere ibudata
2.1. Imepụta Nios V Processor Sistemume ya na onye nrụpụta Platform
Akụrụngwa Quartus Prime gụnyere ngwa nrụnye sistemu Platform Designer nke na-eme ka ọrụ ịkọwapụta na ijikọ Nios V processor IP core na IP ndị ọzọ n'ime nhazi sistemụ Altera FPGA. Onye nrụpụta Platform na-emepụta mgbagha njikọ njikọ na-akpaghị aka site na njikọta ọkwa ọkwa dị elu akọwapụtara. Automation interconnect na-ewepụ ọrụ na-ewe oge nke ịkọwa njikọ HDL ọkwa sistemụ.
© Altera Corporation. Altera, akara Altera, akara 'a', na akara Altera ndị ọzọ bụ ụghalaahịa nke ụlọ ọrụ Altera. Altera nwere ikike ime mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Altera anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Altera kwenyesiri ike na ederede. A dụrụ ndị ahịa Altera ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

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Mgbe nyochachara ihe ngwaike sistemu chọrọ, ị na-eji Quartus Prime kọwapụta Nios V processor core, ebe nchekwa na ihe ndị ọzọ sistemụ gị chọrọ. Onye nrụpụta Platform na-ewepụta mgbagha njikọ njikọ na-akpaghị aka iji jikọta ihe ndị dị na sistemụ ngwaike.

2.1.1. Na-akwado Nios V Processor Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

Isi IP nke onye nrụpụta ọ bụla na-akwado nhọrọ nhazi dị iche iche dabere na nhazi ya pụrụ iche. Ị nwere ike ịkọwapụta nhazi ndị a ka ọ dabara nke ọma mkpa imewe gị.

Tebụl 1.

Nhọrọ nhazi gafee isi iche iche

Nhọrọ nhazi

Nios V/c Processor

Nios V/m Processor

Arịrịọ ntọgharịa jiri megharịa

—

Ọnyà, Mpụga, na nkwụsị

CPU Architecture

ECC

Caches, Mpaghara dị n'akụkụ na TCMs

—

Ntuziaka omenala

—

Mkpọchi

—

Nios V/g Processor

2.1.1.1. Na-eme ngwa ngwa Nios V/c Kọmpat Microcontroller Altera FPGA IP Figure 4. Nios V/c Kọmpat Microcontroller Altera FPGA IP

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2.1.1.1.1. CPU Architecture Tab

Tebụl 2.

CPU Architecture Tab

Njirimara

Nkọwa

Kwado Interface Avalon® na-enyere Avalon Interface maka njikwa nkuzi na njikwa data. Ọ bụrụ na ọ nwere nkwarụ, sistemụ ahụ na-eji interface AXI4-Lite.

uru CSR

Nhọrọ IP na-ezighi ezi. · Ejila mhartid CSR uru na Nios V/c processor.

2.1.1.1.2. Jiri Taabụ Tọgharia arịrịọ

Tebụl 3.

Jiri Ntụgharị Taabụ Tọgharia arịrịọ

Jiri Taabụ Tọgharia arịrịọ

Nkọwa

Tinye interface arịrịọ nrụpụta

Kwado nhọrọ a ikpughe ọdụ ụgbọ mmiri nrụpụta mpaghara ebe onye nwe obodo nwere ike iji ya kpalite Nios V processor ka ọ tọgharịa na-emetụtaghị ihe ndị ọzọ dị na sistemụ nhazi Nios V.
Ihe nrụgharịgharị ahụ nwere mgbama ntinye restreq na mgbama ack mmepụta.
Ị nwere ike ịrịọ maka nrụpụta na Nios V processor core site n'ịkwado mgbama resetreq.
· Mgbama resetreq ga-anọgide na-ekwupụta ruo mgbe onye nrụpụta na-ekwupụta akara ngosi ack. Ọdịda maka mgbama ahụ ka ọ nọgide na-ekwusi ike nwere ike ime ka nhazi ahụ nọrọ n'ọnọdụ enweghị ike ikpebi.
Ihe nhazi Nios V na-aza na nrụpụta ahụ na-aga nke ọma site n'ịkwado akara ngosi ack.
· Mgbe processor na-ọma tọgharịa, nkwuputa nke ack mgbaàmà nwere ike ime otutu ugboro oge ruo mgbe de-nkwuputa nke resetreq mgbaàmà.

2.1.1.1.3. Ọnyà, Mpụga, na Taabụ nkwụsị

Tebụl 4.

Ọnyà, Mpụga, na nkwụsịtụ Ntọala Tab

Ọnyà, Mpụga, na nkwụsị

Nkọwa

Tọgharia ihe nnọchite anya

Tọgharia nkwụghachi

· Ezipụta nkwụghachi nke vector nrụpụta n'akụkụ adreesị ntọala nke onye nrụpụta ahọpụtara. · Platform Designer na-akpaghị aka na-enye ndabara uru maka nrụpụta nrụpụta.

Mara:

Onye nrụpụta Platform na-enye nhọrọ zuru oke, nke na-enye gị ohere ịkọwa adreesị zuru oke na Tọgharia Offset. Jiri nhọrọ a mgbe ebe nchekwa na-echekwa vector nrụpụta dị na mpụga sistemu nhazi na sistemụ.

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2.1.1.1.4. ECC Tab

Tebụl 5.

ECC Tab

ECC

Kwado nchọpụta mperi na mkpesa ọnọdụ

Nkọwa
Kwado nhọrọ a ka itinye atụmatụ ECC maka ihe mgbochi RAM n'ime Nios V. Njirimara ECC chọpụta ihe ruru mperi 2-bit wee meghachi omume dabere na omume ndị a:
- Ọ bụrụ na ọ bụ a correctable njehie 1-bit, processor na-aga n'ihu na-arụ ọrụ mgbe agbazi njehie na processor pipeline. Agbanyeghị, mgbazi adịghị egosipụta na ncheta isi mmalite.
- Ọ bụrụ na njehie bụ uncorrectable, processor na-aga n'ihu na-arụ ọrụ na-enweghị mgbazi ya na processor pipeline na isi iyi na-echeta, nke nwere ike ime ka processor banye nondeterministic ala.

2.1.1.2. Na-eme ngwa ngwa Nios V/m Microcontroller Altera FPGA IP Figure 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Megharịa Tab

Tebụl 6.

Mezigharị Ntọala Tab

Megharịa Tab

Nkọwa

Kwado nbibi
Kwado Tọgharia site na modul nbipu

Kwado nhọrọ a ka ịgbakwunye JTAG modul njikọ ebumnuche na processor Nios V. · Ndị JTAG modul njikọ ebumnuche na-enye ohere ijikọ na Nios V processor site na
JTAG interface pin nke FPGA. · Njikọ ahụ na-enye ikike ndị a bụ isi:
- Malite ma kwụsị ihe nhazi Nios V - Nyochaa ma dezie ndekọ na ebe nchekwa. - Budata ngwa Nios V .elf file na ebe nchekwa processor na oge ojiri gaa site
niosv-nbudata. - Debug ngwa na-agba ọsọ na Nios V processor · Jikọọ dm_agent ọdụ ụgbọ mmiri na ntuziaka nhazi na ụgbọ ala data. Gbaa mbọ hụ na adreesị ntọala n'etiti ụgbọ ala abụọ ahụ bụ otu.
Kwado nhọrọ a ikpughe dbg_reset_out na ndm_reset_in ọdụ ụgbọ mmiri. · JTAG Debugger ma ọ bụ niosv-download -r iwu na-akpalite dbg_reset_out, nke
na-enye ohere nhazi Nios V iji tọgharịa akụkụ sistemu jikọtara na ọdụ ụgbọ mmiri a. Ị ga-ejikọrịrị dbg_reset_out interface na ndm_reset_in kama ịtọgharịa
interface iji kpalite nrụpụta na isi processor na modul ngụ oge. Ị gaghị ejikọta dbg_reset_out interface iji tọgharịa interface iji gbochie omume enweghị njedebe.

2.1.1.2.2. Jiri Taabụ Tọgharia arịrịọ

Tebụl 7.

Jiri Ntụgharị Taabụ Tọgharia arịrịọ

Jiri Taabụ Tọgharia arịrịọ

Nkọwa

Tinye interface arịrịọ nrụpụta

Kwado nhọrọ a ikpughe ọdụ ụgbọ mmiri nrụpụta mpaghara ebe onye nwe obodo nwere ike iji ya kpalite Nios V processor ka ọ tọgharịa na-emetụtaghị ihe ndị ọzọ dị na sistemụ nhazi Nios V.
Ihe nrụgharịgharị ahụ nwere mgbama ntinye restreq na mgbama ack mmepụta.
Ị nwere ike ịrịọ maka nrụpụta na Nios V processor core site n'ịkwado mgbama resetreq.
· Mgbama resetreq ga-anọgide na-ekwupụta ruo mgbe onye nrụpụta na-ekwupụta akara ngosi ack. Ọdịda maka mgbama ahụ ka ọ nọgide na-ekwusi ike nwere ike ime ka nhazi ahụ nọrọ n'ọnọdụ enweghị ike ikpebi.
· Nkwenye nke mgbama restreq na ọnọdụ debug enweghị mmetụta na steeti processor.
Ihe nhazi Nios V na-aza na nrụpụta ahụ na-aga nke ọma site n'ịkwado akara ngosi ack.
· Mgbe processor na-ọma tọgharịa, nkwuputa nke ack mgbaàmà nwere ike ime otutu ugboro oge ruo mgbe de-nkwuputa nke resetreq mgbaàmà.

2.1.1.2.3. Ọnyà, Mpụga, na Taabụ nkwụsị

Tebụl 8.

Ọnyà, Mpụga, na Taabụ nkwụsị

Nkọwa

Tọgharia ihe nnọchite anya

Tọgharia ọnọdụ nkwụsịtụ kwụsịrị

· Ezipụta nkwụghachi nke vector nrụpụta n'akụkụ adreesị ntọala nke onye nrụpụta ahọpụtara. · Platform Designer na-akpaghị aka na-enye ndabara uru maka nrụpụta nrụpụta.
Kpepụta ụdị njikwa nkwụsịtụ Direct ma ọ bụ Vectored. Mara: Ihe nrụpụta Nios V/m enweghị ọkpọkọ anaghị akwado nkwụsị Vectored.
Ya mere, zere iji ọnọdụ nkwụsịtụ Vectored mgbe onye nrụpụta nọ na ọnọdụ enweghị ọkpọkọ.

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Mara:

2.1.1.2.4. CPU Architecture

Tebụl 9.

Ihe nleba anya nke CPU Architecture

CPU Architecture

Nkọwa

Kwado pipelining na CPU

Kwado nhọrọ a iji wepụta ngwa nhazi Nios V/m pipelined. - IPC dị elu na ọnụ ahịa mpaghara mgbagha dị elu yana obere oge Fmax.
Gbanyụọ nhọrọ a ka ọ bụrụ ngwa ngwa Nios V/m processor na-abụghị ọkpọkọ. - Nwere arụmọrụ isi yiri nke Nios V/c processor. - Na-akwado ike debugging na nkwụsịtụ - Mpaghara mgbagha dị ala na ugboro Fmax dị elu na ọnụ ahịa IPC dị ala.

Kwado Interface Avalon

Na-akwado Interface Avalon maka njikwa nkuzi na njikwa data. Ọ bụrụ na ọ nwere nkwarụ, sistemụ ahụ na-eji interface AXI4-Lite.

uru CSR

· Ndebanye aha Hart ID (mhartid) uru bụ 0 na ndabara. · Kenye uru n'etiti 0 na 4094. · Dakọtara na Altera FPGA Avalon Mutex Core HAL API.

Ozi metụtara agbakwunyere ntuziaka onye ọrụ IP mpaghara – Intel FPGA Avalon® Mutex Core

2.1.1.2.5. ECC Tab
Isiokwu 10. ECC Tab
ECC Kwado nchọpụta mperi na mkpesa ọnọdụ

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2.1.1.3. Na-akwalite Nios V/g Onye Nhazi Nzube Ọhaneze Altera FPGA IP
Ọgụgụ 6. Nios V/g Onye Nhazi Nzube Ọhaneze Altera FPGA IP – Nkebi 1

Onyonyo 7.

Nios V/g Onye Nhazi Nzube Ozuruọnụ Altera FPGA IP – Nkebi nke 2 (Gbanyụọ Kwado Onye njikwa nkwụsịtụ isi ọkwa)

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 16

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Onyonyo 8.

Nios V/g Onye Nhazi Nzube Ozuruọnụ Altera FPGA IP – Nkebi 2 (Gbanye Kwado Onye njikwa nkwụsị nke ọkwa isi)

Ọgụgụ 9. Nios V/g Onye Nhazi Nzube Ọhaneze Altera FPGA IP – Nkebi 3

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Ọgụgụ 10. Nios V/g Onye Nhazi Nzube Ọhaneze Altera FPGA IP – Nkebi 4

2.1.1.3.1. CPU Architecture

Isiokwu 11. CPU Architecture Parameters

CPU Architecture Tab Kwado nkeji floating

Nkowa Kwado nhọrọ a ka ịtinye nkeji n'elu mmiri (“F” ndọtị) na isi ihe nrụpụta.

Kwado amụma Alaka

Kwado amụma alaka ụlọ ọrụ kwụ ọtọ (Alaghachi azụ na Agagharịghị ewere) maka ntuziaka alaka.

uru CSR

· Ndebanye aha Hart ID (mhartid) uru bụ 0 na ndabara. · Kenye uru n'etiti 0 na 4094. · Dakọtara na Altera FPGA Avalon Mutex Core HAL API.

Gbanyụọ ntuziaka FSQRT & FDIV maka FPU

· Wepu arụmọrụ square mgbọrọgwụ (FSQRT) na floating-point division (FDIV) arụ ọrụ na FPU.
Tinye nṅomi software na ntụziaka abụọ ahụ n'oge ọ na-agba ọsọ.

Ozi metụtara agbakwunyere ntuziaka onye ọrụ IP mpaghara – Intel FPGA Avalon® Mutex Core

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 18

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2.1.1.3.2. Megharịa Tab

Isiokwu 12. Debug Tab Parameters

Megharịa Tab

Nkọwa

Kwado nbibi
Kwado Tọgharia site na modul nbipu

2.1.1.3.3. Tebụl mkpọchi steepụ 13. Mkpọchi mgbachi
Paramita Kwado Mkpọchi step Ọdụm Oge Ọpụpụ Kwado ihu nrụgharị agbatịkwuru

Nkọwa · Kwado sistemu steepụ mkpọchi isi abuo. Uru ndabara nke oge mmemme nwere ike ime na ọpụpụ ntọgharị (n'etiti 0 na 255). Kwado ihe nrụgharị nrụpụta ndọtị agbakwunyere maka njikwa nrụpụta ndọtị agbatị. Mgbe ọ gbanyụrụ, fRSmartComp na-arụ ọrụ njikwa nrụpụta ntọala.

2.1.1.3.4. Jiri Taabụ Tọgharia arịrịọ

Tebụl 14. Jiri Paramita Tabghari arịrịọ nrụpụta

Jiri Taabụ Tọgharia arịrịọ

Nkọwa

Tinye interface arịrịọ nrụpụta

Kwado nhọrọ a ikpughe ọdụ ụgbọ mmiri nrụpụta mpaghara ebe onye nwe obodo nwere ike iji ya kpalite Nios V processor ka ọ tọgharịa na-emetụtaghị ihe ndị ọzọ dị na sistemụ nhazi Nios V.
Ihe nrụgharịgharị ahụ nwere mgbama ntinye restreq na mgbama ack mmepụta.
Ị nwere ike ịrịọ maka nrụpụta na Nios V processor core site n'ịkwado mgbama resetreq.
· Mgbama resetreq ga-anọgide na-ekwupụta ruo mgbe onye nrụpụta na-ekwupụta akara ngosi ack. Ọdịda maka mgbama ahụ ka ọ nọgide na-ekwusi ike nwere ike ime ka nhazi ahụ nọrọ n'ọnọdụ enweghị ike ikpebi.
· Nkwenye nke mgbama restreq na ọnọdụ debug enweghị mmetụta na steeti processor.
Ihe nhazi Nios V na-aza na nrụpụta ahụ na-aga nke ọma site n'ịkwado akara ngosi ack.
· Mgbe processor na-ọma tọgharịa, nkwuputa nke ack mgbaàmà nwere ike ime otutu ugboro oge ruo mgbe de-nkwuputa nke resetreq mgbaàmà.

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2.1.1.3.5. Ọnyà, Mpụga, na Taabụ nkwụsị

Tebụl 15.

Ọnyà, Mpụga, na Taabụ nkwụsị mgbe agbanyụrụ onye njikwa nkwụsị ọkwa isi

Ọnyà, Mpụga, na Taabụ nkwụsị
Tọgharia ihe nnọchite anya

Nkọwa
Ebe nchekwa na-anabata vector nrụpụta (adreesị nrụpụta nrụpụta Nios V) ebe koodu nrụpụta bi.
Ị nwere ike họrọ modul ebe nchekwa ọ bụla ejikọrọ na Nios V processor instruction master na nkwado nke Nios V processor boot flow dị ka onye nrụpụta nrụpụta.

Tọgharia nkwụghachi

Kwado onye njikwa nkwụsịtụ ọkwa isi (CLIC)

Kwado CLIC ka ọ kwado nkwụsị nkwụsịtụ na ọnọdụ nkwụsịtụ nwere ike ịhazi ya.
· Mgbe enyere gị aka, ị nwere ike hazie ọnụọgụ nkwụsị nke ikpo okwu, tọọ ọnọdụ ịkpalite, wee kọwaa ụfọdụ nkwụsị dị ka ihe na-ebu ụzọ.

Ndebanye aha onyinyo nkwụsịtụ Files

Ezipụta ụdị nkwụsịtụ dị ka Direct, ma ọ bụ Vectored Kwado aha onyinyo iji belata ntụgharị okwu mgbe nkwụsịtụ.

Tebụl 16.

Ọnyà, Mpụga na nkwụsị mgbe agbanyere njikwa nkwụsịtụ isi

Ọnyà, Mpụga, na nkwụsị

Nkọwa

Tọgharia ihe nnọchite anya
Tọgharia nkwụghachi
Kwado onye njikwa nkwụsịtụ ọkwa isi (CLIC)

Ebe nchekwa na-anabata vector nrụpụta (adreesị nrụpụta nrụpụta Nios V) ebe koodu nrụpụta bi.
Ị nwere ike họrọ modul ebe nchekwa ọ bụla ejikọrọ na Nios V processor instruction master na nkwado nke Nios V processor boot flow dị ka onye nrụpụta nrụpụta.
· Ezipụta nkwụghachi nke vector nrụpụta n'akụkụ adreesị ntọala nke onye nrụpụta ahọpụtara. · Platform Designer na-akpaghị aka na-enye ndabara uru maka nrụpụta nrụpụta.
Kwado CLIC ka ọ kwado nkwụsị nkwụsịtụ na ọnọdụ nkwụsịtụ nwere ike ịhazi ya. · Mgbe enyere gị aka, ị nwere ike hazie ọnụọgụ nkwụsị nke ikpo okwu, tọọ ọnọdụ ịkpalite,
ma họpụta ụfọdụ nkwụsị dị ka ihe na-ebute ụzọ.

Ụdị nkwụsị

Ezipụta ụdị nkwụsịtụ dị ka Direct, Vectored, ma ọ bụ CLIC.

Ndebanye aha onyinyo Files

Kwado ndebanye aha onyinyo iji belata ngbanwe ọnọdụ mgbe nkwụsịtụ.
· Na-enye ụzọ abụọ:
- Ọnụọgụ nkwụsịtụ CLIC
- Ọnụọgụ nkwụsịtụ CLIC - 1: Nhọrọ a bara uru mgbe ịchọrọ ọnụọgụ aha file mbipụta ga-adaba na ọnụọgụ M20K ma ọ bụ M9K.
Kwado ihe nhazi Nios V ka o jiri ndekọ onyinyo files nke na-ebelata ntụgharị okwu n'elu mgbe ọ kwụsịrị.
Maka ozi ndị ọzọ gbasara ndebanye aha onyinyo files, rụtụ aka na akwụkwọ ntuziaka Nios V Processor.

Ọnụọgụ nke ikpo okwu nkwụsị isi mmalite

Na-akọwapụta ọnụọgụ nkwụsịtụ ikpo okwu n'etiti 16 ruo 2048.
Mara: CLIC na-akwado ntinye nkwụsịtụ 2064, yana ntinye nkwụsịtụ 16 nke mbụ na-ejikọtakwa na njikwa nkwụsịtụ bụ isi.

Nhazi tebụl vector CLIC

· Kpebisie ike na-akpaghị aka dabere na ọnụ ọgụgụ isi mmalite nkwụsị nke ikpo okwu. Ọ bụrụ na ị na-eji nhazi nke dị n'okpuru uru akwadoro, CLIC na-abawanye mgbagha
mgbagwoju anya site n'ịgbakwụnye mgbakwunye mgbakwunye iji rụọ mgbakọ vectoring. · Ọ bụrụ na ị na-eji nhazi nke dị n'okpuru uru akwadoro, nke a na-ebute mmụba
mgbagwoju anya mgbagha na CLIC.
gara n'ihu…

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Ọnyà, Mpụga, na nkwụsị
Ọnụọgụ nke ọkwa nkwụsị
Ọnụọgụ nke ebute ụzọ n'otu ọkwa
Enwere ike ịhazi nkwụsịtụ polarity Nkwado akụkụ kpalitere nkwụsịtụ

Nkọwa
· Na-akọwapụta ọnụọgụ nkwụsịtụ yana ọkwa mgbakwunye 0 maka koodu ngwa. Nkwụsị nke ọkwa dị elu nwere ike ịkwụsị (bupu ụzọ) onye njikwa na-agba ọsọ maka nkwụsịtụ dị ala.
· Site na ọkwa nkwụsịtụ na-abụghị efu dị ka naanị nhọrọ maka nkwụsịtụ, koodu ngwa na-adị mgbe niile na ọkwa kachasị ala 0. Rịba ama: nhazi oge nkwụsị nke ọkwa nkwụsịtụ na ihe kachasị mkpa na-eme n'otu ndekọ 8-bit. Ọ bụrụ na ọnụọgụ nkwụsịtụ bụ 256, ọ gaghị ekwe omume ịhazi mkpa nkwụsịtụ n'oge ọsọ. Ma ọ bụghị ya, ọnụ ọgụgụ kachasị nke ihe ndị a na-ahazi bụ 256 / (ọnụọgụ nkwụsịtụ - 1).
· Na-akọwapụta ọnụọgụ nkwụsịtụ ụzọ, nke CLIC na-eji ekpebi usoro nke a na-akpọ ndị njikwa nkwụsịtụ na-adịghị ebu ụzọ. Mara: Mkpokọta ọnụ ahịa ọnụọgụ abụọ nke ọkwa nkwụsịtụ ahọpụtara na mkpa nkwụsị ahọpụtara ga-enwerịrị ihe na-erughị bit 8.
· Na-enye gị ohere ịhazi nkwụsịtụ polarity n'oge oge ojiri gaa. · Ndabere polarity bụ mma polarity.
Ọ na-enye gị ohere ịhazi ọnọdụ nkwụsịtụ n'oge oge ojiri gaa, ntụgharị ọkwa dị elu kpalitere ma ọ bụ ihe dị mma kpalitere (mgbe nkwụsịtụ polarity dị mma na Configurable interrupt polarity).
Ọndụ mkpalite ndabara na-ebute nkwụsịtụ.

Mara:

Ozi emetụtara Nios® V Akwụkwọ ntuziaka Processor

2.1.1.3.6. Tab nhazi nhazi ebe nchekwa

Tebụl 17. Ntọala nhazi nhazi ebe nchekwa

Otu

Tab nhazi ebe nchekwa

Nkọwa

Cache

Nha cache data

· Na-akọwa oke nke cache data. Nha ziri ezi sitere na 0 kilobytes (KB) ruo 16 KB. Gbanyụọ cache data mgbe nha bụ 0 KB.

Nha cache ntuziaka

· Ezipụta nha cache ntuziaka. Nha ziri ezi sitere na 0 KB ruo 16 KB. · Gbanyụọ cache ntụziaka mgbe nha bụ 0 KB.

Mpaghara Peripheral A na B

Nha

· Na-akọwapụta nha mpaghara mpaghara.
Nha ziri ezi sitere na 64 KB ruo 2 gigabytes (GB), ma ọ bụ Ọ nweghị. Ịhọrọ ọnweghị nke na-egbochi mpaghara mpụta.

Adreesị isi

· Ezipụta adreesị ntọala nke mpaghara mpaghara mgbe ịhọrọchara nha.
Adreesị niile dị na mpaghara mpaghara na-emepụta ohere data enweghị ike ịchọta.
Adreesị ntọala mpaghara ga-adakọrịrị na nha mpaghara mpaghara.

Ncheta jikọtara nke ọma

Nha

Na-akọwapụta nha ebe nchekwa jikọtara ọnụ. - Ogo nha sitere na 0 MB ruo 512 MB.

Mmalite adreesị ntọala File

Na-akọwapụta adreesị ntọala nke ebe nchekwa jikọtara ọnụ. · Ezipụta mmalite file maka ebe nchekwa jikọtara ọnụ.

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Mara:

N'ime sistemụ nhazi Nios V nwere oghere oghere, ị ga-edobe akụkụ sistemu n'ime mpaghara mpụta. Ị nwere ike iji mpaghara mpụta iji kọwaa azụmahịa enweghị ike ịchekwa maka akụkụ dị ka UART, PIO, DMA, na ndị ọzọ.

2.1.1.3.7. ECC Tab

Isiokwu 18. ECC Tab
ECC Kwado nchọpụta mperi na mkpesa ọnọdụ
Kwado Ndozi Otu Bit

Nkọwa
Kwado nhọrọ a ka itinye atụmatụ ECC maka ihe mgbochi RAM n'ime Nios V. Njirimara ECC chọpụta ihe ruru mperi 2-bit wee meghachi omume dabere na omume ndị a:
- Ọ bụrụ na ọ bụ a correctable otu bit njehie na Kwado Single Bit Mmezi agbanyụrụ, processor na-aga n'ihu na-arụ ọrụ mgbe agbazi njehie na processor pipeline. Agbanyeghị, mgbazi adịghị egosipụta na ncheta isi mmalite.
- Ọ bụrụ na ọ bụ a correctable otu bit njehie na Kwado Single Bit mmezi agbanwuru, processor na-aga n'ihu na-arụ ọrụ mgbe agbazi njehie na processor pipeline na isi iyi na-echeta.
- Ọ bụrụ na ọ bụ njehie na-enweghị ike idozi, onye nrụpụta na-akwụsị ọrụ ya.
Kwado mmezi otu ntakịrị na ngọngọ ebe nchekwa agbakwunyere na isi.

2.1.1.3.8. Tab ntụziaka omenala

Mara:

Nke a taabụ dị naanị maka Nios V/g processor core.

Ntuziaka Omenala Nios V Omenala Ntuziaka ngwaike Interface Tebụl
Nios V Omenala Ntuziaka Software Macro Tebụl

Nkọwa
· Nios V processor na-eji nke a tebụl kọwaa ya omenala ntụziaka njikwa interfaces.
0 - Opcode (CUSTOM3-3) na 7 ibe n'ibe nke ọrụ kpuchiri oghere njikwa ntụziaka omenala akọwapụtara n'ụzọ pụrụ iche.
Ị nwere ike kọwaa ruo ngụkọta nke 32 onye omenala ntụziaka interfaces.
· Nios V processor na-eji tebụl a na-eji kọwaa omenala ntụziaka software encodings maka kọwaa omenala ntụziaka interfaces.
N'ihi na onye ọ bụla akọwapụtara ntuziaka ntuziaka software encoding, na Opcode (CUSTOM0-3) na 3 ibe n'ibe nke function7[6:4] encoding ga-emekọrịtara na a kọwaa omenala ntụziaka interface encoding na Custom Ntuziaka Hardware Interface Tebụl.
Ị nwere ike iji funct7[6:4], funct7[3:0], na funct3[2:0] kọwapụta agbakwunyere ngbanwe maka nkuzi omenala enyere, ma ọ bụ akọwapụtara dị ka X ka a ga-ebufe dị ka arụmụka nkuzi ọzọ.
Ihe nhazi Nios V na-enye nkọwa sọftụwia ntuziaka akọwapụtara dị ka emepụtara C-macros na system.h, ma soro usoro nkuzi ụdị R-RISC-V.
Enwere ike iji mnemonics kọwaa aha omenala maka: - C-Macros emepụtara na system.h.
- Mnemonics GDB ewepụtara na custom_instruction_debug.xml.

Ozi metụtara
AN 977: Ntuziaka omenala Nios V Processor Maka ozi ndị ọzọ gbasara ntuziaka omenala na-enye gị ohere ịhazi nhazi Nios® V iji gboo mkpa nke otu ngwa.

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 22

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2.1.2. Na-akọwapụta akụkụ sistemụ
Jiri Platform Designer kọwapụta njirimara ngwaike nke sistemụ nhazi Nios V wee tinye n'ime ihe ndị achọrọ. Eserese na-esonụ na-egosi nhazi usoro nhazi Nios V nke nwere ihe ndị a: · Nios V processor core · On-Chip Memory · JTAG UART · Ngụ oge (nhọrọ) (1)
Mgbe agbakwunyere Ebe nchekwa On-Chip ọhụrụ na sistemụ Onye nrụpụta Platform, mee Sync System Infos iji gosipụta akụkụ ebe nchekwa agbakwunyere na nrụpụta. N'aka nke ọzọ, ị nwere ike mee ka mmekọrịta akpaaka na Platform Designer gosipụta mgbanwe akụrụngwa kachasị ọhụrụ na-akpaghị aka
Nyocha 11. Ọpụampnjikọ nke Nios V processor na akụkụ ndị ọzọ na Platform Designer

(1) Ị nwere nhọrọ iji njirimara Nios V Internal Timer iji dochie ngụ oge nke mpụga na Platform Designer.

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Ị ga-akọwarịrị ntụtụ ọrụ maka mbupụ dị ka conduit n'ime sistemụ Onye nrụpụta Platform gị. Maka example, a kọwapụtara ndepụta nrụ ọrụ FPGA kwesịrị ekwesị dị ka n'okpuru mana ọnweghị oke na:
· Elekere
· Tọgharia
· Mgbama m/O
2.1.3. Na-akọwapụta adreesị ntọala yana ihe ndị ga-ebute ụzọ na-arịọ arịrịọ
Iji kọwapụta ka ihe ndị agbakwunyere na nhazi ahụ si emekọrịta iji mepụta usoro, ịkwesịrị ịnye adreesị ntọala maka akụrụngwa nnọchite ọ bụla wee kenye arịrịọ nkwụsịtụ (IRQ) ụzọ maka J.TAG UART na oge etiti oge. Onye nrụpụta Platform na-enye iwu - Nyefee adreesị ntọala - nke na-ekenye adreesị ntọala kwesịrị ekwesị na ihe niile dị na sistemụ na-akpaghị aka. Agbanyeghị, ịnwere ike ịhazigharị adreesị ntọala dabere na mkpa gị.
Ndị a bụ ụfọdụ ntuziaka maka ikenye adreesị ntọala:
Nios V processor core nwere ogologo adreesị 32-bit. Iji nweta akụrụngwa ndị nnọchite anya, adreesị ntọala ha ga-adị n'etiti 0x00000000 na 0xFFFFFFFF.
· Mmemme Nios V na-eji ihe atụ agbanwe agbanwe na-ezo aka na adreesị. Ị gaghị ahọrọ ụkpụrụ adreesị ndị dị mfe icheta.
· ụkpụrụ adreesị nke na-eme ka ihe dị iche iche na-eji naanị otu-bit dị iche iche na-emepụta ngwaike na-arụ ọrụ nke ọma. Ịkwesighi ịkwakọba adreesị ntọala niile n'ime ebe adreesị kacha nta nwere ike ime n'ihi na compacting nwere ike ịmepụta ngwaike na-adịghị mma.
Onye nrụpụta Platform anaghị anwa ịhazi akụkụ ebe nchekwa dị iche iche na ebe nchekwa na-aga n'ihu. Maka exampYabụ, ọ bụrụ na ịchọrọ ọtụtụ ihe nchekwa On-Chip ebe nchekwa nwere ike ịkọwa dị ka ebe nchekwa na-aga n'ihu, ị ga-ekenye adreesị ntọala n'ụzọ doro anya.
Onye nrụpụta Platform na-enyekwa iwu akpaaka - Nyefee ọnụọgụ nkwụsị nke jikọtara akara IRQ iji mepụta nsonaazụ ngwaike dị mma. Agbanyeghị, ikenye IRQ nke ọma chọrọ nghọta nke omume nzaghachi sistemu niile. Onye nrụpụta Platform enweghị ike ịkọ nkọ maka ọrụ IRQ kacha mma.
Uru IRQ kacha ala nwere ihe kacha mkpa. N'ime usoro dị mma, Altera na-atụ aro ka mpaghara ngụ oge nwee IRQ kachasị mkpa, ya bụ, uru kacha nta, iji nọgide na-enwe izi ezi nke akara elekere sistemụ.
N'ọnọdụ ụfọdụ, ị nwere ike ịkenye ihe kacha mkpa na mpụta oge (dị ka ndị na-ahụ maka vidiyo), nke chọrọ ọnụego nkwụsịtụ dị elu karịa ngwa ngụ oge.
Ozi metụtara
Ntuziaka onye ọrụ Quartus Prime Pro Edition: Ozi ndị ọzọ gbasara ịmepụta Sistemu na Onye Mmebe Platform.

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2.2. Na-ejikọta Sistemụ Mmebe Platform n'ime Quartus Prime Project
Mgbe emechara nhazi sistemụ Nios V na Platform Designer, rụọ ọrụ ndị a iji tinye modul sistemu Nios V n'ime ọrụ nhazi Quartus Prime FPGA. Melite modul Nios V ngwa ngwa na Quartus Prime project · Jikọọ akara sitere na modul sistemu Nios V gaa na akara ndị ọzọ na mgbagha FPGA · Kenye ebe ntụtụ anụ ahụ · Machie imewe FPGA
2.2.1. Ịmelite Module Sistemu Nhazi Nios V na Quartus Prime Project
Onye nrụpụta Platform na-ewepụta ihe eji emepụta modul sistemu nke ị nwere ike itinye ozugbo na Quartus Prime. Otu esi eme ka modul sistemu ngwa ngwa dabere na usoro ntinye imewe maka oru Quartus Prime n'ozuzu ya. Maka exampYa mere, ọ bụrụ na ị na-eji Verilog HDL maka ntinye imewe, mee ka modul dabere na Verilog. Ọ bụrụ na-amasị gị iji usoro eserese ngọngọ maka ntinye imewe, tinye akara modul sistemu .bdf file.
2.2.2. Ijikọ akara na ikenye ebe pin anụ ahụ
Iji jikọọ imewe Altera FPGA gị na nhazi ọkwa bọọdụ gị, rụọ ọrụ ndị a: · Chọpụta ọkwa dị elu. file maka imewe gị na akara iji jikọọ na Altera mpụga
FPGA ngwaọrụ atụdo. · Ghọta atụdo ị ga-ejikọ site na ntuziaka onye ọrụ nhazi ọkwa bọọdụ gị ma ọ bụ
schematics. · Kenye akara n'ụdị ọkwa dị elu n'ọdụ ụgbọ mmiri dị na ngwaọrụ Altera FPGA gị nwere pin
ngwa ọrụ.
Sistemụ nrụpụta Platform gị nwere ike ịbụ nhazi ọkwa kachasị elu. Agbanyeghị, Altera FPGA nwekwara ike ịgụnye mgbagha ọzọ dabere na mkpa gị wee webata ọkwa dị elu nke omenala. file. Nke kacha-ọkwa file na-ejikọta akara modul processor Nios V na mgbama imewe Altera FPGA ọzọ.
Ozi emetụtara Quartus Prime Pro ntuziaka onye ọrụ: Mgbochi imewe
2.2.3. Na-amachibido imewe Altera FPGA
Nhazi sistemu Altera FPGA kwesịrị ekwesị gụnyere mmachi imewe iji hụ na imewe ahụ mezuru mmechi oge yana ihe mgbochi mgbagha ndị ọzọ. Ị ga-amachibido imewe Altera FPGA gị iji mezuo ihe ndị a n'ụzọ doro anya site na iji ngwaọrụ ndị enyere na Quartus Prime software ma ọ bụ ndị na-enye EDA ndị ọzọ. Akụrụngwa Quartus Prime na-eji mmachi enyere n'oge usoro nchịkọta iji nweta nsonaazụ ntinye kacha mma.

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Ozi metụtara · Quartus Prime Pro Edition Guide User: Constraints Design · Partners EDA Partners · Quartus Prime Pro Edition Guide User Guide: Time Analyzer
2.3. Ịmepụta Sistemụ ebe nchekwa Nios V Processor
Akụkụ a na-akọwa omume kachasị mma maka ịhọrọ ngwaọrụ ebe nchekwa na sistemu Platform Designer nwere ihe nrụpụta Nios V yana ịrụ ọrụ kacha mma. Ngwa ebe nchekwa na-arụ ọrụ dị oke mkpa n'ịkwalite arụmọrụ n'ozuzu nke sistemu agbakwunyere. Ebe nchekwa sistemu agbakwunyere na-echekwa ntuziaka mmemme na data.
2.3.1. Ebe nchekwa na-adịghị agbanwe agbanwe
Isi ihe dị iche na ụdị ebe nchekwa bụ mgbanwe. Ebe nchekwa na-adịghị agbanwe agbanwe na-ejide naanị ọdịnaya ya mgbe ị na-enye ike na ngwaọrụ ebe nchekwa. Ozugbo i wepụrụ ike, ebe nchekwa na-atụfu ọdịnaya ya.
ExampEbe nchekwa na-agbanwe agbanwe bụ RAM, cache na ndekọ. Ndị a bụ ụdị ebe nchekwa ngwa ngwa na-abawanye arụmọrụ na-agba ọsọ. Altera na-akwado ka ibu ma mebie ntuziaka nhazi Nios V na RAM wee jikọta Nios V IP core na On-Chip Memory IP ma ọ bụ Interface ebe nchekwa Mpụga IP maka ịrụ ọrụ kacha mma.
Iji meziwanye arụmọrụ, ị nwere ike iwepụ ngwa mgbakwunye Platform Designer site na ijikọ ụdị interface data njikwa data Nios V nwere RAM buut. Maka exampYa mere, ị nwere ike hazie On-Chip Memory II na interface AXI-32 4-bits, nke dabara na interface njikwa data Nios V.
Ozi metụtara · Interfaces ebe nchekwa mpụ IP Ebe nchekwa · Ebe nchekwa On-Chip (RAM ma ọ bụ ROM) Altera FPGA IP · On-Chip Memory II (RAM or ROM) Altera FPGA IP · Nios V Processor Application Execute-In-Place from OCRAM na ibe 54
2.3.1.1. Nhazi ebe nchekwa On-Chip RAM ma ọ bụ ROM
Ị nwere ike hazie Altera FPGA On-Chip Memory IP dị ka RAM ma ọ bụ ROM. RAM na-enye ike ịgụ na ide ma nwee ọdịdị na-agbanwe agbanwe. Ọ bụrụ na ị bụ
na-ebupụ ihe nhazi Nios V site na On-Chip RAM, ị ghaghị ijide n'aka na echekwara ọdịnaya buut ma ghara imerụ ya ma ọ bụrụ na a tọgharịa n'oge oge ịgba ọsọ. Ọ bụrụ na ihe nrụpụta Nios V na-ebupụ site na ROM, ahụhụ sọftụwia ọ bụla dị na Nios V processor enweghị ike idegharị ọdịnaya nke Ebe nchekwa On-Chip n'ụzọ na-ezighi ezi. Ya mere, ibelata ihe ize ndụ nke nrụrụ ngwanrọ buut.
Ozi metụtara · Ebe nchekwa On-Chip (RAM ma ọ bụ ROM) Altera FPGA IP · On-Chip Memory II (RAM or ROM) Altera FPGA IP · Nios V Processor Application Execute-In-place from OCRAM na ibe 54

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2.3.1.2. Cache
A na-ejikarị ebe nchekwa on-chip mejuputa arụ ọrụ cache n'ihi obere oge ha dị ala. Ihe nhazi Nios V na-eji ebe nchekwa on-chip maka nkuzi ya na cache data. Ikike oke nke ebe nchekwa na mgbawa anaghị abụkarị okwu maka cache n'ihi na ha na-adịkarị obere.
A na-ejikarị cache eme ihe n'okpuru ọnọdụ ndị a:
Ebe nchekwa oge niile dị na mgbanyụ ọkụ ma nwee ohere ịnweta ogologo karịa ebe nchekwa na mgbawa.
· Akụkụ arụmọrụ-dị oke egwu nke koodu ngwanrọ nwere ike dabara na cache nkuzi, na-emezi arụmọrụ sistemụ.
· Akụkụ arụmọrụ-dị oke mkpa, nke a na-ejikarị eme ihe nke data nwere ike dabara na cache data, na-eme ka arụmọrụ sistemụ dị mma.
Ịkwado caches na Nios V processor na-emepụta ọkwa ebe nchekwa, nke na-ebelata oge ịnweta ebe nchekwa.
2.3.1.2.1. Mpaghara mpaghara
Agaghị echekwa mpaghara IP ọ bụla agbakwunyere, dị ka UART, I2C, na SPI. A na-atụ aro cache nke ukwuu maka ncheta mpụga nke oge nnweta ogologo na-emetụta, ebe enwere ike ịwepu ihe ncheta ime n'ihi obere ohere ha. Ị gaghị echekwa IP ọ bụla agbakwunyere, dị ka UART, I2C, na SPI, belụsọ maka ncheta. Nke a dị mkpa n'ihi na ihe omume sitere na ngwaọrụ ndị dị na mpụga, dị ka ngwaọrụ ndị nnọchi anya na-emelite IP dị nro, anaghị ejide cache processor, n'aka nke ya, onye nrụpụta anaghị anabata ya. N'ihi ya, ihe omume ndị a nwere ike ghara ịhụta ruo mgbe ị na-ehichapụ cache, nke nwere ike iduga omume na-atụghị anya ya na usoro gị. Na nchịkọta, mpaghara ebe nchekwa mapụtara nke IP dị n'akụkụ agbakwunyere enweghị ike ịchekwa ya ma ga-ebirịrị n'ime mpaghara ihe nrụpụta.
Ka ịtọọ mpaghara mpụta, soro usoro ndị a:
1. Mepee Map Adreesị sistemu na Onye nrụpụta Platform.
2. Gaa na map adreesị nke processor's Ntuziaka Manager na Data Manager.
3. Chọpụta peripherals na ebe nchekwa na sistemụ gị.
Nyocha 12. Ọpụample nke adreesị Map

Mara: Àkụ na-acha anụnụ anụnụ na-atụ aka na ncheta. 4. Kpọkọta ihe ndị dị n'akụkụ:
a. Ebe nchekwa dị ka cacheable b. Peripherals dị ka enweghị ike ịchọta

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Tebụl 19. Mpaghara nwere ike ịchebe na enweghị ike ịchọta

N'okpuru

Maapụ Adreesị

Ọnọdụ

Mpaghara mpaghara

Nha

Adreesị isi

user_application_mem.s1

0x0 ~ 0x3ffff

Enwere ike ịchekwa

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Enweghị ike ịchọta cache

65536 bytes N/A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Enweghị ike ịchọta cacheable enweghị ike ịchọta

144 bytes (nha nkeji bụ 65536 bytes)

0x54000

sysid_qsys_0.control_ohu

0x54080 ~ 0x54087

Enweghị ike ịchọta

uart.avalon_jtag_ohu

0x54088 ~ 0x5408f

Enweghị ike ịchọta

5. Dozie mpaghara ndị dị n'akụkụ na nha ha kpọmkwem:
· Dịka ọmụmaatụample, ọ bụrụ na nha bụ 65536 bytes, ọ dabara na 0x10000 bytes. Ya mere, adreesị ntọala ekwenyere ga-abụrịrị ọnụọgụ nke 0x10000.
· CPU.dm_agent na-eji adreesị ntọala nke 0x40000, nke bụ otutu nke 0x10000. N'ihi ya, Peripheral Region A, nke nwere nha 65536 bytes na adreesị ntọala nke 0x40000, na-emezu ihe achọrọ.
· Adreesị isi nke nchịkọta mpaghara a na-apụghị ịchọta na 0x54000 abụghị otutu nke 0x10000. Ị ga-ekenye ha na 0x60000 ma ọ bụ ọtụtụ ndị ọzọ nke 0x10000. Ya mere, Peripheral Region B, nke nwere nha 65536 bytes na adreesị ntọala nke 0x60000, na-egbo njirisi.

Tebụl 20. Mpaghara nwere ike ịchekwa na enweghị ike ịchekwa ya na ntinyegharị ya

N'okpuru

Maapụ Adreesị

Ọnọdụ

Mpaghara mpaghara

Nha

Adreesị isi

user_application_mem.s1

0x0 ~ 0x3ffff

Enwere ike ịchekwa

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

65536 bytes enweghị ike ịchọta

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Enwere ike ịchekwa

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Enweghị ike ịchọta cacheable enweghị ike ịchọta

144 bytes (nha nkeji bụ 65536 bytes)

0x60000

uart.avalon_jtag_ohu

0x60088 ~ 0x6008f

Enweghị ike ịchọta

2.3.1.3. Ebe nchekwa jikọtara nke ọma
A na-etinye ihe ncheta jikọtara ọnụ (TCM) site na iji ebe nchekwa on-chip ka obere nkwụsị ha na-eme ka ha dabara nke ọma na ọrụ ahụ. TCM bụ ihe ncheta mapụtara na oghere adreesị a na-ahụkarị mana ha nwere interface raara onwe ya nye microprocessor ma nwee arụmọrụ dị elu, njirimara dị ala nke ebe nchekwa cache. TCM na-enyekwa interface dị n'okpuru maka ndị ọbịa na-apụ apụ. Onye nrụpụta na onye nnabata mpụga nwere otu ikike ikike ijikwa TCM.

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Mara:

Mgbe ejikọrọ ọdụ ụgbọ mmiri dị n'okpuru TCM na onye ọbịa mpụga, enwere ike igosipụta ya na adreesị ntọala dị iche karịa adreesị ntọala ekenyere na isi ihe nrụpụta. Altera na-atụ aro ka ịhazi adreesị abụọ ahụ n'otu uru.

2.3.1.4. Interface ebe nchekwa mpụga (EMIF)
EMIF (Mpụga ebe nchekwa Interface) na-arụ ọrụ n'otu aka ahụ na SRAM (Static Random Access Memory), mana ọ na-arụ ọrụ ma na-achọ ume ọhụrụ oge iji dowe ọdịnaya ya. Mkpụrụ ndụ ebe nchekwa dị ike na EMIF dị obere karịa sel ebe nchekwa static dị na SRAM, nke na-ebute ikike dị elu yana ngwaọrụ ebe nchekwa dị ọnụ ala.
Na mgbakwunye na mkpa ume ọhụrụ a chọrọ, EMIF nwere ihe achọrọ interface akọwapụtara nke na-achọkarị ngwaike njikwa pụrụ iche. N'adịghị ka SRAM, nke nwere ahịrị adreesị edobere, EMIF na-ahazi oghere ebe nchekwa ya n'ime ụlọ akụ, ahịrị, na kọlụm. Ịgbanwe n'etiti ụlọ akụ na ahịrị na-ewebata ụfọdụ ihe karịrị, yabụ ị ga-eji nlezianya tụọ ebe nchekwa ohere iji EMIF rụọ ọrụ nke ọma. EMIF na-atụgharịkwa adreesị ahịrị na kọlụm n'otu ahịrị adreesị ahụ, na-ebelata ọnụọgụ ntụtụ achọrọ maka nha EMIF nyere.
Ụdị EMIF dị elu dị elu, dị ka DDR, DDR2, DDR3, DDR4, na DDR5, na-etinye ihe nrịbama siri ike nke ndị na-emepụta PCB ga-atụle.
Ngwa EMIF dị n'etiti ụdị RAM kachasị dị ọnụ ahịa yana ikike dị elu, na-eme ka ha bụrụ nhọrọ a ma ama. Otu akụkụ dị mkpa nke interface EMIF bụ EMIF IP, nke na-ahụ maka ọrụ ndị metụtara ịza ajụjụ ọtụtụ, na-enye ume ọhụrụ, na ịgbanwe n'etiti ahịrị na ụlọ akụ. Nhazi a na-enye ohere ka usoro ndị ọzọ nweta EMIF na-enweghị mkpa ịghọta nhazi ime ya.

Ozi emetụtara Interfaces ebe nchekwa mpụga ebe nchekwa IP

2.3.1.4.1. Adreesị Span Extender IP
Adreesị Span Extender Altera FPGA IP na-enye ohere oghere ndị ọbịa nwere mapụtara ebe nchekwa iji nweta maapụ adreesị buru ibu ma ọ bụ pere mpe karịa obosara akara adreesị ha na-enye ohere. Adreesị Span Extender IP na-ekewa oghere enwere ike ịza n'ime ọtụtụ windo dị iche iche ka onye ọbịa nwee ike ịnweta akụkụ kwesịrị ekwesị nke ebe nchekwa site na windo.
Adreesị Span Extender anaghị ejedebe obosara ndị ọbịa na ndị nnọchi anya na nhazi 32-bit na 64bit. Ị nwere ike iji Adreesị Span Extender nwere windo adreesị 1-64 bit.

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Ọgụgụ 13. Adreesị Span Extender Altera FPGA IP
Adreesị Okwu Onye nnọchite anya

Adreesị Span Extender

Tebụl eserese
Ọdụ ụgbọ mmiri Control A

…

Njikwa ndekọ 0 Njikwa ndekọ Z-1

Adreesị ndị ọbịa gbasapụrụ H

Ozi metụtara
Ntuziaka onye ọrụ Quartus® Prime Pro Edition: Platform Designer Rụtụ aka na isiokwu Span Extender Intel® FPGA IP maka ozi ndị ọzọ.

2.3.1.4.2. Iji Adreesị Span Extender IP na Nios V Processor
Ihe nhazi Nios V nke 32-bit nwere ike ikwu ihe ruru 4 GB nke ogologo adreesị. Ọ bụrụ na EMIF nwere ihe karịrị 4GB nke ebe nchekwa, ọ gafere ogologo adreesị akwadoro, na-eme ka sistemu Platform Designer bụrụ nke ezighi ezi. Achọrọ IP Span Extender Adreesị iji dozie esemokwu a site n'ikesa otu oghere adreesị EMIF n'ime ọtụtụ windo ndị pere mpe.
Altera na-atụ aro ka ị tụlee paramita ndị a.

Tebụl 21. Parameters Span Extender Adreesị

Oke

Ntọala akwadoro

Obosara Data Ụzọ
obosara Adreesị Byte Master agbasagoro

Họrọ 32-bits, nke na-adabere na nhazi 32-bit. Dabere na nha ebe nchekwa EMIF.

Adreesị Okwu Ohu obosara Burstcount obosara

Họrọ 2 GB ma ọ bụ obere. Edobere ogologo oge adreesị nke Nios V maka IP ndị ọzọ agbakwunyere nro.
Malite na 1 wee jiri nwayọọ nwayọọ mụbaa uru a iji melite arụmọrụ.

Ọnụọgụ nke obere windo

Họrọ 1 sub-window ma ọ bụrụ na ị na-ejikọta EMIF na Nios V processor dị ka ntụziaka na ebe nchekwa data, ma ọ bụ ha abụọ. Ịgbanwe n'etiti ọtụtụ obere windo ka Nios V processor na-arụ ọrụ site na EMIF dị ize ndụ.

Kwado ọdụ ụgbọ mmiri njikwa ohu

Gbanyụọ ọdụ ụgbọ mmiri njikwa ohu ma ọ bụrụ na ị na-ejikọta EMIF na Nios V processor dị ka ntụziaka na/ma ọ bụ ebe nchekwa data. Otu nchegbu dị ka Ọnụọgụ nke obere windo.

Ọgụgụ kacha echere

Malite na 1 wee jiri nwayọọ nwayọọ mụbaa uru a iji melite arụmọrụ.

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Ọgụgụ 14. Ijikọ ntuziaka na onye njikwa data na adreesị Span Extender

Ọgụgụ 15. Mapping adreesị

Rịba ama na Adreesị Span Extender nwere ike ịnweta ohere nchekwa 8GB dum nke EMIF. Agbanyeghị, site na Adreesị Span Extender, Nios V processor nwere ike nweta naanị oghere ebe nchekwa 1GB mbụ nke EMIF.

Onyonyo 16. Ihe osise ngọngọ dị mfe

Sistemụ Mmebe Platform

Nke fọdụrụ 3 GB

Adreesị Nios V processor

span bụ maka agbakwunyere

NNioios sVV PProrocecsesosor r
M

IP dị nro na otu usoro.
1 GB windo

Ogologo adreesị

Ihe ndọtị

Naanị 1 GB mbụ

Ebe nchekwa EMIF jikọtara ya na Nios V

EMIF

nhazi.

8 GB
S

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2.3.1.4.3. Na-akọwapụta Adreesị Span Extender Linker Device Memory 1. Kọwaa Adreesị Span Extender (EMIF) dị ka vector nrụpụta. N'aka nke ọzọ, ị nwere ike kenye Nios V processor reset vector na ncheta ndị ọzọ, dị ka OCRAM ma ọ bụ ngwaọrụ flash.
Ọgụgụ 17. Ọtụtụ Nhọrọ dị ka Tọgharia Vector
Otú ọ dị, nchịkọta nkwado Board (BSP) enweghị ike ịdebanye aha na adreesị Span Extender (EMIF) ozugbo dị ka ebe nchekwa dị mma. Dabere na nhọrọ ị mere, ị na-ahụ ọnọdụ abụọ dị iche iche dị ka egosiri na ọnụ ọgụgụ ndị a. Ọgụgụ 18. Njehie BSP mgbe a na-akọwapụta Adreesị Span Extender (EMIF) dị ka Tọgharia Vector

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Ọgụgụ 19. EMIF na-efu efu mgbe a na-akọwapụta ncheta ndị ọzọ dị ka Vector tọgharịa

2. Ị ga-eji aka tinye Address Span Extender (EMIF) site na iji Tinye Device Memory, Tinye Linker Memory Region, na Tinye Njikọ Nkebi nkewa na BSP Linker Script tab.
3. Soro usoro ndị a:
a. Kpebie ebe adres nke dị n'Adres Span Extender site na iji Map ebe nchekwa (The example na ọnụ ọgụgụ ndị a na-eji Adreesị Span Extender nso site na 0x0 ruo 0x3fff_ffff).
Ọgụgụ 20. Ebe nchekwa Map

b. Pịa Tinye Ngwaọrụ ebe nchekwa, wee dejupụta dabere na ozi dị na Map ebe nchekwa nke imewe gị: i. Aha ngwaọrụ: emif_ddr4. Mara: Gbaa mbọ hụ na idetuo otu aha ahụ site na Map ebe nchekwa. ii. Adreesị isi: 0x0 iii. Nha: 0x40000000
c. Pịa Tinye ka ịgbakwunye mpaghara ebe nchekwa njikọ njikọ ọhụrụ:

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Tebụl 22. Na-agbakwụnye Mpaghara ebe nchekwa Linker

Nzọụkwụ

Tọgharịa Vector

emif_ddr4

Ihe ncheta ndị ọzọ

Tinye mpaghara ebe nchekwa Linker ọhụrụ akpọrọ nrụpụta. Tinye mpaghara ebe nchekwa Linker ọhụrụ maka

Aha mpaghara: tọgharịa

emif_ddr4.

Nha mpaghara: 0x20

· Aha mpaghara: emif_ddr4

· Ngwaọrụ ebe nchekwa: emif_ddr4

Nha mpaghara: 0x40000000

· Mwepu ebe nchekwa: 0x0

· Ngwaọrụ ebe nchekwa: emif_ddr4

· Mwepu ebe nchekwa: 0x0

Tinye mpaghara ebe nchekwa Linker ọhụrụ maka

nke fọdụrụ emif_ddr4.

· Aha mpaghara: emif_ddr4

Nha mpaghara: 0x3ffffffe0

· Ngwaọrụ ebe nchekwa: emif_ddr4

· Mwepu ebe nchekwa: 0x20

Ọgụgụ 21. Mpaghara Linker mgbe a na-akọwapụta Adreesị Span Extender (EMIF) dị ka Reset Vector

Ọgụgụ 22. Mpaghara Linker mgbe a na-akọwapụta ncheta ndị ọzọ dị ka Reset Vector
d. Ozugbo agbakwunyere emif_ddr4 na BSP, ị nwere ike họrọ ya maka ngalaba njikọ ọ bụla.
Ọgụgụ 23. Agbakwunyere Adreesị Span Extender (EMIF) na-aga nke ọma

e. Ileghara ịdọ aka ná ntị gbasara ngwaọrụ ebe nchekwa emif_ddr4 adịghị ahụ anya na nhazi SOPC.
f. Gaba n'ịmepụta BSP.
Ozi emetụtara Okwu Mmalite nke Nios V Processor usoro nbio na ibe 51

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2.3.2. Ebe nchekwa na-adịghị agbanwe agbanwe
Ebe nchekwa na-adịghị agbanwe agbanwe na-ejigide ọdịnaya ya mgbe ọkụ ahụ kwụsịrị, na-eme ka ọ bụrụ nhọrọ dị mma maka ịchekwa ozi nke usoro ahụ ga-eweghachite mgbe usoro ike usoro. Ebe nchekwa na-adịghị agbanwe agbanwe na-echekwaba koodu boot-processor, ntọala ngwa na-adịgide adịgide, yana data nhazi Altera FPGA. Ọ bụ ezie na ebe nchekwa na-adịghị agbanwe agbanwe nwere advantage nke idowe data ya mgbe ị na-ewepụ ike, ọ na-eji nwayọọ nwayọọ tụnyere ebe nchekwa na-agbanwe agbanwe, ma na-enwekarị usoro ederede na ihichapụ ihe mgbagwoju anya. Ebe nchekwa na-adịghị agbanwe agbanwe na-ekwekwa nkwa na a ga-ehichapụ ya ugboro ole na ole, ma emesịa ọ nwere ike ịda.
ExampEbe nchekwa na-adịghị agbanwe agbanwe gụnyere ụdị flash niile, EPROM na EEPROM. Altera na-atụ aro ka ị chekwaa Altera FPGA bitstreams na onyonyo mmemme Nios V na ebe nchekwa na-adịghị agbanwe agbanwe, ma jiri serial flash dị ka ngwaọrụ buut maka ndị nrụpụta Nios V.
Ozi metụtara
Ọdịnaya Serial Flash Interface Altera FPGA IP ntuziaka onye ọrụ
Onye ahịa igbe ozi Altera FPGA IP ntuziaka onye ọrụ · MAX® 10 ntuziaka onye ọrụ ebe nchekwa Flash: On-Chip Flash Altera FPGA IP Core
2.4. Elekere na Tọgharịa Omume Kachasị Mma
Ịghọta ka elekere nhazi Nios V na ngalaba nrụpụta na-emekọrịta ihe na mpaghara ọ bụla ọ na-ejikọta dị mkpa. Sistemụ nhazi Nios V dị mfe na-amalite site na otu ngalaba elekere, ọ nwere ike gbagwojuru anya na sistemu ngalaba elekere ọtụtụ mgbe ngalaba elekere ngwa ngwa na-adaba na ngalaba elekere nwayọ. Ịkwesịrị ịdeba ama ma ghọta ka usoro ngalaba ndị a dị iche iche si esite na nrụpụta wee hụ na enweghị nsogbu ọ bụla dị nro.
Maka omume kachasị mma, Altera na-atụ aro ka itinye Nios V processor na ebe nchekwa buut n'otu ngalaba elekere. Ewepụla ihe nrụpụta Nios V site na nrụpụta na ngalaba elekere ngwa ngwa mgbe ọ na-akpụ akpụ na ebe nchekwa nke bi na ngalaba elekere na-adịghị ngwa ngwa, nke nwere ike ibute njehie weta ntuziaka. Ị nwere ike ịchọ usoro nhazi akwụkwọ ntuziaka gafere ihe Platform Designer na-enye na ndabara, wee hazie nhazigharị topology ntọhapụ dabere na ikpe ojiji gị. Ọ bụrụ na ịchọrọ ịtọgharịa sistemụ gị ka ọ gachara ma na-agba ọsọ nwa oge, tinye otu echiche ahụ na usoro nrụpụta sistemụ na biputere mmalite mmalite chọrọ.
2.4.1. Sistemụ JTAG Elekere
Ịkọwapụta ihe mgbochi elekere na sistemụ nhazi Nios V ọ bụla bụ ihe dị mkpa nleba anya nhazi usoro ma achọrọ maka izi ezi na omume deterministic. Quartus Prime Time Analyzer na-eme nyocha oge kwụ ọtọ iji kwado arụmọrụ oge nke echiche niile dị na imewe gị site na iji mmachi, nyocha na usoro mkpesa ụlọ ọrụ.
Example 1. Isi elekere 100 MHz nwere okirikiri ọrụ 50/50 na 16 MHz JTAG Elekere
#************************************************** Mepụta elekere 100MHz #**************************** Mepụta elekere - aha {clk} -oge 10 [nweta_ọdụ ụgbọ mmiri {clk}] #******************** Mepụta 16MHz JTAG Elekere #************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Ozi metụtara Quartus Prime Time Analyzer Cookbook
2.4.2. Tọgharia arịrịọ arịrịọ
Ihe nrụpụta Nios V gụnyere ngwa nrụpụta nhọrọ nhọrọ. Ebe a na-arịọ arịrịọ nwere reset_req na reset_req_ack.
Iji mee ka arịrịọ nrụpụta nrụpụta dị na Platform Designer: 1. Ẹkedori Nios V Processor IP Parameter Editor. 2. Na-eji ntọala arịrịọ nrụpụta, gbanye Tinye nrụpụta arịrịọ Interface
nhọrọ.
Ọgụgụ 24. Kwado arịrịọ nrụpụta Nios V Processor
Mgbama reset_req na-eme dị ka nkwụsịtụ. Mgbe ị kwuputara reset_req, ị na-arịọ ka ịtọgharịa na isi. Isi ihe na-echere azụmahịa ụgbọ ala ọ bụla pụtara ìhè ka ọ rụchaa ọrụ ya. Maka example, ma ọ bụrụ na e nwere a na-echere ebe nchekwa ohere azụmahịa, isi na-echere a zuru ezu nzaghachi. N'otu aka ahụ, isi na-anabata nzaghachi ntụziaka ọ bụla na-echere mana ọ naghị enye arịrịọ ntụziaka mgbe ọ nwetasịrị mgbama reset_req.
Nrụgharị ọrụ nwere usoro a: 1. Mezue ọrụ niile na-echere 2. Ghichaa pipeline dị n'ime 3. Tọọ ihe omume mmemme na vector nrụpụta 4. Tọgharịa isi ihe nrụpụta ọrụ niile na-ewe okirikiri elekere ole na ole. The reset_req ga-anọgide na-ekwusi ike ruo mgbe reset_req_ack na-ekwuputa na-egosi isi nrụpụta ọrụ emechaala nke ọma. Emeghị nke a na-ebute na isi steeti abụghị ihe na-ekpebi ihe.

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2.4.2.1. Akpa eji eme ihe
Ị nwere ike kwupụta akara reset_req site na ike iji gbochie Nios V processor core ịmalite mmemme mmemme site na vector nrụpụta ya ruo mgbe ndị ọbịa FPGA ndị ọzọ nọ na sistemụ malite ebe nchekwa ihe nrụpụta Nios V. N'okwu a, sistemụ subsystem niile nwere ike nweta nrụpụta ngwaike dị ọcha. A na-ejide ihe nrụpụta Nios V ruo mgbe ebighị ebi na ọnọdụ nrụpụta nrụpụta ruo mgbe ndị ọbịa FPGA ndị ọzọ na-ebido ebe nchekwa buut processor.
· Na a usoro ebe ị ga-tọgharịa Nios V processor isi na-enweghị na-akpaghasị ndị ọzọ nke usoro, ị nwere ike ikwu na reset_req mgbaàmà ka ọcha kwụsị ọrụ ugbu a nke isi na Malitegharịa ekwentị processor si reset vector ozugbo usoro wepụtara reset_req_ack mgbaàmà.
· Onye na-ahụ maka mpụga nwere ike iji nrụgharị arịrịọ nrụgharị iji mee ka mmemme nke ọrụ ndị a dị mfe:
- Kwụsị mmemme nhazi Nios V dị ugbu a.
- Budata mmemme ọhụrụ n'ime ebe nchekwa ihe nrụpụta Nios V.
- Kwe ka processor malite na-emezu ihe omume ọhụrụ.
Altera na-atụ aro ka ị mejuputa usoro nkwụsị oge iji nyochaa ọnọdụ mgbama reset_req_ack. Ọ bụrụ na isi ihe nrụpụta Nios V dabara na ọnọdụ steeti echere na-enweghị ngwụcha wee daa n'ihi ihe amaghị ama, reset_req_ack enweghị ike ikwupụta ruo mgbe ebighi ebi. Usoro nhazi oge na-enyere gị aka:
· Kọwaa oge mgbake ma rụọ usoro mgbake na nrụpụta ọkwa sistemụ.
Mee nrụpụta ọkwa ngwaike.
2.4.3. Tọgharịa IP ntọhapụ
Ngwa dabere na Altera SDM na-eji ihe nrụkọ, ihe owuwu dabere na ngalaba nke na-ekesa mgbagha echiche akwa n'ofe ọtụtụ ngalaba. Altera na-atụ aro ka ị jiri Tọgharia Mwepụta Altera FPGA IP dịka otu ntinye mbụ na sekit nrụpụta. Ngwaọrụ dabere na Intel® SDM gụnyere Stratix® 10, yana ngwaọrụ AgilexTM. Ngwa ndị dabere na ngọngọ njikwa anaghị emetụta ihe a chọrọ.
Ozi metụtara
AN 891: Iji ntọgharị ntọhapụ Altera FPGA IP
2.5. Na-ekenye onye nnọchi anya ndabara
Onye nrụpụta Platform na-enye gị ohere ịkọwapụta onye nnọchi anya nke na-eme dị ka onye nnọchi anya nzaghachi njehie. Onye nnọchi anya nke ị họpụtara na-enye ọrụ nzaghachi njehie maka ndị ọbịa na-anwa ịbanye na maapụ adreesị nke enweghị koodu.
Ihe ndapụta ndị a na-ebute mmemme anaghị edepụta ya:
Nchebi obodo nchekwa azụmahịa ụgbọ ala
Nweta azụmahịa na mpaghara ebe nchekwa enweghị nkọwa
· Nwepu emume na wdg.

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Ekwesịrị inye onye nnọchi anya ndabara ka ọ na-ahụ maka mmemme ndị dị otú ahụ, ebe a na-ebugharị azụmahịa na-akọwaghị ya na onye nnọchi anya ma mechaa zaghachi processor Nios V na nzaghachi njehie.
Ozi metụtara
Ntuziaka onye ọrụ Quartus Prime Pro Edition: Onye nrụpụta Platform. Ịhọpụta onye nnọchi anya
Ntuziaka onye ọrụ Quartus Prime Pro Edition: Onye nrụpụta Platform. Nzaghachi mperi Ohu Altera FPGA IP
Github – Ngwa nrụpụta mgbakwunye maka Qsys

2.6. Na-ekenye onye nnọchi anya UART maka mbipụta
Mbipụta bara uru maka ịmegharị ngwa ngwanrọ, yana maka nyochaa ọkwa nke sistemụ gị. Altera na-akwado ibipụta ozi bụ isi dị ka ozi mmalite, ozi mperi, na mmezu nke ngwa ngwa ngwa.
Zere iji ọrụ printf() n'ọbá akwụkwọ n'okpuru ọnọdụ ndị a: · Ọbá akwụkwọ printf() na-eme ka ngwa ahụ kwụsị ma ọ bụrụ na ọ nweghị onye ọbịa na-agụpụta ihe.
Nke a dabara na JTAG UART naanị. Ọbá akwụkwọ printf() na-eri nnukwu ebe nchekwa mmemme.

2.6.1. Mgbochi ụlọ ahịa nke JTAG UART

Tebụl 23. Ọdịiche dị n'etiti UART ọdịnala na JTAG UART

Ụdị UART Omenala UART

Nkọwa
Na-ebufe data nsonazụ n'agbanyeghị ma onye ọbịa si mpụga na-ege ntị. Ọ bụrụ na ọ nweghị onye ọbịa na-agụ data serial, data ahụ efunahụla.

JTAG UART

Na-ede data ebufetara na ebe nchekwa mmepụta ma dabere na onye ọbịa na-apụ apụ ka ọ gụọ site na nchekwa ka ịtọpụ ya.

Ihe JTAG Onye ọkwọ ụgbọ ala UART na-echere mgbe ihe nchekwa mmepụta juru. Ihe JTAG Onye ọkwọ ụgbọ ala UART na-echere onye ọbịa na-apụ apụ ka ọ gụọ site na ntinye mmepụta tupu ya edekwuo data na-ebufe. Usoro a na-egbochi ọnwụ nke nnyefe data.
Agbanyeghị, ọ bụrụ na achọghị nbibi sistemu, dị ka n'oge mmepụta, a na-etinye sistemu agbakwunyere na-enweghị PC nnabata ejikọrọ na J.TAG UART. Ọ bụrụ na sistemụ ahụ ahọrọla JTAG UART dị ka onye na-ahụ maka UART, ọ nwere ike ime ka usoro nkwụsịtụ n'ihi na ọ nweghị ndị ọbịa mpụga jikọtara.
Iji gbochie nkwụsị nke JTAG UART, tinye n'ime nhọrọ ndị a:

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Tebụl 24. Mgbochi na Ịkwụsị site n'aka JTAG UART

Nhọrọ
Enweghị interface UART na onye ọkwọ ụgbọ ala dị ugbu a
Jiri interface UART ọzọ na ọkwọ ụgbọ ala
Chekwaa JTAG UART interface (na-enweghị ọkwọ ụgbọ ala)

N'oge Mmepe Ngwaike (na Platform Designer)

N'oge Mmepe Software (na nchịkọta nchịkọta nkwado Board)

Wepu JTAG UART sitere na sistemụ

Hazie hal.stdin, hal.stdout na hal.stderr ka ọ nweghị.

Dochie JTAG UART na ndị ọzọ dị nro Hazie hal.stdin, hal.stdout na hal.stderr

UART IP

ya na UART IP ndị ọzọ dị nro.

Chekwaa JTAG UART na sistemụ

Hazie hal.stdin, hal.stdout na hal.stderr ka ọ nweghị onye na nchịkọta ngwugwu nkwado Board.
Gbanyụọ JTAG UART ọkwọ ụgbọala na BSP Driver tab.

2.7. JTAG Akara ngosi
Nios V processor debug module na-eji JTAG interface maka nbudata ELF software na nbipu ngwanrọ. Mgbe ị na-eji JTAG interface, JTAG A na-emejuputa akara TCK, TMS, TDI, na TDO dịka akụkụ nke imewe. Na-akọwapụta JTAG Mgbochi mgbaàmà na sistemụ nhazi Nios V ọ bụla bụ ihe dị mkpa nleba anya imewe sistemụ ma achọrọ maka izi ezi na omume deterministic.
Altera na-atụ aro ka usoro elekere sistemụ ọ bụla nwere ọ dịkarịa ala okpukpu anọ karịa JTAG Ugboro elekere iji hụ na akụrụngwa on-chip instrumentation (OCI) na-arụ ọrụ nke ọma.
Ozi metụtara · Akwụkwọ nri Quartus® Prime Time Analyzer: JTAG Akara ngosi
Maka ozi ndị ọzọ gbasara JTAG ntuziaka mgbochi oge. KDB: Gịnị kpatara niosv-download na-eji ngwa Nios® V/m na-abụghị ọkpọkọ na
JTAG ugboro 24MHz ma ọ bụ 16Mhz?
2.8. Arụmọrụ Sistemụ Nrụpụta Platform na-ebuli elu
Onye nrụpụta Platform na-enye ngwaọrụ maka ịkwalite arụmọrụ nke sistemụ njikọ maka atụmatụ Altera FPGA.

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Ọgụgụ 25. Optimization Examples

The example egosiri na onu ogugu a gosiputara usoro ndia:
1. Na-agbakwunye akwa Pipeline iji belata ụzọ dị oke egwu site n'itinye ya: a. N'etiti Onye njikwa nkuzi na ndị nnọchi anya ya b. N'etiti Data Manager na ndị ọrụ ya
2. Tinye True Dual port On-Chip RAM, na ọdụ ụgbọ mmiri ọ bụla raara nye onye njikwa ntuziaka na onye njikwa data n'otu n'otu.

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Rụtụ aka na njikọ ndị a metụtara n'okpuru ebe a, nke na-enye usoro maka iji ngwá ọrụ dịnụ na ahia ahia nke mmejuputa iwu ọ bụla.
Ozi emetụtara · Quartus® Prime Pro Edition Guide User: Platform Designer
Rụtụ aka n'isiokwu a na-eme ka arụmọrụ sistemu nrụpụta ikpo okwu dị mma maka ozi ndị ọzọ. Ntuziaka onye ọrụ Quartus® Prime Standard Edition: Platform Designer Tụtụ aka n'isiokwu na-arụ ọrụ Sistemụ Nrụpụta Platform maka ozi ndị ọzọ.

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3. Nios V Processor Software System Design
Isiakwụkwọ a na-akọwa usoro mmepe sọftụwia Nios V na ngwa ngwanrọ ị nwere ike iji na-emepụta sistemu imewe gị agbakwunyere. Ọdịnaya na-eje ozi dị ka ihe karịrịview tupu ịmepụta sistemụ ngwanrọ Nios V.
Ọgụgụ 26. Ntugharị Nhazi Software
Malite

Mepụta BSP na Platform Designer Iji BSP Editor

Mepụta BSP Iji Nios V Command Shell
Mepụta ngwa CMee Mee File Iji Nios V Command Shell

Mara:

Bubata BSP na Ngwa CMee Mee File
Mee ngwa Nios V Processor site na iji
RiscFree IDE maka Intel FPGA

Jiri nke ọ bụla wulite ngwa Nios V Processor
iwu-akara koodu nchịkọta akụkọ, CMake, na Mee
iwu
Ọgwụgwụ

Altera na-atụ aro ka ị jiri ngwa mmepe Altera FPGA ma ọ bụ bọọdụ prototype omenala maka mmepe ngwanrọ na nbipu. Ọtụtụ akụkụ na atụmatụ ọkwa sistemụ dị naanị mgbe ngwanro gị na-agba na bọọdụ n'ezie.

© Altera Corporation. Altera, akara Altera, akara 'a', na akara Altera ndị ọzọ bụ ụghalaahịa nke ụlọ ọrụ Altera. Altera nwere ikike ime mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Altera anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Altera kwenyesiri ike na ederede. A dụrụ ndị ahịa Altera ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

3. Nios V Processor Software System Design 726952 | 2025.07.16
3.1. Nios V Processor Mmepe Software Flow
3.1.1. Ọrụ ngwugwu nkwado Board
Ihe ngwungwu Nkwado Board nke Nios V (BSP) bụ ọbá akwụkwọ pụrụ iche nwere koodu nkwado usoro akọwapụtara. BSP na-enye gburugburu ngwa ngwa ngwa ngwa ahaziri maka otu nhazi na sistemụ ngwaike Nios V.
Ngwa Quartus Prime na-enye Nios V Board Support Package Editor na ngwa niosv-bsp iji gbanwee ntọala na-achịkwa omume nke BSP.
BSP nwere ihe ndị a: · oyi akwa abstraction ngwaike · Ndị ọkwọ ụgbọ ala · Ngwungwu ngwanrọ nhọrọ · Sistemụ arụmọrụ ezigbo oge.
3.1.2. Ngwa Ngwa
Arụmọrụ ngwa Nios VC/C++ nwere atụmatụ ndị a: · Mere mkpokọta koodu isi mmalite yana CMakeLists.txt.
-CMakeLists.txt na-achịkọta koodu isi mmalite wee jikọta ya na BSP yana otu ọba akwụkwọ nhọrọ ma ọ bụ karịa, iji mepụta otu .elf. file
· Otu n'ime isi iyi files nwere isi ọrụ (). · Gụnyere koodu na-akpọ ọrụ na ọba akwụkwọ na BSP.
Altera na-enye ngwa ngwa niosv-app na ngwa ngwa ngwa Quartus Prime iji mepụta Ngwa CMekeLists.txt, yana RiscFree IDE maka Altera FPGA iji gbanwee koodu isi mmalite na gburugburu dabere Eclipse.
3.2. Ngwa mmepe agbakwunyere Altera FPGA
Ihe nhazi Nios V na-akwado ngwaọrụ ndị a maka mmepe ngwanrọ: · Ihe nrụnye ihe osise (GUI) - Ngwa mmepe eserese dị na ya.
ma Windows* na Linux* Sistemụ arụmọrụ (OS). - Onye nchịkọta akụkọ nkwado Nios V Board (Nios V BSP Editor) - Ashling RiscFree IDE maka Altera FPGAs · Command-Line Tools (CLI) - Ngwa mmepe nke sitere na Nios V Command Shell. Ngwá ọrụ ọ bụla na-enye akwụkwọ nke ya n'ụdị enyemaka a na-enweta site na akara iwu. Mepee Nios V Command Shell wee pịnye iwu a: -enyere aka view menu enyemaka. - Ngwa Nios V Utilities - File Ngwá Ọrụ Ngbanwe Hazie - Ngwa Ngwa Ndị Ọzọ

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Tebụl 25. Ngwa GUI na Ngwa-akara Ngwa Nchịkọta Ọrụ

Ọrụ

Ngwa GUI

Ngwá ọrụ akara iwu

Ịmepụta BSP

Nios V BSP Editor

Na ngwa Quartus Prime Pro Edition: niosv-bsp -c -s=<.qsys file> -t= [Nhọrọ] ntọala.bsp
· Na Quartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t= [Nhọrọ] ntọala.bsp

Ịmepụta BSP site na iji .bsp dị file
Na-emelite BSP

Onye nchịkọta akụkọ Nios V BSP Nios V BSP Editor

niosv-bsp -g [Nhọrọ] ntọala.bsp niosv-bsp -u [Nhọrọ] ntọala.bsp

Nyochaa BSP

Nios V BSP Editor

niosv-bsp -q -E= [Nhọrọ] ntọala.bsp

Ịmepụta ngwa

–

niosv-app -a= -b= -s= fileakwụkwọ ndekọ aha> [OPTIONS]

Ịmepụta ọba akwụkwọ onye ọrụ

–

niosv-app -l= -s= files ndekọ> -p= [Nhọrọ]

Ịgbanwe ngwa Na-agbanwe ọbá akwụkwọ onye ọrụ Iwulite ngwa

IDE RiscFree maka Altera FPGAs
IDE RiscFree maka Altera FPGAs
IDE RiscFree maka Altera FPGAs

Onye ndezi isi iyi ọ bụla
Onye ndezi isi iyi ọ bụla
· eme · ime

Iwulite ọba akwụkwọ onye ọrụ

IDE RiscFree maka Altera FPGAs

· eme · ime

Ịbudata ngwa ELF
Na-atụgharị .elf file

IDE RiscFree maka Altera FPGAs
–

niosv-nbudata
· elf2flash · elf2hex

Ozi metụtara
Ashling RiscFree Integrated Development Environment (IDE) maka ntuziaka onye ọrụ Altera FPGA

3.2.1. Onye nchịkọta akụkọ ngwugwu nkwado Nios V Processor Board
Ị nwere ike iji Nios V processor Editor BSP rụọ ọrụ ndị a: · Mepụta ma ọ bụ gbanwee ọrụ Nios V processor BSP · Dezie ntọala, mpaghara njikọ, na nkewa ngalaba · Họrọ ngwugwu ngwanrọ na ndị ọkwọ ụgbọala ngwaọrụ.
Ike nke BSP Editor gụnyere ike nke ngwa niosv-bsp. Enwere ike ịmepụta ọrụ ọ bụla emepụtara na Editor BSP site na iji ngwa-ahụ maka iwu.

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Mara:

Maka ngwanrọ Quartus Prime Standard Edition, rụtụ aka na AN 980: Nios V Processor Quartus Prime Software Nkwado maka usoro ịkpọku BSP Editor GUI.

Iji malite editọ BSP, soro usoro ndị a: 1. Mepee Platform Designer, wee gaa na ebe a. File menu.
a. Ka imepe ntọala BSP dị file, pịa Mepee… b. Iji mepụta BSP ọhụrụ, pịa BSP ọhụrụ… 2. Họrọ taabụ Editor BSP wee nye nkọwa dabara adaba.

Ọgụgụ 27. Mwepụta BSP Editor

Ozi metụtara AN 980: Nios V Processor Quartus Prime Nkwado Software
3.2.2. IDE RiscFree maka Altera FPGAs
IDE RiscFree maka Altera FPGA bụ IDE dabere na Eclipse maka nhazi Nios V. Altera na-atụ aro ka ịmepụta Nios V processor software na IDE a n'ihi ihe ndị a: · Emepụtara ma gosipụta njirimara ndị ahụ na ọ dabara na Nios V.
processor ewu eruba. · Kwadoro na niile mkpa toolchains na-akwado ngwaọrụ nke na-enyere gị aka
iji malite mmepe Nios V ngwa ngwa.
Ozi metụtara Ashling RiscFree Integrated Development Environment (IDE) maka ntuziaka onye ọrụ Altera FPGA
3.2.3. Ngwa Nios V Utilities
Ị nwere ike ịmepụta, gbanwee ma wuo mmemme Nios V na iwu ndị e denyere n'ahịrị iwu ma ọ bụ tinye n'ime edemede. Ngwaọrụ iwu Nios V nke akọwara na ngalaba a dị na /niosv/bin ndekọ.

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Isiokwu 26. Ngwa Nios V Utilities

Ngwa-akara Ngwa

Nchịkọta

niosv-app niosv-bsp niosv-budata niosv-shell niosv-stack-akụkọ

Iji mepụta na hazie ọrụ ngwa.
Ka imepụta ma ọ bụ melite ntọala BSP file ma mepụta BSP files. Ka ibudata ELF file gaa na Nios® V processor.
Ka imepee Nios V Command Shell. Iji gwa gị maka oghere ebe nchekwa aka ekpe dị na ngwa gị .elf maka iji tojupụtara ma ọ bụ ikpo ọkụ.

3.2.4. File Hazie Ngwa Ntụgharị

File Ntugharị usoro na-adị mkpa mgbe ụfọdụ mgbe ị na-ebufe data site n'otu ọrụ gaa na nke ọzọ. Nke file Usoro ntụgharị ngwaọrụ dị na
ndekọ nwụnye software>/niosv/bin ndekọ.

Tebụl 27. File Hazie Ngwa Ntụgharị

Ngwaọrụ Command-Line elf2flash elf2hex

Nchịkọta Ịsụgharị .elf file ka .srec usoro maka flash ebe nchekwa mmemme. Ịsụgharị .elf file ka .hex usoro maka mmalite ebe nchekwa.

3.2.5. Ngwa Ngwa Ndị Ọzọ

Ị nwere ike ịchọ ngwá ọrụ ahịrị iwu ndị a mgbe ị na-ewu usoro nhazi Nios V. Ngwá ọrụ akara iwu ndị a bụ nke Intel na-enye /quartus/bin ma ọ bụ enwetara site na
ngwaọrụ mepere emepe.

Tebụl 28. Ngwaọrụ Iwu-Line ndị ọzọ

Ngwa-akara Ngwa

Ụdị

Nchịkọta

juart-terminal

Intel-nyere

Iji nyochaa stdout na stderr, na ịnye ntinye na nhazi Nios® V
subsystem site na stdin. Ngwa a na-emetụta naanị JTAG UART IP mgbe ejikọrọ ya na Nios® V processor.

openocd

Intel-nyere iji mebie OpenOCD.

openocd-cfg-gen

Enyere Intel · Iji mepụta nhazi OpenOCD file. · Igosipụta JTAG yinye ngwaọrụ index.

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4. Nios V Nhazi Nhazi na Ngwọta Booting
Ị nwere ike hazie ihe nhazi Nios V ka ọ buut ma rụọ ngwanrọ sitere na ebe nchekwa dị iche iche. Ebe nchekwa buut bụ Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), ma ọ bụ ebe nchekwa Tightly Coupled (TCM).
Ozi emetụtara · Ọnọdụ ike na-akpalite na ibe 193 · Ihe na-akpalite ike
Maka ozi ndị ọzọ gbasara ihe ndị na-ebuli elu.
4.1. Okwu mmalite
The Nios V processor na-akwado ụdị abụọ nke buut usoro: · Execute-in-Place (XIP) iji alt_load () ọrụ · Mmemme depụtaghachiri na RAM site na iji boot copier. Mmepe mmemme agbakwunyere Nios V dabere na oyi akwa abstraction ngwaike (HAL). HAL na-enye obere mmemme bootloader (nke a makwaara dị ka boot copier) nke na-edepụta ngalaba njikọ dị mkpa site na ebe nchekwa buut ruo ebe ha na-agba ọsọ n'oge buut. Ị nwere ike ịkọwapụta mmemme na ebe nchekwa data ebe oge na-agba ọsọ site na ijikwa ntọala nchịkọta nchịkọta Board Support Package (BSP). Nkebi a na-akọwa: · Nios V processor boot copier na akpụkpọ ụkwụ gị Nios V processor usoro dị ka
nhọrọ ebe nchekwa buut · Nhọrọ nhazi nke Nios V na ọsọ izugbe · Nios V mmemme mmemme maka ebe nchekwa buut ahọpụtara
4.2. Ngwa njikọ
Mgbe ị na-emepụta ọrụ nhazi Nios V, onye nchịkọta akụkọ BSP na-emepụta njikọ njikọ abụọ files: · linker.x: Iwu njikọ file nke emepụtara ngwa ahụfile eji
ịmepụta ọnụọgụ abụọ .elf file. linker.h: Nwere ozi gbasara nhazi ebe nchekwa njikọ. Mgbanwe niile ntọala njikọ njikọ ị na-eme na ọrụ BSP na-emetụta ọdịnaya nke njikọ abụọ a files. Ngwa Nios V ọ bụla nwere ngalaba njikọ ndị a:
© Altera Corporation. Altera, akara Altera, akara 'a', na akara Altera ndị ọzọ bụ ụghalaahịa nke ụlọ ọrụ Altera. Altera nwere ikike ime mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Altera anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Altera kwenyesiri ike na ederede. A dụrụ ndị ahịa Altera ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

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Isiokwu 29. Njikọ Njikọ

.ederede

Ngalaba Linker

.rodata

.rwdata

.bss

.kpobo

.nkpoko

Koodu executable nkọwa. Ihe ọ bụla agụ-naanị data ejiri na mmezu nke mmemme. Na-echekwa data agụ-ede ejiri mee ihe na mmemme mmemme. Nwere data static na-ebidobeghị. Nwere ebe nchekwa ekenyere ike. Na-echekwa parampat oku ọrụ yana data nwa oge ndị ọzọ.

Ị nwere ike ịgbakwunye ngalaba njikọ na .elf file iji jide koodu omenala na data. A na-edobe ngalaba njikọ ndị a na mpaghara ebe nchekwa akpọrọ aha, akọwapụtara ya na ngwaọrụ ebe nchekwa anụ ahụ na adreesị. Site na ndabara, BSP Editor na-ewepụta ngalaba njikọ ndị a na-akpaghị aka. Agbanyeghị, ịnwere ike ijikwa ngalaba njikọ maka otu ngwa.

4.2.1. Omume njikọ
Akụkụ a na-akọwa omume njikọ ndabara Editor BSP yana otu esi ejikwa omume njikọ.

4.2.1.1. Njikọ BSP ezighi ezi
N'oge nhazi BSP, ngwaọrụ ndị a na-eme usoro ndị a na-akpaghị aka:
1. Kenye aha mpaghara ebe nchekwa: Kenye aha na ngwaọrụ ebe nchekwa sistemu ọ bụla wee tinye aha ọ bụla na njikọ file dị ka ebe nchekwa mpaghara.
2. Chọta ebe nchekwa kachasị: Chọpụta mpaghara ebe nchekwa ọgụgụ na-ede kachasị na njikọ njikọ file.
3. Kenye ngalaba njikọ: Debe ngalaba njikọ ndabara (.text, .rodata, .rwdata, .bss, .heap, and .stack) na mpaghara ebe nchekwa achọpụtara na nzọụkwụ gara aga.
4. Dee files: Dee linker.x na linker.h files.
Dịka, atụmatụ oke ngalaba njikọ na-arụ ọrụ n'oge usoro mmepe ngwanrọ n'ihi na ngwa ahụ ga-arụ ọrụ ma ọ bụrụ na ebe nchekwa buru ibu.
Iwu maka omume njikọ ndabara dị na Altera-generated Tcl scripts bsp-set-defaults.tcl na bsp-linker-utils.tcl dị na /niosv/scripts/bsp-ndefaults ndekọ. Iwu niosv-bsp na-akpọ edemede ndị a. Emezigharịla edemede ndị a ozugbo.

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4.2.1.2. Njikọ BSP nwere ike ịhazi
Ị nwere ike ijikwa omume njikọ ndabara na taabụ Linker Script nke BSP Editor. Jiri ụzọ ndị a jigharịa script njikọ: · Tinye mpaghara ebe nchekwa: Maapụ aha mpaghara ebe nchekwa na ngwaọrụ ebe nchekwa anụ ahụ. Tinye maapụ ngalaba: Maapụ aha ngalaba na mpaghara ebe nchekwa. Ụlọ ọrụ BSP
Editor na-enye gị ohere view map ebe nchekwa tupu na mgbe emechara mgbanwe.

4.3. Ụzọ Nios V Processor Booting Ụzọ

Enwere ụzọ ole na ole iji bulite Nios V processor na ngwaọrụ Altera FPGA. Ụzọ iji bulite Nios V processor dịgasị iche dabere na nhọrọ ebe nchekwa flash na ezinụlọ ngwaọrụ.

Tebụl 30. Ihe ncheta Flash akwadoro na nhọrọ buut dị iche iche

Ncheta buut akwadoro

Ngwaọrụ

Flash On-Chip (maka nhazi ime)

Ngwa kacha 10 naanị (nwere On-Chip Flash IP)

Ebumnuche izugbe QSPI Flash (maka naanị data onye ọrụ)

Ngwa FPGA niile akwadoro (ya na Interface Serial Flash Interface FPGA IP)

Nhazi QSPI Flash (maka nhazi Serial nọ n'ọrụ)

dabere na ngọngọ njikwa
ngwaọrụ (ya na Generic
Oghere Usoro Flash Interface Intel FPGA IP (2)

Ụzọ Nios V Processor Booting Ụzọ

Ebe ojiri ngwa ngwa

Ihe mkpuchi buut

Ngwa Nios V na-arụ ọrụ nhazi site na On-Chip Flash

Flash on-Chip (XIP) + OCRAM / RAM mpụga (maka akụkụ data edere)

ọrụ alt_load().

Ngwa Nios V nke ihe nrụpụta sitere na On-Chip Flash depụtaghachiri site na iji mpempe akwụkwọ buut

OCRAM / RAM mpụga

Na-ejigharị Bootloader site na GSFI

Ngwa nhazi Nios V na-eme n'ime ebe site na ebumnuche QSPI flash zuru oke

Ebumnuche izugbe QSPI flash (XIP) + OCRAM/ RAM mpụga (maka akụkụ data edere)

ọrụ alt_load().

Ngwa ihe nhazi Nios V e depụtaghachiri site na ebumnuche izugbe QSPI flash gaa na RAM site na iji akpụkpọ ụkwụ buut

OCRAM / RAM mpụga

Bootloader site na GSFI

Ngwa nhazi Nios V na-eme n'ime ebe site na nhazi QSPI flash

Nhazi QSPI flash (XIP) + OCRAM/ RAM mpụga (maka akụkụ data edere)

ọrụ alt_load().

Ngwa ihe nhazi Nios V e depụtaghachiri site na nhazi QSPI flash gaa na RAM site na iji akpụkpọ ụkwụ buut

OCRAM / Mpụga RAM Bootloader site na GSFI gara n'ihu…

(2) rụtụ aka na AN 980: Nios V Processor Quartus Prime Software Nkwado maka ndepụta ngwaọrụ.

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Ncheta buut akwadoro
Ebe nchekwa on-chip (OCRAM) Ebe nchekwa jikọtara ọnụ (TCM)

Ngwaọrụ
Ngwa dabere na SDM (ya na onye ahịa igbe ozi Intel FPGA IP). (2)
Ngwa Altera FPGA niile akwadoro (2)
Ngwa Altera FPGA niile akwadoro(2)

Ụzọ Nios V Processor Booting Ụzọ
Ngwa ihe nhazi Nios V e depụtaghachiri site na nhazi QSPI flash gaa na RAM site na iji akpụkpọ ụkwụ buut
Ngwa Nios V na-arụ ọrụ site na OCRAM
Ngwa Nios V na-arụ ọrụ site na TCM

Ebe ojiri ngwa ngwa

Ihe mkpuchi buut

OCRAM / Mpụga RAM Bootloader site na SDM

OCRAM

ọrụ alt_load().

Ntuziaka TCM (XIP) Ọ dịghị + Data TCM (maka akụkụ data ederede)

Ọgụgụ 28. Nios V Processor Boot Flow

Tọgharia

Ihe nhazi wụliri elu iji tọgharịa vector (mbido koodu buut)

Enwere ike iṅomi koodu ngwa na ebe nchekwa ọzọ (dabere na nhọrọ buut)
Koodu buut na-ebido onye nrụpụta

Dabere na nhọrọ buut, koodu buut nwere ike idetuo ụkpụrụ mbụ maka data/koodu na oghere ebe nchekwa ọzọ (alt_load)
Koodu buut na-ebido koodu ngwa yana oghere ebe nchekwa data
Koodu buut na-eji ndị ọkwọ ụgbọ ala HAL (alt_main) bido akụkụ sistemụ niile.
Ntinye na isi
Ozi emetụtara · Generic Serial Flash Interface Altera FPGA IP ntuziaka onye ọrụ
Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 50

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Onye ahịa igbe ozi Altera FPGA IP ntuziaka onye ọrụ · AN 980: Nios V Processor Quartus Prime Nkwado Software
4.4. Okwu Mmalite nke Nios V Processor Ụzọ Booting
Sistemụ nhazi Nios V chọrọ ka ahazi onyonyo sọftụwia na ebe nchekwa sistemu tupu onye nrụpụta enwee ike ịmalite ime mmemme ngwa. Rụtụ aka na ngalaba Linker maka ngalaba njikọ ndabara.
Onye nchịkọta akụkọ BSP na-emepụta edemede njikọ nke na-arụ ọrụ ndị a: · Gbaa mbọ hụ na ejikọtara ngwanrọ processor dịka ntọala njikọ njikọ.
nke BSP editọ na-ekpebi ebe software bi na ebe nchekwa. · Debe mpaghara koodu processor na mpaghara ebe nchekwa dịka nke
ekenyere ebe nchekwa components.
Nkebi na-esonụ na-akọwa nkenke ụzọ Nios V processor booting dị.
4.4.1. Ngwa Nios V Processor Mezue-N'ebe site na Boot Flash
Altera haziri ndị na-ahụ maka ọkụ ọkụ ka ọ bụrụ oghere adreesị boot flash ga-enweta ngwa ngwa na processor Nios V na nrụpụta sistemụ, na-enweghị mkpa ibido njikwa ebe nchekwa ma ọ bụ ngwaọrụ ebe nchekwa. Nke a na-enyere ndị nrụpụta Nios V aka ime koodu ngwa echekwara na ngwaọrụ buut ozugbo na-ejighi ihe nbipụta buut iji detuo koodu ahụ na ụdị ebe nchekwa ọzọ. Ndị na-ahụ maka ọkụ bụ: · On-Chip Flash na On-Chip Flash IP (naanị na ngwaọrụ MAX® 10) · Nzube zuru oke QSPI flash na Generic Serial Flash Interface IP · Nhazi QSPI flash na Generic Serial Flash Interface IP (ma e wezụga MAX 10).
ngwaọrụ)
Mgbe ngwa nhazi Nios V na-arụ ọrụ site na boot flash, BSP Editor na-arụ ọrụ ndị a: · Na-edobe akụkụ njikọ .text na mpaghara ebe nchekwa boot flash. · Tọọ akụkụ .bss,.rodata, .rwdata, .stack na .heap njikọ na RAM
ebe nchekwa mpaghara. Ị ga-emerịrị ọrụ alt_load() dị na Ntọala BSP iji detuo ngalaba data (.rodata, .rwdata,, .exceptions) na RAM n'elu ntọgharị sistemu. Akụkụ koodu (.ederede) na-anọgide na mpaghara ebe nchekwa boot flash.
Ozi metụtara · Generic Serial Flash Interface Altera FPGA IP ntuziaka onye ọrụ · Altera MAX 10 ntuziaka onye ọrụ ebe nchekwa Flash.
4.4.1.1. alt_load()
Ị nwere ike mee ka ọrụ alt_load() dị na koodu HAL site na iji BSP Editor.
Mgbe ejiri ya na ịgba ọsọ buut na-eme, ọrụ alt_load() na-arụ ọrụ ndị a:

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· Na-arụ ọrụ dị ka obere ihe nṅomi nke na-edegharị akụkụ ebe nchekwa na RAM dabere na ntọala BSP.
· Detuo ngalaba data (.rodata, .rwdata, .iche) na RAM ma ọ bụghị ngalaba koodu (.ederede) .Ngalaba koodu (.ederede) ngalaba bụ ngalaba na-agụ naanị ma na-anọgide na mpaghara ebe nchekwa flash booting. Nkewa a na-enyere aka ibelata ojiji RAM mana ọ nwere ike belata arụmọrụ mmebe koodu n'ihi na ịnweta ebe nchekwa flash na-adị nwayọ karịa ịnweta RAM na mgbawa.

Tebụlụ na-esonụ depụtara ntọala na ọrụ Editor BSP:

Tebụl 31. Ntọala nchịkọta akụkọ BSP
Onye nchịkọta akụkọ BSP ntọala hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_exceptions

Ọrụ na-akwado ọrụ alt_load(). akụkụ alt_load() .rodata na RAM. akụkụ alt_load() .rwdata na RAM. mbipụta alt_load() .ngalaba ewepu na RAM.

4.4.2. Ngwa Nios V Processor Edepụtara site na Boot Flash gaa na RAM Iji Boot Copier
Ihe nhazi Nios V na HAL na-agụnye ihe nbipụta buut nke na-enye ọrụ zuru oke maka ọtụtụ ngwa nhazi Nios V ma dị mma iji mejuputa na Nios V software eruba.
Mgbe ngwa ahụ na-eji akpụkpọ ụkwụ buut, ọ na-edobe akụkụ niile njikọ (.text, .heap, .rwdata, .rodata, .bss, .stack) na RAM n'ime ma ọ bụ mpụga. Iji mpempe akwụkwọ buut iji detuo ngwa ihe nrụpụta Nios V site na boot flash gaa na RAM nke ime ma ọ bụ mpụga maka igbu ya na-enyere aka melite arụmọrụ ogbugbu.
Maka nhọrọ buut a, ihe nrụpụta Nios V na-amalite ime ngwa ngwa nbipụta boot na nrụpụta sistemụ. Akụrụngwa na-eṅomi ngwa ahụ site na flash buut gaa na RAM nke ime ma ọ bụ mpụga. Ozugbo usoro ahụ mechara, Nios V processor na-ebufe njikwa mmemme na ngwa ahụ.

Mara:

Ọ bụrụ na copier boot dị na flash, mgbe ahụ, ọrụ alt_load() adịghị mkpa ka a kpọọ ya n'ihi na ha abụọ na-arụ otu nzube.

4.4.2.1. Nios V Processor Bootloader site na Generic Serial Flash Interface
The Bootloader site na GSFI bụ Nios V processor boot copier nke na-akwado QSPI flash memory na njikwa ngwaọrụ dabere. Bootloader site na GSFI gụnyere atụmatụ ndị a:
· Chọta ngwa ngwa ngwa na ebe nchekwa na-adịghị agbanwe agbanwe.
· Ebupu ma detuo foto ngwa ngwa na RAM.
* Na-agbanwe nhazi nhazi na akpaghị aka na koodu ngwa na RAM ka emechara.

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 52

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Onyonyo buut dị ozugbo ihe nbipụta buut gasịrị. Ịkwesịrị ijide n'aka na nrụpụta nrụpụta ihe nrụpụta Nios V na mmalite nke ihe nbipute buut. Ọgụgụ: Map ebe nchekwa maka QSPI Flash nwere Bootloader site na maapụ ebe nchekwa GSFI maka QSPI Flash nwere Bootloader site na GSFI na-egosi maapụ ebe nchekwa flash maka Flash QSPI mgbe ị na-eji ihe nbibi buut. Maapụ ebe nchekwa a na-eche na ebe nchekwa flash na-echekwa onyonyo FPGA na ngwa ngwa.

Tebụl 32. Bootloader site na GSFI maka Nios V Processor Core

Nios V Processor Core
Nios V/m processor

Bootloader site na GSFI File Ebe
/niosv/Components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/Components/bootloader/ niosv_g_bootloader.srec

Ọgụgụ 29. Map ebe nchekwa maka QSPI Flash na Bootloader site na GSFI

Data ndị ahịa (*.hex)

Koodu ngwa

Mara:

Tọgharịa Vector Offset

Ihe mkpuchi buut

0x01E00000

Foto FPGA (* .sof)

0x00000000

1. Na mmalite nke map ebe nchekwa bụ ihe oyiyi FPGA na-esote data gị, nke mejupụtara akpụkpọ ụkwụ na koodu ngwa.
2. Ị ga-edozi nrụgharị nrụpụta ihe nrụpụta Nios V na Platform Designer wee rụtụ aka na mmalite nke ihe nrụpụta buut.
3. A maghị nha nke ihe oyiyi FPGA. Ị nwere ike ịmata kpọmkwem nha ya mgbe Quartus Prime chịkọtara ọrụ. Ị ga-ekpebi oke elu maka nha onyonyo Altera FPGA. Maka example, ọ bụrụ na nha nke onyonyo FPGA na-eche na ọ na-erughị 0x01E00000, tọọ Tọgharia Offset na 0x01E00000 na Platform Designer, nke bụkwa mmalite nke onye na-edepụta ihe.
4. Omume imewe dị mma bụ ịtọ ntọala vector offset na mpaghara mpaghara ọkụ iji hụ na ihichapụ ihe onyonyo FPGA agaghị adị ma ọ bụrụ na emelitere ngwa ngwa.

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4.4.2.2. Nios V Processor Bootloader site na njikwa ngwaọrụ echekwara
Bootloader site na njikwa ngwaọrụ nchekwa (SDM) bụ koodu ngwa HAL na-eji onye ahịa igbe ozi Altera FPGA IP HAL ọkwọ ụgbọ ala maka booting processor. Altera na-akwado ngwa bootloader a mgbe ị na-eji nhazi QSPI flash na ngwaọrụ dabere na SDM iji buo ihe nrụpụta Nios V.
Mgbe nrụgharị sistemu, ihe nrụpụta Nios V na-ebu ụzọ bute Bootloader site na SDM site na obere ebe nchekwa na mgbawa wee mebie Bootloader site na SDM iji kparịta ozi na nhazi QSPI flash site na iji igbe ozi IP Client.
Bootloader site na SDM na-arụ ọrụ ndị a: · Chọta ngwa ngwa Nios V na nhazi QSPI flash. · Detuo ngwa Nios V n'ime RAM on-chip ma ọ bụ RAM mpụga. Na-atụgharị ogbugbu processor na Nios V software n'ime RAM on-chip ma ọ bụ
RAM mpụga.
Ozugbo usoro ahụ mechara, Bootloader site na SDM na-ebufe njikwa mmemme na ngwa onye ọrụ. Altera na-akwado nzukọ ebe nchekwa dị ka akọwara na Ebe nchekwa maka Bootloader site na SDM.
Ọgụgụ 30. Bootloader site na SDM Process Flow

Nhazi

Flash

Nios V Software

SDM

Ngwa FPGA dabere na SDM

IP onye ahịa igbe ozi

FPGA Logic Nios V

4 RAM mpụga
Nios V Software

On-Chip 4

EMIF

RAM

Ebe nchekwa On-Chip

Nios V

Ngwa ngwa

Bootloader site na SDM

1. Nios V processor na-agba ọsọ Bootloader site na SDM site na ebe nchekwa on-chip.
2. Bootloader site na SDM na-ekwurịta okwu na nhazi nhazi ma chọta Nios V software.
3. Bootloader site na SDM na-eṅomi Nios V software si nhazi Flash n'ime RAM na mgbawa / RAM mpụga.
4. Bootloader site na SDM na-atụgharị ogbugbu Nios V na ngwanrọ Nios V na RAM na mgbawa / RAM mpụga.

4.4.3. Ngwa Nios V Processor Mezue-N'ebe sitere na OCRAM
Na usoro a, a na-edozi adreesị nrụpụta nrụpụta Nios V na adreesị ntọala nke ebe nchekwa on-chip (OCRAM). ọnụọgụ abụọ ngwa (.hex) file A na-etinye ya n'ime OCRAM mgbe ahaziri FPGA, mgbe ejikọtachara ngwaike na ngwa Quartus Prime. Ozugbo nrụpụta Nios V megharịrị, ngwa ahụ na-amalite ime ya na alaka ruo ebe ntinye.

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 54

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Mara:

Execute-In-Place si OCRAM anaghị achọ ihe nbipụta boot n'ihi na ngwa nhazi Nios V adịlarị na nrụpụta sistemụ.
Altera na-atụ aro ka ịmee alt_load() maka usoro ịgbanye nke a ka sọftụwia agbakwunyere na-akpa àgwà n'otu aka ahụ mgbe emegharịrị na-enweghị nhazigharị onyonyo ngwaọrụ FPGA.
Ị ga-emerịrị ọrụ alt_load() dị na Ntọala BSP iji detuo ngalaba .rwdata n'elu nhazi usoro. Na usoro a, a na-echekwa ụkpụrụ mbụ maka mgbanwe mmalite dị iche iche site na mgbanwe ndị kwekọrọ na ya iji zere idegharị na mmemme mmemme.

4.4.4. Ngwa Nios V Processor Mezue-N'ebe sitere na TCM
Usoro a na-eme n'ime ebe na-edobe adreesị nrụpụta Nios V na adreesị ntọala nke ebe nchekwa jikọtara ọnụ (TCM). ọnụọgụ abụọ ngwa (.hex) file A na-etinye ya na TCM mgbe ị haziri FPGA mgbe ị chịkọtachara ngwaike na ngwa Quartus Prime. Ozugbo nrụpụta Nios V megharịrị, ngwa ahụ na-amalite ime ya na alaka ruo ebe ntinye.

Mara:

Execute-In-Place sitere na TCM achọghị ihe nbibi boot n'ihi na ngwa nhazi Nios V adịlarị na nrụpụta sistemụ.

4.5. Nios V Processor na-ebuli site na On-Chip Flash (UFM)

Nios V processor booting na mmebe sọftụwia sitere na on-chip flash (UFM) dị na ngwaọrụ MAX 10 FPGA. Ihe nhazi Nios V na-akwado nhọrọ buut abụọ ndị a site na iji On-Chip Flash n'okpuru ọnọdụ nhazi nke ime:
Ngwa Nios V na-arụ ọrụ site na On-Chip Flash.
· A na-eṅomi ngwa Nios V processor site na On-Chip Flash na RAM site na iji akpụkpọ ụkwụ buut.

Tebụl 33. Ihe ncheta Flash akwadoro nwere nhọrọ buut dị iche iche

Ncheta buut akwadoro

Ụzọ Nios V Booting

Ebe ojiri ngwa ngwa

Ihe mkpuchi buut

Ngwa MAX 10 naanị (nwere OnChip Flash IP)

Ngwa Nios V na-arụ ọrụ nhazi site na On-Chip Flash
Ngwa Nios V nke ihe nrụpụta sitere na On-Chip Flash depụtaghachiri site na iji mpempe akwụkwọ buut

Flash on-Chip (XIP) + OCRAM / RAM mpụga (maka akụkụ data edere)

ọrụ alt_load().

OCRAM / RAM mpụga

Na-ejigharị Bootloader site na GSFI

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Onyonyo 31.

Nhazi, Nhazi, na Ntugharị Booting
Imepụta · Mepụta Nios V Processor gị site na iji Platform Designer. Hụ na e nwere RAM mpụga ma ọ bụ na-agbawa RAM na nhazi usoro.

Nhazi na mkpokọta FPGA
· Tọọ otu ụdị nhazi ime na On-chip Flash IP na Platform Designer na Quartus Prime software. Tọọ onye nrụpụta nrụpụta Nios V ka ọ bụrụ Flash on-chip. Họrọ usoro mbido UFM masịrị gị. · Mepụta imewe gị na Platform Designer. · Chịkọta ọrụ gị na Quartus Prime software.

Ngwa onye ọrụ BSP Project · Mepụta Nios V processor HAL BSP dabere na .sopcinfo file kere site Platform Designer. Dezie Nios V nhazi ntọala BSP na Linker Script na BSP Editor. · Mepụta ọrụ BSP.
Ngwa APP Project · Mepụta koodu ngwa nhazi Nios V. Chịkọta ngwa nhazi Nios V wee mepụta ngwa nhazi Nios V (.hex) file. · Kwakọta ọrụ gị na Quartus Prime software ma ọ bụrụ na ịlelee ibido ọdịnaya ebe nchekwa nhọrọ na Intel FPGA On-Chip Flash IP.

Mmemme Files Ntụgharị, Download na-agba ọsọ · N'ịwa na On-Chip Flash .pof file iji tọghata mmemme Files atụmatụ na Quartus Prime software.
Mmemme .pof file banye na ngwaọrụ MAX 10 gị. · Ike okirikiri akụrụngwa gị.
4.5.1. Nkọwa Flash On-Chip MAX 10 FPGA
Ngwaọrụ MAX 10 FPGA nwere ọkụ na mgbawa nke kewara ụzọ abụọ: · Nhazi Flash Memory (CFM) - na-echekwa data nhazi ngwaike maka ya.
MAX 10 FPGA. Ebe nchekwa Flash onye ọrụ (UFM) - na-echekwa data onye ọrụ ma ọ bụ ngwa ngwanrọ.
Ihe owuwu UFM nke ngwaọrụ MAX 10 bụ ngwakọta nke IP dị nro na nke siri ike. Ị nwere ike ịnweta UFM naanị site na iji On-Chip Flash IP Core na Quartus Prime software.
Ihe on-chip Flash IP isi na-akwado atụmatụ ndị a: · Gụọ ma ọ bụ dee ohere ịnweta UFM na CFM (ọ bụrụ na enyere ya aka na Platform Designer)
iji Avalon MM data na njikwa ohu interface. · Na-akwado ihichapu ibe, mkpochapụ ngalaba na ide ihe. · Ihe nlere anya maka ịgụ / dee ohere UFM site na iji ngwa ịme anwansị EDA dị iche iche.

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 56

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Tebụl 34. Mpaghara Flash na-agbawa na ngwaọrụ MAX 10 FPGA

Mpaghara Flash

Ọrụ

Ebe nchekwa Flash nhazi (ngalaba CFM0-2)

Nhazi FPGA file nchekwa

Ebe nchekwa Flash onye ọrụ (ngalaba UFM0-1)

Ngwa Nios V processor na data onye ọrụ

Ngwaọrụ MAX 10 FPGA na-akwado ọtụtụ ụdị nhazi yana ụfọdụ n'ime ụdịdị ndị a na-ekwe ka CFM1 na CFM2 mee ihe dị ka mpaghara UFM ọzọ. Tebụlụ na-esote na-egosi ebe nchekwa nke onyonyo nhazi FPGA dabere na ụdị nhazi MAX 10 FPGA.

Tebụl 35. Ebe nchekwa ihe onyonyo nhazi FPGA

Ụdị nhazi onyonyo abịakọrọ abụọ

Foto agbakwunyere CFM2

CFM1

Foto agbakwunyere CFM0

Otu onyonyo enweghị mgbako

Virtual UFM

Onyonyo anaghị agbakọ

Otu onyonyo enweghị mgbako na mmalite ebe nchekwa

Onyonyo enweghị mgbako (nwere ọdịnaya ebe nchekwa na mgbawa ewepụtara ya)

Otu onyonyo abịakọrọ na mbido ebe nchekwa onyonyo agbakwunyere (nwere ọdịnaya ebe nchekwa etinyegoro na mgbawa)

Otu onyonyo abịakọrọ

Virtual UFM

Onyonyo emetụtara

Ị ga-ejiri On-chip Flash IP core iji nweta ebe nchekwa flash na MAX 10 FPGA. Ị nwere ike ime ngwa ngwa na jikọọ On-chip Flash IP na ngwa Quartus Prime. Ihe nrụpụta Nios V soft core na-eji njikọta nke Platform Designer iji kparịta ụka na On-chip Flash IP.
Ọgụgụ 32. Njikọ n'etiti On-chip Flash IP na Nios V Processor

Mara:

Gbaa mbọ hụ na ejikọrọ ọdụ ụgbọ mmiri Csr On-chip na Nios V processor data_manager iji mee ka onye nrụpụta nwee ike ịchịkwa ide na hichapụ ọrụ.
Ihe on-chip Flash IP isi nwere ike inye ohere ịnweta mpaghara ọkụ ise - UFM0, UFM1, CFM0, CFM1, na CFM2.
Ozi dị mkpa gbasara ngalaba UFM na CFM .: · Akụkụ CFM bụ maka nhazi (bitstream) data (* .pof) nchekwa.
Enwere ike ịchekwa data onye ọrụ na mpaghara UFM ma nwee ike zoo ya, ma ọ bụrụ na ahọpụtara ntọala ziri ezi na ngwaọrụ Platform Designer.
Ụfọdụ ngwaọrụ enweghị ngalaba UFM1. Ị nwere ike na-ezo aka na tebụl: UFM na CFM Sector Size maka akụkụ dị na onye ọ bụla MAX 10 FPGA ngwaọrụ.

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Ị nwere ike ịhazi CFM2 ka ọ bụrụ UFM mebere site n'ịhọrọ nhazi nhazi onyonyo Single Uncompressed.
Ị nwere ike hazie CFM2 na CFM1 dị ka a mebere UFM site na-ahọpụta Single Uncompressed Image nhazi mode.
Ogo nke ngalaba ọ bụla dịgasị iche na ngwaọrụ MAX 10 FPGA ahọpụtara.

Tebụl 36.

UFM na CFM Sector Size
Tebụl a na-edepụta akụkụ nke usoro UFM na CFM.

Ngwaọrụ

Ibe n'otu ngalaba

UFM1 UFM0 CFM2 CFM1 CFM0

Nha ibe (Kbit)

Onye ọrụ kacha
Nha ebe nchekwa Flash (Kbit) (3)

Ngụkọta nha ebe nchekwa nhazi nhazi (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

Nha OCRAM (Kbit)
108 189 378 549 675 1260 1638

Ozi metụtara · MAX 10 FPGA nhazi ntuziaka onye ọrụ · Altera MAX 10 ntuziaka onye ọrụ ebe nchekwa Flash.

4.5.2. Ngwa Nios V Processor Mezue-N'ebe sitere na UFM

Execute-In-Place sitere na ngwọta UFM dabara maka ngwa nhazi Nios V nke chọrọ iji ebe nchekwa nwere oke. Ọrụ alt_load() na-arụ ọrụ dị ka obere ihe nnomi buut nke na-edepụta akụkụ data (.rodata, .rwdata, ma ọ bụ .iche) site na ebe nchekwa buut gaa na RAM dabere na ntọala BSP. Akụkụ koodu (.ederede),
nke bụ naanị ngalaba na-agụ, na-anọgide na mpaghara ebe nchekwa Flash MAX 10 On-chip. Ntọlite a na-ebelata ojiji RAM mana ọ nwere ike belata arụmọrụ mmebe koodu ka ịnweta ebe nchekwa flash dị nwayọ karịa RAM na mgbawa.

Emebere ngwa nhazi Nios V n'ime ngalaba UFM. Ihe nrụpụta nrụpụta Nios V na-arụtụ aka na adreesị ntọala UFM iji mebie koodu sitere na UFM mgbe sistemụ ahụ tọgharịa.

Ọ bụrụ na ị na-eji ihe nbibi ọkwa isi mmalite iji mebie ngwa gị, ị ga-ejirịrị ebe nkwụsị ngwaike. Nke a bụ n'ihi na UFM anaghị akwado ịnweta ebe nchekwa random, nke dị mkpa maka nbipu ntụpọ nro.

Mara:

Ị nweghị ike ihichapụ ma ọ bụ dee UFM ka ị na-arụ ọrụ-na-ebe na MAX 10. Gbanwee ka buut copier obibia ma ọ bụrụ na ị chọrọ ihichapụ ma ọ bụ dee UFM.

(3) Uru kachasị ike, nke dabere na ọnọdụ nhazi ị họrọ.

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Ọgụgụ 33. Nios V Processor Ngwa XIP sitere na UFM

Ngwa kacha 10

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Onye mmemme Quartus

Flash on-Chip

CFM

Nios V Hardware

UFM

Nios V Software

Nhazi nke ime

Na-na-Chip Flash IP

FPGA Logic
Nios V Processor

RAM on-Chip

Mpụga

RAM

EMIF

4.5.2.1. Usoro nhazi ngwaike
Akụkụ na-esonụ na-akọwa usoro nzọụkwụ site na iji wuo sistemụ bootable maka ngwa nhazi Nios V sitere na On-Chip Flash. The exampA na-eji ngwaọrụ Max 10 rụọ le n'okpuru.
Ntọala akụrụngwa IP
1. Mepụta ihe nrụpụta Nios V gị site na iji Quartus Prime na Onye nrụpụta Platform. 2. Gbaa mbọ hụ na agbakwunyere RAM mpụga ma ọ bụ Ebe nchekwa On-Chip (OCRAM) na Platform gị
Usoro mmebe.

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Nyocha 34. ỌpụampNjikọ IP na Onye nrụpụta Platform maka Booting Nios V site na OnChip Flash (UFM)

3. Na On-Chip Flash IP parameter editor, tọọ ọnọdụ nhazi ka ọ bụrụ otu n'ime ihe ndị a, dị ka mmasị imewe gị: · Single Uncompressed Image · Single Compressed Image · Single Uncompressed Image with Memory Initialization · Single Compressed Image with Memory Initialization
Maka ozi ndị ọzọ gbasara onyonyo emetụtara Dual, rụtụ aka na ntuziaka onye ọrụ nhazi MAX 10 FPGA - nkwalite sistemụ dịpụrụ adịpụ.

Mara:

Ị ga-ekenye ohere ezoro ezo na mpaghara CFM ọ bụla na On-Chip Flash IP.

Ọgụgụ 35. Nhọrọ ọnọdụ nhazi na On-Chip Flash Parameter Editor

Ntọala IP Flash On-Chip - Mmalite UFM Ị nwere ike ịhọrọ otu n'ime ụzọ ndị a dịka mmasị gị si dị:

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Mara:

Usoro dị n'isiakwụkwọ ndị na-esote (Software Design Flow and Programming) dabere na nhọrọ ị mere ebe a.

· Usoro 1: Malite data UFM na SOF n'oge nchịkọta
Quartus Prime gụnyere data mbido UFM na SOF n'oge nchịkọta. Achọrọ nchikota SOF ma ọ bụrụ na enwere mgbanwe na data UFM.
1. Lelee ibido ọdịnaya flash na Kwado mmalite na-abụghị nke ndapụta file.

Ọgụgụ 36. Malite ọdịnaya Flash ma mee ka mmalite na-abụghị nke ndapụta File

2. Ezipụta ụzọ nke emepụtara .hex file (site na elf2hex iwu) na Onye ọrụ kere hex ma ọ bụ mif file.
Ọgụgụ 37. Na-agbakwụnye .hex File Ụzọ

· Usoro 2: Jikọta data UFM na SOF a chịkọtara n'oge ọgbọ POF
A na-ejikọta data UFM na SOF achịkọtara mgbe ị na-atụgharị mmemme files. Ịkwesighi ịchịkọta SOF, ọbụlagodi na data UFM gbanwere. N'oge mmepe, ịgaghị achịkọta SOF files maka mgbanwe na ngwa. Alterare kwadoro usoro a maka ndị mmepe ngwa.
1. Mepepụ akara ma malite ọdịnaya flash.
Ọgụgụ 38. Welite ọdịnaya Flash na mbido na-abụghị nke ndapụta File

Tọgharia ntọala ndị nnọchi anya maka Nios V Processor Mezu usoro-N'ebe
1. Na Nios V nhazi ihe nhazi paramita, tọọ onye nrụpụta nrụpụta ka ọ bụrụ On-Chip Flash.
Ọgụgụ 39. Ntọala Editọ Nios V Processor Parameter nwere Tọgharia Onye nnọchite anya na Flash On-Chip

2. Pịa n'ịwa HDL mgbe Generation dialog igbe pụtara. 3. Ezipụta mmepụta file nhọrọ ọgbọ wee pịa N'ịwa.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Pịa OK ka ịpụ na Device na Pin Nhọrọ window,
3. Pịa OK ka pụọ na Device window.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Mara:

Ọ bụrụ na ntọala ọnọdụ nhazi na Quartus Prime software na Platform Designer parameter editọ dị iche, ọrụ Quartus Prime dara na ozi njehie na-esote.

Onyonyo 41.

Ozi mperi maka mperi nhazi ọnọdụ nhazi dị iche iche (14740): Ụdị nhazi na atom "q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block". Melite ma megharịa sistemu Qsys ka ọ dabara na ntọala ọrụ.

Ozi emetụtara MAX 10 Ntuziaka onye ọrụ nhazi FPGA

4.5.2.2. Usoro nhazi ngwanrọ
Akụkụ a na-enye usoro nhazi iji mepụta ma wuo ọrụ ngwanrọ Nios V. Iji hụ na ọ na-aga n'ihu na-arụ ọrụ nke ọma, a na-agba gị ume ịmepụta osisi ndekọ aha yiri ya na ọrụ nhazi gị. Usoro nhazi ngwanrọ na-esote dabere na osisi ndekọ a.
Iji mepụta akwụkwọ ndekọ aha ngwanrọ software, soro usoro ndị a: 1. N'ime folda ihe nrụpụta gị, mepụta folda akpọrọ software. 2. Na nchekwa software, mepụta nchekwa abụọ a na-akpọ hal_app na hal_bsp.
Ọgụgụ 42. Software Project Directory Tree

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Ịmepụta ngwa BSP Project
Iji malite editọ BSP, soro usoro ndị a: 1. Tinye Nios V Command Shell. 2. Jiri iwu niosv-bsp-editor kpọọ BSP Editor. 3. Na BSP Editor, pịa File BSP ọhụrụ iji malite ọrụ BSP gị. 4. Hazie ntọala ndị a:
· Ozi SOPC File aha: Nye SOPINFO file (.sopcinfo). · Aha CPU: Họrọ Nios V processor. Sistemụ arụmọrụ: Họrọ sistemụ arụmọrụ nke Nios V processor. · Ụdị: Hapụ dị ka ndabere. · Akwụkwọ ndekọ aha ebumnuche BSP: Họrọ ụzọ ndekọ aha nke ọrụ BSP. Ị nwere ike
buru ụzọ tọọ ya na /software/hal_bsp site n'ịkwalite Jiri ọnọdụ ndabara. · Ntọala BSP File aha: Pịnye aha Ntọala BSP File. · Additional Tcl scripts: Provide a BSP Tcl script by enabling Enable Additional Tcl script. 5. Click OK.
Figure 43. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

Akwụkwọ ntuziaka Nios® V agbakwunyere Processor 64

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Tụgharịa mmemme Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Ntọala
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file ntughari.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Mara:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Ngwa kacha 10

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Onye mmemme Quartus

RAM mpụga
Nios V Software

Flash on-Chip

CFM

Nios V Hardwa

Akwụkwọ / akụrụngwa

altera Nios V Embedded Processor [pdf] Ntuziaka onye ọrụ
Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

Ntụaka

Akwụkwọ ntuziaka onye ọrụ

altera Nios V Embedded Processor

Nkọwapụta

Nios V Processor Hardware System Design

Nios V Processor Software System Design

Nios V Processor Configuration and Booting Solutions

Akwụkwọ / akụrụngwa

Ntụaka

Hapụ ikwu

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