altera Nios V Embedded processor User Guide

About the Nios® V Embedded Processor
1.1. Altera® FPGA le Embedded processors Fetaview
Lisebelisoa tsa Altera FPGA li ka kenya tšebetsong logic e sebetsang e le microprocessor e felletseng ha e ntse e fana ka likhetho tse ngata.
Phapang ea bohlokoa lipakeng tsa discrete microprocessors le Altera FPGA ke hore lesela la Altera FPGA ha le na kelello ha le phahama. Sesebelisoa sa Nios® V ke processor e bonolo ea thepa ea bohlale (IP) e ipapisitseng le litlhaloso tsa RISC-V. Pele o tsamaisa software ho sistimi e thehiloeng ho processor ea Nios V, o tlameha ho lokisa sesebelisoa sa Altera FPGA ka moralo oa Hardware o nang le processor ea Nios V. O ka beha processor ea Nios V kae kapa kae ho Altera FPGA, ho latela litlhoko tsa moralo.

Ho nolofalletsa sistimi ea hau e kenelletseng ea Altera® FPGA IP ho sebetsa joalo ka sistimi e thehiloeng ho microprocessor, sistimi ea hau e lokela ho kenyelletsa tse latelang: · AJTAG segokanyimmediamentsi sa sebolokigolo ho tšehetsa Altera FPGA tlhophiso, hardware le software
debugging · Mochini oa ho matlafatsa Altera FPGA
Haeba sistimi ea hau e na le bokhoni bona, o ka qala ho nchafatsa moralo oa hau ho tsoa ho moralo oa lisebelisoa tse lekiloeng tse kentsoeng ho Altera FPGA. Ho sebelisa Altera FPGA ho boetse ho u fa monyetla oa ho fetola moralo oa hau kapele ho rarolla mathata kapa ho eketsa ts'ebetso e ncha. U ka leka meralo ena e mecha ea lisebelisoa habonolo ka ho lokisa Altera FPGA u sebelisa sesebelisoa sa hau sa JTAG segokahanyi.
Leano la JTAG segokanyimmediamentsi sa sebolokigolo tšehetsa hardware le software ntshetsopele. U ka etsa mesebetsi e latelang u sebelisa JTAG sehokelo: · Hlophisa Altera FPGA · Khoasolla le ho lokisa software · Buisana le Altera FPGA ka sehokelo se kang UART (JTAG UART
terminal) · Debug hardware (ka Signal Tap embedded logic analyzer) · Memori ya flash ya lenaneo
Kamora hore o lokise Altera FPGA ka moralo o thehiloeng ho processor ea Nios V, phallo ea ntlafatso ea software e ts'oana le phallo ea meralo ea discrete ea microcontroller.

Lintlha Tse Amanang · AN 985: Tutorial ea Nios V processor
Tataiso e potlakileng ea ho theha sistimi e bonolo ea Nios V le ho tsamaisa sesebelisoa sa Hello World.
© Altera Corporation. Altera, logo ea Altera, letšoao la `a', le matšoao a mang a Altera ke matšoao a Altera Corporation. Altera e na le tokelo ea ho etsa liphetoho ho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera ha e nke boikarabelo kapa boikarabelo bo hlahang ka lebaka la kopo kapa tšebeliso ea tlhahisoleseding leha e le efe, sehlahisoa, kapa tšebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Altera. Bareki ba Altera ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

1. Mabapi le Nios® V Embedded Processor 726952 | 2025.07.16
· Nios V processor Reference Manual E fana ka leseli mabapi le litekanyetso tsa ts'ebetso ea processor ea Nios V, meralo ea processor, mofuta oa lenaneo, le ts'ebetsong ea mantlha.
· Embedded Peripherals IP User Guide · Nios V processor Software Developer Handbook

E hlalosa tikoloho ea ntlafatso ea processor ea Nios V, lisebelisoa tse teng, le mokhoa oa ho aha software e tla sebetsa ho processor ea Nios V. · Ashling* RiscFree* Tikoloho e Kopantsoeng ea Nts'etsopele (IDE) bakeng sa Bukana ea Mosebelisi ea Altera FPGAs E Hlalosa tikoloho ea ntlafatso e kopaneng ea RiscFree* (IDE) bakeng sa Altera FPGAs Arm*-based HPS le Nios V core processor. · Nios V processor Altera FPGA IP Release Notes
1.2. Quartus® Prime Software Support
Phallo ea processor ea Nios V e fapane bakeng sa software ea Quartus® Prime Pro Edition le software ea Quartus Prime Standard Edition. Sheba AN 980: Nios V processor Quartus Prime Software Support bakeng sa tlhaiso-leseling e batsi mabapi le phapang.
Lintlha tse amanang le AN 980: Nios V Processor Quartus Prime Software Support
1.3. Laesense ea processor ea Nios V
Mofuta o mong le o mong oa processor oa Nios V o na le senotlolo sa laesense. Ha u se u fumane senotlolo sa laesense, u ka sebelisa senotlolo se tšoanang sa laesense bakeng sa merero eohle ea processor ea Nios V ho fihlela letsatsi la ho felloa ke nako. U ka fumana laesense ea Nios V processor Altera FPGA IP ka litšenyehelo tsa zero.
Lethathamo la linotlolo tsa laesense ea processor ea Nios V le fumaneha Setsing sa Lilaesense sa Boithaopo sa Altera FPGA. Tobetsa konopo ea Sign up for Evaluation kapa Free License, ebe u khetha likhetho tse lumellanang ho etsa kopo.
Setšoantšo sa 1. Altera FPGA Setsi sa Lilaesense sa Boithaopo

Ka linotlolo tsa laesense, u ka:
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· Kenya tšebetsong processor ea Nios V ka har'a sistimi ea hau. * Etsisa boits'oaro ba sistimi ea processor ea Nios V. · Netefatsa tshebetso ya moralo, joalo ka boholo le lebelo. · Hlahisa lenaneo la lisebelisoa files. · Theha sesebelisoa 'me u netefatse moralo ho hardware.
Ha o hloke laesense ho nts'etsapele software ho Ashling* RiscFree* IDE bakeng sa Altera FPGAs.
Lintlha Tse Amanang le Setsi sa Altera FPGA Self-Service Licensing Center
Ho fumana lintlha tse ling mabapi le ho fumana linotlolo tsa laesense tsa Nios V processor Altera FPGA IP. · Altera FPGA Kemiso le Lilaesense tsa Software Bakeng sa tlhaiso-leseling e batsi mabapi le ho fana ka laesense ea software ea Altera FPGA le ho theha laesense e tsitsitseng le seva sa laesense ea marang-rang.
1.4. Moralo oa Sistimi e kenyellelitsoeng
Palo e latelang e bonts'a phallo e nolofalitsoeng ea processor ea Nios V e thehiloeng ho sistimi, ho kenyeletsoa ka bobeli hardware le nts'etsopele ea software.

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Setšoantšo sa 2.

Phallo ea Moralo oa Moqapi oa Nios V
Khopolo ea Tsamaiso

Sekaseka Litlhoko Tsa Tsamaiso

Nios® V
Li-processor Cores le Lisebelisoa tse Tloaelehileng

Hlalosa le ho Hlahisa Sisteme ho
Moqapi oa Sethala

Phallo ea Hardware: Kopanya le ho Kopanya Intel Quartus Prime Project

Phallo ea Software: Ntlafatsa le ho Haha Nios V Proposal Software

Phallo ea Hardware: Khoasolla Moralo oa FPGA
ho Board Board

Phallo ea Software: Teko le ho Debug Nios V processor Software

Software No Meets Spec?
Ee
Hardware No Meets Spec? Ee
Tsamaiso e Felletse

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2. Nios V processor Hardware System Design e nang le Quartus Prime Software le Platform Designer

Setšoantšo sa 3.

Setšoantšo se latelang se bonts'a moralo o tloaelehileng oa processor ea Nios V. Nios V processor System Phallo ea Hardware Design

Qala

Nios V Cores le Likarolo tse Tloaelehileng

Sebelisa Moqapi oa Platform ho Rala Sisteme e Thehiloeng ea Nios V
Hlahisa Moralo oa Moqapi oa Platform

Kopanya Setsi sa Moqapi oa Platform le Intel Quartus Prime Project
Abela Libaka tsa Pin, Litlhoko tsa Nako, le Litšitiso tse ling tsa Moralo
Kopanya Hardware bakeng sa Sesebelisoa sa Target ho Intel Quartus Prime

Itokiselitse ho Download
2.1. Ho theha Moralo oa Sistimi ea processor ea Nios V ka Moqapi oa Platform
Software ea Quartus Prime e kenyelletsa sesebelisoa sa ho kopanya sa Platform Designer se nolofatsang mosebetsi oa ho hlalosa le ho kopanya Nios V processor IP core le li-IP tse ling ho moralo oa sistimi ea Altera FPGA. Moqapi oa Platform o iketsetsa mohopolo oa khokahanyo ho tsoa ho khokahanyo e boletsoeng ea boemo bo holimo. The interconnect automation e felisa mosebetsi o jang nako oa ho hlakisa likhokahano tsa HDL tsa boemo ba sistimi.
© Altera Corporation. Altera, logo ea Altera, letšoao la `a', le matšoao a mang a Altera ke matšoao a Altera Corporation. Altera e na le tokelo ea ho etsa liphetoho ho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera ha e nke boikarabelo kapa boikarabelo bo hlahang ka lebaka la kopo kapa tšebeliso ea tlhahisoleseding leha e le efe, sehlahisoa, kapa tšebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Altera. Bareki ba Altera ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

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Kamora ho sekaseka litlhoko tsa lisebelisoa tsa sistimi, o sebelisa Quartus Prime ho hlakisa mantlha ea processor ea Nios V, memori le likarolo tse ling tseo sistimi ea hau e li hlokang. Moqapi oa Platform o iketsetsa mohopolo oa khokahano ho kopanya likarolo tsa sistimi ea Hardware.

2.1.1. Instantiating Nios V Processor Altera FPGA IP

You can instantiate any of the processor IP cores in Platform Designer IP Catalog Processors and Peripherals Embedded Processors.

IP ea mantlha ea processor e 'ngoe le e' ngoe e tšehetsa likhetho tse fapaneng tsa tlhophiso ho ipapisitsoe le meralo ea eona e ikhethang. U ka hlalosa litlhophiso tsena ho lumellana hantle le litlhoko tsa hau tsa moralo.

Lethathamo la 1.

Likhetho tsa Tlhophiso ho Likaroloana tsa Core

Dikgetho tsa Tlhophiso

Nios V/c processor

Nios V/m processor

Debug Sebelisa Reset Kopo

—

Maraba, Mekhelo, le Litšitiso

CPU Architecture

ECC

Li-Cache, Libaka tsa Peripheral le TCMs

—

Litaelo tse Tloaelehileng

—

Lockstep

—

Nios V/g processor

2.1.1.1. Instantiating Nios V/c Compact Microcontroller Altera FPGA IP Figure 4. Nios V/c Compact Microcontroller Altera FPGA IP

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2.1.1.1.1. CPU Architecture Tab

Lethathamo la 2.

CPU Architecture Tab

Sebopeho

Tlhaloso

Numella Avalon® Interface E nolofalletsa Avalon Interface bakeng sa molaoli oa litaelo le molaoli oa data. Haeba e holofetse, sistimi e sebelisa sebopeho sa AXI4-Lite.

mhartid CSR boleng

· Khetho e sa sebetseng ea IP. · Se ke oa sebelisa boleng ba mhartid CSR ho processor ea Nios V/c.

2.1.1.1.2. Sebelisa Reset Request Tab

Lethathamo la 3.

Sebelisa Parameter ea Reset Request Tab

Sebelisa Reset Request Tab

Tlhaloso

Kenya Reset Request Interface

· Numella khetho ena ho pepesa likou tsa reset ea lehae moo monghali oa lehae a ka e sebelisang ho etsa hore processor ea Nios V e boele e seta ntle le ho ama likarolo tse ling tsa sistimi ea Nios V.
· Sehokelo sa ho seta bocha se na le lets'oao la ho kenya retreq le lets'oao la ack.
· O ka kopa ho hlophisoa bocha ho processor ea Nios V ka ho tiisa lets'oao la retreq.
· Letšoao la retreq le tlameha ho lula le tiisitsoe ho fihlela processor e fana ka lets'oao la ack. Ho hloleha hore lets'oao le lule le tiile ho ka etsa hore processor e be maemong a sa tsitsang.
· Motlakase oa Nios V o arabela hore ho tsosolosa ho atlehile ka ho tiisa letšoao la ack.
· Kamora hore processor e hlophisoe ka katleho, polelo ea lets'oao la ack e ka etsahala hangata nako le nako ho fihlela ho hlakoloa ha lets'oao la resetreq.

2.1.1.1.3. Tab ea Maraba, Mekhelo, le Litšitiso

Lethathamo la 4.

Traps, Exceptions, le Interrupts Tab Parameters

Maraba, Mekhelo, le Litšitiso

Tlhaloso

Seta hape Moemeli

Seta hape Offset

· E totobatsa ho felisoa ha vector e seta botjha e amanang le aterese ea setsi se khethiloeng. · Moqapi oa Platform o fana ka boleng ba kamehla bakeng sa reset offset.

Hlokomela:

Moqapi oa Platform o fana ka khetho e felletseng, e u lumellang ho hlakisa aterese e felletseng ho Reset Offset. Sebelisa khetho ena ha memori e bolokang vector ea reset e fumaneha kantle ho sistimi ea processor le li-subsystems.

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2.1.1.1.4. Lethathamo la lintlha tsa ECC

Lethathamo la 5.

Lethathamo la lintlha tsa ECC

ECC

Lumella ho Fumana Phoso le Tlaleho ea Boemo

Tlhaloso
· Numella khetho ena ho sebelisa sebopeho sa ECC bakeng sa li-block tsa RAM tsa processor ea Nios V. · Likarolo tsa ECC li bona liphoso tse fihlang ho 2-bits ebe li arabela ho latela boitšoaro bo latelang:
- Haeba e le phoso e ka lokisoang 1-bit, processor e ntse e tsoela pele ho sebetsa ka mor'a ho lokisa phoso pompong ea processor. Leha ho le joalo, khalemelo ha e bontšoe mehopolong ea mohloli.
- Haeba phoso e sa lokisoe, processor e tsoela pele ho sebetsa ntle le ho e lokisa pompong ea processor le mehopolo ea mohloli, e ka etsang hore processor e kene maemong a sa tsitsang.

2.1.1.2. Instantiating Nios V/m Microcontroller Altera FPGA IP Figure 5. Nios V/m Microcontroller Altera FPGA IP

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2.1.1.2.1. Taba ea ho lokisa

Lethathamo la 6.

Debug Tab Parameters

Taba ea ho lokisa

Tlhaloso

Numella Debug
Numella ho Seta Botjha ho tsoa ho Debug Module

· Numella khetho ena ho eketsa faele ea JTAG target connection module to Nios V processor. · JTAG target connection module lumella ho hokela ho Nios V processor ka
JTAG li-interface pins tsa FPGA. · Khokahano e fana ka bokhoni bo latelang ba mantlha:
— Qala le ho emisa processor ea Nios V — Hlahloba le ho hlophisa lirejisete le memori. — Khoasolla sesebelisoa sa Nios V .elf file ho memori ea processor ka nako ea ho sebetsa ka
niosv-download. - Hlakola ts'ebeliso e sebetsang ho processor ea Nios V · Hokela boema-kepe ba dm_agent ho litaelo tsa processor le bese ea data. Netefatsa hore aterese ea motheo lipakeng tsa libese ka bobeli e tšoana.
· Numella khetho ena ho pepesa dbg_reset_out le ndm_reset_in ports. · JTAG debugger kapa niosv-download -r taelo qala dbg_reset_out, e leng
e lumella processor ea Nios V ho seta lisebelisoa tsa sistimi tse hokelang boema-kepeng bona. · O tlameha ho hokela dbg_reset_out interface ho ndm_reset_in ho fapana le ho seta bocha.
sehokelo ho etsa hore ho behoe botjha ho processor core le module ea nako. Ha oa tlameha ho hokela dbg_reset_out segokanyimmediamentsi sa sebolokigolo ho thibela boits'oaro bo sa feleng.

2.1.1.2.2. Sebelisa Reset Request Tab

Lethathamo la 7.

Sebelisa Parameter ea Reset Request Tab

Sebelisa Reset Request Tab

Tlhaloso

Kenya Reset Request Interface

· Numella khetho ena ho pepesa likou tsa reset ea lehae moo monghali oa lehae a ka e sebelisang ho etsa hore processor ea Nios V e boele e seta ntle le ho ama likarolo tse ling tsa sistimi ea Nios V.
· Sehokelo sa ho seta bocha se na le lets'oao la ho kenya retreq le lets'oao la ack.
· O ka kopa ho hlophisoa bocha ho processor ea Nios V ka ho tiisa lets'oao la retreq.
· Letšoao la retreq le tlameha ho lula le tiisitsoe ho fihlela processor e fana ka lets'oao la ack. Ho hloleha hore lets'oao le lule le tiile ho ka etsa hore processor e be maemong a sa tsitsang.
· Polelo ea lets'oao la resetreq ka mokhoa oa ho lokisa bothata ha e na phello ho boemo ba processor.
· Motlakase oa Nios V o arabela hore ho tsosolosa ho atlehile ka ho tiisa letšoao la ack.
· Kamora hore processor e hlophisoe ka katleho, polelo ea lets'oao la ack e ka etsahala hangata nako le nako ho fihlela ho hlakoloa ha lets'oao la resetreq.

2.1.1.2.3. Tab ea Maraba, Mekhelo, le Litšitiso

Lethathamo la 8.

Tab ea Maraba, Mekhelo, le Litšitiso

Tlhaloso

Seta hape Moemeli

Seta bocha mokhoa oa ho sitisa oa Offset

· E totobatsa ho felisoa ha vector e seta botjha e amanang le aterese ea setsi se khethiloeng. · Moqapi oa Platform o fana ka boleng ba kamehla bakeng sa reset offset.
Hlalosa mofuta oa li-control controller ebang ke Direct kapa Vectored. Tlhokomeliso: Sesebelisoa sa Nios V/m se senang liphaephe ha se tšehetse litšitiso tsa Vectored.
Ka hona, qoba ho sebelisa Vectored interrupt mode ha processor e le maemong a Nonpipelined.

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Hlokomela:

2.1.1.2.4. CPU Architecture

Lethathamo la 9.

Li-parameter tsa Tab ea Architecture ea CPU

CPU Architecture

Tlhaloso

Numella Pipelining ho CPU

· Numella khetho ena ho kenya processor ea liphaephe ea Nios V/m. - IPC e phahame ka theko ea sebaka se phahameng sa logic le maqhubu a tlase a Fmax.
· Tlosa khetho ena ho kenya processor ea Nios V/m e sa keneng. - E na le ts'ebetso ea mantlha e ts'oanang le processor ea Nios V / c. - E ts'ehetsa bokhoni ba ho lokisa le ho sitisa - Sebaka se tlase sa logic le maqhubu a phahameng a Fmax ka theko ea IPC e tlase.

Lumella Avalon Interface

E nolofalletsa Avalon Interface bakeng sa molaoli oa litaelo le mookameli oa data. Haeba e holofetse, sistimi e sebelisa sebopeho sa AXI4-Lite.

mhartid CSR boleng

· Hart ID rejisete (mhartid) boleng ke 0 kamehla. · Abela boleng pakeng tsa 0 le 4094. · E tsamaisana le Altera FPGA Avalon Mutex Core HAL API.

Tlhahisoleseding e Amanang e Kenyelitsoeng Peripheral IP User Guide - Intel FPGA Avalon® Mutex Core

2.1.1.2.5. Lethathamo la lintlha tsa ECC
Letlapa la 10. Taba ea ECC
ECC E nolofalletsa ho Fumana Phoso le Tlaleho ea Boemo

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2.1.1.3. Instantiating Nios V/g General Purpose Processor Altera FPGA IP
Setšoantšo sa 6. Nios V / g General Purpose Processor Altera FPGA IP - Karolo ea 1

Setšoantšo sa 7.

Nios V/g General Purpose Processor Altera FPGA IP - Karolo ea 2 (Tima Noble Core Level Interrupt Controller)

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Setšoantšo sa 8.

Nios V/g General Purpose processor Altera FPGA IP - Karolo ea 2 (Bulela Noble Level Interrupt Controller)

Setšoantšo sa 9. Nios V / g General Purpose Processor Altera FPGA IP - Karolo ea 3

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Setšoantšo sa 10. Nios V / g General Purpose Processor Altera FPGA IP - Karolo ea 4

2.1.1.3.1. CPU Architecture

Letlapa la 11. Li-Parameters tsa Architecture tsa CPU

Tabo ea Meaho ea CPU E nolofalletsa Yuniti ea Lintlha tse Phaphamang

Tlhaloso Numella khetho ena ho eketsa yuniti ea floating-point ("F" extension) mokokotlong oa processor.

Thusa Polelo ea Lekala

Numella bolepi ba lekala le sa sisinyeheng (Ho Nkoa ka Morao le ho Tsoela Pele Ha hoa Nkoa) bakeng sa litaelo tsa lekala.

mhartid CSR boleng

· Hart ID rejisete (mhartid) boleng ke 0 kamehla. · Abela boleng pakeng tsa 0 le 4094. · E tsamaisana le Altera FPGA Avalon Mutex Core HAL API.

Tlosa litaelo tsa FSQRT le FDIV bakeng sa FPU

· Tlosa ts'ebetso ea floating-point square root (FSQRT) le karolo ea floating-point (FDIV) ho FPU.
· Sebelisa mohlala oa software ho litaelo ka bobeli nakong ea ho sebetsa.

Tlhahisoleseding e Amanang e Kenyelitsoeng Peripheral IP User Guide - Intel FPGA Avalon® Mutex Core

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2.1.1.3.2. Taba ea ho lokisa

Letlapa la 12. Li-Parameters tsa Tab ea Debug

Taba ea ho lokisa

Tlhaloso

Numella Debug
Numella ho Seta Botjha ho tsoa ho Debug Module

2.1.1.3.3. Lockstep Tab Tab 13. Lockstep Tab
Liparamente Lumella Lockstep Default Timeout Nako Lumella Interface e Atolositsoeng ea ho Seta Botjha

Tlhaloso · Numella sistimi ea mantlha ea Lockstep. · Boleng ba kamehla ba nako e lokiselitsoeng ho tsoa ha re seta bocha (pakeng tsa 0 le 255). · Numella Sehokelo se Atolositsoeng sa Reset bakeng sa Taolo e Atolositsoeng ea Reset. · Ha e holofalitsoe, fRSmartComp e sebelisa Basic Reset Control.

2.1.1.3.4. Sebelisa Reset Request Tab

Letlapa la 14. Sebelisa Reset Request Tab Parameter

Sebelisa Reset Request Tab

Tlhaloso

Kenya Reset Request Interface

· Numella khetho ena ho pepesa likou tsa reset ea lehae moo monghali oa lehae a ka e sebelisang ho etsa hore processor ea Nios V e boele e seta ntle le ho ama likarolo tse ling tsa sistimi ea Nios V.
· Sehokelo sa ho seta bocha se na le lets'oao la ho kenya retreq le lets'oao la ack.
· O ka kopa ho hlophisoa bocha ho processor ea Nios V ka ho tiisa lets'oao la retreq.
· Letšoao la retreq le tlameha ho lula le tiisitsoe ho fihlela processor e fana ka lets'oao la ack. Ho hloleha hore lets'oao le lule le tiile ho ka etsa hore processor e be maemong a sa tsitsang.
· Polelo ea lets'oao la resetreq ka mokhoa oa ho lokisa bothata ha e na phello ho boemo ba processor.
· Motlakase oa Nios V o arabela hore ho tsosolosa ho atlehile ka ho tiisa letšoao la ack.
· Kamora hore processor e hlophisoe ka katleho, polelo ea lets'oao la ack e ka etsahala hangata nako le nako ho fihlela ho hlakoloa ha lets'oao la resetreq.

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2.1.1.3.5. Tab ea Maraba, Mekhelo, le Litšitiso

Lethathamo la 15.

Traps, Exceptions, and Interrupts Tab ha Enable Core Level Interrupt Controller e Timiloe

Tab ea Maraba, Mekhelo, le Litšitiso
Seta hape Moemeli

Tlhaloso
· Memori e nang le vector ea reset (aterese ea ho seta processor ea Nios V) moo khoutu ea ho seta bocha e lula teng.
· O ka khetha mojule ofe kapa ofe oa memori o hokahantsoeng le master instruction processor ea Nios V mme o tšehetsoa ke "Nios V processor boot flow".

Seta hape Offset

· E totobatsa ho felisoa ha vector e seta botjha e amanang le aterese ea setsi se khethiloeng. · Moqapi oa Platform o fana ka boleng ba kamehla bakeng sa reset offset.

Numella Core Level Interrupt Controller (CLIC)

· Numella CLIC ho ts'ehetsa litšitiso tsa pele ho ts'ebetso le maemo a ka lokisehang a tšitiso.
· Ha o nolofalitsoe, o ka lokisa palo ea litšitiso tsa sethala, oa beha maemo a sesosa, 'me u khethe tse ling tsa litšitiso e le tsa pele.

Thibela Rejistara ea Moriti oa Mokhoa Files

Hlalosa mefuta ea litšitiso joalo ka Direct, kapa Vectored Enable shadow registeri ho fokotsa ho fetoha ha maemo ha ho sitisoa.

Lethathamo la 16.

Maraba, Mekhelo le Litšitiso ha Numella Core Level Interrupt Controller e Buletsoe

Maraba, Mekhelo, le Litšitiso

Litlhaloso

Seta hape Moemeli
Seta hape Offset
Numella Core Level Interrupt Controller (CLIC)

· Memori e nang le vector ea reset (aterese ea ho seta processor ea Nios V) moo khoutu ea ho seta bocha e lula teng.
· O ka khetha mojule ofe kapa ofe oa memori o hokahantsoeng le master instruction processor ea Nios V mme o tšehetsoa ke "Nios V processor boot flow".
· E totobatsa ho felisoa ha vector e seta botjha e amanang le aterese ea setsi se khethiloeng. · Moqapi oa Platform o fana ka boleng ba kamehla bakeng sa reset offset.
· Numella CLIC ho ts'ehetsa litšitiso tsa pele ho ts'ebetso le maemo a ka lokisehang a tšitiso. · Ha o nolofalitsoe, o ka hlophisa palo ea litšitiso tsa sethala, beha maemo a ho tsosa,
le ho khetha tse ling tsa litšitiso e le tsa pele.

Khatiso ea Mokhoa

* Hlalosa mefuta ea litšitiso e le Direct, Vectored, kapa CLIC.

Ngoliso ea Moriti Files

‣ Numella rejisetara ea moriti ho fokotsa ho fetoha ha maemo nakong ea tšitiso.
· E fana ka mekhoa e 'meli:
- Palo ea maemo a sitisang CLIC
- Palo ea maemo a sitisang CLIC - 1: Khetho ena e bohlokoa ha o batla palo ea ngoliso file likopi ho lekana palo e nepahetseng ea li-block tsa M20K kapa M9K.
· Numella processor ea Nios V ho sebelisa rejisetara ea moriti files e fokotsang ho feto-fetoha ha maemo ha ho sitisoa.
Bakeng sa tlhahisoleseling e eketsehileng mabapi le ngoliso ea moriti files, sheba Bukana ea Reference ea processor ea Nios V.

Palo ea mehloli e sitisang Platform

· E hlalosa palo ea tšitiso ea sethala pakeng tsa 16 le 2048.
Tlhokomeliso: CLIC e ts'ehetsa lintho tse kenang tse fihlang ho tse 2064, 'me lintlha tsa pele tse 16 tse sitisang le tsona li hokahane le selaoli sa tšitiso ea mantlha.

Ho tsamaisana le Tafole ea Vector ea CLIC

· Iketsetse qeto ho ipapisitsoe le palo ea mehloli e sitisang sethaleng. · Haeba o sebelisa tepo e ka tlase ho boleng bo khothalelitsoeng, CLIC e eketsa mohopolo
ho rarahana ka ho kenya seretse se eketsehileng ho etsa lipalo tsa vectoring. · Haeba o sebelisa tekano e ka tlase ho boleng bo khothalelitsoeng, sena se fella ka keketseho
ho rarahana ha kelello ho CLIC.
e tsoela pele…

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Maraba, Mekhelo, le Litšitiso
Palo ea Maemo a Khatiso
Palo ea Likhatiso tse ka Sehloohong mohato ka mong
Configurable sitisa polarity Tšehetso e bakile litšitiso

Litlhaloso
· E hlalosa palo ea likhaello tsa tšitiso ka boemo bo eketsehileng ba 0 bakeng sa khoutu ea kopo. Litšitiso tsa boemo bo holimo li ka sitisa (pre-empt) sebatli se mathang bakeng sa tšitiso ea boemo bo tlase.
· Ka maemo a sa sitisoeng ke zero e le tsona feela likhetho tsa litšitiso, khoutu ea kopo e lula e le boemong bo tlase ka ho fetesisa 0. Ela hloko: Tokiso ea nako ea ho matha ea boemo ba tšitiso le ntho e tlang pele e etsoa ho rejisetara e le 'ngoe ea 8-bit. Haeba palo ea likhakanyo tsa tšitiso e le 256, ho ke ke ha khoneha ho hlophisa tšitiso e tlang pele ka nako ea ts'ebetso. Ho seng joalo, palo e kholo ea lintho tse tlang pele tse ka lokisoang ke 256 / (palo ea maemo a tšitiso - 1).
· E hlakisa palo ea lintho tse tlang pele tse sitisang, tseo CLIC e li sebelisang ho fumana hore na batho ba sa sitiseng letho ba bitsoa joang. Tlhokomeliso: Khokahano ea boleng ba binary ea boemo bo khethiloeng ba tšitiso le ntho e tlang pele ea tšitiso e tlameha ho ba ka tlase ho li-bits tse 8.
· E u lumella ho hlophisa polarity e sitisang nakong ea ho sebetsa. · Polarity ea kamehla ke polarity e ntle.
· E o lumella ho lokisa boemo ba tšitiso nakong ea ts'ebetso, ke hore, boemo bo phahameng bo hlahisitsoeng kapa chebahalo e ntle (ha polarity ea tšitiso e le ntle ho Configurable interrupt polarity).
· Default trigger boemo ke boemo ba ile ba sitisa.

Hlokomela:

Tlhahisoleseding e Amanang le Bukana ea Reference ea Nios® V

2.1.1.3.6. Taba ea Litlhophiso tsa Memori

Letlapa la 17. Mekhahlelo ea Memori ea Tlhophiso ea Memori

Sehlopha

Taba ea Tlhophiso ea Memori

Tlhaloso

Cache

Boholo ba Cache ea data

· E hlalosa boholo ba cache ea data. · Boholo bo sebetsang bo tloha ho 0 kilobytes (KB) ho isa ho 16 KB. • Tima cache ea data ha boholo bo le 0 KB.

Litaelo Cache Size

· E hlalosa boholo ba cache ea litaelo. · Boholo bo sebetsang bo tloha ho 0 KB ho isa ho 16 KB. • Tima cache ea litaelo ha boholo bo le 0 KB.

Peripheral Region A le B

Boholo

· E hlalosa boholo ba sebaka sa peripheral.
· Boholo bo sebetsang bo tloha ho 64 KB ho isa ho 2 gigabytes (GB), kapa Ha ho letho. Ho Khetha Ha ho letho ho tima sebaka sa peripheral.

Aterese ea Motheo

· E hlalosa aterese ea motheo ea sebaka sa peripheral ka mor'a hore u khethe boholo.
· Liaterese tsohle tse sebakeng sa peripheral li hlahisa phihlello e sa khoneheng ea data.
· Aterese ea motheo ea tikoloho e tlameha ho tsamaellana le boholo ba sebaka sa peripheral.

Mehopolo e Kopanetsoeng Hantle

Boholo

· E hlalosa boholo ba memori e kopantsoeng ka thata. - Boholo bo sebetsang bo tloha ho 0 MB ho isa ho 512 MB.

Ho qala Aterese ea Motheo File

· E totobatsa aterese ea mantlha ea mohopolo o kopantsoeng ka thata. · E bolela ho qala file bakeng sa memori e kopantsoeng ka thata.

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Hlokomela:

Sistimi ea processor ea Nios V e nang le cache e nolofalitsoeng, o tlameha ho beha li-peripheral tsa sistimi sebakeng sa peripheral. U ka sebelisa libaka tsa peripheral ho hlalosa transaction e sa bolokeheng bakeng sa li-peripherals tse kang UART, PIO, DMA, le tse ling.

2.1.1.3.7. Lethathamo la lintlha tsa ECC

Letlapa la 18. Taba ea ECC
ECC E nolofalletsa ho Fumana Phoso le Tlaleho ea Boemo
Numella Tokiso ea Bit e le 'Ngoe

Tlhaloso
· Numella khetho ena ho sebelisa sebopeho sa ECC bakeng sa li-block tsa RAM tsa processor ea Nios V. · Likarolo tsa ECC li bona liphoso tse fihlang ho 2-bits ebe li arabela ho latela boitšoaro bo latelang:
- Haeba e le phoso e ka lokisoang, 'me Enable Single Bit Correction e tingoa, processor e ntse e tsoela pele ho sebetsa ka mor'a ho lokisa phoso pompong ea processor. Leha ho le joalo, khalemelo ha e bontšoe mehopolong ea mohloli.
- Haeba e le phoso e ka lokisoang, 'me Enable Single Bit Correction e buletsoe, processor e ntse e tsoela pele ho sebetsa ka mor'a ho lokisa phoso pompong ea processor le mehopolo ea mohloli.
- Haeba e le phoso e sa lokisoeng, processor e emisa ts'ebetso ea eona.
Numella tokiso ea biti e le 'ngoe ho li-blocks tse kentsoeng ka har'a mantlha.

2.1.1.3.8. Tab ea Taelo e Tloaelehileng

Hlokomela:

Taba ena e fumaneha feela bakeng sa mantlha ea processor ea Nios V/g.

Taelo e Tloaelehileng Nios V Custom Instruction Hardware Interface Table
Nios V Custom Instruction Software Macro Tafole

Tlhaloso
· Nios V processor e sebelisa tafole ena ho hlalosa li-interface tsa eona tsa taolo ea litaelo.
· Likamano tse hlalositsoeng tsa molaoli oa moetlo li kentsoe ka mokhoa o ikhethileng ke Opcode (CUSTOM0-3) le li-bits tse 3 tsa funct7[6:4].
· U ka hlalosa lihokelo tse 32 tsa taolo ea motho ka mong.
· Nios V processor e sebelisa tafole ena e sebelisetsoa ho hlalosa li-encodings tsa software ea taeo bakeng sa li-interfaces tse hlalositsoeng tsa mookameli oa litaelo.
· Bakeng sa khouto e 'ngoe le e 'ngoe e hlalositsoeng ea software ea taeo, Opcode (CUSTOM0-3) le 3 bits of funct7[6:4] encoding e tlameha ho hokahanngoa le khouto e hlalositsoeng ea molaoli oa litaelo ho Tafole ea Custom Instruction Hardware Interface.
U ka sebelisa funct7[6:4], funct7[3:0], le funct3[2:0] ho hlalosa khouto e eketsehileng bakeng sa taeo e fanoeng ka tloaelo, kapa e hlalositsoe e le Xs e tla fetisoa e le mabaka a tlatsetso a litaelo.
· Nios V processor e fana ka li-encodings tsa software ea taeo e tloaelehileng joalo ka ha C-macros e hlahisitsoe ka system.h, 'me e latele mofuta oa taeo oa mofuta oa R RISC-V.
· Menemonics e ka sebelisoa ho hlalosa mabitso a tloaelo bakeng sa: — The generated C-Macros in system.h.
— Menemonics e hlahisitsweng ya GDB ho custom_instruction_debug.xml.

Lintlha Tse Amanang
AN 977: Nios V Custom Custom Instruction Bakeng sa tlhahisoleseling e eketsehileng mabapi le litaelo tsa tloaelo tse u lumellang hore u iketsetse processor ea Nios® V ho fihlela litlhoko tsa sesebelisoa se itseng.

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2.1.2. Ho Hlalosa Moralo oa Karolo ea Tsamaiso
Sebelisa Moqapi oa Platform ho hlalosa litšobotsi tsa Hardware tsa sistimi ea processor ea Nios V le ho kenyelletsa likarolo tse lakatsehang. Sets'oants'o se latelang se bonts'a moralo oa mantlha oa processor ea Nios V ka likarolo tse latelang: · Nios V processor core · On-Chip Memory · JTAG UART · Nako ea Nako (boikhethelo)(1)
Ha On-Chip Memory e ncha e eketsoa ho sistimi ea Moqapi oa Platform, etsa Sync System Infos ho bonts'a likarolo tsa memori tse kentsoeng ha u seta bocha. Ntle le moo, o ka nolofalletsa Auto Sync ho Platform Designer ho bonahatsa ka bo eona liphetoho tsa morao-rao tsa likarolo
Setšoantšo sa 11. Example khokahano ea processor ea Nios V le lisebelisoa tse ling ho Moqapi oa Platform

(1) U na le khetho ea ho sebelisa likarolo tsa Nios V Internal Timer ho nkela sebaka sa kantle sa Nako ea Nako ho Moqapi oa Platform.

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U tlameha hape ho hlalosa lithapo tsa ts'ebetso tse tla romelloa kantle ho naha e le mokhoa oa hau oa Moqapi oa Platform. Bakeng sa mohlalaampLeha ho le joalo, lenane le nepahetseng la lipini tsa ts'ebetso ea FPGA le hlalosoa ka tlase empa ha le felle feela ho:
· Oache
· Seta bocha
· Lipontšo tsa I/O
2.1.3. Ho Hlalosa Liaterese Tsa Motheo le Lintho Tse Tlang Pele Tse Kopang Khatiso
Ho hlakisa hore na likarolo tse kenyellelitsoeng moralong li sebelisana joang ho theha sistimi, o hloka ho fana ka liaterese tsa motheo bakeng sa karolo e 'ngoe le e' ngoe ea moemeli le ho fana ka likopo tsa tšitiso (IRQ) bakeng sa J.TAG UART le nako ea nako. Moqapi oa Platform o fana ka taelo - Fana ka Liaterese tsa Base - e fanang ka liaterese tse nepahetseng ho likarolo tsohle tsa sistimi. Leha ho le joalo, o ka fetola liaterese tsa motheo ho latela litlhoko tsa hau.
Lintlha tse latelang ke tse ling tsa ho fana ka liaterese tsa motheo:
· Nios V processor core e na le aterese ea 32-bit. Ho fihlella likarolo tsa moemeli, liaterese tsa bona tsa motheo li tlameha ho tloha pakeng tsa 0x00000000 le 0xFFFFFFFF.
· Mananeo a Nios V a sebelisa li-constants tsa tšoantšetso ho bua ka liaterese. Ha ho hlokahale hore u khethe litekanyetso tsa aterese tseo ho leng bonolo ho li hopola.
· Litaelo tsa aterese tse khethollang likarolo tse nang le phapang e le 'ngoe feela ea aterese li hlahisa hardware e sebetsang hantle haholoanyane. Ha ho hlokahale hore u kopanye liaterese tsohle tsa motheo sebakeng se senyenyane ka ho fetisisa sa liaterese hobane ho kopanya ho ka hlahisa lisebelisoa tse sa sebetseng hantle.
· Moqapi oa Platform ha a leke ho hokahanya likarolo tsa memori tse arohaneng sebakeng se kopaneng sa memori. Bakeng sa mohlalaampLeha ho le joalo, haeba u batla likarolo tse ngata tsa Memory On-Chip tse ka rarolloang e le mofuta o le mong oa memori o kopaneng, o tlameha ho fana ka liaterese tsa motheo ka ho hlaka.
Moqapi oa Platform o boetse o fana ka taelo ea othomathike - Fana ka Linomoro tsa Khatiso e hokahanyang mats'oao a IRQ ho hlahisa liphetho tse nepahetseng tsa Hardware. Leha ho le joalo, ho abela li-IRQ ka nepo ho hloka kutloisiso ea boitšoaro bo akaretsang ba karabelo ea sistimi. Moqapi oa Platform ha a khone ho hakanya ka mosebetsi o motle ka ho fetisisa oa IRQ.
Boleng bo tlase ba IRQ bo na le bohlokoa bo holimo. Ka sistimi e nepahetseng, Altera e khothaletsa hore karolo ea sebali-nako e be le IRQ e tlang pele ka ho fetesisa, ke hore, boleng bo tlase, ho boloka ts'epahalo ea letšoao la oache ea sistimi.
Maemong a mang, o ka beha lintho tse tlang pele ho lisebelisoa tsa nako ea nnete (joalo ka lilaoli tsa video), tse hlokang sekhahla se phahameng sa tšitiso ho feta likarolo tsa nako.
Lintlha Tse Amanang
Tataiso ea Mosebelisi ea Quartus Prime Pro Edition: Lintlha tse ling mabapi le ho theha Sisteme e nang le Moqapi oa Platform.

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2.2. Ho kopanya Setsi sa Moqapi oa Platform ho Morero oa Quartus Prime
Kamora ho hlahisa moralo oa sistimi ea Nios V ho Moqapi oa Sethala, etsa mesebetsi e latelang ho kopanya mojule oa sistimi ea Nios V morerong oa moralo oa Quartus Prime FPGA. · Kenya mochini oa Nios V ho projeke ea Quartus Prime · Hokela mats'oao a tsoang ho Nios V system ho ea ho matšoao a mang ho FPGA logic
2.2.1. Ho kenya ts'ebetsong ea Nios V Processor System Module ho Quartus Prime Project
Moqapi oa Platform o hlahisa mokhatlo oa moralo oa module oa sistimi oo o ka o kenyang ho Quartus Prime. Mokhoa oa ho kenya mojule oa sistimi o ipapisitse le mokhoa oa ho kenya moralo bakeng sa projeke e akaretsang ea Quartus Prime. Bakeng sa mohlalaample, haeba u ne u sebelisa Verilog HDL bakeng sa ho kena ka moralo, kenya mochine oa Verilog based system module. Haeba u khetha ho sebelisa mokhoa oa "block diagram" bakeng sa ho kenya moralo, kenya letšoao la mojule oa sistimi .bdf file.
2.2.2. Ho kopanya Lipontšo le ho Abela Libaka tsa Pin ea 'Mele
Ho hokela moralo oa hau oa Altera FPGA le moralo oa boemo ba boto ea hau, etsa mesebetsi e latelang: · hloaea boemo bo holimo. file bakeng sa moralo oa hau le matšoao a ho hokela ho Altera ea kantle
Lithako tsa lisebelisoa tsa FPGA. · Utloisisa hore na ke lithakhisa life tseo u lokelang ho li hokela ka tataiso ea mosebelisi oa moetso oa boto kapa
meralo. · Fana ka matšoao a moralo oa boemo bo holimo ho likou tsa sesebelisoa sa hau sa Altera FPGA ka phini
lisebelisoa tsa kabelo.
Sistimi ea hau ea Moqapi oa Platform e ka ba moralo oa boemo bo holimo. Leha ho le joalo, Altera FPGA e ka boela ea kenyelletsa lintlha tse eketsehileng tse thehiloeng litlhoko tsa hau 'me kahoo e hlahisa maemo a holimo a tloaelehileng. file. Boemo bo holimo file e hokela matšoao a module ea processor ea Nios V le logic e 'ngoe ea moralo oa Altera FPGA.
Tlhahisoleseding e Amanang le Quartus Prime Pro Edition User Guide: Litšitiso tsa Moqapi
2.2.3. E thibela Moralo oa Altera FPGA
Moralo o nepahetseng oa sistimi ea Altera FPGA e kenyelletsa lithibelo tsa moralo ho netefatsa hore moralo o kopana le ho koaloa ha nako le litlhoko tse ling tsa logic. U tlameha ho qobella moralo oa hau oa Altera FPGA ho fihlela litlhoko tsena ka ho hlaka u sebelisa lisebelisoa tse fanoeng ho Quartus Prime software kapa bafani ba EDA ba mokha oa boraro. Software ea Quartus Prime e sebelisa litšitiso tse fanoeng nakong ea ho kopanya ho fumana liphetho tse nepahetseng tsa ho beoa.

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Lintlha tse Amanang · Quartus Prime Pro Edition Tataiso ea Mosebelisi: Litšitiso tsa Moralo · Basebelisi ba EDA ba mokha oa boraro · Quartus Prime Pro Edition Tataiso ea mosebelisi: Mohlahlobi oa Nako
2.3. Ho theha Sisteme ea Memori ea processor ea Nios V
Karolo ena e hlalosa mekhoa e metle ea ho khetha lisebelisoa tsa memori ho sistimi e kentsoeng ea Moqapi oa Platform e nang le processor ea Nios V le ho fihlela ts'ebetso e nepahetseng. Lisebelisoa tsa memori li bapala karolo ea bohlokoa ho ntlafatseng ts'ebetso e akaretsang ea sistimi e kentsoeng. Memori ea sistimi e kentsoeng e boloka litaelo tsa lenaneo le data.
2.3.1. Mehopolo e sa fetoheng
Phapang e ka sehloohong mofuteng oa memori ke volatility. Memori e feto-fetohang e tšoara feela likahare tsa eona ha o ntse o fana ka matla ho sesebelisoa sa memori. Hang ha o tlosa matla, memori e lahleheloa ke litaba tsa eona.
ExampMehopolo e sa tsitsang ke RAM, cache le lirejistara. Tsena ke mefuta ea memori e potlakileng e eketsang ts'ebetso ea ho sebetsa. Altera e khothaletsa hore u kenye le ho sebelisa litaelo tsa processor ea Nios V ho RAM 'me u para Nios V IP core le On-Chip Memory IP kapa External Memory Interface IP bakeng sa ts'ebetso e nepahetseng.
Ho ntlafatsa ts'ebetso, o ka felisa likarolo tse ling tsa ho ikamahanya le Moqapi oa Platform ka ho bapisa mofuta oa sebopeho sa mookameli oa data oa Nios V kapa bophara le boot RAM. Bakeng sa mohlalaample, o ka lokisa On-Chip Memory II ka sebopeho sa 32-bits AXI-4, se lumellanang le sebopeho sa mookameli oa data oa Nios V.
Tlhahisoleseding e Amanang · Litšebelisano tsa Kantle tsa Memori Setsi sa Tšehetso sa IP · On-Chip Memory (RAM kapa ROM) Altera FPGA IP · On-Chip Memory II (RAM kapa ROM) Altera FPGA IP · Nios V Kopo ea Ts'ebetso ea Ts'ebetso ea Ts'ebetso ho tloha OCRAM leqepheng la 54
2.3.1.1. On-Chip Memory Configuration RAM kapa ROM
O ka lokisa Altera FPGA On-Chip Memory IPs joalo ka RAM kapa ROM. · RAM e fana ka bokhoni ba ho bala le ho ngola ebile e na le sebopeho se feto-fetohang. Haeba u
ho bulela processor ea Nios V ho tsoa ho RAM ea On-Chip, o tlameha ho etsa bonnete ba hore litaba tsa boot li bolokiloe 'me ha li senyehe ha ho ka etsoa reset nakong ea nako. · Haeba processor ea Nios V e qala ho tsoa ROM, bug efe kapa efe ea software ho processor ea Nios V e ke ke ea hlakola litaba tsa On-Chip Memory ka phoso. Kahoo, ho fokotsa kotsi ea bobolu ba software ea boot.
Tlhahisoleseding e Amanang · On-Chip Memory (RAM kapa ROM) Altera FPGA IP · On-Chip Memory II (RAM kapa ROM) Altera FPGA IP · Nios V processor Application Execute-In-Place ho tloha OCRAM leqepheng la 54

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2.3.1.2. Cache
Mehopolo ea on-chip e atisa ho sebelisoa ho kenya ts'ebetso ea cache ka lebaka la latency ea bona e tlaase. Mochine oa Nios V o sebelisa memori ea on-chip bakeng sa litaelo tsa eona le li-cache tsa data. Bokhoni bo fokolang ba memori ea on-chip hangata ha se bothata bakeng sa li-cache hobane hangata li nyane.
Li-cache hangata li sebelisoa tlas'a maemo a latelang:
· Memori ea kamehla e fumaneha kantle ho chip mme e na le nako e telele ea phihlello ho feta memori ea on-chip.
· Likarolo tsa bohlokoa tsa ts'ebetso ea khoutu ea software li ka lumellana le cache ea litaelo, tsa ntlafatsa ts'ebetso ea sistimi.
· Karolo ea bohlokoa ea ts'ebetso, e sebelisoang khafetsa ea data e ka lumellana le cache ea data, ea ntlafatsa ts'ebetso ea sistimi.
Ho nolofalletsa li-cache ho processor ea Nios V ho theha sehlopha sa memori, se fokotsang nako ea phihlello ea memori.
2.3.1.2.1. Peripheral region
Lisebelisoa life kapa life tse kentsoeng tsa IP, joalo ka UART, I2C, le SPI ha lia tlameha ho bolokoa. Cache e khothaletsoa haholo bakeng sa mehopolo ea kantle e anngoeng ke nako e telele ea phihlello, athe mehopolo ea kahare ho chip e kanna ea qheleloa ka thoko ka lebaka la nako e khuts'oane ea phihlello. Ha oa tlameha ho boloka li-IP tsa peripheral tse kenelletseng, joalo ka UART, I2C, le SPI, ntle le mehopolo. Sena ke sa bohlokoa hobane liketsahalo tse tsoang lisebelisoa tse ka ntle, tse kang lisebelisoa tsa moemeli tse ntlafatsang li-IP tse bonolo, ha li tšoaroe ke cache ea processor, le eona ha e amoheloe ke processor. Ka lebaka leo, liketsahalo tsena li ka tsamaea li sa hlokomeloe ho fihlela u hlakola cache, e leng se ka lebisang boitšoarong bo sa reroang tsamaisong ea hau. Ka bokhutšoanyane, sebaka se kentsoeng mohopolong sa li-IP tsa peripheral tse kenelletseng ha se khonehe 'me se tlameha ho lula ka har'a libaka tsa processor.
Ho seta sebaka sa peripheral, latela mehato ena:
1. Bula 'Mapa oa Aterese oa sistimi ho Moqapi oa Sethala.
2. Tsamaea ho ea 'mapeng oa aterese oa Mookameli oa Taelo ea processor le Data Manager.
3. Lemoha lintho tse amanang le peripherals le mehopolo tsamaisong ea hau.
Setšoantšo sa 12. Example ea Aterese Map

Tlhokomeliso: Metsu e putsoa e supa mehopolo. 4. Hlopha liphapang:
a. Memori e ka bolokoang b. Li-peripherals ha li khonehe

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Lethathamo la 19. Sebaka sa Cacheable le se sa khoneheng

Ya tlase

'Mapa oa Aterese

Boemo

Sebaka sa Peripheral

Boholo

Aterese ea Motheo

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent bootcopier_rom.s1

0x40000 ~ 0x4ffff 0x50000 ~ 0x517ff

Uncacheable Cacheable

65536 byte N/A

0x40000 N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm

0x52000 ~ 0x537ff 0x54000 ~ 0x5403f 0x54040 ~ 0x5407f

Cacheable Uncacheable Uncacheable

144 byte (boholo bo fokolang ke 65536 byte)

0x54000

sysid_qsys_0.control_slave

0x54080 ~ 0x54087

E sa khoneheng

uart.avalon_jtag_lekhoba

0x54088 ~ 0x5408f

E sa khoneheng

5. Hlophisa libaka tsa peripheral le boholo ba tsona bo ikhethileng:
· Bakeng sa mohlample, haeba boholo ke 65536 bytes, e lumellana le 0x10000 bytes. Ka hona, aterese ea motheo e lumelletsoeng e tlameha ho ba makhetlo a mangata a 0x10000.
· CPU.dm_agent e sebelisa aterese ea motheo ea 0x40000, e leng makhetlo a mangata a 0x10000. Ka lebaka leo, Sebaka sa Peripheral A, se nang le boholo ba li-byte tsa 65536 le aterese ea motheo ea 0x40000, se finyella litlhoko.
· Aterese ea motheo ea pokello ea libaka tse sa khoneheng ho 0x54000 ha se palo e ngata ea 0x10000. U tlameha ho li abela hape ho 0x60000 kapa tse ling tse ngata tsa 0x10000. Kahoo, Peripheral Region B, e nang le boholo ba li-byte tse 65536 le aterese ea motheo ea 0x60000, e khotsofatsa litekanyetso.

Letlapa la 20. Sebaka sa Cacheable le se sa khoneheng se nang le Reassignment

Ya tlase

'Mapa oa Aterese

Boemo

Sebaka sa Peripheral

Boholo

Aterese ea Motheo

user_application_mem.s1

0x0 ~ 0x3ffff

Cacheable

N/A

cpu.dm_agent

0x40000 ~ 0x4ffff

Uncacheable 65536 byte

0x40000

bootcopier_rom.s1

0x50000 ~ 0x517ff

Cacheable

N/A

bootcopier_ram.s1 cpu.timer_sw_agent mailbox.avmm sysid_qsys_0.control_slave

0x52000 ~ 0x537ff 0x60000 ~ 0x6003f 0x60040 ~ 0x6007f 0x60080 ~ 0x60087

Cacheable Uncacheable Uncacheable Uncacheable

144 byte (boholo bo fokolang ke 65536 byte)

0x60000

uart.avalon_jtag_lekhoba

0x60088 ~ 0x6008f

E sa khoneheng

2.3.1.3. Mehopolo e Kopanetsoeng ka thata
Mehopolo e kopantsoeng ka thata (TCMs) e kengoa ts'ebetsong ho sebelisoa mohopolo oa on-chip kaha latency ea bona e tlase e ba etsa hore ba lokele mosebetsi. Li-TCM ke mehopolo e kentsoeng sebakeng se tloaelehileng sa aterese empa e na le sebopeho se inehetseng ho microprocessor mme e na le ts'ebetso e phahameng, e tlase ea latency ea memori ea cache. TCM e boetse e fana ka sebopeho se ka tlase bakeng sa moamoheli oa kantle. Moqapi le moamoheli oa kantle o na le boemo bo tšoanang ba tumello ea ho sebetsana le TCM.

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Hlokomela:

Ha boema-kepe bo tlase ba TCM bo hokahantsoe le moamoheli oa kantle, bo ka hlahisoa ka aterese e fapaneng ho feta aterese ea mantlha e fanoeng ho processor core. Altera e khothaletsa ho hokahanya liaterese ka bobeli ho boleng bo lekanang.

2.3.1.4. Sebopeho sa Memori sa Kantle (EMIF)
EMIF (External Memory Interface) e sebetsa ka ho tšoana le SRAM (Static Random Access Memory), empa e matla ebile e hloka ho khatholla nako le nako ho boloka litaba tsa eona. Lisele tsa memori tse matla ho EMIF li nyane haholo ho feta lisele tsa memori tse sa fetoheng ho SRAM, tse hlahisang bokhoni bo phahameng le lisebelisoa tsa memori tse theko e tlase.
Ntle le tlhoko ea ho nchafatsa, EMIF e na le litlhoko tse ikhethileng tsa sehokelo tseo hangata li hlokang lisebelisoa tsa taolo e khethehileng. Ho fapana le SRAM, e nang le sete e tsitsitseng ea mela ea aterese, EMIF e hlophisa sebaka sa eona sa mohopolo ka libanka, mela le likholomo. Ho feto-fetoha lipakeng tsa libanka le mela ho hlahisa taba e itseng, ka hona, o tlameha ho odara phihlello ea memori ka hloko ho sebelisa EMIF hantle. EMIF e boetse e atisa liaterese tsa mela le kholomo holim'a mela e tšoanang ea liaterese, e fokotsa palo ea liphini tse hlokahalang bakeng sa boholo bo fanoeng ba EMIF.
Liphetolelo tse phahameng ka ho fetisisa tsa EMIF, tse kang DDR, DDR2, DDR3, DDR4, le DDR5, li beha litlhoko tse tiileng tsa botšepehi tseo baetsi ba PCB ba lokelang ho li nahana.
Lisebelisoa tsa EMIF li har'a mefuta ea RAM e theko e tlaase le e phahameng haholo e fumanehang, e leng se etsang hore e be khetho e tsebahalang. Karolo ea bohlokoa ea sebopeho sa EMIF ke EMIF IP, e laolang mesebetsi e amanang le ho sebetsana le ho pheta-pheta, ho khatholla le ho fetola pakeng tsa mela le libanka. Moralo ona o lumella sistimi eohle ho fihlella EMIF ntle le ho hloka ho utloisisa meralo ea eona ea kahare.

Lintlha tse amanang le Setsi sa Ts'ehetso sa Memori ea Kantle ea IP

2.3.1.4.1. Aterese ea Span Extender IP
Aterese ea Span Extender Altera FPGA IP e lumella li-interface tsa moamoheli tse kentsoeng mohopolong hore li fihle ho 'mapa o moholo kapa o monyane oa aterese ho feta bophara ba matšoao a aterese ea bona. Aterese ea Span Extender IP e arola sebaka seo ho ka rarolloang ho sona hore e be tse ngata tse arohaneng lifensetere e le hore moamoheli a ka fihlella karolo e nepahetseng ea memori ka fensetere.
Aterese ea Span Extender ha e behe moeli oa moamoheli le bophara ba moemeli ho tlhophiso ea 32-bit le 64bit. U ka sebelisa Aterese ea Span Extender ka 1-64-bit aterese ea lifensetere.

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Setšoantšo sa 13. Aterese Span Extender Altera FPGA IP
Aterese ea Lentsoe la Moemeli

Aterese ea Span Extender

Lethathamo la 'Mapa
Control Port A

…

Ngoliso ea Taolo 0 Ngoliso ea Taolo ea Z-1

Aterese e Atolositsoeng ea Moamoheli H

Lintlha Tse Amanang
Tataiso ea Mosebelisi ea Quartus® Prime Pro Edition: Moqapi oa Platform Sheba sehlooho Aterese Span Extender Intel® FPGA IP bakeng sa tlhaiso-leseling e batsi.

2.3.1.4.2. Ho sebelisa Aterese ea Span Extender IP e nang le Nios V processor
Mochine oa 32-bit Nios V o ka sebetsana le 4 GB ea sebaka sa aterese. Haeba EMIF e na le memori e fetang 4GB, e feta boholo ba aterese e tšehelitsoeng, e leng se etsang hore sistimi ea Moqapi oa Platform e fosahetse. Aterese ea Span Extender IP ea hlokahala ho rarolla bothata bona ka ho arola sebaka se le seng sa aterese ea EMIF ka lifensetere tse nyane tse ngata.
Altera e khothaletsa hore u nahane ka liparamente tse latelang.

Letlapa la 21. Aterese Span Extender Parameters

Paramethara

Lisebelisoa tse khothalletsoang

Bophara ba Datapath
Bophara bo Atolositsoeng ba Aterese ea Master Byte

Khetha li-32-bits, tse amanang le processor ea 32-bit. E ipapisitse le boholo ba memori ea EMIF.

Aterese ea Lentsoe la Lekhoba Bophara Bophahamo ba Burstcount Width

Khetha 2 GB kapa ka tlase ho moo. Nako e setseng ea aterese ea processor ea Nios V e boloketsoe li-IP tse ling tse kentsoeng.
Qala ka 1 'me butle-butle eketsa boleng bona ho ntlafatsa tshebetso.

Palo ea lifensetere tse nyane

Khetha fensetere e 1 e nyane haeba o hokela EMIF ho processor ea Nios V joalo ka taeo le memori ea data, kapa ka bobeli. Ho fetoha lipakeng tsa lifensetere tse nyane tse ngata ha processor ea Nios V e ntse e tsoa ho EMIF ho kotsi.

Numella Boema-kepe ba Taolo ea Makhoba

Tlosa boema-kepe ba taolo ea makhoba haeba u hokela EMIF ho processor ea Nios V joalo ka taeo le/kapa memori ea data. Matšoenyeho a tšoanang le Palo ea lifensetere tse nyane.

Boholo bo Emetseng ho Bala

Qala ka 1 'me butle-butle eketsa boleng bona ho ntlafatsa tshebetso.

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Setšoantšo sa 14. Ho kopanya Taelo le Mookameli oa Boitsebiso ho Aterese Span Extender

Setšoantšo sa 15. 'Mapa oa Aterese

Hlokomela hore Aterese ea Span Extender e ka fihlella sebaka sohle sa memori sa 8GB sa EMIF. Leha ho le joalo, ka Aterese ea Span Extender, processor ea Nios V e ka fihlella feela sebaka sa memori sa 1GB sa EMIF.

Setšoantšo sa 16. Setšoantšo se Nolofalitsoeng sa Block

Sistimi ea Moqapi oa Sethala

E setseng 3 GB

Aterese ea processor ea Nios V

span ke bakeng sa embedded

NNioios sVV Prorocesosor r
M

li-IP tse bonolo tsamaisong e tšoanang.
1 GB fensetere

Aterese Span

Extender

Ke 1 GB ea pele feela

memori ea EMIF e hokahane le Nios V

EMIF

processor.

8 GB
S

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2.3.1.4.3. Ho Hlalosa Aterese ea Span Extender Linker Memory Device 1. Hlalosa Aterese ea Span Extender (EMIF) joalo ka vector e seta bocha. Ntle le moo, o ka abela vector ea processor ea Nios V mehopolong e meng, joalo ka OCRAM kapa lisebelisoa tsa flash.
Setšoantšo sa 17. Likhetho tse ngata e le Reset Vector
Leha ho le joalo, Board Support Package (BSP) Editor e ke ke ea ngolisa aterese ea Span Extender (EMIF) ka bo eona e le mohopolo o nepahetseng. Ho itšetlehile ka khetho eo ue entseng, u bona maemo a mabeli a fapaneng joalokaha a bontšitsoe litšoantšong tse latelang. Setšoantšo sa 18. Phoso ea BSP ha U Hlalosa Aterese Span Extender (EMIF) e le Reset Vector.

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Setšoantšo sa 19. EMIF e sieo ha e Hlalosa Mehopolo e meng joalo ka Vector ea Seta Bocha

2. U tlameha ho kenya Aterese ea Span Extender (EMIF) ka bowena u sebelisa Add Memory Device, Add Linker Memory Region, le ho Eketsa Limmapa tsa Karolo ea Linker ho tab ea BSP Linker Script.
3. Latela mehato ena:
a. Etsa qeto ea bolelele ba aterese ea Aterese ea Span Extender u sebelisa 'Mapa oa Memori (The example setšoantšong se latelang se sebelisa aterese ea Span Extender ho tloha 0x0 ho isa 0x3fff_ffff).
Setšoantšo sa 20. 'Mapa oa Memori

b. Tobetsa Eketsa Sesebediswa sa Memori, mme o tlatse ho ya ka tlhahisoleseding e ho Memory Map ya moetso wa hao: i. Lebitso la Sesebelisoa: emif_ddr4. Tlhokomeliso: Netefatsa hore u kopitsa lebitso le tšoanang ho Memory Map. ii. Aterese ea Motheo: 0x0 iii. Boholo: 0x40000000
c. Tobetsa Eketsa ho kenya sebaka se secha sa memori ea sehokelo:

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Letlapa la 22. Ho eketsa Sebaka sa Memory Linker

Mehato

Seta Vector bocha

emif_ddr4

Mehopolo e meng

Kenya sebaka se secha sa Memory Linker se bitsoang reset. Kenya sebaka se secha sa Memory Linker bakeng sa

· Lebitso la Sebaka: reta bocha

emif_ddr4.

· Boholo ba Sebaka: 0x20

· Lebitso la Sebaka: emif_ddr4

· Sesebelisoa sa Memori: emif_ddr4

· Boholo ba Sebaka: 0x40000000

· Memori Offset: 0x0

· Sesebelisoa sa Memori: emif_ddr4

· Memori Offset: 0x0

Kenya sebaka se secha sa Memory Linker bakeng sa

emif_ddr4 e setseng.

· Lebitso la Sebaka: emif_ddr4

· Boholo ba Sebaka: 0x3fffffe0

· Sesebelisoa sa Memori: emif_ddr4

· Memori Offset: 0x20

Setšoantšo sa 21. Sebaka sa Khokahano ha U Hlalosa Aterese Span Extender (EMIF) joalo ka Vector ea Reset

Setšoantšo sa 22. Sebaka sa Khokahano ha se Hlalosa Mehopolo e meng e le Reset Vector
d. Hang ha emif_ddr4 e kentsoe ho BSP, u ka e khetha bakeng sa Karolo efe kapa efe ea Linker.
Setšoantšo sa 23. Aterese e Ekelitsoeng Span Extender (EMIF) Ka Katleho

e. Hlokomoloha temoso mabapi le sesebelisoa sa Memory emif_ddr4 ha e bonahale moetsong oa SOPC.
f. Tsoela pele ho Hlahisa BSP.
Tlhahisoleseding e Amanang le Kenyelletso ea Mekhoa ea ho qalisa processor ea Nios V leqepheng la 51

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2.3.2. Mehopolo e sa Feleng
Memori e sa fetoheng e boloka likahare tsa eona ha motlakase o tima, e leng se etsang hore e be khetho e ntle ea ho boloka tlhahisoleseling eo sistimi e tlamehang ho e fumana kamora potoloho ea matla a sistimi. Memori e sa fetoheng hangata e boloka processor boot-code, li-setting tse phehellang tsa ts'ebeliso, le data ea tlhophiso ea Altera FPGA. Le hoja mohopolo o sa fetoheng o na le advantage ea ho boloka data ea eona ha o tlosa matla, e lieha haholo ha e bapisoa le mohopolo o tsitsitseng, 'me hangata e na le mekhoa e rarahaneng ea ho ngola le ho hlakola. Mehopolo e sa fetoheng le eona hangata e tiisetsoa feela hore e ka hlakoloa ka makhetlo a mangata, ka mor'a moo e ka hloleha.
ExampMemori e sa fetoheng e kenyelletsa mefuta eohle ea flash, EPROM, le EEPROM. Altera e khothaletsa hore u boloke li-bitstreams tsa Altera FPGA le litšoantšo tsa lenaneo la Nios V mohopolong o sa fetoheng, 'me u sebelise serial flash e le sesebelisoa sa boot bakeng sa li-processor tsa Nios V.
Lintlha Tse Amanang
· Generic Serial Flash Interface Altera FPGA IP User Guide
· Lebokose la mangolo la Client Altera FPGA IP User Guide · MAX® 10 User Flash Memory Guide: On-Chip Flash Altera FPGA IP Core
2.4. Lioache le ho Seta Bocha Mekhoa e Molemohali
Ho bohlokoa ho utloisisa hore na oache ea processor ea Nios V le domain reset e sebelisana joang le karolo e 'ngoe le e 'ngoe eo e hokahaneng le eona. Sistimi e bonolo ea Nios V processor e qala ka domain name ea oache e le 'ngoe,' me e ka rarahana le sistimi ea lioache tse ngata ha sebaka sa oache se potlakileng se thulana le sebaka se liehang sa oache. U hloka ho ela hloko le ho utloisisa hore na libaka tsena tse fapaneng li tatellana joang le ho etsa bonnete ba hore ha ho na mathata a poteletseng.
Bakeng sa mekhoa e metle, Altera e khothaletsa ho beha processor ea Nios V le memori ea boot sebakeng se le seng sa oache. Se ke oa lokolla processor ea Nios V hore e se ke ea hlophisoa bocha sebakeng sa nako e potlakileng ha e tloha mohopolong o lulang sebakeng se liehang haholo, se ka bakang phoso ea ho lata litaelo. U ka 'na ua hloka tatellano ea matsoho ho feta seo Moqapi oa Platform a fanang ka sona ka ho sa feleng, 'me u rale topollo ea tokollo bocha ho latela ts'ebeliso ea hau. Haeba u batla ho tsosolosa tsamaiso ea hau ka mor'a hore e hlahe 'me e sebetsa ka nakoana, sebelisa lintlha tse tšoanang ho tatellano ea ho tsosolosa tsamaiso le tlhokahalo ea ho qala ka poso.
2.4.1. Sistimi ea JTAG Tshupanako
Ho hlakisa lithibelo tsa oache ho sistimi e 'ngoe le e' ngoe ea processor ea Nios V ke mohopolo oa bohlokoa oa moralo oa sistimi mme oa hlokahala bakeng sa ho nepahala le boits'oaro bo ikemiselitseng. Quartus Prime Timing Analyzer e etsa tlhahlobo ea nako e tsitsitseng ho netefatsa ts'ebetso ea nako ea mabaka ohle moralong oa hau o sebelisa tšitiso ea maemo a indasteri, tlhahlobo le mokhoa oa ho tlaleha.
Example 1. Oache ea Motheo ea 100 MHz e nang le 50/50 Duty Cycle le 16 MHz JTAG Tshupanako
#************************************************************ # Theha 100MHz Clock #************************************************************************************** etsa_leina -name {clk} -period 10 [get_ports {clk}] #************************ Theha 16MHz JTAG Oache #****************************

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create_clock -name {altera_reserved_tck} -period 62.500 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] Information Related Quartus Prime Time Analyzer Cookbook
2.4.2. Seta Sebopeho sa Kopo bocha
Nios V processor e kenyelletsa sesebelisoa sa boikhethelo sa ho seta bocha. Setsi sa kopo ea ho seta bocha se na le matšoao a reset_req le reset_req_ack.
Ho nolofalletsa kopo ea ho tsosolosa ho Moqapi oa Platform: 1. Qala Nios V processor IP Parameter Editor. 2. Ho Setting ea Use Reset Request, bulela Add Reset Request Interface
kgetho.
Setšoantšo sa 24. Etsa hore Nios V Reset Kopo ea ho tsosolosa
Letšoao la reset_req le sebetsa joalo ka tšitiso. Ha o re reset_req, o kopa ho khutlela mantlha. Koko e emetse hore teraka efe kapa efe e setseng ea libese e phethe mosebetsi oa eona. Bakeng sa mohlalaample, haeba ho na le ts'ebetso ea phihlello ea memori e emetseng, mantlha e emetse karabo e felletseng. Ka mokhoa o ts'oanang, mantlha e amohela karabo efe kapa efe e ntseng e emetse ea litaelo empa ha e fane ka kopo ea litaelo kamora ho amohela lets'oao la reset_req.
Ts'ebetso ea ho seta bocha e na le phallo e latelang: 1. Qetella lits'ebetso tsohle tse emetseng 2. Hlakola phaephe e kahare 3. Beha Sebali sa Lenaneo ho vector ea reset 4. Seta konokono Ts'ebetso eohle ea ho seta botjha e nka lipotoloho tse 'maloa tsa oache. Reset_req e tlameha ho lula e le joalo ho fihlela reset_req_ack e bonts'a hore ts'ebetso ea mantlha e phethetsoe ka katleho. Ho hloleha ho etsa joalo ho fella ka hore core's state e se be deterministic.

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2.4.2.1. Maemo a Tloaelehileng a Tšebeliso
· U ka tiisa lets'oao la reset_req ho tloha ho matla ho thibela processor ea Nios V ho qala ts'ebetso ea lenaneo ho tsoa ho vector ea eona ea reset ho fihlela mabotho a mang a FPGA a sistimi a qala memori ea processor ea Nios V. Tabeng ena, tsamaiso eohle ea tsamaiso e ka ba le ts'ebetso e hloekileng ea hardware reset. Motlakase oa Nios V o tšoaretsoe ka nako e sa lekanyetsoang sebakeng sa kopo ea ho seta bocha ho fihlela mabotho a mang a FPGA a qala memori ea processor boot.
· Ka mokhoa oo u tlamehang ho tsosolosa motsoako oa motlakase oa Nios V ntle le ho senya tsamaiso eohle, u ka tiisa hore reset_req lets'oao ho emisa ka mokhoa o hloekileng ts'ebetso ea morao-rao ea mantlha le ho qala processor ho tloha ho reset vector hang ha sistimi e lokolla letšoao la reset_req_ack.
· Motho ea amohelang kantle a ka sebelisa sebopeho sa kopo ea reset ho nolofatsa ts'ebetsong ea mesebetsi e latelang:
- Emisa lenaneo la hona joale la processor ea Nios V.
- Kenya lenaneo le lecha mohopolong oa boot processor oa Nios V.
- Lumella processor ho qala ho etsa lenaneo le lecha.
Altera eu khothalletsa hore u sebelise mokhoa oa ho qeta nako ho lekola boemo ba reset_req_ack signal. Haeba processor ea Nios V ea mantlha e oela maemong a sa feleng a ho leta le li-stall ka lebaka le sa tsejoeng, reset_req_ack e ke ke ea tiisa ka ho sa feleng. Mokhoa oa ho qeta nako o u thusa ho:
· Hlalosa nako ea nako ea ho hlaphoheloa 'me u etse tsosoloso ea tsamaiso ka ho tsosolosa boemo ba tsamaiso.
· Ho lokisa boemo ba hardware.
2.4.3. Seta hape IP ea Phatlalatso
Lisebelisoa tse thehiloeng ho Altera SDM li sebelisa meralo e ts'oanang, e thehiloeng lekaleng e abang mohopolo oa mantlha oa masela makaleng a mangata. Altera e khothaletsa hore u sebelise Reset Release Altera FPGA IP e le e 'ngoe ea lintho tse kenyellelitsoeng ho potoloha potoloho. Lisebelisoa tse thehiloeng ho Intel® SDM li kenyelletsa Stratix® 10, le lisebelisoa tsa AgilexTM. Lisebelisoa tse thehiloeng ho li-block-block ha li amehe ke tlhoko ena.
Lintlha Tse Amanang
AN 891: Ho Sebelisa Phatlalatso ea Reset Altera FPGA IP
2.5. Ho Abela Moemeli ea Ikemetseng
Moqapi oa Platform o u lumella ho hlakisa moemeli oa kamehla ea sebetsang e le moemeli oa karabelo ea liphoso. Moemeli oa kamehla eo u mo khethileng o fana ka litšebeletso tsa karabo ea liphoso bakeng sa baamoheli ba lekang ho kena ka mokhoa o sa hlakoloeng 'mapeng oa aterese.
Maemo a latelang a qala ketsahalo e sa hlakoloeng:
· Ts'ireletso ea boemo ba ts'ireletso ea libese
· Phihlello ea transaction sebakeng sa memori se sa hlalosoang
· Ketsahalo ea mokhelo joalo-joalo.

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Moemeli oa kamehla o lokela ho abeloa ho sebetsana le liketsahalo tse joalo, moo transaction e sa hlalosoang e fetisetsoang ho moemeli oa kamehla ebe e arabela processor ea Nios V ka karabelo ea phoso.
Lintlha Tse Amanang
· Quartus Prime Pro Edition User Guide: Moqapi oa Platform. Ho Khetha Moemeli ea Ikemetseng
· Quartus Prime Pro Edition User Guide: Moqapi oa Platform. Phoso Karabo Lekhoba Altera FPGA IP
· Github - Likarolo tsa Tlatsetso tsa Reset bakeng sa Qsys

2.6. Ho Abela Moemeli oa UART bakeng sa Khatiso
Ho hatisa ho molemo bakeng sa ho lokisa lisebelisoa tsa software, hammoho le ho lekola boemo ba sistimi ea hau. Altera e khothaletsa ho hatisa tlhahisoleseling ea mantlha joalo ka molaetsa oa ho qala, molaetsa oa phoso, le tsoelo-pele ea ts'ebetso ea software.
Qoba ho sebedisa printf() library tshebetsong tlasa maemo a latelang: · printf() laeborari e etsa hore tshebediso e eme haeba ho se na moamohedi ya balang tlhahiso.
Sena se sebetsa ho JTAG UART feela. · The printf() laebrari e jang palo e kholo ea memori ya lenaneo.

2.6.1. Thibelo ea li-Stalls ka JTAG UART

Letlapa la 23. Phapano lipakeng tsa UART ea Setso le JTAG UART

Mofuta oa UART oa Setso sa UART

Tlhaloso
E fetisa lintlha tsa serial ho sa tsotelehe hore na moamoheli oa kantle o mametse. Haeba ho se na moamoheli ea balang data ea serial, data e lahlehile.

JTAG UART

E ngola lintlha tse fetisoang ho buffer ea tlhahiso 'me e itšetlehe ka moamoheli oa kantle ho bala ho tsoa ho buffer ho e tšolla.

Leano la JTAG Mokhanni oa UART o ema ha buffer e tletse. The JTAG Mokhanni oa UART o emela moamoheli oa kantle ho bala ho tsoa ho buffer pele a ngola data e fetisang. Ts'ebetso ena e thibela tahlehelo ea data ea ho fetisa.
Leha ho le joalo, ha ho sa hlokahale ho lokisa tsamaiso, joalo ka nakong ea tlhahiso, litsamaiso tse kentsoeng li romelloa ntle le PC e amohelang e hokahantsoeng le J.TAG UART. Haeba sistimi e khethile JTAG UART joalo ka moemeli oa UART, e ka baka ho emisa tsamaiso hobane ha ho moamoheli oa kantle ea hokahaneng.
Ho thibela ho tsilatsila ha JTAG UART, sebelisa likhetho tse latelang:

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Lethathamo la 24. Thibelo ka ho Stalling ka JTAG UART

Dikgetho
Ha ho sebopeho sa UART le mokhanni ea teng
Sebelisa sebopeho se seng sa UART le mokhanni
Sireletsa JTAG UART interface (ntle le mokhanni)

Nakong ea Nts'etsopele ea Hardware (ho Moqapi oa Platform)

Nakong ea Nts'etsopele ea Software (ho Board Support Package Editor)

Tlosa JTAG UART e tsoang ho sistimi

Hlophisa hal.stdin, hal.stdout le hal.stderr e le None.

Tlohela JTAG UART le tse ling tse bonolo Configure hal.stdin, hal.stdout le hal.stderr

UART IP

le tse ling tse bonolo tsa UART IP.

Sireletsa JTAG UART ka har'a sistimi

· Hlophisa hal.stdin, hal.stdout le hal.stderr e le Ha e Seng ho Boto Mohlophisi oa Liphutheloana.
· Tlosa JTAG UART mokhanni ho BSP Driver tab ya.

2.7. JTAG Lipontšo
Mojule oa Nios V processor debug o sebelisa sesebelisoa sa JTAG segokanyimmediamentsi sa sebolokigolo bakeng sa ho jarolla ELF software le debugging software. Ha o lokisa moralo oa hau ka JTAG interface, JTAG matšoao TCK, TMS, TDI, le TDO li kengoa tšebetsong e le karolo ea moralo. Ho hlalosa JTAG lithibelo tsa matšoao tsamaisong e 'ngoe le e 'ngoe ea processor ea Nios V ke mohopolo oa bohlokoa oa moralo oa sistimi mme oa hlokahala bakeng sa ho nepahala le boits'oaro bo ikemiselitseng.
Altera e khothaletsa hore maqhubu a lioache tsa moralo ofe kapa ofe a be bonyane makhetlo a mane ho feta JTAG maqhubu a oache ho netefatsa hore sesebelisoa sa on-chip (OCI) se sebetsa hantle.
Lintlha Tse Amanang le Ena · Quartus® Prime Timing Analyzer Cookbook: JTAG Lipontšo
Ho fumana lintlha tse ling ka JTAG litataiso tsa lithibelo tsa nako. KDB: Hobaneng ha niosv-download e hloleha ho sebelisa processor e sa kengoang ea Nios® V/m ho
JTAG maqhubu a 24MHz kapa 16Mhz?
2.8. Ho ntlafatsa Ts'ebetso ea Sisteme ea Moqapi oa Platform
Moqapi oa Platform o fana ka lisebelisoa tsa ho ntlafatsa ts'ebetso ea khokahano ea sistimi bakeng sa meralo ea Altera FPGA.

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Setšoantšo sa 25. Ho ntlafatsa Examples

Exampe bontšitsoeng setšoantšong e bontša mehato e latelang:
1. E eketsa Borokho ba Pipeline ho fokotsa litsela tsa bohlokoa ka ho e beha: a. Pakeng tsa Mookameli oa Litaelo le baemeli ba eona b. Pakeng tsa Data Manager le baemeli ba eona
2. Etsa kopo ea True Dual port On-Chip RAM, 'me kou ka 'ngoe e inehetse ho Motsamaisi oa Litaelo le Motsamaisi oa Lintlha ka ho latellana.

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Sheba lihokelo tse latelang tse amanang le tsona tse ka tlase, tse fanang ka mekhoa ea ho sebelisa lisebelisoa tse teng le mekhoa ea khoebo ea ts'ebetsong ka 'ngoe.
Lintlha Tse Amanang · Quartus® Prime Pro Edition User Guide: Platform Designer
Sheba sehlooho Ho Ntlafatsa Ts'ebetso ea Moqapi oa Platform bakeng sa tlhaiso-leseling e batsi. · Quartus® Prime Standard Edition User Guide: Moqapi oa Platform Sheba sehlooho Ho Ntlafatsa Ts'ebetso ea Moqapi oa Platform bakeng sa tlhaiso-leseling e batsi.

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3. Moralo oa Tsamaiso ea Ts'ebetso ea Nios V
Khaolo ena e hlalosa phallo ea ntlafatso ea software ea Nios V le lisebelisoa tsa software tseo u ka li sebelisang ho nts'etsapele sistimi ea hau e kentsoeng ea moralo. Litaba li sebetsa e le ho qetelaview pele o theha sistimi ea processor ea Nios V.
Setšoantšo sa 26. Phallo ea Moralo oa Software
Qala

Hlahisa BSP ho Moqapi oa Platform U Sebelisa BSP Editor

Hlahisa BSP U sebelisa Nios V Command Shell
Hlahisa Kopo CMake Build File Ho sebelisa Nios V Command Shell

Hlokomela:

Kenya BSP le Kopo CMake Build File
Haha Sesebelisoa sa processor sa Nios V u sebelisa sesebelisoa sa
RiscFree IDE bakeng sa Intel FPGA

Haha sesebelisoa sa Nios V processor u sebelisa leha e le efe
mohlophisi oa khoutu ea mohloli oa taelo, CMake, le Make
ditaelo
QETA

Altera e khothaletsa hore u sebelise lisebelisoa tsa ntlafatso tsa Altera FPGA kapa boto ea mohlala bakeng sa nts'etsopele ea software le ho lokisa liphoso. Lisebelisoa tse ngata le likarolo tsa boemo ba sistimi li fumaneha feela ha software ea hau e sebetsa botong ea 'nete.

© Altera Corporation. Altera, logo ea Altera, letšoao la `a', le matšoao a mang a Altera ke matšoao a Altera Corporation. Altera e na le tokelo ea ho etsa liphetoho ho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera ha e nke boikarabelo kapa boikarabelo bo hlahang ka lebaka la kopo kapa tšebeliso ea tlhahisoleseding leha e le efe, sehlahisoa, kapa tšebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Altera. Bareki ba Altera ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

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3.1. Phallo ea ntlafatso ea Software ea Nios V
3.1.1. Project Support Package Project
Morero oa Nios V Board Support Package (BSP) ke laebrari e ikhethileng e nang le khoutu e khethehileng ea tšehetso. BSP e fana ka tikoloho ea nako ea ho sebetsa ea software e etselitsoeng processor e le 'ngoe ho sistimi ea processor ea Nios V.
Software ea Quartus Prime e fana ka Nios V Board Support Package Editor le lisebelisoa tsa utility tsa niosv-bsp ho fetola litlhophiso tse laolang boitšoaro ba BSP.
BSP e na le lintlha tse latelang: · Hardware abstraction layer · Bakhanni ba lisebelisoa · Liphutheloana tsa boikhethelo tsa software · Mokhoa oa boikhethelo oa nako ea nnete.
3.1.2. Morero oa Kopo
Morero oa kopo oa Nios VC/C++ o na le likarolo tse latelang: · E na le pokello ea khoutu ea mohloli le CMakeLists.txt.
- The CMakeLists.txt e bokella khoutu ea mohloli ebe e e hokahanya le BSP le laeborari e le 'ngoe kapa ho feta, ho theha .elf e le 'ngoe file
· E 'ngoe ea mohloli files e na le mosebetsi oa mantlha (). · E kenyelletsa khoutu e bitsang mesebetsi lilaeboraring le li-BSP.
Altera e fana ka sesebelisoa sa utility sa niosv-app ho lisebelisoa tsa lisebelisoa tsa software tsa Quartus Prime ho theha Kopo ea CMakeLists.txt, le RiscFree IDE bakeng sa Altera FPGAs ho fetola khoutu ea mohloli tikolohong e thehiloeng ho Eclipse.
3.2. Altera FPGA Embedded Development Tools
Sesebelisoa sa Nios V se ts'ehetsa lisebelisoa tse latelang tsa nts'etsopele ea software: · Graphical User Interface (GUI) - Lisebelisoa tsa ntlafatso ea Graphical tse fumanehang ho
ka bobeli Windows* le Linux* Operating Systems (OS). - Nios V Board Support Package Editor (Nios V BSP Editor) - Ashling RiscFree IDE bakeng sa Altera FPGAs · Command-Line Tools (CLI) - Lisebelisoa tsa ntlafatso tse qalisoang ho tloha ho Nios V Command Shell. Sesebelisoa se seng le se seng se fana ka litokomane tsa sona ka mokhoa oa thuso e fumanehang ho tsoa molaong oa taelo. Bula Nios V Command Shell ebe u thaepa taelo e latelang: - thusa ho view menu ya Thuso. - Lisebelisoa tsa Nios V - File Lisebelisoa tsa ho Fetola Format - Lisebelisoa tse ling tsa lisebelisoa

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Letlapa la 25. GUI Tools le Taelo-line Tools Kakaretso ea Mesebetsi

Mosebetsi

Sesebelisoa sa GUI

Sesebelisoa sa mola oa taelo

Ho theha BSP

Mohlophisi oa Nios V BSP

· Ho software ea Quartus Prime Pro Edition: niosv-bsp -c -s=<.qsys file> -t= [OPTIONS] litlhophiso.bsp
· In Quartus Prime Standard Edition software: niosv-bsp -c -s=<.sopcinfo file> -t= [OPTIONS] litlhophiso.bsp

Ho hlahisa BSP ho sebelisa .bsp e teng file
Ho nchafatsa BSP

Nios V BSP Editor Nios V BSP Editor

litlhophiso tsa niosv-bsp -g [OPTIONS].bsp niosv-bsp -u [OPTIONS] litlhophiso.bsp

Ho hlahloba BSP

Mohlophisi oa Nios V BSP

niosv-bsp -q -E= [OPTIONS] litlhophiso.bsp

Ho etsa kopo

–

niosv-app -a= -b= -s= files directory> [MEKHETHO]

Ho theha laeborari ea basebelisi

–

niosv-app -l= -s= files directory> -p= [DIKGETHO]

Ho fetola sesebelisoa Ho fetola laebrari ea mosebelisi Ho aha sesebelisoa

RiscFree IDE bakeng sa Altera FPGAs
RiscFree IDE bakeng sa Altera FPGAs
RiscFree IDE bakeng sa Altera FPGAs

Mohlophisi ofe kapa ofe oa mola oa taelo
Mohlophisi ofe kapa ofe oa mola oa taelo
· etsa · cmake

Ho aha laeborari ea basebelisi

RiscFree IDE bakeng sa Altera FPGAs

· etsa · cmake

Ho khoasolla sesebelisoa sa ELF
Ho fetolela .elf file

RiscFree IDE bakeng sa Altera FPGAs
–

niosv-download
· elf2flash · elf2hex

Lintlha Tse Amanang
Ashling RiscFree Tikoloho e Kopantsoeng ea Ntlafatso (IDE) bakeng sa Tataiso ea Basebelisi ea Altera FPGAs

3.2.1. Nios V processor Board Support Package Editor
U ka sebelisa processor ea Nios V BSP Editor ho etsa mesebetsi e latelang: · Theha kapa u fetole projeke ea BSP ea processor ea Nios V · Fetola litlhophiso, libaka tsa lihokela, le limmapa tsa likarolo · Khetha liphutheloana tsa software le likhanni tsa lisebelisoa.
Bokhoni ba BSP Editor bo kenyelletsa bokhoni ba lisebelisoa tsa niosv-bsp. Morero ofe kapa ofe o entsoeng ho BSP Editor le ona o ka etsoa ho sebelisoa lisebelisoa tsa mohala oa taelo.

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Hlokomela:

Bakeng sa software ea Quartus Prime Standard Edition, sheba AN 980: Nios V Processor Quartus Prime Software Support bakeng sa mehato ea ho kopa BSP Editor GUI.

Ho thakhola BSP Editor, latela mehato ena: 1. Bula Platform Designer, 'me u tsamaee ho ea ho File menu.
a. Ho bula maemo a teng a BSP file, tobetsa Bula… b. Ho theha BSP e ncha, tobetsa BSP e Ncha… 2. Kgetha tab ya BSP Editor mme o fane ka dintlha tse nepahetseng.

Setšoantšo sa 27. Qala BSP Editor

Lintlha tse amanang le AN 980: Nios V Processor Quartus Prime Software Support
3.2.2. RiscFree IDE bakeng sa Altera FPGAs
RiscFree IDE bakeng sa Altera FPGAs ke IDE e thehiloeng ho Eclipse bakeng sa processor ea Nios V. Altera e khothaletsa hore o hlahise software ea processor ea Nios V ho IDE ena ka mabaka a latelang: · Likarolo li ntlafalitsoe le ho netefatsoa hore li tsamaisana le Nios V.
ho phalla ha processor. · E na le lisebelisoa tsohle tse hlokahalang le lisebelisoa tse u thusang tse u thusang
ho qala nts'etsopele ea processor ea Nios V habonolo.
Tlhahisoleseding e Amanang le Ashling RiscFree Integrated Development Environment (IDE) bakeng sa Altera FPGAs User Guide
3.2.3. Lisebelisoa tsa Nios V Utilities
O ka theha, oa fetola, 'me oa haha li-program tsa Nios V ka litaelo tse tlatsitsoeng moleng oa taelo kapa tse kentsoeng ka har'a script. Lisebelisoa tsa line-taelo tsa Nios V tse hlalositsoeng karolong ena li ho /niosv/bin directory.

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Letlapa la 26. Lisebelisoa tsa Nios V Utilities

Lisebelisoa tsa Mola oa Taelo

Kakaretso

niosv-app niosv-bsp niosv-khoarolla niosv-shell niosv-stack-report

Ho hlahisa le ho lokisa morero oa kopo.
Ho theha kapa ho nchafatsa li-setting tsa BSP file le ho theha BSP files. Ho jarolla ELF file ho processor ea Nios® V.
Ho bula Nios V Command Shell. Ho o tsebisa ka sebaka sa memori se setseng se fumanehang ts'ebelisong ea hau .elf bakeng sa tšebeliso ea stack kapa qubu.

3.2.4. File Lisebelisoa tsa ho Fetola Sebopeho

File ho fetola sebopeho ka linako tse ling hoa hlokahala ha o fetisa data ho tloha ho sesebelisoa se seng ho ea ho se seng. The file lisebelisoa tsa ho fetola sebopeho li ho
sesebelisoa sa ho kenya software>/niosv/bin directory.

Lethathamo la 27. File Lisebelisoa tsa ho Fetola Sebopeho

Lisebelisoa tsa Mola oa Taelo elf2flash elf2hex

Summary Ho fetolela .elf file to .srec format bakeng sa ho etsa flash memory programming. Ho fetolela .elf file ho .hex sebopeho bakeng sa ho qala memori.

3.2.5. Lisebelisoa tse ling tsa lisebelisoa

U kanna ua hloka lisebelisoa tse latelang tsa line-taelo ha u theha sistimi e thehiloeng ho Nios V. Lisebelisoa tsena tsa line-taelo li fanoe ke Intel in /quartus/bin kapa e fumanweng ho tswa ho
lisebelisoa tse bulehileng.

Lethathamo la 28. Lisebelisoa tse ling tsa Taelo-Mola

Lisebelisoa tsa Mola oa Taelo

Mofuta

Kakaretso

juart-terminal

Intel e fanoeng

Ho beha leihlo stdout le stderr, le ho fana ka tlhahiso ho processor ea Nios® V
subsystem ka stdin. Sesebelisoa sena se sebetsa feela ho JTAG UART IP ha e hokahantsoe le processor ea Nios® V.

openocd

Intel e fanoe ho kenya OpenOCD.

openocd-cfg-gen

Intel e fanoeng · Ho hlahisa tlhophiso ea OpenOCD file. · Ho hlahisa JTAG index ea sesebelisoa sa ketane.

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4. Nios V processor Configuration le Booting Solutions
O ka hlophisa processor ea Nios V ho qalisa le ho kenya software ho tsoa libakeng tse fapaneng tsa memori. Memori ea boot ke Quad Serial Peripheral Interface (QSPI) flash, On-Chip Memory (OCRAM), kapa Tightly Coupled Memory (TCM).
Lintlha Tse Amanang · Maemo a ho Hlahisa Matla a Matla leqepheng la 193 · Litšusumetso tsa Matla a Matla
Bakeng sa tlhaiso-leseling e batsi mabapi le li-triggers tsa motlakase.
4.1. Selelekela
Mochine oa Nios V o tšehetsa mefuta e 'meli ea mekhoa ea ho qalisa boot: · Phetha-in-Place (XIP) ka ho sebelisa alt_load() tshebetso · Lenaneo le kopitsoe ho RAM ho sebelisoa boot copier. Nts'etsopele ea mananeo a kentsoeng a Nios V a ipapisitse le "hardware abstraction layer" (HAL). HAL e fana ka lenaneo le lenyenyane la bootloader (eo hape e tsejoang e le boot copier) e kopitsang likarolo tse amanang le lihokelo ho tloha mohopolong oa boot ho ea sebakeng sa bona sa nako ea ho matha ka nako ea boot. O ka hlakisa libaka tsa nako ea ho tsamaisa memori ea data ka ho sebelisa litlhophiso tsa Mohlophisi oa Boto ea Tšehetso ea Boto (BSP). Karolo ena e hlalosa: · Nios V processor boot copier e tsamaisang sistimi ea hau ea Nios V ho latela
khetho ea memori ea boot · Likhetho tsa processor tsa Nios V le phallo e akaretsang · Litharollo tsa mananeo a Nios V bakeng sa memori e khethiloeng ea boot
4.2. Ho kopanya Lisebelisoa
Ha o hlahisa projeke ea processor ea Nios V, BSP Editor e hlahisa lihokelo tse peli tse amanang files: · linker.x: Taelo ya kgokahanyo file seo sesebelisoa se hlahisitsoeng se se entsengfile tshebediso
ho bopa .elf binary file. · linker.h: E na le tlhahisoleseding mabapi le sebopeho sa memori sa sehokelo. Liphetoho tsohle tsa li-linker setting tseo u li etsang morerong oa BSP li ama litaba tsa lihokelo tsena tse peli files. Sesebelisoa se seng le se seng sa processor sa Nios V se na le likarolo tse latelang tsa lihokela:
© Altera Corporation. Altera, logo ea Altera, letšoao la `a', le matšoao a mang a Altera ke matšoao a Altera Corporation. Altera e na le tokelo ea ho etsa liphetoho ho lihlahisoa le litšebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Altera ha e nke boikarabelo kapa boikarabelo bo hlahang ka lebaka la kopo kapa tšebeliso ea tlhahisoleseding leha e le efe, sehlahisoa, kapa tšebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Altera. Bareki ba Altera ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

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Lethathamo la 29. Likarolo tsa Khokahanyo

.mongolo

Likarolo tsa Linker

.rodata

.rwdata

.bss

.qubu

.stack

Litlhaloso Khoutu e phethisoang. Lintlha tse ling tsa ho bala feela tse sebelisitsoeng ts'ebetsong ea lenaneo. Mabenkele a ho bala-ho ngola lintlha tse sebelisitsoeng ts'ebetsong ea lenaneo. E na le data e sa fetoheng. E na le memori e abetsweng ka matla. E boloka liparamente tsa mehala le lintlha tse ling tsa nakoana.

U ka eketsa likarolo tse ling tsa linker ho .elf file ho boloka khoutu le data tse ikhethileng. Likarolo tsena tsa lihokela li behiloe libakeng tsa memori tse nang le mabitso, tse hlalosoang hore li tsamaisana le lisebelisoa tsa mohopolo le liaterese. Ka ho sa feleng, BSP Editor e iketsetsa likarolo tsena tsa lihokela. Leha ho le joalo, o ka laola likarolo tsa linker bakeng sa ts'ebeliso e itseng.

4.2.1. Ho Kopanya Boitshwaro
Karolo ena e hlalosa boits'oaro ba khokahano ea kamehla ea BSP Editor le mokhoa oa ho laola boitšoaro ba khokahano.

4.2.1.1. Khokahano ea kamehla ea BSP
Nakong ea tlhophiso ea BSP, lisebelisoa li etsa mehato e latelang ka bo eona:
1. Abela mabitso a libaka tsa memori: Fana ka lebitso ho sesebelisoa se seng le se seng sa memori ea sistimi ebe u eketsa lebitso ka leng ho sehokelo file joalo ka sebaka sa memori.
2. Fumana mohopolo o moholo ka ho fetisisa: Hlalosa sebaka se seholo sa mohopolo oa ho bala le ho ngola sehokelong file.
3. Abela likarolo tsa li-linker: Beha likarolo tsa li-linker tsa kamehla (.text, .rodata, .rwdata, .bss, .heap, le .stack) sebakeng sa memori se khethiloeng mohatong o fetileng.
4. Ngola files: Ngola linker.x le linker.h files.
Ka tloaelo, leano la kabo ea karolo ea li-linker le sebetsa nakong ea ts'ebetso ea nts'etsopele ea software hobane kopo e netefalitsoe hore e tla sebetsa haeba memori e le kholo ka ho lekana.
Melao bakeng sa boitšoaro ba ho hokahana ka mehla e fumaneha ho Altera-generated Tcl scripts bsp-set-defaults.tcl le bsp-linker-utils.tcl e fumanoang ho /niosv/scripts/bsp-defaults directory. Taelo ea niosv-bsp e kopa mangolo ana. Se ke oa fetola mangolo ana ka kotloloho.

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4.2.1.2. Khokahano ea BSP e hlophisitsoeng
U ka khona ho laola mekhoa ea ho hokahanya ea kamehla ho tab ea Linker Script ea BSP Editor. Sebelisa mongolo oa linker ka mekhoa e latelang: · Eketsa sebaka sa memori: Mebapa ea lebitso la sebaka sa memori ho sesebelisoa sa memori sa 'mele. · Eketsa 'mapa oa karolo: E tsamaisa lebitso la karolo sebakeng sa memori. Setšoantšo sa BSP
Editor lumella u ho view 'mapa oa memori pele le ka mora ho etsa liphetoho.

4.3. Mekhoa ea ho qalisa processor ea Nios V

Ho na le mekhoa e 'maloa ea ho bulela processor ea Nios V lisebelisoa tsa Altera FPGA. Mekhoa ea ho qalisa processor ea Nios V e fapana ho latela khetho ea memori ea flash le malapa a lisebelisoa.

Letlapa la 30. Memori ea Flash e ts'ehelitsoeng e nang le likhetho tse fapaneng tsa Boot

Memori ea Boot e tšehelitsoeng

Sesebelisoa

On-Chip Flash (bakeng sa tlhophiso ea ka hare)

Lisebelisoa tse 10 feela (tse nang le On-Chip Flash IP)

Morero o Akaretsang QSPI Flash (bakeng sa data ea mosebelisi feela)

Lisebelisoa tsohle tsa FPGA tse tšehetsoeng (tse nang le Generic Serial Flash Interface FPGA IP)

Tlhophiso ea QSPI Flash (bakeng sa tlhophiso ea Active Serial)

Taolo e thehiloeng ho thibela
lisebelisoa (tse nang le Generic
Serial Flash Interface Intel FPGA IP)(2)

Mekhoa ea ho qalisa processor ea Nios V

Kopo Runtime Location

Boot Copier

Sesebelisoa sa processor sa Nios V se tsoa sebakeng sa On-Chip Flash

On-Chip Flash (XIP) + OCRAM/ RAM e kantle (bakeng sa likarolo tsa data tse ngoloang)

alt_load () mosebetsi

Sesebelisoa sa processor sa Nios V se kopitsoe ho tloha ho On-Chip ho ea ho RAM ho sebelisoa mochini oa ho qopitsa

OCRAM / RAM ea kantle

Ho sebelisa Bootloader hape ka GSFI

Sesebelisoa sa processor sa Nios V se etsa sebaka ho tsoa ho sepheo se akaretsang sa QSPI flash

Sepheo se akaretsang sa QSPI flash (XIP) + OCRAM/ RAM ea kantle (bakeng sa likarolo tsa data tse ngoloang)

alt_load () mosebetsi

Sesebelisoa sa processor sa Nios V se kopitsoe ho tloha ho sepheo se akaretsang sa QSPI flash ho ea ho RAM ho sebelisa mochini oa boot

OCRAM / RAM ea kantle

Bootloader ka GSFI

Sesebelisoa sa processor sa Nios V e etsa sebaka ho tsoa ho tlhophiso ea QSPI flash

Tlhophiso ea QSPI flash (XIP) + OCRAM/ RAM ea kantle (bakeng sa likarolo tsa data tse ngoloang)

alt_load () mosebetsi

Sesebelisoa sa processor sa Nios V se kopitsoe ho tloha ho tlhophiso ea QSPI flash ho ea ho RAM ho sebelisoa boot copier

OCRAM/ Bootloader ea RAM ea kantle ka GSFI e tsoela pele…

(2) Sheba AN 980: Nios V Processor Quartus Prime Software Support bakeng sa lenane la lisebelisoa.

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Memori ea Boot e tšehelitsoeng
Memori ea On-chip (OCRAM) Memori e kopantsoeng ka thata (TCM)

Sesebelisoa
Lisebelisoa tse thehiloeng ho SDM (ka Mailbox Client Intel FPGA IP). (2)
Lisebelisoa tsohle tsa Altera FPGA tse tšehetsoeng (2)
Lisebelisoa tsohle tsa Altera FPGA tse tšehetsoeng (2)

Mekhoa ea ho qalisa processor ea Nios V
Sesebelisoa sa processor sa Nios V se kopitsoe ho tloha ho tlhophiso ea QSPI flash ho ea ho RAM ho sebelisoa boot copier
Sesebelisoa sa processor sa Nios V se tsoa sebakeng sa OCRAM
Sesebelisoa sa processor sa Nios V se tsoa sebakeng sa TCM

Kopo Runtime Location

Boot Copier

OCRAM/ Bootloader ea RAM ea kantle ka SDM

OCRAM

alt_load () mosebetsi

Taelo TCM (XIP) Ha ho + Data TCM (bakeng sa likarolo tsa lintlha tse ngoloang)

Setšoantšo sa 28. Nios V Processor Boot Flow

Seta bocha

processor e tlolela ho seta vector bocha (ho qala khoutu ea boot)

Khoutu ea kopo e ka kopitsoa sebakeng se seng sa memori (ho ipapisitse le likhetho tsa boot)
Khoutu ea boot e qala processor

Ho ipapisitsoe le likhetho tsa boot, khoutu ea boot e ka kopitsa boleng ba data / khoutu sebakeng se seng sa memori (alt_load)
Khoutu ea boot e qala khoutu ea ts'ebeliso le sebaka sa memori ea data
Khoutu ea boot e qala lisebelisoa tsohle tsa sistimi e nang le bakhanni ba HAL (alt_main)
Ho kena ka sehloohong
Lintlha Tse Amanang le Ena · Generic Serial Flash Interface Altera FPGA IP User Guide
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· Lebokose la mangolo Client Altera FPGA IP User Guide · AN 980: Nios V Processor Quartus Prime Software Support
4.4. Kenyelletso ea Mekhoa ea Booting ea Nios V
Sistimi ea processor ea Nios V e hloka hore litšoantšo tsa software li hlophisoe mohopolong oa sistimi pele processor e ka qala ho etsa lenaneo la kopo. Sheba Likarolo tsa Linker bakeng sa likarolo tsa lihokelo tsa kamehla.
BSP Editor e hlahisa mongolo oa khokahanyo o etsang mesebetsi e latelang: · E netefatsa hore software ea processor e hoketsoe ho latela litlhophiso tsa khokahano.
ea mohlophisi oa BSP mme e etsa qeto ea hore na software e lula kae mohopolong. · Beha sebaka sa khoutu ea processor karolong ea memori ho latela
dikarolo tsa memori tse abetsweng.
Karolo e latelang e hlalosa ka bokhutšoanyane mekhoa e fumanehang ea Nios V processor booting.
4.4.1. Sesebelisoa sa Nios V processor se Phetha-Sebakeng ho tsoa ho Boot Flash
Altera e entse li-flash controller e le hore sebaka sa aterese ea boot flash se fihle hang-hang ho processor ea Nios V ha sistimi e seta bocha, ntle le tlhoko ea ho qala taolo ea memori kapa lisebelisoa tsa memori. Sena se nolofalletsa processor ea Nios V hore e phethe khoutu ea kopo e bolokiloeng lisebelisoa tsa boot ka kotloloho ntle le ho sebelisa kopi ea boot ho kopitsa khoutu ho mofuta o mong oa memori. Lilaoli tsa flash ke: · On-Chip Flash e nang le On-Chip Flash IP (feela ka sesebelisoa sa MAX® 10) · Sepheo se akaretsang sa QSPI flash e nang le Generic Serial Flash Interface IP · Configuration QSPI flash e nang le Generic Serial Flash Interface IP (ntle le MAX 10
lisebelisoa)
Ha Nios V processor application e etsa-in-place ho tloha boot flash, BSP Editor e etsa mesebetsi e latelang: · E beha likarolo tsa .text linker sebakeng sa memori ea boot flash. · E beha likarolo tsa .bss,.rodata, .rwdata, .stack le .heap linker ho RAM
sebaka sa mohopolo. O tlameha ho nolofalletsa tšebetso ea alt_load() ho Litlhophiso tsa BSP ho kopitsa likarolo tsa data (.rodata, .rwdata,, .exceptions) ho RAM ha sistimi e seta bocha. Karolo ea khoutu (.text) e sala sebakeng sa memori ea boot flash.
Lintlha tse amanang le tsona · Generic Serial Flash Interface Altera FPGA IP User Guide · Altera MAX 10 User Flash Memory User Guide
4.4.1.1. alt_load()
U ka nolofalletsa tšebetso ea alt_load() ho khoutu ea HAL u sebelisa BSP Editor.
Ha e sebelisoa ho phallo ea boot-in-place, mosebetsi oa alt_load () o etsa mesebetsi e latelang:

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· E sebetsa joalo ka mini boot copier e kopitsang likarolo tsa memori ho RAM ho latela litlhophiso tsa BSP.
· Kopitsa likarolo tsa data (.rodata, .rwdata, .exceptions) ho RAM empa eseng likarolo tsa khoutu (.text) .Karolo ea khoutu (.text) ke karolo ea ho bala feela 'me e sala sebakeng sa memori ea flash booting. Karohano ena e thusa ho fokotsa ts'ebeliso ea RAM empa e ka fokotsa ts'ebetso ea khoutu hobane phihlello ea memori ea flash e lieha ho feta phihlello ea on-chip RAM.

Tafole e latelang e thathamisa litlhophiso le mesebetsi ea BSP Editor:

Lethathamo la 31. Litlhophiso tsa Mohlophisi oa BSP
Tlhophiso ea Mohlophisi oa BSP hal.linker.enable_alt_load hal.linker.enable_alt_load_copy_rodata hal.linker.enable_alt_load_copy_rwdata hal.linker.enable_alt_load_copy_mekhelo

Mosebetsi o thusa alt_load() tshebetso. alt_load () likopi .rodata karolo ho RAM. alt_load() likopi .rwdata karolo ho RAM. alt_load() likopi .exceptions karolo ho RAM.

4.4.2. Sesebelisoa sa Nios V processor se kopitsoe ho tloha ho Boot Flash ho ea ho RAM ho sebelisoa Boot Copier
Motlakase oa Nios V le HAL li kenyelletsa mochini oa ho kopitsa o fanang ka ts'ebetso e lekaneng bakeng sa lisebelisoa tse ngata tsa Nios V 'me e loketse ho e sebelisa ka phallo ea ntlafatso ea software ea Nios V.
Ha kopo e sebelisa boot copier, e beha likarolo tsohle tsa li-linker ( .text, .heap , .rwdata, .rodata , .bss, .stack) ho RAM e ka hare kapa e ka ntle. Ho sebelisa boot copier ho kopitsa kopo ea processor ea Nios V ho tloha boot flash ho RAM e ka hare kapa e ka ntle bakeng sa ts'ebetso ho thusa ho ntlafatsa ts'ebetso ea ts'ebetso.
Bakeng sa khetho ena ea boot, processor ea Nios V e qala ho sebelisa software ea boot copier ha sistimi e seta bocha. Software e kopiletsa ts'ebeliso ho tloha ho boot flash ho ea ho RAM e kahare kapa kantle. Hang ha ts'ebetso e felile, processor ea Nios V e fetisetsa taolo ea lenaneo ho kopo.

Hlokomela:

Haeba boot copier e le ka flash, joale mosebetsi oa alt_load () ha o hloke ho bitsoa hobane ka bobeli ba sebeletsa morero o le mong.

4.4.2.1. Nios V processor Bootloader ka Generic Serial Flash Interface
Bootloader ka GSFI ke Nios V processor boot copier e tšehetsang memori ea flash ea QSPI ho lisebelisoa tse thehiloeng ho li-block. Bootloader ka GSFI e kenyelletsa lintlha tse latelang:
· E fumana ts'ebeliso ea software mohopolong o sa fetoheng.
· E manolla le ho kopitsa setšoantšo sa sesebelisoa sa software ho RAM.
* E fetolela ka bo eona ts'ebetso ea processor ho khoutu ea kopo ho RAM kamora hore kopi e phethe.

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Setšoantšo sa boot se fumaneha hang ka mor'a mochine oa boot. U hloka ho etsa bonnete ba hore processor ea Nios V e tsosolosa lintlha tsa offset ho tloha qalong ea kopi ea boot. Setšoantšo: 'Mapa oa Memori bakeng sa QSPI Flash e nang le Bootloader ka 'mapa oa memori oa GSFI bakeng sa QSPI Flash e nang le Bootloader ka GSFI e bonts'a 'mapa oa memori oa flash bakeng sa lebone la QSPI ha o sebelisa mochini oa ho kopitsa. 'Mapa ona oa memori o nka hore memori ea flash e boloka setšoantšo sa FPGA le software ea ts'ebeliso.

Letlapa la 32. Bootloader ka GSFI bakeng sa Nios V Processor Core

Nios V processor Core
processor ea Nios V/m

Bootloader ka GSFI File Sebaka
/niosv/components/bootloader/ niosv_m_bootloader.srec

Nios V/g processor

/niosv/components/bootloader/ niosv_g_bootloader.srec

Setšoantšo sa 29. 'Mapa oa Memori bakeng sa QSPI Flash e nang le Bootloader ka GSFI

Lintlha tsa Bareki (*.hex)

Khoutu ea Kopo

Hlokomela:

Seta bocha Vector Offset

Boot Copier

0x01E00000

FPGA Setšoantšo (*.sof)

0x00000000

1. Qalong ea 'mapa oa memori ke setšoantšo sa FPGA se lateloang ke data ea hau, e nang le boot copier le khoutu ea kopo.
2. U tlameha ho seta "Nios V processor reset offset" ho Platform Designer 'me u e supe qalong ea mochini oa ho kopitsa.
3. Boholo ba setšoantšo sa FPGA ha bo tsejoe.U ka tseba feela boholo bo nepahetseng ka mor'a ho bokelloa ha morero oa Quartus Prime. U tlameha ho khetha moeli o ka holimo bakeng sa boholo ba setšoantšo sa Altera FPGA. Bakeng sa mohlalaample, haeba boholo ba setšoantšo sa FPGA bo hakanngoa hore bo ka tlase ho 0x01E00000, beha Reset Offset ho 0x01E00000 ho Platform Designer, eo hape e leng qalo ea mochine oa boot.
4. Mokhoa o motle oa ho etsa moralo o kenyelletsa ho seta reset vector offset moeling oa karolo ea flash ho netefatsa hore ha ho hlakoloe ka mokhoa o itseng oa setšoantšo sa FPGA haeba sesebelisoa sa software se ka nchafatsoa.

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4.4.2.2. Nios V processor Bootloader ka Secure Device Manager
Bootloader ka Secure Device Manager (SDM) ke khoutu ea ts'ebeliso ea HAL e sebelisang Lebokose la Mail Client Altera FPGA IP HAL mokhanni bakeng sa ho qala processor. Altera e khothaletsa sesebelisoa sena sa bootloader ha u sebelisa setaele sa QSPI ho lisebelisoa tse thehiloeng ho SDM ho bulela processor ea Nios V.
Ha sistimi e seta bocha, processor ea Nios V e qala Bootloader ka SDM ho tsoa mohopolong o monyane oa on-chip mme e phethisa Bootloader ka SDM ho buisana le QSPI flash e sebelisang Mailbox Client IP.
Bootloader ka SDM e etsa mesebetsi e latelang: · E fumana software ea Nios V ho flash ea QSPI ea tlhophiso. * Kopitsa software ea Nios V ho RAM ea on-chip kapa RAM e kantle. · Fetolela ts'ebetso ea processor ho software ea Nios V ka har'a RAM ea on-chip kapa
RAM ea kantle.
Hang ha ts'ebetso e phethiloe, Bootloader ka SDM e fetisetsa taolo ea lenaneo ho sesebelisoa sa mosebelisi. Altera e khothaletsa mokhatlo oa memori joalo ka ha o hlalositsoe ho Memory Organisation for Bootloader ka SDM.
Setšoantšo sa 30. Bootloader ka SDM Process Flow

Tlhophiso

Khanya

Nios V Software

SDM

Sesebelisoa sa FPGA se thehiloeng ho SDM

Lebokose la poso la Client IP

FPGA Logic Nios V

4 RAM ea kantle
Nios V Software

On-Chip 4

EMIF

RAM

Memori ea On-Chip

Nios V

Software

Bootloader ka SDM

1. Nios V processor e tsamaisa Bootloader ka SDM ho tsoa mohopolong oa on-chip.
2. Bootloader ka SDM e buisana le flash ea tlhophiso mme e fumana software ea Nios V.
3. Bootloader ka SDM e kopitsa software ea Nios V ho tloha ho Configuration Flash ho ea ho RAM / RAM ea kantle.
4. Bootloader ka SDM e fetola ts'ebetso ea processor ea Nios V ho software ea Nios V ho RAM ea on-chip / RAM e kantle.

4.4.3. Kopo ea Nios V processor e Phetha-Sebakeng ho tsoa ho OCRAM
Ka mokhoa ona, aterese ea reset ea processor ea Nios V e behiloe atereseng ea motheo ea memori ea on-chip (OCRAM). Binary ya tshebediso (.hex) file e kenngoa ka har'a OCRAM ha FPGA e hlophisoa, ka mor'a hore moralo oa hardware o hlophisoe ka har'a software ea Quartus Prime. Hang ha processor ea Nios V e qala hape, ts'ebeliso e qala ho sebetsa le makala ho fihla moo ho kenang.

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Hlokomela:

· Phethahatso-ka-Sebaka ho tsoa ho OCRAM ha e hloke boot copier hobane ts'ebeliso ea Nios V processor e se e ntse e le teng ha sistimi e seta bocha.
· Altera e khothaletsa ho nolofalletsa alt_load() bakeng sa mokhoa ona oa ho qala e le hore software e kentsoeng e sebetse ka mokhoa o ts'oanang ha e seta botjha ntle le ho lokisa sets'oants'o sa FPGA.
· U tlameha ho lumella tšebetso ea alt_load() ho Litlhophiso tsa BSP ho kopitsa karolo ea .rwdata ha sistimi e seta bocha. Ka mokhoa ona, litekanyetso tsa pele tsa mefuta-futa tse qalileng li bolokoa ka thoko ho mefuta e lumellanang ho qoba ho ngola ho feta ts'ebetsong ea lenaneo.

4.4.4. Nios V processor Kopo ea Phethahatsa-Sebakeng ho tsoa ho TCM
Mokhoa oa ho phethahatsa o beha aterese ea processor ea Nios V atereseng ea mantlha ea memori e kopantsoeng ka thata (TCM). Binary ya tshebediso (.hex) file e kenngoa ka har'a TCM ha u lokisa FPGA ka mor'a hore u bokelle moralo oa hardware ho software ea Quartus Prime. Hang ha processor ea Nios V e qala hape, ts'ebeliso e qala ho sebetsa le makala ho fihla moo ho kenang.

Hlokomela:

Execute-In-Place ho tsoa ho TCM ha e hloke boot copier hobane ts'ebeliso ea processor ea Nios V e se e ntse e le teng ha ho hlophisoa bocha sistimi.

4.5. Nios V processor e qala ho tsoa ho On-Chip Flash (UFM)

Nios V processor e qala le ho sebelisa software ho tsoa ho on-chip flash (UFM) e fumaneha ka lisebelisoa tsa MAX 10 FPGA. Mochine oa Nios V o tšehetsa likhetho tse peli tse latelang tsa boot o sebelisa On-Chip Flash tlas'a Internal Configuration mode:
· Sesebelisoa sa processor sa Nios V se sebetsa sebakeng se tsoang ho On-Chip Flash.
* Sesebelisoa sa processor sa Nios V se kopitsoa ho tloha ho On-Chip Flash ho ea ho RAM ho sebelisoa mochini oa ho kopitsa.

Letlapa la 33. Memori ea Flash e ts'ehelitsoeng ka likhetho tse fapaneng tsa Boot

Memori ea Boot e tšehelitsoeng

Mekhoa ea ho qalisa Nios V

Kopo Runtime Location

Boot Copier

Lisebelisoa tsa MAX 10 feela (ka OnChip Flash IP)

Sesebelisoa sa processor sa Nios V se tsoa sebakeng sa On-Chip Flash
Sesebelisoa sa processor sa Nios V se kopitsoe ho tloha ho On-Chip ho ea ho RAM ho sebelisoa mochini oa ho qopitsa

On-Chip Flash (XIP) + OCRAM/ RAM e kantle (bakeng sa likarolo tsa data tse ngoloang)

alt_load () mosebetsi

OCRAM/ RAM ya kantle

Ho sebelisa Bootloader hape ka GSFI

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Setšoantšo sa 31.

Moralo, Tlhophiso, le Phallo ea ho qalisa
Moralo · Theha projeke ea hau e thehiloeng ho Nios V u sebelisa Moqapi oa Platform. Netefatsa hore ho na le RAM ea kantle kapa RAM ea on-chip moralong oa sistimi.

FPGA Configuration le Competion
· Beha mokhoa o ts'oanang oa tlhophiso ea kahare ho On-chip Flash IP ho Platform Designer le Quartus Prime software. · Beha moemeli oa ho seta botjha ho processor ea Nios V ho On-chip Flash. · Khetha mokhoa oo u o ratang oa ho qala UFM. · Hlahisa moralo oa hau ho Moqapi oa Platform. · Kopanya morero oa hau ho software ea Quartus Prime.

User Application BSP Project · Create Nios V processor HAL BSP based on .sopcinfo file e entsoeng ke Moqapi oa Platform. · Fetola litlhophiso tsa BSP tsa processor ea Nios V le Linker Script ho BSP Editor. · Hlahisa morero oa BSP.
Morero oa APP ea Mosebelisi · Theha khoutu ea kopo ea processor ea Nios V. * Kopanya sesebelisoa sa processor sa Nios V 'me u hlahise sesebelisoa sa processor sa Nios V (.hex) file. · Hlahisa morero oa hau hape ka software ea Quartus Prime haeba u sheba Qala khetho ea dikahare tsa memori ho Intel FPGA On-Chip Flash IP.

Lenaneo Files Phetoho, Khoasolla le ho Matha · Hlahisa Flash ea On-Chip .pof file sebelisa Convert Programming Files tšobotsi ho software ea Quartus Prime.
· Lenaneo la .pof file sesebelisoa sa hau sa MAX 10. · Potoloho ea motlakase ea lisebelisoa tsa hau.
4.5.1. MAX 10 FPGA On-Chip Tlhaloso ea Flash
Lisebelisoa tsa MAX 10 FPGA li na le on-chip flash e arotsoeng likarolo tse peli: · Configuration Flash Memory (CFM) - e boloka data ea tlhophiso ea hardware bakeng sa
MAX 10 FPGAs. · User Flash Memory (UFM) — e boloka data kapa lisebelisoa tsa software.
Moralo oa UFM oa sesebelisoa sa MAX 10 ke motsoako oa li-IP tse bonolo le tse thata. O ka fihlella UFM feela o sebelisa On-Chip Flash IP Core ho software ea Quartus Prime.
On-chip Flash IP core e tshehetsa dikarolo tse latelang: · Bala kapa o ngole phihlello ho UFM le CFM (haeba e dumellwa makaleng a Moqapi wa Platform)
ho sebelisa data ea Avalon MM le ho laola sebopeho sa makhoba. · E ts'ehetsa ho hlakola leqephe, ho hlakola likarolo le ho ngola ka lekala. * Mohlala oa ketsiso oa phihlello ea ho bala / ho ngola ea UFM o sebelisa lisebelisoa tse fapaneng tsa papiso ea EDA.

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Letlapa la 34. Libaka tsa Flash tsa On-chip ho MAX 10 FPGA Devices

Libaka tsa Flash

Tshebetso

Configuration Flash Memory (mekhahlelo CFM0-2)

Sebopeho sa FPGA file polokelo

Memori ea Flash Flash (mafapha a UFM0-1)

Sesebelisoa sa processor sa Nios V le data ea mosebelisi

Lisebelisoa tsa MAX 10 FPGA li tšehetsa mekhoa e mengata ea tlhophiso 'me e meng ea mekhoa ena e lumella CFM1 le CFM2 ho sebelisoa e le sebaka se eketsehileng sa UFM. Tafole e latelang e bonts'a sebaka sa polokelo ea litšoantšo tsa tlhophiso ea FPGA e ipapisitseng le mekhoa ea tlhophiso ea MAX 10 FPGA.

Letlapa la 35. Sebaka sa polokelo ea litšoantšo tsa FPGA tsa Configuration

Mokhoa oa ho hlophisa Litšoantšo tse hatelitsoeng habeli

CFM2 Compressed Image 2

CFM1

CFM0 Compressed Image 1

Setšoantšo se le seng se sa hatelloang

UFM ea sebele

Setšoantšo se sa hatelletsoeng

Setšoantšo se le seng se sa hatelletsoeng se nang le Memory Initialization

Setšoantšo se sa hatelletsoeng (se nang le litaba tsa memori ea chip)

Setšoantšo se le seng se hatisitsoeng se nang le Memory Initialization ea setšoantšo se hatelitsoeng (se nang le litaba tsa memori ea on-chip)

Setšoantšo se petelitsoeng se le seng

UFM ea sebele

Setšoantšo se hatisitsoeng

U tlameha ho sebelisa On-chip Flash IP core ho fihlella memori ea flash ka MAX 10 FPGAs. U ka tiisa le ho hokela On-chip Flash IP ho software ea Quartus Prime. Nios V soft core processor e sebelisa likhokahano tsa Moqapi oa Platform ho buisana le On-chip Flash IP.
Setšoantšo sa 32. Khokahano pakeng tsa On-chip Flash IP le Nios V Processor

Hlokomela:

Netefatsa hore boema-kepe ba On-chip Flash csr bo hoketsoe ho Nios V processor data_manager ho thusa processor ho laola ho ngola le ho hlakola tšebetso.
On-chip Flash IP core e ka fana ka phihlello ho mafapha a mahlano a flash - UFM0, UFM1, CFM0, CFM1, le CFM2.
Lintlha tsa bohlokoa mabapi le likarolo tsa UFM le CFM
· Lintlha tsa mosebelisi li ka bolokoa makaleng a UFM 'me li ka patoa, haeba ho khethoa litlhophiso tse nepahetseng ho sesebelisoa sa Moqapi oa Sethala.
Lisebelisoa tse ling ha li na karolo ea UFM1. U ka sheba tafole: Boholo ba Lekala la UFM le CFM bakeng sa likarolo tse fumanehang sesebelisoa se seng le se seng sa MAX 10 FPGA.

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· U ka hlophisa CFM2 joalo ka UFM ea sebele ka ho khetha mokhoa oa ho hlophisa setšoantšo se le seng sa Uncompressed.
· O ka hlophisa CFM2 le CFM1 joalo ka UFM ea sebele ka ho khetha mokhoa oa ho hlophisa setšoantšo se le seng sa Uncompressed.
* Boholo ba lekala ka leng bo fapana ho latela lisebelisoa tse khethiloeng tsa MAX 10 FPGA.

Lethathamo la 36.

Boholo ba Lekala la UFM le CFM
Tafole ena e thathamisa litekanyo tsa lihlopha tsa UFM le CFM.

Sesebelisoa

Maqephe ka Lekala

UFM1 UFM0 CFM2 CFM1 CFM0

Boholo ba Leqephe (Kbit)

Boholo ba Mosebedisi
Boholo ba Memori ea Flash (Kbit) (3)

Kakaretso ea Boholo ba Memori ea Tlhophiso (Kbit)

10M02 3

34 16

544

10M04 0

41 29 70 16

1248

2240

10M08 8

41 29 70 16

1376

2240

10M16 4

38 28 66 32

2368

4224

10M25 4

52 40 92 32

3200

5888

10M40 4

48 36 84 64

5888

10752

10M50 4

48 36 84 64

5888

10752

Boholo ba OCRAM (Kbit)
108 189 378 549 675 1260 1638

Lintlha tse amanang · MAX 10 FPGA Configuration User Guide · Altera MAX 10 User Flash Memory User Guide

4.5.2. Nios V processor Kopo ea Phethahatso-Sebakeng ho tsoa ho UFM

The Execute-In-Place ho tsoa ho tharollo ea UFM e loketse lits'ebetso tsa processor tsa Nios V tse hlokang ts'ebeliso e lekanyelitsoeng ea memori ea on-chip. The alt_load() ts'ebetso e sebetsa joalo ka mini boot copier e kopitsang likarolo tsa data (.rodata, .rwdata, or .exceptions) ho tloha boot memory ho RAM ho latela litlhophiso tsa BSP. Karolo ea khoutu (.text),
e leng karolo e baloang feela, e ntse e le sebakeng sa memori sa MAX 10 On-chip Flash. Setupo sena se fokotsa ts'ebeliso ea RAM empa se ka fokotsa ts'ebetso ea khoutu kaha phihlello ea memori ea flash e lieha ho feta ea on-chip RAM.

Sesebelisoa sa processor sa Nios V se hlophiselitsoe lekaleng la UFM. Vector ea processor ea Nios V e supa atereseng ea mantlha ea UFM ho kenya khoutu ho tsoa ho UFM kamora hore sistimi e hlophisoe.

Haeba u sebelisa sesebelisoa sa boemo ba mohloli ho lokisa bothata ba sesebelisoa sa hau, u tlameha ho sebelisa sebaka sa ho senya thepa. Lebaka ke hobane UFM ha e tšehetse phihlello ea memori e sa reroang, e hlokahalang bakeng sa ho lokisa phoso e bonolo.

Hlokomela:

O ka se hlakole kapa ho ngola UFM ha o ntse o etsa execute-in-place ho MAX 10. Fetolela mokhoeng oa ho kopitsa ha o hloka ho hlakola kapa ho ngola UFM.

(3) Boholo bo ka khonehang, bo itšetlehileng ka mokhoa oa ho hlophisa oo u o khethang.

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Setšoantšo sa 33. Nios V Processor Application XIP ho tloha UFM

Max 10 Sesebelisoa

.POF
Nios V Hardware .SOF
Nios V Software .HEX

Lenaneo la Quartus

On-Chip Flash

CFM

Lisebelisoa tsa Nios V

UFM

Nios V Software

Tlhophiso e ka Hare

On-Chip Flash IP

Tlhaloso ea FPGA
Nios V processor

RAM e tsoang ho Chip

Kantle

RAM

EMIF

4.5.2.1. Phallo ea Moralo oa Hardware
Karolo e latelang e hlalosa mokhoa oa mohato ka mohato oa ho aha sistimi ea bootable bakeng sa sesebelisoa sa processor sa Nios V ho tsoa ho On-Chip Flash. Example ka tlase e hahiloe ho sebelisoa sesebelisoa sa MAX 10.
Litlhophiso tsa Karolo ea IP
1. Theha projeke ea hau ea processor ea Nios V u sebelisa Quartus Prime le Platform Designer. 2. Etsa bonnete ba hore RAM ea ka ntle kapa Memory On-Chip (OCRAM) e kenyelelitsoe Platform ea hau
Moqapi oa tsamaiso.

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Setšoantšo sa 34. Example likhokahano tsa IP ho Moqapi oa Platform bakeng sa Booting Nios V ho tsoa ho OnChip Flash (UFM)

3. Ho On-Chip Flash IP parameter editor, beha Mokhoa oa Tlhophiso ho e 'ngoe ea tse latelang, ho ea ka khetho ea hau ea moralo: · Setšoantšo se le seng se sa Hatelletsoeng · Setšoantšo se le seng se Hatelitsoeng · Setšoantšo se le seng se sa Hatelletsoeng ka ho Qala Memori · Setšoantšo se le seng se Hatelitsoeng se nang le Memory Initialization.
Bakeng sa tlhaiso-leseling e batsi mabapi le Lits'oants'o tse Habeli tse Hatelitsoeng, sheba ho MAX 10 FPGA Configuration User Guide - Ntlafatso ea Remote System.

Hlokomela:

U tlameha ho abela Phihlello e Patiloeng libakeng tsohle tsa CFM ho On-Chip Flash IP.

Setšoantšo sa 35. Khetho ea Mokhoa oa Tlhophiso ho On-Chip Flash Parameter Editor

On-Chip Flash IP Settings - UFM Initialization U ka khetha e 'ngoe ea mekhoa e latelang ho latela khetho ea hau:

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Hlokomela:

Mehato e ka har'a li-subchapter tse latelang (Software Design Flow le Programming) e itšetlehile ka khetho eo u e etsang mona.

· Mokhoa oa 1: Qala data ea UFM ho SOF nakong ea ho bokella
Quartus Prime e kenyelletsa lintlha tsa ho qala tsa UFM ho SOF nakong ea ho bokella. Recompilation ea SOF ea hlokahala haeba ho na le liphetoho ho data ea UFM.
1. Sheba Ho qala dikahare tsa flash mme o Nolofalletse ho qala ho sa tsitsang file.

Setšoantšo sa 36. Qala Likahare tsa Flash 'me u Nolofalletse ho Qala ho sa Etsahaleng File

2. Hlalosa tsela ea .hex e hlahisitsoeng file (ho tsoa ho taelo ea elf2hex) ho Mosebelisi o thehile hex kapa mif file.
Setšoantšo sa 37. Ho eketsa .hex File Tsela

· Mokhoa oa 2: Kopanya data ea UFM le SOF e hlophisitsoeng nakong ea tlhahiso ea POF
Lintlha tsa UFM li kopantsoe le SOF e hlophisitsoeng ha ho fetoloa mananeo files. Ha ho hlokahale hore u boele u bokelle SOF, leha data ea UFM e fetoha. Nakong ea nts'etsopele, ha ua tlameha ho bokella SOF files bakeng sa liphetoho ts'ebetsong. E 'ngoe e khothaletsa mokhoa ona bakeng sa baetsi ba lisebelisoa.
1. Tlosa ho hlahlobisisa Qala litaba tsa flash..
Setšoantšo sa 38. Qala Litaba tsa Flash ka mokhoa o sa tsitsang oa ho qala File

Seta bocha Litlhophiso tsa Moemeli bakeng sa Mokhoa oa ho Phethahatsa ka Sebaka sa Nios V
1. Ho Nios V processor parameter editor, seta Setsi sa Reset ho On-Chip Flash.
Setšoantšo sa 39. Nios V processor Parameter Editor Settings with Reset Agent Be set to On-Chip Flash.

2. Tobetsa Hlahisa HDL ha Lebokose la puisano la Moloko le hlaha. 3. Hlalosa tlhahiso file ho hlahisa likhetho ebe o tobetsa Hlahisa.

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Quartus Prime Software Settings 1. In the Quartus Prime software, click Assignments Device Device and Pin
Options Configuration. Set the Configuration mode according to the setting in On-Chip Flash IP. Figure 40. Configuration Mode Selection in Quartus Prime Software

2. Tobetsa OK ho tsoa fensetereng ea Lisebelisoa le Pin,
3. Click OK ho tsoa ka Sesebediswa fensetere.
4. Click Processing Start Compilation to compile your project and generate the .sof file.

Hlokomela:

Haeba maemo a tlhophiso a Quartus Prime software le Platform Designer parameter e fapane, morero oa Quartus Prime o hloleha ka molaetsa o latelang oa phoso.

Setšoantšo sa 41.

Molaetsa oa Phoso bakeng sa Phoso ea Boemo ba Mokhoa o Fapaneng oa Tlhophiso (14740): Mokhoa oa tlhophiso ho atom "q_sys:q_sys_inst| altera_onchip_flash:onchip_flash_1|altera_onchip_flash_block: altera_onchip_flash_block|ufm_block" ha e tsamaellane le tlhophiso ea morero. Ntlafatsa le ho nchafatsa sistimi ea Qsys ho tsamaisana le tlhophiso ea projeke.

Lintlha Tse Amanang le Tataiso ea Mosebelisi ea MAX 10 FPGA

4.5.2.2. Phallo ea Moralo oa Software
Karolo ena e fana ka phallo ea moralo ho hlahisa le ho aha projeke ea software ea Nios V. Ho netefatsa phallo e hlophisitsoeng ea kaho, o khothaletsoa ho theha sefate se ts'oanang sa bukana morerong oa hau oa moralo. Phallo e latelang ea moralo oa software e ipapisitse le sefate sena sa directory.
Ho theha sefate sa directory sa projeke ea software, latela mehato ena: 1. Foldareng ea morero oa moralo oa hau, theha foldara e bitsoang software. 2. Ka har'a foldara ea software, theha lifoldara tse peli tse bitsoang hal_app le hal_bsp.
Setšoantšo sa 42. Sefate sa Directory Project Software

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Ho theha Morero oa Ts'ebeliso ea BSP
Ho thakhola BSP Editor, latela mehato ena: 1. Kenya Nios V Command Shell. 2. Kopa BSP Editor ka taelo ya niosv-bsp-editor. 3. Ho BSP Editor, tobetsa File BSP e ncha ho qala projeke ea hau ea BSP. 4. Hlophisa litlhophiso tse latelang:
· Litaba tsa SOPC File lebitso: Fana ka SOPCINFO file (.sopcinfo). · Lebitso la CPU: Khetha processor ea Nios V. · Sistimi e sebetsang: Khetha sistimi e sebetsang ea processor ea Nios V. · Mofuta: Tloha joalo ka kamehla. · Bukana ea sepheo sa BSP: Khetha tsela ea lenane la morero oa BSP. U ka khona
e behe pele ho /software/hal_bsp ka ho nolofalletsa Sebelisa libaka tsa kamehla. · Litlhophiso tsa BSP File lebitso: Ngola lebitso la Litlhophiso tsa BSP File. · Mengolo ea Tlatsetso ea Tcl: Fana ka sengoliloeng sa BSP Tcl ka ho nolofalletsa ho Nomella mongolo oa Tlatsetso oa Tcl. 5. Tobetsa OK.
Figure 43. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project
You can define the processor’s exception vector either in On-Chip Memory (OCRAM) or On-Chip Flash based on your design preference. Setting the exception vector memory to OCRAM/External RAM is recommended to make the interrupt processing faster. 1. Go to Main Settings Advanced hal.linker. 2. If you select On-Chip Flash as exception vector,
a. Enable the following settings:

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· allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata Figure 44. Advanced.hal.linker Settings

b. Click on the Linker Script tab in the BSP Editor. c. Set the .exceptions and .text regions in the Linker Section Name to
On-Chip Flash. d. Set the rest of the regions in the Linker Section Name list to the On-Chip
Memory (OCRAM) or external RAM.
Figure 45. Linker Region Settings (Exception Vector Memory: On-Chip Flash)

3. If you select OCRAM/External RAM as exception vector, a. Enable the following settings: · allow_code_at_reset · enable_alt_load · enable_alt_load_copy_rodata · enable_alt_load_copy_rwdata · enable_alt_load_copy_exception
Figure 46. Linker Region Settings (Exception Vector Memory: OCRAM/External RAM)

b. Click on the Linker Script tab in the BSP Editor.
c. Set the.text regions in the Linker Section Name to On-Chip Flash.
d. Set the rest of the regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.

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Figure 47. Linker Region Settings (Exception Vector Memory: OCRAM)
4. Click Generate to generate the BSP project. Generating the User Application Project File 1. Navigate to the software/hal_app folder and create your application source
code. 2. Launch the Nios V Command Shell. 3. Execute the command below to generate the application CMakeLists.txt.
niosv-app –app-dir=software/hal_app –bsp-dir=software/hal_bsp –srcs=software/hal_app/<user application>
Building the User Application Project You can choose to build the user application project using Ashling RiscFree IDE for Altera FPGAs or through the command line interface (CLI). If you prefer using CLI, you can build the user application using the following command: cmake -G “Unix Makefiles” -B software/hal_app/build -S software/hal_app make -C software/hal_app/build
The application (.elf) file is created in software/hal_app/build folder. Generating the HEX File You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices. 1. Launch the Nios V Command Shell. 2. For Nios V processor application boot from On-Chip Flash, use the following
command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file. elf2hex software/hal_app/build/<user_application>.elf -o onchip_flash.hex
-b <base address of On-Chip Flash UFM region> -w 8 -e <end address of On-Chip Flash UFM region> 3. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.

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4.5.2.3. Programming 1. In Quartus Prime, click File Fetola Programming Files. 2. Under Output programming file, choose Programmer Object File (.pof) as Programming file type. 3. Set Mode to Internal Configuration.
Figure 48. Convert Programming File Litlhophiso
4. Click Options/Boot info…, the MAX 10 Device Options window appears. 5. Based on the Initialize flash content settings in the On-chip Flash IP, perform
one of the following steps: · If Initialize flash content is checked (Method 1), the UFM initialization data
was included in the SOF duringQuartus Prime compilation. — Select Page_0 for UFM source: option. Click OK and proceed to the
next. Figure 49. Setting Page_0 for UFM Source if Initialize Flash Content is Checked

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· If Initialize flash content is not checked (Method 2), choose Load memory file for the UFM source option. Browse to the generated On-chip Flash HEX file (onchip_flash.hex) in the File path: and click OK. This step adds UFM data separately to the SOF file during the programming file tshokoloho.
Figure 50. Setting Load Memory File for UFM Source if Initialize Flash Content is Not Checked

6. In the Convert Programming File dialog box, at the Input files to convert section, click Add File… and point to the generated Quartus Prime .sof file.
Figure 51. Input Files to Convert in Convert Programming Files for Single Image Mode

7. Click Generate to create the .pof file. 8. Program the .pof file into your MAX 10 device. 9. Power cycle your hardware.

4.5.3. Nios V Processor Application Copied from UFM to RAM using Boot Copier

Altera recommends this solution for MAX 10 FPGA Nios V processor system designs where multiple iterations of application software development and high system performance are required. The boot copier is located within the UFM at an offset that is the same address as the reset vector. The Nios V application is located next to the boot copier.

For this boot option, the Nios V processor starts executing the boot copier upon system reset to copy the application from the UFM sector to the OCRAM or external RAM. Once copying is complete, the Nios V processor transfers the program control over to the application.

Hlokomela:

The applied boot copier is the same as the Bootloader via GSFI.

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Figure 52. Nios V Application Copied from UFM to RAM using Boot Copier

Max 10 Sesebelisoa

.POF
Nios V Hardware .SOF
Nios V Software .HEX
Bootloader .SREC

Lenaneo la Quartus

RAM ea kantle
Nios V Software

On-Chip Flash

CFM

Nios V Hardwa

Litokomane / Lisebelisoa

altera Nios V Embedded Processor [pdf] Bukana ea Mosebelisi
Nios V, Nios V-m, Nios V-g, Nios V-c, Nios V Embedded Processor, Nios V, Embedded Processor, Processor

Litšupiso

Bukana ea Mosebelisi

altera Nios V Embedded Processor

Litlhaloso

Nios V Processor Hardware System Design

Nios V Processor Software System Design

Nios V Processor Configuration and Booting Solutions

Litokomane / Lisebelisoa

Litšupiso

Tlohela maikutlo

Hlakola karabo