intel F-Tile CPRI PHY FPGA IP Design Example
Jagoran Fara Mai Sauri
F-Tile CPRI PHY Intel® FPGA IP core yana ba da gwajin siminti da ƙirar kayan masarufi.ampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi.
Intel kuma yana ba da tarin-kawai exampaikin da za ku iya amfani da shi don kimanta yankin ainihin IP da lokaci da sauri.
F-Tile CPRI PHY Intel FPGA IP core yana ba da damar samar da ƙiraampLes don duk haɗin haɗin kai na adadin tashoshi na CPRI da ƙimar bit na layin CPRI. The testbench da zane exampgoyan bayan haɗe-haɗe masu yawa na F-Tile CPRI PHY Intel FPGA IP core.
Hoto 1. Matakan Ci gaba don Zane Example
Bayanai masu alaƙa
- F-Tile CPRI PHY Intel FPGA IP Jagorar Mai amfani
- Don cikakkun bayanai akan F-tile CPRI PHY IP.
- F-Tile CPRI PHY Intel FPGA IP Bayanan Bayani na Sakin
- Bayanan Bayanin Sakin IP ya lissafa canje-canjen IP a cikin wani saki na musamman.
Bukatun Hardware da Software
Don gwada tsohonampDon ƙira, yi amfani da hardware da software masu zuwa:
- Intel Quartus® Prime Pro Edition software
- Na'urar wasan bidiyo na tsarin
- Goyan bayan Simulators:
- Bayanan Bayani na VCS*
- Rahoton da aka ƙayyade na VCS MX
- Siemens* EDA ModelSim* SE ko Questa* — Questa-Intel FPGA Edition
Samar da Zane
Hoto 2. Tsari
Hoto 3. ExampZazzage Tab a cikin Editan Sigar IP
Don ƙirƙirar aikin Intel Quartus Prime Pro Edition:
- A cikin Intel Quartus Prime Pro Edition, danna File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Quartus Prime, ko File ➤ Bude Project don buɗe aikin Intel Quartus Prime da ke gudana. Mayen yana tambayarka don saka na'ura.
- Ƙayyade dangin Agilex (I-jerin) na na'urar kuma zaɓi na'urar da ta cika duk waɗannan buƙatu:
- Tile mai jujjuyawa shine F-tile
- Makin gudun transceiver shine -1 ko -2
- Mahimmin saurin gudu shine -1 ko -2 ko -3
- Danna Gama.
Bi waɗannan matakan don samar da F-Tile CPRI PHY Intel FPGA IP ƙirar kayan masarufi example da testbench:
- A cikin Catalog na IP, gano wuri kuma zaɓi F-Tile CPRI PHY Intel FPGA IP. Sabuwar taga Bambancin IP yana bayyana.
- Ƙayyade sunan babban matakin don bambancin IP ɗin ku na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
- Danna Ok. Editan siga ya bayyana.
- A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
- A kan Exampshafin Zane, ƙarƙashin Exampda Design Files, zaɓi zaɓin Simulation don samar da bench ɗin gwaji da aikin tattarawa kawai. Zaɓi zaɓin Synthesis don samar da ƙirar kayan masarufi example. Dole ne ku zaɓi aƙalla ɗaya daga cikin zaɓuɓɓukan Simulation da Synthesis don samar da ƙirar ƙiraample.
- A kan ExampDon Zane shafin, ƙarƙashin Ƙirƙirar HDL Format, zaɓi Verilog HDL ko VHDL. Idan ka zaɓi VHDL, dole ne ka kwaikwayi testbench tare da na'urar na'urar na'ura mai haɗaɗɗiyar harshe. Na'urar da ake gwadawa a cikin tsohon_ directory samfurin VHDL ne, amma babban testbench file shi ne System Verilog file.
- Danna Generate Example Design button. Zaɓi ExampTagar Zane Directory ya bayyana.
- Idan kana so ka gyara zane examphanyar directory ko suna daga abubuwan da aka saba nunawa (cpriphy_ftile_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampsunan directory (ample_dir>).
Tsarin Jagora
F-Tile CPRI PHY Intel FPGA IP core design example file kundin adireshi ya ƙunshi abubuwan da aka samar files don zane example.
Hoto 4. Tsarin Rubutu na Ƙarfafa Exampda Design
Tebur 1. Testbench File Bayani
| File Sunaye | Bayani |
| Key Testbench da Kwaikwayo Files | |
| <tsari_example_dir>/ misaliample_testbench/basic_avl_tb_top.sv | Babban matakin gwajin benci file. Testbench yana aiwatar da abin rufewar DUT kuma yana gudanar da ayyukan Verilog HDL don samarwa da karɓar fakiti. |
| <tsari_example_dir>/ misaliample_testbench/ cpriphy_ftile_wrapper.sv | DUT wrapper wanda ke hanzarta DUT da sauran abubuwan da aka gyara na testbench. |
| Rubutun Testbench (1) | |
| <tsari_example_dir>/ misaliample_testbench/run_vsim.do | Rubutun Siemens EDA ModelSim SE ko Questa ko Questa-Intel FPGA Edition don gudanar da gwajin benci. |
| <tsari_example_dir>/ misaliample_testbench/run_vcs.sh | Rubutun Synopsys VCS don gudanar da gwajin benci. |
| <tsari_example_dir>/ misaliample_testbench/run_vcsmx.sh | Rubutun Synopsys VCS MX (haɗe Verilog HDL da SystemVerilog tare da VHDL) don gudanar da gwajin benci. |
Yi watsi da kowane rubutun na'urar kwaikwayo a cikinample_dir>/ misaliample_testbench/ babban fayil.
Tebura 2. Zane Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kasa na Ƙasa ta Duniyaample File Bayani
| File Sunaye | Bayani |
| <tsari_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Intel Quartus Prime aikin file. |
| <tsari_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Saitin aikin Intel Quartus Prime file. |
| <tsari_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Ƙuntataccen Ƙira na Synopsys files. Kuna iya kwafa da gyara waɗannan files don ƙirar Intel Agilex™ na ku. |
| <tsari_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Babban matakin ƙirar Verilog HDL example file. |
| <tsari_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | DUT wrapper wanda ke hanzarta DUT da sauran abubuwan da aka gyara na testbench. |
| <tsari_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Babban file don samun damar System Console. |
Simulating da Design Exampda Testbench
Hoto 5. Tsari
Bi waɗannan matakan don kwaikwaya testbench:
- A saurin umarni, canza zuwa littafin simulations na testbenchample_dir>/ misaliample_testbench. cd /example_testbench
- Gudu quartus_tlg akan aikin da aka samar file: quartus_tlg cpriphy_ftile_hw
- Run ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
- Gudanar da rubutun kwaikwayo na na'urar kwaikwayo mai goyan bayan zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo. Koma zuwa teburin Matakai don Kwaikwayi Testbench.
- Yi nazarin sakamakon. Gwajin da ya yi nasara ya karɓi manyan firam biyar, kuma yana nuna “PASSED”.
Tebur 3. Matakai don Kwaikwaya Testbench a cikin Synopsys VCS* Na'urar kwaikwayo
| Na'urar kwaikwayo | Umarni | |
| VCS | A cikin layin umarni, rubuta: | |
| sh run_vcs.sh | ||
| ci gaba… | ||
| Na'urar kwaikwayo | Umarni | |
| Farashin VCS MX | A cikin layin umarni, rubuta: | |
| sh run_vcsmx.sh | ||
| ModelSim SE ko Questa ko Questa-Intel FPGA Edition | A cikin layin umarni, rubuta: | |
| vsim -do run_vsim.do | ||
| Idan kun fi son yin kwaikwayo ba tare da kawo GUI ba, rubuta: | ||
| vsim -c -do run_vsim.do | ||
Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation don 24.33024 Gbps tare da tashoshi 4 na CPRI:
Ƙirƙirar Aikin Tari-Kawai
Don haɗa tarin-kawai exampdon aikin, bi waɗannan matakan:
- Tabbatar da ƙirar ƙira example tsara ya cika.
- A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- A cikin menu na sarrafawa, danna Fara Tari.
- Bayan nasarar tattarawa, ana samun rahotannin lokaci da kuma amfani da albarkatu a cikin zaman ku na Intel Quartus Prime Pro Edition.
Bayanai masu alaƙa
Toshe-Tsarin Ƙirar Ƙira
Ƙirƙirar da Ƙaddamar da Zane Exampa cikin Hardware
Don haɗa kayan ƙirar kayan aiki example kuma saita shi akan na'urar Intel Agilex, bi waɗannan matakan:
- Tabbatar da ƙirar hardware example tsara ya cika.
- A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Gyara .qsf file don sanya fil bisa ga kayan aikin ku.
- A cikin menu na sarrafawa, danna Fara Tari.
- Bayan nasarar hadawa, a .sof file yana samuwa a cikiample_dir>/hardware_test_design/output_files directory.
Bi waɗannan matakan don tsara kayan ƙirar kayan aikin exampa kan na'urar Intel Agilex:
- Haɗa Intel Agilex I-jerin Kit ɗin Ci gaban Siginar Siginar Transceiver zuwa kwamfutar mai masaukin baki.
Lura: An riga an shirya kayan haɓakawa tare da daidaitattun mitocin agogo ta tsohuwa. Ba kwa buƙatar amfani da aikace-aikacen Ikon Agogo don saita mitoci. - A cikin Tools menu, danna Programmer.
- A cikin Programmer, danna Saitin Hardware.
- Zaɓi na'urar shirye-shirye.
- Tabbatar cewa an saita Yanayin zuwa JTAG.
- Zaɓi na'urar Intel Agilex kuma danna Ƙara Na'ura. Mai Shirya shirye-shirye yana nuna zanen toshewar haɗin kai tsakanin na'urorin da ke kan allo.
- A cikin jere tare da sof ɗinku, duba akwatin don .sof.
- Duba akwatin da ke cikin ginshiƙin Shirin/Sanya.
- Danna Fara.
Bayanai masu alaƙa
- Toshe-Tsarin Ƙirar Ƙira
- Shirye-shiryen na'urorin Intel FPGA
- Nazari da Gyara Zane-zane tare da Console System
Gwajin Tsarin Hardware Example
Bayan kun tattara F-Tile CPRI PHY Intel FPGA IP core design exampda kuma saita shi akan na'urar Intel Agilex, zaku iya amfani da System Console don tsara ainihin IP da PHY IP core rajista.
Don kunna System Console da gwada ƙirar kayan masarufi exampko, bi waɗannan matakan:
- Bayan hardware zane example an saita a kan na'urar Intel Agilex, a cikin Intel Quartus Prime Pro Edition software, akan menu na Kayan aiki, danna Kayan aikin Debugging System ➤ System Console.
- A cikin rukunin Tcl Console, rubuta cd hwtest don canza shugabanci zuwaample_dir>/hardware_test_design/hwtest_sl.
- Buga tushen main_script.tcl don buɗe haɗi zuwa JTAG master kuma fara gwajin.
Zane Example Bayanin
Zane example yana nuna ainihin aikin F-Tile CPRI PHY Intel FPGA IP core. Kuna iya samar da zane daga ExampLe Design shafin a cikin F-Tile CPRI PHY Intel FPGA IP editan siga.
Don samar da zane exampDon haka, dole ne ka fara saita ƙimar sigina don bambancin ainihin IP ɗin da kake son samarwa a ƙarshen samfurinka. Za ka iya zabar don samar da zane examptare da ko ba tare da fasalin RS-FEC ba. Ana samun fasalin RS-FEC tare da 10.1376, 12.1651 da 24.33024 Gbps CPRI bit bit bit line.
Tebur 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| Farashin Layin CPRI (Gbps) | Tallafin RS-FEC | Agogon Magana (MHz) | Taimakon Latency Ƙaddara |
| 1.2288 | A'a | 153.6 | Ee |
| 2.4576 | A'a | 153.6 | Ee |
| 3.072 | A'a | 153.6 | Ee |
| 4.9152 | A'a | 153.6 | Ee |
| 6.144 | A'a | 153.6 | Ee |
| 9.8304 | A'a | 153.6 | Ee |
| 10.1376 | Tare da Ba tare da | 184.32 | Ee |
| 12.1651 | Tare da Ba tare da | 184.32 | Ee |
| 24.33024 | Tare da Ba tare da | 184.32 | Ee |
Siffofin
- Ƙirƙirar ƙira examptare da fasalin RS-FEC
- Asalin ikon duba fakiti gami da ƙidayar latency na zagaye
Tsarin Simulators Example
F-Tile CPRI PHY Intel FPGA IP ƙirar misaliample yana haifar da simulation testbench da simulation files wanda ke hanzarta F-Tile CPRI PHY Intel FPGA IP core lokacin da kuka zaɓi zaɓin Simulation.
Hoto 6. Tsarin Toshe don 10.1316, 12.1651, da 24.33024 Gbps (tare da kuma ba tare da RS-FEC) Matsakaicin Layi ba
Hoto 7. Tsarin Toshe don 1.228, 2.4576, 3.072, 4.9152, 6.144, da 9.8304 Gbps Layin Layi
A cikin wannan zane example, simulation testbench yana ba da ayyuka na asali kamar farawa da jira kulle, watsawa da karɓar fakiti.
Gudun gwajin nasara yana nuna fitarwa mai tabbatar da halaye masu zuwa:
- Dabarar abokin ciniki tana sake saita ainihin IP.
- Hankalin abokin ciniki yana jiran daidaita hanyoyin bayanan RX.
- Dabarar abokin ciniki tana watsa hyperframes akan mahaɗin TX MII kuma yana jira don karɓar manyan firam biyar akan mu'amalar RX MII. Ana watsa manyan firam ɗin kuma ana karɓar su akan dubawar MII bisa ga ƙayyadaddun CPRI v7.0.
Lura: Ƙididdigar CPRI wanda ke nufin 1.2, 2.4, 3, 4.9, 6.1, da 9.8 Gbps layin layi suna amfani da 8b/10b dubawa da kuma zane-zanen da ke 10.1, 12.1 da 24.3 Gbps (tare da kuma ba tare da RS-FEC) suna amfani da MII interface. Wannan zane exampLe ya haɗa da lissafin tafiye-tafiye don ƙidaya jinkirin tafiya daga TX zuwa RX. - Mahimmancin abokin ciniki yana karanta ƙimar jinkirin tafiya zagaye kuma yana bincika abun ciki da daidaiton bayanan hyperframes a gefen RX MII da zarar ma'aunin ya kammala ƙidayar latency na zagaye.
Bayanai masu alaƙa
- Bayanan Bayani na CPRI
Tsarin Hardware Example
Hoto 8. Hardware Design Exampda Block zane
Lura
- Tsarin CPRI tare da ƙimar layin CPRI na 2.4/4.9/9.8 Gbps suna amfani da ƙirar 8b/10b kuma duk sauran ƙirar layin CPRI suna amfani da ƙirar MII.
- Tsarin CPRI tare da ƙimar layin CPRI na 2.4/4.9/9.8 Gbps yana buƙatar agogon nuni na 153.6 MHz kuma duk sauran ƙimar layin CPRI suna buƙatar 184.32 MHz.
F-Tile CPRI PHY Intel FPGA IP core ƙirar ƙirar kayan masarufiample ya ƙunshi abubuwa masu zuwa:
- F-Tile CPRI PHY Intel FPGA IP core.
- Fakitin dabaru na abokin ciniki wanda ke haifar da karɓar zirga-zirga.
- Gwajin tafiya zagaye.
- IOPLL don samar da sampagogon ling don ƙayyadaddun dabaru na latency a cikin IP, da ɓangaren juyi na tafiya a testbench.
- Tsarin PLL don samar da agogon tsarin don IP.
- Avalon®-MM mai gyara adireshin don ƙaddamar da sarari adireshin sake saitawa don CPRI, Transceiver, da na'urorin Ethernet yayin sake saita damar shiga.
- Tushen da bincike don tabbatar da sake saiti da sa ido kan agogo da ƴan matsayi.
- JTAG mai sarrafawa wanda ke sadarwa tare da Console System. Kuna sadarwa tare da dabaru na abokin ciniki ta System Console.
Siginonin Sadarwa
Tebur 5. Zane Exampda Alamar Interface
| Sigina | Hanyar | Bayani |
| ref_clk100MHz | Shigarwa | Agogon shigarwa don samun damar CSR akan duk mu'amalar sake saitawa. Tuba a 100 MHz. |
| i_clk_ref[0] | Shigarwa | Agogon magana don System PLL. Tuba a 156.25 MHz. |
| i_clk_ref[1] | Shigarwa | Agogon magana mai jujjuyawa. Tuba a
• 153.6 MHz don ƙimar layin CPRI 1.2, 2.4, 3, 4.9, 6.1, da 9.8 Gbps. • 184.32 MHz don ƙimar layin CPRI 10.1,12.1, da 24.3 Gbps tare da kuma ba tare da RS-FEC ba. |
| i_rx_serial[n] | Shigarwa | Serial bayanan shigar da Transceiver PHY. |
| o_tx_serial[n] | Fitowa | Serial bayanan fitarwa na Transceiver PHY. |
Zane Exampda Rajista
Tebur 6. Zane Exampda Rajista
| Lambar Channel | Adireshin Base (Adireshin Byte) | Nau'in Rijista |
|
0 |
0 x00000000 | CPRI PHY Reconfiguration yayi rajista don Channel 0 |
| 0 x00100000 | Ethernet Reconfiguration yayi rajista don Channel 0 | |
| 0 x00200000 | Transceiver Reconfiguration yayi rajista don Channel 0 | |
|
1(2) |
0 x01000000 | CPRI PHY Reconfiguration yayi rajista don Channel 1 |
| 0 x01100000 | Ethernet Reconfiguration yayi rajista don Channel 1 | |
| 0 x01200000 | Transceiver Reconfiguration yayi rajista don Channel 1 | |
|
2(2) |
0 x02000000 | CPRI PHY Reconfiguration yayi rajista don Channel 2 |
| 0 x02100000 | Ethernet Reconfiguration yayi rajista don Channel 2 | |
| 0 x02200000 | Transceiver Reconfiguration yayi rajista don Channel 2 | |
| ci gaba… | ||
| Lambar Channel | Adireshin Base (Adireshin Byte) | Nau'in Rijista |
|
3(2) |
0 x03000000 | CPRI PHY Reconfiguration yayi rajista don Channel 3 |
| 0 x03100000 | Ethernet Reconfiguration yayi rajista don Channel 3 | |
| 0 x03200000 | Transceiver Reconfiguration yayi rajista don Channel 3 |
Ana adana waɗannan rijistar idan ba a yi amfani da tashar ba.
F-Tile CPRI PHY Intel FPGA IP Design ExampRukunin Rubutun Jagorar Mai Amfani
Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.
| Intel Quartus Prime Version | IP Core Version | Jagorar Mai Amfani |
| 21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design ExampJagorar Mai Amfani |
Tarihin Bita na Takardu don F-Tile CPRI PHY Intel FPGA IP Design ExampJagorar Mai Amfani
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Sakin farko. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
Takardu / Albarkatu
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Jagorar mai amfani F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
