Intel F-Tile CPRI PHY FPGA IP Dhizaini Example

Quick Start Guide

Iyo F-Tile CPRI PHY Intel® FPGA IP musimboti inopa simulation testbench uye hardware dhizaini ex.ample iyo inotsigira kuunganidza uye kuyedza hardware. Paunogadzira iyo dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
Intel inopawo yekubatanidza-chete example purojekiti yaunogona kushandisa kukurumidza kufungidzira IP musimboti nzvimbo uye nguva.
Iyo F-Tile CPRI PHY Intel FPGA IP musimboti inopa kugona kwekugadzira dhizaini examples kune ese anotsigirwa musanganiswa wenhamba yeCPRI chiteshi uye CPRI mutsara bit rates. Iyo testbench uye dhizaini exampinotsigira akawanda parameter musanganiswa weF-Tile CPRI PHY Intel FPGA IP musimboti.

Mufananidzo 1. Matanho Ekuvandudza eKugadzira Example

Related Information

• F-Tile CPRI PHY Intel FPGA IP User Guide
  • Kuti uwane ruzivo rwakadzama paF-tile CPRI PHY IP.
• F-Tile CPRI PHY Intel FPGA IP Release Notes
  • Iyo IP Release Notes inonyora IP shanduko mune imwe kuburitswa.

Hardware uye Software Zvinodiwa

Kuedza example dhizaini, shandisa zvinotevera Hardware uye software:

• Intel Quartus® Prime Pro Edition software
• System console
• Inotsigirwa Simulators:
  • Synopsy* VCS*
  • Synopsys VCS MX
  • Siemens* EDA ModelSim* SE kana Questa*— Questa-Intel FPGA Edition

Kugadzira Dhizaini

Mufananidzo 2. Maitiro

Mufananidzo 3. Exampuye Dhizaina Tab muIP Parameter Mharidzo

Kugadzira Intel Quartus Prime Pro Edition chirongwa:

1. MuIntel Quartus Prime Pro Edition, tinya File ➤ New Project Wizard kugadzira itsva Quartus Prime project, kana File ➤ Vhura Project kuvhura iripo Intel Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo.
2. Taura mudziyo mhuri Agilex (I-series) uye sarudza mudziyo unosangana nezvose izvi zvinodiwa:
   • Transceiver tile ndeye F-tile
   • Transceiver speed giredhi ndeye -1 kana -2
   • Core kumhanya giredhi -1 kana -2 kana -3
3. Dzvanya Finish.

Tevedza nhanho idzi kugadzira iyo F-Tile CPRI PHY Intel FPGA IP hardware dhizaini example uye testbench:

1. Mune IP Catalog, tsvaga uye sarudza F-Tile CPRI PHY Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
2. Taura zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
3. Dzvanya OK. Iyo parameter editor inooneka.
4. PaI IP tab, tsanangura maparamita eiyo IP yako musimboti musiyano.
5. Pamusoro peExample Dhizaini tab, pasi peExample Dhizaini Files, sarudza Simulation sarudzo yekugadzira testbench uye yekubatanidza-chete purojekiti. Sarudza iyo Synthesis sarudzo yekugadzira iyo hardware dhizaini example. Iwe unofanirwa kusarudza inokwana imwe yeSimulation uye Synthesis sarudzo kuti ugadzire iyo dhizaini example.
6. Pamusoro peExample Dhizaini tebhu, pasi Yakagadzirwa HDL Format, sarudza Verilog HDL kana VHDL. Kana ukasarudza VHDL, unofanira kutevedzera testbench ine musanganiswa-mutauro simulator. Mudziyo urikuedzwa mune ex_ dhairekitori imhando yeVHDL, asi iyo huru testbench file iri System Verilog file.
7. Dzvanya iyo Gadzira Example Dhizaini bhatani. Sarudza Example Dhizaini Dhairekitori hwindo rinoonekwa.
8. Kana iwe uchida kugadzirisa iyo dhizaini example dhairekitori nzira kana zita kubva kune zvisizvo zvakaratidzwa (cpriphy_ftile_0_example_design), tsvaga kunzira nyowani uye nyora iyo nyowani dhizaini exampzita rezita (ample_dir>).

Directory Structure

Iyo F-Tile CPRI PHY Intel FPGA IP musimboti dhizaini example file madhairekitori ane zvinotevera kugadzirwa files yekugadzira example.

Mufananidzo 4. Dhairekitori Magadzirirwo eiyo Yakagadzirwa Example Dhizaini

Tafura 1. Testbench File Tsanangudzo

File Mazita	Tsanangudzo
Key Testbench uye Simulation Files
<design_example_dir>/ example_testbench/basic_avl_tb_top.sv	Top-level testbench file. Testbench inosimbisa iyo DUT wrapper uye inomhanyisa Verilog HDL mabasa kugadzira uye kugamuchira mapaketi.
<design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv	DUT wrapper inosimbisa DUT uye zvimwe zvinhu zvetestbench.
Testbench Scripts(1)
<design_example_dir>/ example_testbench/run_vsim.do	Iyo Siemens EDA ModelSim SE kana Questa kana Questa-Intel FPGA Edition script yekumhanyisa testbench.
<design_example_dir>/ example_testbench/run_vcs.sh	Iyo Synopsys VCS script yekumhanyisa testbench.
<design_example_dir>/ example_testbench/run_vcsmx.sh	Iyo Synopsys VCS MX script (yakasanganiswa Verilog HDL uye SystemVerilog ine VHDL) kumhanyisa testbench.

Rega chero imwe simulator script muample_dir>/example_testbench/ folda.

Tafura 2. Hardware Design Example File Tsanangudzo

File Mazita	Tsanangudzo
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf	Intel Quartus Prime chirongwa file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf	Intel Quartus Prime chirongwa chekugadzirisa file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc	Synopsys Design Constraints files. Unogona kukopa uye kugadzirisa izvi files yeIntel Agilex™ dhizaini yako.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v	Yepamusoro-chikamu Verilog HDL dhizaini example file.
<design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv	DUT wrapper inosimbisa DUT uye zvimwe zvinhu zvetestbench.
<design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl	Main file yekuwana System Console.

Kutevedzera Dhizaini Example Testbench

Mufananidzo 5. Maitiro

Tevera matanho aya kutevedzera testbench:

1. Pakuraira kwekuraira, shandura kune testbench simulation dhairekitoriample_dir>/example_testbench. cd /example_testbench
2. Mhanya quartus_tlg pane yakagadzirwa purojekiti file: quartus_tlg cpriphy_ftile_hw
3. Mhanya ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
4. Mhanya iyo simulation script yeiyo inotsigirwa simulator yesarudzo yako. Iyo script inounganidza uye inomhanyisa testbench mune simulator. Tarisa kune tafura Matanho ekutevedzera Testbench.
5. Ongorora zvabuda. Iyo testbench yakabudirira yakagamuchira hyperframes mashanu, uye inoratidza "PASSED".

Tafura 3. Matanho ekutevedzera Testbench muSynopsy VCS* Simulator

Simulator	Mirayiridzo
VCS	Mumutsara wekuraira, nyora:
	sh run_vcs.sh
akaenderera…

Simulator	Mirayiridzo
VCS MX	Mumutsara wekuraira, nyora:
	sh run_vcsmx.sh
ModelSim SE kana Questa kana Questa-Intel FPGA Edition	Mumutsara wekuraira, nyora:
	vsim -do run_vsim.do
	Kana iwe uchida kutevedzera pasina kuunza iyo GUI, nyora:
	vsim -c -do run_vsim.do

Inotevera sample output inoratidza yakabudirira simulation test run ye24.33024 Gbps ine 4 CPRI chiteshi:

Kugadzira iyo Compilation-Chete Project

Kuunganidza iyo yekuunganidza-chete example project, tevera matanho aya:

1. Iva nechokwadi chekubatanidza dhizaini example generation yapera.
2. MuIntel Quartus Prime Pro Edition software, vhura iyo Intel Quartus Prime Pro Edition chirongwaample_dir>/compilation_test_design/cpriphy_ftile.qpf.
3. Pane iyo Processing menyu, tinya Start Compilation.
4. Mushure mekubudirira kuunganidza, mishumo yenguva uye yekushandisa zviwanikwa inowanikwa mune yako Intel Quartus Prime Pro Edition chikamu.

Related Information
Block-Yakavakirwa Dhizaini Inoyerera

Kunyora uye Kugadzirisa Dhizaini Example mu Hardware

Kuunganidza iyo hardware dhizaini example uye gadzirisa pane yako Intel Agilex mudziyo, tevera matanho aya:

1. Ita shuwa kuti hardware dhizaini example generation yapera.
2. MuIntel Quartus Prime Pro Edition software, vhura iyo Intel Quartus Prime purojekitiample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
3. Edit the .qsf file kugovera mapini zvichienderana nehardware yako.
4. Pane iyo Processing menyu, tinya Start Compilation.
5. Mushure mekubudirira kuunganidza, a .sof file inowanikwa muample_dir>/hardware_test_design/output_files directory.

Tevedza matanho aya kuronga hardware dhizaini examppane iyo Intel Agilex mudziyo:

• Batanidza Intel Agilex I-series Transceiver Signal Integrity Development Kit kune komputa inotambira.
  Ongorora: Iyo kit yekuvandudza inofanorongwa neiyo chaiyo wachi ma frequency nekusarudzika. Iwe haufanire kushandisa iyo Clock Control application kuseta ma frequency.
• PaZvishandiso menyu, tinya Programmer.
• MuPurogiramu, tinya Hardware Setup.
• Sarudza chigadzirwa chepurogiramu.
• Ita shuwa kuti Mode yakaiswa kuna JTAG.
• Sarudza iyo Intel Agilex mudziyo uye tinya Wedzera Chishandiso. Iyo Programmer inoratidza dhizaini yebhuroka yekubatana pakati pemidziyo iri pabhodhi rako.
• Mumutsara ne .sof yako, tarisa bhokisi re .sof.
• Tarisa bhokisi riri muPurogiramu/Gadzirisa column.
• Click Start.

Related Information

• Block-Yakavakirwa Dhizaini Inoyerera
• Kuronga Intel FPGA Zvishandiso
• Kuongorora uye Kugadzirisa Dhizaini neSystem Console

Kuedza iyo Hardware Dhizaini Example

Mushure mekunyora iyo F-Tile CPRI PHY Intel FPGA IP musimboti dhizaini example uye gadzirisa pane yako Intel Agilex mudziyo, unogona kushandisa iyo System Console kuronga iyo IP musimboti uye yayo PHY IP musimboti marejista.
Kuvhura iyo System Console uye kuyedza iyo hardware dhizaini example, tevera matanho aya:

1. Mushure meiyo hardware dhizaini exampiyo inogadziriswa paIntel Agilex mudziyo, muIntel Quartus Prime Pro Edition software, pane Zvishandiso menyu, tinya System Debugging Zvishandiso ➤ System Console.
2. MuTcl Console pane, nyora cd hwtest kuti uchinje dhairekitori kutiample_dir>/hardware_test_design/hwtest_sl.
3. Nyora kunobva main_script.tcl kuvhura chinongedzo kuJTAG tenzi uye tanga bvunzo.

Design Example Description

Iyo yakagadzirwa example inoratidza basa rekutanga reF-Tile CPRI PHY Intel FPGA IP musimboti. Iwe unogona kugadzira dhizaini kubva kuExample Dhizaini tebhu muF-Tile CPRI PHY Intel FPGA IP parameter mupepeti.
Kugadzira iyo dhizaini exampuye, iwe unofanirwa kutanga waisa iyo parameter kukosha kweiyo IP musimboti mutsauko waunoda kugadzira mune yako yekupedzisira chigadzirwa. Iwe unogona kusarudza kugadzira iyo dhizaini example ine kana isina iyo RS-FEC chimiro. Iyo RS-FEC chimiro inowanikwa ne10.1376, 12.1651 uye 24.33024 Gbps CPRI mutsetse bit rates.
Tafura 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix

CPRI Line Bit Rate (Gbps)	RS-FEC Tsigiro	Reference Clock (MHz)	Deterministic Latency Support
1.2288	Aihwa	153.6	Ehe
2.4576	Aihwa	153.6	Ehe
3.072	Aihwa	153.6	Ehe
4.9152	Aihwa	153.6	Ehe
6.144	Aihwa	153.6	Ehe
9.8304	Aihwa	153.6	Ehe
10.1376	With uye Pasina	184.32	Ehe
12.1651	With uye Pasina	184.32	Ehe
24.33024	With uye Pasina	184.32	Ehe

Features

• Gadzira iyo dhizaini example ine RS-FEC chimiro
• Basic packet yekutarisa masimba kusanganisira kutenderera rwendo latency kuverenga

Simulation Dhizaini Example

Iyo F-Tile CPRI PHY Intel FPGA IP dhizaini example inogadzira simulation testbench uye simulation files iyo inosimbisa iyo F-Tile CPRI PHY Intel FPGA IP musimboti paunosarudza iyo Simulation sarudzo.

Mufananidzo 6. Block Diagram ye10.1316, 12.1651, uye 24.33024 Gbps (ine uye isina RS-FEC) Line Rates

Mufananidzo 7. Block Diagram ye1.228, 2.4576, 3.072, 4.9152, 6.144, uye 9.8304 Gbps Line Rate

Muchirongwa ichi example, iyo simulation testbench inopa basa rekutanga sekutanga uye kumirira kukiya, kutumira uye kugamuchira mapaketi.
Iyo yakabudirira bvunzo run inoratidza inobuda inosimbisa inotevera maitiro:

1. Iyo mutengi logic inogadzirisa iyo IP musimboti.
2. Iyo mutengi logic inomirira iyo RX datapath alignment.
3. Iyo mutengi mantiki inofambisa hyperframes paTX MII interface uye inomirira kuti ma hyperframes mashanu agamuchirwe paRX MII interface. Hyperframes inofambiswa uye inogamuchirwa paMII interface zvinoenderana neCPRI v7.0 yakatarwa.
   Cherechedza: Iyo CPRI inogadzira iyo inotarisa 1.2, 2.4, 3, 4.9, 6.1, uye 9.8 Gbps mutsara mutsara inoshandisa 8b / 10b interface uye magadzirirwo anotarisa 10.1, 12.1 uye 24.3 Gbps (ine uye pasina RS-FEC) inoshandisa MII interface. Iyi dhizaini example inosanganisira kaunda yekufamba nekudzoka kuverenga rwendo rwekudzoka latency kubva kuTX kuenda kuRX.
4. Iyo mutengi mantiki inoverenga rwendo rwekutenderera latency kukosha uye inotarisa zvemukati uye kurongeka kweiyo hyperframes data paRX MII kudivi kana kaunda yapedza rwendo rwekudzoka latency kuverenga.

Related Information

• CPRI Specifications

Hardware Dhizaini Example

Mufananidzo 8. Hardware Design Exampuye Block Diagram

 

Cherechedza

1. Iyo CPRI inogadzira ne 2.4 / 4.9 / 9.8 Gbps CPRI mitsara mitsara inoshandisa 8b / 10b interface uye mamwe ese CPRI mitsara mitsetse magadzirirwo anoshandisa MII interface.
2. Iyo CPRI inogadzira ine 2.4 / 4.9 / 9.8 Gbps CPRI mitsara mitsetse inoda 153.6 MHz transceiver referensi wachi uye mamwe ese CPRI mutsetse mazinga anoda 184.32 MHz.

Iyo F-Tile CPRI PHY Intel FPGA IP yakakosha hardware dhizaini example inosanganisira zvinotevera zvikamu:

• F-Tile CPRI PHY Intel FPGA IP musimboti.
• Packet client logic block iyo inogadzira uye inogamuchira traffic.
• Round trip counter.
• IOPLL kugadzira sampling wachi ye deterministic latency logic mukati meIP, uye rwendo rwekutenderera counter chikamu patestbench.
• System PLL kugadzira mawachi ehurongwa eIP.
• Avalon®-MM kero decoder kuti idecode reconfiguration kero nzvimbo yeCPRI, Transceiver, uye Ethernet modules panguva yekudzokorora kuwana.
• Zvitubu uye probes yekusimbisa reset uye yekutarisa wachi uye mashoma mamiriro mabheti.
• JTAG controller inotaurirana neSystem Console. Iwe unotaurirana nemutengi logic kuburikidza neSystem Console.

Interface Signals

Tafura 5. Dhizaini Example Interface Signals

Signal	Direction	Tsanangudzo
ref_clk100MHz	Input	Input wachi yekuwana CSR pane ese ekugadzirisa maficha. Dhiraivha pa100 MHz.
i_clk_ref[0]	Input	Reference wachi yeSystem PLL. Dhiraivha pa156.25 MHz.
i_clk_ref[1]	Input	Transceiver reference wachi. Dhiraivha pa • 153.6 MHz yeCPRI mutsetse chiyero 1.2, 2.4, 3, 4.9, 6.1, uye 9.8 Gbps. • 184.32 MHz yeCPRI mutsetse mazinga 10.1,12.1, uye 24.3 Gbps ine uye isina RS-FEC.
i_rx_serial[n]	Input	Transceiver PHY inopinza serial data.
o_tx_serial[n]	Output	Transceiver PHY yakabuda serial data.

Design Example Registers

Tafura 6. Dhizaini Example Registers

Channel Number	Kero yekutanga (Byte Kero)	Register Type
0	0x00000000	CPRI PHY Reconfiguration marejista eChannel 0
	0x00100000	Ethernet Reconfiguration marejista eChannel 0
	0x00200000	Transceiver Reconfiguration marejista eChannel 0
1(2)	0x01000000	CPRI PHY Reconfiguration marejista eChannel 1
	0x01100000	Ethernet Reconfiguration marejista eChannel 1
	0x01200000	Transceiver Reconfiguration marejista eChannel 1
2(2)	0x02000000	CPRI PHY Reconfiguration marejista eChannel 2
	0x02100000	Ethernet Reconfiguration marejista eChannel 2
	0x02200000	Transceiver Reconfiguration marejista eChannel 2
akaenderera…

Channel Number	Kero yekutanga (Byte Kero)	Register Type
3(2)	0x03000000	CPRI PHY Reconfiguration marejista eChannel 3
	0x03100000	Ethernet Reconfiguration marejista eChannel 3
	0x03200000	Transceiver Reconfiguration marejista eChannel 3

Aya marejista anochengetwa kana chiteshi chisina kushandiswa.

F-Tile CPRI PHY Intel FPGA IP Dhizaini Example User Guide Archives

Kana IP core vhezheni isina kunyorwa, gwara remushandisi rekare IP core version rinoshanda.

Intel Quartus Prime Version	IP Core Version	User Guide
21.2	2.0.0	F-Tile CPRI PHY Intel FPGA IP Dhizaini Example User Guide

Gwaro Rekudzokorora Nhoroondo yeF-Tile CPRI PHY Intel FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2021.10.04	21.3	3.0.0	Yakawedzera rutsigiro rwema simulators matsva muchikamu: Hardware uye Software Zvinodiwa. Matanho akagadziridzwa muchikamu: Kutevedzera Dhizaini Example Testbench. Yakagadziridza zvikamu zvinotevera neruzivo rutsva rwechiyero chemutsara: Design Example Description Simulation Dhizaini Example Interface Signals Yakagadziridza kero muchikamu: Design Example Registers.
2021.06.21	21.2	2.0.0	Kusunungurwa kwekutanga.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Zvinyorwa / Zvishandiso

Intel F-Tile CPRI PHY FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi F-Tile CPRI PHY FPGA IP Dhizaini Example, PHY FPGA IP Dhizaini Example, F-Tile CPRI IP Dhizaini Example, IP Dhizaini Example, IP Dhizaini

References

• User Manual