intel F-Tile CPRI PHY FPGA IP Design Example
Quick Start Guide
I-F-Tile CPRI PHY Intel® FPGA IP core inikeza ibhentshi lokuhlola lokulingisa kanye ne-ex ye-hardware designample esekela ukuhlanganiswa nokuhlolwa kwehadiwe. Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.
I-Intel iphinde inikeze i-ex yokuhlanganisa kuphelaample phrojekthi ongayisebenzisa ukuze ulinganisele ngokushesha indawo eyinhloko ye-IP nesikhathi.
I-F-Tile CPRI PHY Intel FPGA IP core inikeza amandla okukhiqiza i-design exampi-les yazo zonke izinhlanganisela ezisekelwayo zenani lamashaneli e-CPRI kanye nezilinganiso zebhithi zomugqa we-CPRI. I-testbench kanye ne-design exampisekela izinhlanganisela eziningi zepharamitha ye-F-Tile CPRI PHY Intel FPGA IP core.
Umfanekiso 1. Izinyathelo Zokuthuthukisa Zomklamo Example
Ulwazi Oluhlobene
- F-Tile CPRI PHY Intel FPGA IP Umhlahlandlela Womsebenzisi
- Ukuze uthole ulwazi oluningiliziwe nge-F-tile CPRI PHY IP.
- I-F-Tile CPRI PHY Intel FPGA IP Amanothi okukhishwa
- Uhlu lwamanothi okukhishwa kwe-IP lushintsha ekukhishweni okuthile.
Izingxenyekazi zekhompuyutha nezidingo zeSoftware
Ukuhlola i-example design, sebenzisa ihadiwe nesoftware elandelayo:
- Isoftware ye-Intel Quartus® Prime Pro Edition
- Ikhonsoli yesistimu
- Izilingisi ezisekelwayo:
- Ama-synopsy* VCS*
- I-synopsy ye-VCS MX
- Siemens* EDA ModelSim* SE noma Questa*— Questa-Intel FPGA Edition
Ikhiqiza Umklamo
Umfanekiso 2. Inqubo
Umfanekiso 3. Isbampne-Design Tab ku-IP Parameter Editor
Ukwakha iphrojekthi ye-Intel Quartus Prime Pro Edition:
- Ku-Intel Quartus Prime Pro Edition, chofoza File ➤ Iseluleki Sephrojekthi Esisha sokudala iphrojekthi entsha ye-Quartus Prime, noma File ➤ Vula Iphrojekthi ukuze uvule iphrojekthi ekhona ye-Intel Quartus Prime. Iwizadi ikutshela ukuthi ucacise idivayisi.
- Cacisa i-Agilex yomndeni wedivayisi (I-series) bese ukhetha idivayisi ehlangabezana nazo zonke lezi zidingo:
- Ithayela le-Transceiver lingu-F-tile
- Ibanga lejubane le-Transceiver ngu-1 noma -2
- Ibanga lesivinini esiyinhloko ngu-1 noma -2 noma -3
- Chofoza okuthi Qeda.
Landela lezi zinyathelo ukuze ukhiqize i-F-Tile CPRI PHY Intel FPGA IP hardware design example kanye ne-testbench:
- Kukhathalogi ye-IP, thola bese ukhetha i-F-Tile CPRI PHY Intel FPGA IP. Iwindi le-New IP Variation liyavela.
- Cacisa igama lezinga eliphezulu ngokuhlukahluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
- Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
- Kuthebhu ye-IP, cacisa imingcele yokuhluka kwakho okubalulekile kwe-IP.
- Ku-Example Dizayini ithebhu, ngaphansi kwe-Example Design Files, khetha inketho yokulingisa ukuze ukhiqize ibhentshi lokuhlola kanye nephrojekthi yokuhlanganisa kuphela. Khetha inketho ye-Synthesis ukuze ukhiqize i-ex ye-hardware designample. Kufanele ukhethe okungenani eyodwa yezinketho Zokulingisa kanye Nokuhlanganiswa ukuze ukhiqize i-ex yedizayiniample.
- Ku-Example Design ithebhu, ngaphansi kwefomethi ye-HDL Ekhiqiziwe, khetha i-Verilog HDL noma i-VHDL. Uma ukhetha i-VHDL, kufanele ulingise ibhentshi lokuhlola ngesilingisi solimi oluxubile. Idivayisi ingaphansi kokuhlolwa ku-ex_ uhla lwemibhalo luyimodeli ye-VHDL, kodwa ibhentshi eliyinhloko lokuhlola file I-Verilog yesistimu file.
- Chofoza okuthi Khiqiza i-Exampinkinobho ethi Design. Khetha ExampIwindi le-Design Directory liyavela.
- Uma ufuna ukushintsha i-design exampindlela yohla lwemibhalo noma igama elisuka kokumisiwe okubonisiwe (cpriphy_ftile_0_example_design), phequlula endleleni entsha bese uthayipha umklamo omusha exampigama lenkomba (ample_dir>).
Ukwakheka Kwemibhalo
I-F-Tile CPRI PHY Intel FPGA IP core design example file uhla lwemibhalo luqukethe okulandelayo okwenziwe files ye-design example.
Umfanekiso 4. Ukwakheka Kwemibhalo Ye-Ex Ekhiqiziweample Design
Ithebula 1. Testbench File Izincazelo
| File Amagama | Incazelo |
| I-Testbench Eyisihluthulelo Nokulingisa Files | |
| <design_example_dir>/isbample_testbench/basic_avl_tb_top.sv | I-testbench yezinga eliphezulu file. I-testbench iqinisekisa ukusonga kwe-DUT futhi iqhuba imisebenzi ye-Verilog HDL ukuze ikhiqize futhi yamukele amaphakethe. |
| <design_example_dir>/isbample_testbench/ cpriphy_ftile_wrapper.sv | I-DUT wrapper eqinisekisa i-DUT nezinye izingxenye ze-testbench. |
| Izikripthi ze-Testbench(1) | |
| <design_example_dir>/isbample_testbench/run_vsim.do | Iskripthi se-Siemens EDA ModelSim SE noma i-Questa noma i-Questa-Intel FPGA Edition ukuze kusetshenziswe ibhentshi le-test. |
| <design_example_dir>/isbample_testbench/run_vcs.sh | Iskripthi se-Synopsy VCS sokuqalisa ibhentshi lokuhlola. |
| <design_example_dir>/isbample_testbench/run_vcsmx.sh | Iskripthi se-Synopsys VCS MX (kuhlanganiswe i-Verilog HDL ne-SystemVerilog ne-VHDL) ukuze kuqalise ibhentshi lokuhlola. |
Ziba noma isiphi esinye iskripthi sesifanisi kuample_dir>/example_testbench/ ifolda.
Ithebula 2. I-Hardware Design Example File Izincazelo
| File Amagama | Izincazelo |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Iphrojekthi ye-Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Ukulungiselelwa kwephrojekthi ye-Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | I-Synopsys Design Constrants files. Ungakopisha futhi ulungise lezi files yedizayini yakho ye-Intel Agilex™. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Idizayini yezinga eliphezulu ye-Verilog HDL example file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | I-DUT wrapper eqinisekisa i-DUT nezinye izingxenye ze-testbench. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Okuyinhloko file ukuze ufinyelele Ikhonsoli Yesistimu. |
Ukulingisa i-Design Example Testbench
Umfanekiso 5. Inqubo
Landela lezi zinyathelo ukuze ulingise i-testbench:
- Emyalweni womyalo, shintshela kumkhombandlela wokulingisa we-testbenchample_dir>/example_testbench. cd /isibample_testbench
- Qalisa i-quartus_tlg kuphrojekthi ekhiqiziwe file: quartus_tlg cpriphy_ftile_hw
- Qalisa i-ip-setup-simulation: ip-setup-simulation -output-directory=./sim_script -use-relative-paths -quartus project=cpriphy_ftile_hw.qpf
- Qalisa iskripthi sokulingisa sesifanisi esisekelwayo ozikhethele sona. Umbhalo uhlanganisa futhi uqhube ibhentshi lokuhlola kusifanisi. Bheka ithebula elithi Izinyathelo Zokulingisa Ibhentshi Lokuhlola.
- Hlaziya imiphumela. Ibhentshi lokuhlola eliphumelele lithole ama-hyperframe amahlanu, kanye nezibonisi ezithi “PASSED”.
Ithebula 3. Izinyathelo Zokulingisa Ibhentshi Lokuhlola Ku-Synopsy VCS* Isilingisi
| Isifanisi | Iziyalezo | |
| I-VCS | Emugqeni womyalo, thayipha: | |
| sh run_vcs.sh | ||
| waqhubeka... | ||
| Isifanisi | Iziyalezo | |
| I-VCS MX | Emugqeni womyalo, thayipha: | |
| sh run_vcsmx.sh | ||
| I-ModelSim SE noma i-Questa noma i-Questa-Intel FPGA Edition | Emugqeni womyalo, thayipha: | |
| vsim -do run_vsim.do | ||
| Uma ukhetha ukulingisa ngaphandle kokuveza i-GUI, thayipha: | ||
| vsim -c -do run_vsim.do | ||
Okulandelayo sampokukhiphayo kubonisa ukuqaliswa kokuhlolwa kokulingisa okuyimpumelelo kwe-24.33024 Gbps eneziteshi ezi-4 ze-CPRI:
Ukuhlanganisa Iphrojekthi Yokuhlanganiswa Kuphela
Ukuhlanganisa isib sokuhlanganiswa kuphelaample phrojekthi, landela lezi zinyathelo:
- Qinisekisa ukuhlanganisa idizayini exampisizukulwane sesiphelile.
- Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.
- Ngemva kokuhlanganiswa ngempumelelo, imibiko yokubeka isikhathi kanye nokusetshenziswa kwensiza iyatholakala kuseshini yakho ye-Intel Quartus Prime Pro Edition.
Ulwazi Oluhlobene
Ukugeleza Kwedizayini Okusekelwe Ebhulokhini
Ukuhlanganisa kanye nokulungiselela i-Design Exampku-Hardware
Ukuhlanganisa i-hardware design example futhi uyilungiselele kudivayisi yakho ye-Intel Agilex, landela lezi zinyathelo:
- Qinisekisa ukuthi i-hardware design exampisizukulwane sesiphelile.
- Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Hlela i-.qsf file ukwabela izikhonkwane ngokusekelwe kuhadiwe yakho.
- Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.
- Ngemva kokuhlanganiswa ngempumelelo, i-.sof file iyatholakala kuample_dir>/hardware_test_design/output_files lwemibhalo.
Landela lezi zinyathelo ukuze uhlele i-hardware design example kudivayisi ye-Intel Agilex:
- Xhuma i-Intel Agilex I-series Transceiver Signal Integrity Development Kit kukhompuyutha engusokhaya.
Qaphela: Ikhithi yokuthuthukisa ihlelwe ngaphambilini namafrikhwensi ewashi alungile ngokuzenzakalela. Awudingi ukusebenzisa uhlelo Lokulawula Iwashi ukuze usethe amaza. - Kumenyu yamathuluzi, chofoza uMhleli.
- Ku-Programmer, chofoza Ukusethwa Kwezingxenyekazi zekhompuyutha.
- Khetha idivayisi yokuhlela.
- Qinisekisa ukuthi Imodi isethwe ku-JTAG.
- Khetha idivayisi ye-Intel Agilex bese uchofoza Engeza idivayisi. I-Programmer ibonisa idayagramu yebhlokhi yokuxhumana phakathi kwamadivayisi ebhodini lakho.
- Emgqeni ne-.sof yakho, hlola ibhokisi le-.sof.
- Thikha ibhokisi kokuthi Uhlelo/Lungisa ikholomu.
- Chofoza Qala.
Ulwazi Oluhlobene
- Ukugeleza Kwedizayini Okusekelwe Ebhulokhini
- Izinhlelo ze-Intel FPGA Amadivayisi
- Ukuhlaziya nokulungisa amadizayini nge-System Console
Ihlola i-Hardware Design Example
Ngemva kokuhlanganisa i-F-Tile CPRI PHY Intel FPGA IP core design example futhi uyilungiselele kudivayisi yakho ye-Intel Agilex, ungasebenzisa Ikhonsoli Yesistimu ukuze uhlele umongo we-IP kanye namarejista awo ayinhloko we-PHY IP.
Ukuze uvule ikhonsoli Yesistimu futhi uhlole idizayini yezingxenyekazi zekhompuyutha example, landela lezi zinyathelo:
- Ngemva kwe-hardware design example ilungiselelwe kudivayisi ye-Intel Agilex, kusofthiwe ye-Intel Quartus Prime Pro Edition, kumenyu yamathuluzi, chofoza Amathuluzi Okulungisa Amaphutha Esistimu ➤ Ikhonsoli Yesistimu.
- Kufasitelana le-Tcl Console, thayipha i-cd hwtest ozoshintshela kuyo uhla lwemibhaloample_dir>/hardware_test_design/hwtest_sl.
- Thayipha umthombo main_script.tcl ukuze uvule uxhumano ku-JTAG master futhi uqale isivivinyo.
I-Design Example Incazelo
Umklamo exampI-le ibonisa ukusebenza okuyisisekelo kwe-F-Tile CPRI PHY Intel FPGA IP core. Ungakwazi ukukhiqiza umklamo kusukela Example Design ithebhu kusihleli sepharamitha ye-F-Tile CPRI PHY Intel FPGA IP.
Ukukhiqiza i-design exampNokho, kufanele uqale usethe amanani epharamitha okuhluka okuyinhloko kwe-IP ohlose ukukukhiqiza kumkhiqizo wakho wokugcina. Ungakhetha ukukhiqiza i-ex designample noma ngaphandle kwesici se-RS-FEC. Isici se-RS-FEC siyatholakala ngezilinganiso zebhithi zomugqa we-10.1376, 12.1651 no-24.33024 Gbps CPRI.
Ithebula 4. I-F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| I-CPRI Line Bit Rate (Gbps) | Ukusekelwa kwe-RS-FEC | Iwashi Lereferensi (MHz) | Ukusekela Ukubambezeleka Okunqunyiwe |
| 1.2288 | Cha | 153.6 | Yebo |
| 2.4576 | Cha | 153.6 | Yebo |
| 3.072 | Cha | 153.6 | Yebo |
| 4.9152 | Cha | 153.6 | Yebo |
| 6.144 | Cha | 153.6 | Yebo |
| 9.8304 | Cha | 153.6 | Yebo |
| 10.1376 | Ngaphakathi Nangaphandle | 184.32 | Yebo |
| 12.1651 | Ngaphakathi Nangaphandle | 184.32 | Yebo |
| 24.33024 | Ngaphakathi Nangaphandle | 184.32 | Yebo |
Izici
- Khiqiza i-ex designample ngesici se-RS-FEC
- Amakhono ayisisekelo okuhlola iphakethe okuhlanganisa ukubala ukubambezeleka kohambo lokuya nokubuya
Idizayini yokulingisa Isibample
I-F-Tile CPRI PHY Intel FPGA IP design exampi-le ikhiqiza ibhentshi lokulinganisa lokulingisa nokulingisa files eqinisa i-F-Tile CPRI PHY Intel FPGA IP core lapho ukhetha inketho yokulingisa.
Umfanekiso 6. Umdwebo Webhulokhi we-10.1316, 12.1651, kanye ne-24.33024 Gbps (ene-RS-FEC nangaphandle) Amanani Womugqa
Umfanekiso 7. Block Diagram ka-1.228, 2.4576, 3.072, 4.9152, 6.144, kanye ne-9.8304 Gbps Line Rate
Kulo mklamo exampfuthi, ibhentshi lesivivinyo sokulingisa linikeza ukusebenza okuyisisekelo njengokuqalisa nokulinda ukukhiya, ukudlulisa nokwamukela amaphakethe.
Ukuhlolwa okuphumelelayo kukhombisa okukhiphayo okuqinisekisa ukuziphatha okulandelayo:
- I-logic yeklayenti imisa kabusha i-IP core.
- I-logic yeklayenti ilinda ukuqondanisa kwe-datapath ye-RX.
- I-logic yeklayenti ithumela ama-hyperframe kusixhumi esibonakalayo se-TX MII futhi ilinde ama-hyperframe amahlanu ukuthi amukelwe kusixhumi esibonakalayo se-RX MII. Ama-Hyperframe athunyelwa futhi atholwa kusixhumi esibonakalayo se-MII ngokuya ngemininingwane ye-CPRI v7.0.
Qaphela: I-CPRI idizayina eqondise u-1.2, 2.4, 3, 4.9, 6.1, kanye no-9.8 Gbps wesilinganiso somugqa isebenzisa isixhumi esibonakalayo esingu-8b/10b namadizayini aqondise u-10.1, 12.1 no-24.3 Gbps (nge-RS-FEC nangaphandle kwayo) asebenzisa isixhumi esibonakalayo se-MII. Lo mklamo exampI-le ihlanganisa ikhawunta yohambo oluya nokubuya ukubala ukubambezeleka kohambo olubuyayo ukusuka e-TX ukuya e-RX. - Ingqondo yeklayenti ifunda ivelu yokubambezeleka kohambo lokuya nokubuya futhi ihlole okuqukethwe nokunemba kwedatha yama-hyperframe ohlangothini lwe-RX MII uma ikhawunta isiqedile ukubala ukubambezeleka kohambo olubuyayo.
Ulwazi Oluhlobene
- Imininingwane ye-CPRI
I-Hardware Design Example
Umfanekiso 8. I-Hardware Design Example Block Diagram
Qaphela
- I-CPRI idizayina ngezilinganiso zolayini ezingu-2.4/4.9/9.8 Gbps CPRI zisebenzisa isixhumi esibonakalayo esingu-8b/10b futhi yonke eminye imiklamo yezilinganiso zomugqa we-CPRI isebenzisa isixhumi esibonakalayo se-MII.
- Amadizayini e-CPRI anezilinganiso zolayini we-2.4/4.9/9.8 Gbps CPRI adinga iwashi lereferensi ye-transceiver engu-153.6 MHz futhi zonke ezinye izilinganiso zomugqa we-CPRI zidinga u-184.32 MHz.
I-F-Tile CPRI PHY Intel FPGA IP core design hardware example ihlanganisa izingxenye ezilandelayo:
- I-F-Tile CPRI PHY Intel FPGA IP core.
- I-Packet client logic block ekhiqiza futhi yamukele ithrafikhi.
- Ikhawunta yohambo olujikelezayo.
- I-IOPLL ukukhiqiza i-sampIwashi lewashi le-deterministic latency logic ngaphakathi kwe-IP, kanye nengxenye yokubala yohambo olubuyayo ku-testbench.
- Isistimu ye-PLL yokukhiqiza amawashi esistimu e-IP.
- Idekhoda yekheli ye-Avalon®-MM ukuze kuqondwe isikhala sekheli sokumisa kabusha samamojula e-CPRI, Transceiver, ne-Ethernet phakathi nokufinyelela kokulungisa kabusha.
- Imithombo nama-probe okuqinisekisa ukusetha kabusha nokuqapha amawashi nezingcezu ezimbalwa zezimo.
- JTAG isilawuli esixhumana Nekhonsoli Yesistimu. Uxhumana ne-logic yeklayenti nge-System Console.
Izimpawu Zokuxhumana
Ithebula 5. Idizayini Example Interface Signals
| Isiginali | Isiqondiso | Incazelo |
| ref_clk100MHz | Okokufaka | Iwashi lokokufaka lokufinyelela kwe-CSR kuzo zonke izixhumi ezibonakalayo zokulungisa kabusha. Shayela ngo-100 MHz. |
| i_clk_ref[0] | Okokufaka | Iwashi eliyisethenjwa le-System PLL. Shayela ku-156.25 MHz. |
| i_clk_ref[1] | Okokufaka | Iwashi lereferensi ye-Transceiver. Shayela ku
• 153.6 MHz ngesilinganiso somugqa we-CPRI 1.2, 2.4, 3, 4.9, 6.1, kanye no-9.8 Gbps. • 184.32 MHz kuzilinganiso zomugqa we-CPRI 10.1,12.1, kanye no-24.3 Gbps nge-RS-FEC nangaphandle kwayo. |
| i_rx_serial[n] | Okokufaka | I-Transceiver PHY idatha yesiriyeli yokufaka. |
| o_tx_serial[n] | Okukhiphayo | I-Transceiver PHY yomkhiqizo wedatha ye-serial. |
I-Design Example Registers
Ithebula 6. Idizayini Example Registers
| Inombolo yesiteshi | Ikheli Lesisekelo (Ikheli Le-Byte) | Uhlobo lokubhalisa |
|
0 |
0x00000000 | Irejista ye-CPRI PHY yokumisa Kabusha Yesiteshi 0 |
| 0x00100000 | Amarejista okulungisa kabusha i-Ethernet Channel 0 | |
| 0x00200000 | Irejista yokumisa kabusha i-Transceiver Yesiteshi 0 | |
|
1(2) |
0x01000000 | Irejista ye-CPRI PHY yokumisa Kabusha Yesiteshi 1 |
| 0x01100000 | Amarejista okulungisa kabusha i-Ethernet Channel 1 | |
| 0x01200000 | Irejista yokumisa kabusha i-Transceiver Yesiteshi 1 | |
|
2(2) |
0x02000000 | Irejista ye-CPRI PHY yokumisa Kabusha Yesiteshi 2 |
| 0x02100000 | Amarejista okulungisa kabusha i-Ethernet Channel 2 | |
| 0x02200000 | Irejista yokumisa kabusha i-Transceiver Yesiteshi 2 | |
| waqhubeka... | ||
| Inombolo yesiteshi | Ikheli Lesisekelo (Ikheli Le-Byte) | Uhlobo lokubhalisa |
|
3(2) |
0x03000000 | Irejista ye-CPRI PHY yokumisa Kabusha Yesiteshi 3 |
| 0x03100000 | Amarejista okulungisa kabusha i-Ethernet Channel 3 | |
| 0x03200000 | Irejista yokumisa kabusha i-Transceiver Yesiteshi 3 |
Lawa marejista agciniwe uma isiteshi singasetshenziswa.
I-F-Tile CPRI PHY Intel FPGA IP Design Example Izingobo zomlando zomhlahlandlela womsebenzisi
Uma inguqulo ye-IP eyinhloko ingekho ohlwini, umhlahlandlela womsebenzisi wenguqulo yangaphambilini ye-IP iyasebenza.
| Inguqulo ye-Intel Quartus Prime | Inguqulo ye-IP Core | Umhlahlandlela Womsebenzisi |
| 21.2 | 2.0.0 | I-F-Tile CPRI PHY Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi |
Umlando Wokubuyekeza Idokhumenti we-F-Tile CPRI PHY Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi
| Inguqulo Yedokhumenti | Inguqulo ye-Intel Quartus Prime | Inguqulo ye-IP | Izinguquko |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Ukukhishwa kokuqala. |
Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.
Amadokhumenti / Izinsiza
 |
intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
