intel F-Tile CPRI PHY FPGA IP Design Example
Alakaʻi hoʻomaka wikiwiki
Hāʻawi ka F-Tile CPRI PHY Intel® FPGA IP core i kahi papa hoʻokolohua simulation a me ka hoʻolālā ʻana o nā lakoample e kākoʻo ana i ka hoʻopili ʻana a me ka hoʻāʻo ʻana i nā lako. Ke hana ʻoe i ka hoʻolālā example, hana 'akomi ka mea hooponopono parameter i ka files pono e simulate, hōʻuluʻulu, a ho'āʻo i ka hoʻolālā i ka lako.
Hāʻawi pū ʻo Intel i kahi ex compilation-wale nōampka papahana hiki iā ʻoe ke hoʻohana no ka hoʻohālikelike wikiwiki ʻana i ka wahi IP a me ka manawa.
Hāʻawi ka F-Tile CPRI PHY Intel FPGA IP core i ka hiki ke hana i ka hoʻolālā examples no nā hui kākoʻo a pau o ka helu o nā kaha CPRI a me nā pākēneka laina CPRI. ʻO ka papa hōʻike a me ka hoʻolālā exampKākoʻo ia i nā hui hoʻohālikelike he nui o ka F-Tile CPRI PHY Intel FPGA IP core.
Kiʻi 1. Nā ʻanuʻu hoʻomohala no ka Design Example
ʻIke pili
- F-Tile CPRI PHY Intel FPGA IP alakaʻi hoʻohana
- No ka ʻike kikoʻī e pili ana i ka F-tile CPRI PHY IP.
- F-Tile CPRI PHY Intel FPGA IP Hoʻokuʻu memo
- Hoʻololi ka IP Release Notes IP i kahi hoʻokuʻu kūikawā.
Pono nā lako lako a me nā lako polokalamu
E ho'āʻo i ka exampe hoʻolālā, e hoʻohana i ka lako a me ka lako polokalamu:
- polokalamu Intel Quartus® Prime Pro Edition
- Pūnaehana console
- Nā Simulators i kākoʻo ʻia:
- Nā huaʻōlelo * VCS*
- Synopsys VCS MX
- Siemens* EDA ModelSim* SE a i ʻole Questa*— Questa-Intel FPGA Edition
Hana i ka Hoʻolālā
Kiʻi 2. Kaʻina hana
Kiʻi 3. Example Hoʻolālā Tab i ka IP Parameter Editor
No ka hana ʻana i kahi papahana Intel Quartus Prime Pro Edition:
- Ma ka Intel Quartus Prime Pro Edition, kaomi File ➤ New Project Wizard e hana i kahi papahana Quartus Prime hou, a i ʻole File ➤ Open Project e wehe i kahi papahana Intel Quartus Prime. Koi ka wizard iā ʻoe e kuhikuhi i kahi mea hana.
- E wehewehe i ka ʻohana ʻohana ʻo Agilex (I-series) a koho i kahi hāmeʻa e kūpono i kēia mau koi:
- ʻO ka tile transceiver he F-tile
- ʻO ka māmā māmā o ka transceiver he -1 a i ʻole -2
- He -1 a i ʻole -2 a i ʻole -3 ka papa wikiwiki
- Kaomi Hoʻopau.
E hahai i kēia mau ʻanuʻu no ka hoʻokumu ʻana i ka hoʻolālā ʻenehana F-Tile CPRI PHY Intel FPGA IPample and testbench:
- Ma ka IP Catalog, e huli a koho i ka F-Tile CPRI PHY Intel FPGA IP. Hōʻike ʻia ka puka aniani IP Variation hou.
- E wehewehe i kahi inoa kiʻekiʻe no kāu hoʻololi IP maʻamau. Mālama ka mea hoʻoponopono hoʻoponopono i nā hoʻonohonoho hoʻololi IP ma kahi file inoa ʻia .ip.
- Kaomi OK. Hōʻike ʻia ka mea hoʻoponopono hoʻohālikelike.
- Ma ka ʻaoʻao IP, e kuhikuhi i nā ʻāpana no kāu hoʻololi kumu IP.
- Ma ka Example Design tab, ma lalo o Example Hoʻolālā Files, koho i ke koho Simulation e hoʻopuka i ka papa hoʻāʻo a me ka papahana hoʻohui wale nō. E koho i ke koho Synthesis e hoʻohua i ka hoʻolālā ʻenehana example. Pono ʻoe e koho ma kahi liʻiliʻi o nā koho Simulation and Synthesis e hana i ka hoʻolālā example.
- Ma ka Example Design tab, ma lalo o Generated HDL Format, koho i ka Verilog HDL a i ʻole VHDL. Inā koho ʻoe iā VHDL, pono ʻoe e hoʻohālikelike i ka papa hoʻāʻo me kahi simulator ʻōlelo huikau. ʻO ka mea i hoʻāʻo ʻia ma ex_ ʻO ka papa kuhikuhi he kumu hoʻohālike VHDL, akā ʻo ka testbench nui file he System Verilog file.
- Kaomi i ka Generate Example pihi Hoʻolālā. ʻO ke koho Example Design Directory puka makani.
- Inā makemake ʻoe e hoʻololi i ka hoʻolālā exampke ala papa kuhikuhi a i ʻole ka inoa mai nā kuhi hewa i hōʻike ʻia (cpriphy_ftile_0_example_design), e nānā i ke ala hou a paʻi i ka ex design houampka inoa papa kuhikuhi (ample_dir>).
Papa kuhikuhi
ʻO ka F-Tile CPRI PHY Intel FPGA IP core design example file Aia nā papa kuhikuhi i nā mea i hana ʻia files no ka hoʻolālā example.
Kiʻi 4. Hoʻonohonoho Papa kuhikuhi o ka Generated Example Hoʻolālā
Papa 1. Papa hoao File Nā wehewehe
File Na inoa | wehewehe |
Key Testbench a me ka Simulation Files | |
<design_example_dir>/ example_testbench/basic_avl_tb_top.sv | pae hoʻāʻo pae kiʻekiʻe file. Hoʻomaka koke ka testbench i ka wīwī DUT a holo i nā hana Verilog HDL e hana a ʻae i nā ʻeke. |
<design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv | DUT wrapper e hoʻomaka koke ana i ka DUT a me nā mea hoʻāʻo ʻē aʻe. |
Nā Palapala Hōʻikeʻike (1) | |
<design_example_dir>/ example_testbench/run_vsim.do | ʻO ka Siemens EDA ModelSim SE a i ʻole Questa a i ʻole Questa-Intel FPGA Edition script e holo i ka papa hōʻike. |
<design_example_dir>/ example_testbench/run_vcs.sh | ʻO ka palapala Synopsys VCS e holo i ka papa hōʻike. |
<design_example_dir>/ example_testbench/run_vcsmx.sh | ʻO ka palapala Synopsys VCS MX (i hui pū ʻia ʻo Verilog HDL a me SystemVerilog me VHDL) e holo i ka papa hōʻike. |
E haʻalele i kekahi palapala simulator ʻē aʻe ma kaample_dir>/example_testbench/ waihona.
Papa 2. Mea Hana Lako Example File Nā wehewehe
File Na inoa | Nā wehewehe |
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Papahana Intel Quartus Prime file. |
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Hoʻonohonoho papahana Intel Quartus Prime file. |
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Nā Palena Hoʻolālā Synopsys files. Hiki iā ʻoe ke kope a hoʻololi i kēia mau mea files no kāu hoʻolālā Intel Agilex™ ponoʻī. |
<design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Hoʻolālā kiʻekiʻe ʻo Verilog HDL example file. |
<design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | DUT wrapper e hoʻomaka koke ana i ka DUT a me nā mea hoʻāʻo ʻē aʻe. |
<design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Nui file no ke komo ʻana i ka System Console. |
Hoʻohālike i ka Hoʻolālā Example Hōʻikeʻike
Kiʻi 5. Kaʻina hana
E hahai i kēia mau ʻanuʻu e hoʻohālike i ka papa hoʻokolohua:
- Ma ke kauoha kauoha, e hoʻololi i ka papa kuhikuhi simulation testbenchample_dir>/example_testbench. cd /example_testbench
- Holo i ka quartus_tlg ma ka papahana i hana ʻia file: quartus_tlg cpriphy_ftile_hw
- Holo ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
- E holo i ka palapala simulation no ka simulator kākoʻo o kāu koho. Hoʻopili ka ʻatikala a holo i ka papa hōʻike ma ka simulator. E nānā i ka papaʻaina Nā ʻanuʻu e hoʻohālike i ka Testbench.
- E noʻonoʻo i nā hopena. Ua loaʻa i ka papa hoʻokolohua kūleʻa ʻelima hyperframes, a hōʻike iā "PASSED".
Papa 3. Nā ʻanuʻu e hoʻohālike i ka Testbench ma Synopsys VCS* Simulator
Mea hoʻomeamea | Nā kuhikuhi | |
VCS | Ma ka laina kauoha, e kikokiko: | |
sh run_vcs.sh | ||
hoʻomau… |
Mea hoʻomeamea | Nā kuhikuhi | |
VCS MX | Ma ka laina kauoha, e kikokiko: | |
sh run_vcsmx.sh | ||
ModelSim SE a i ʻole Questa a i ʻole Questa-Intel FPGA Edition | Ma ka laina kauoha, e kikokiko: | |
vsim -hana run_vsim.do | ||
Inā makemake ʻoe e hoʻohālike me ka lawe ʻole ʻana i ka GUI, ʻano: | ||
vsim -c -do run_vsim.do |
samphōʻike ʻia ka hoʻopuka ʻana i kahi holo hoʻāʻo simulation kūleʻa no 24.33024 Gbps me nā kaha 4 CPRI:
Ka Houluulu ana i ka Papahana Houluulu wale
No ka hōʻuluʻulu ʻana i ka exampka papahana, e hahai i kēia mau ʻanuʻu:
- E hōʻoia i ka hoʻolālā hōʻuluʻulu exampua pau ka hanauna.
- Ma ka polokalamu Intel Quartus Prime Pro Edition, wehe i ka papahana Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- Ma ka papa kuhikuhi Processing, kaomi i ka Start Compilation.
- Ma hope o ka hōʻuluʻulu kūleʻa, loaʻa nā hōʻike no ka manawa a me ka hoʻohana waiwai i kāu kau Intel Quartus Prime Pro Edition.
ʻIke pili
Nā Kahe Hoʻolālā Hoʻokumu Paʻa
Hoʻopili a hoʻonohonoho i ka Design Example ma Lako
No ka hōʻuluʻulu ʻana i ka hoʻolālā ʻenehana exampa hoʻonohonoho iā ia ma kāu polokalamu Intel Agilex, e hahai i kēia mau ʻanuʻu:
- E hōʻoia i ka hoʻolālā ʻana o nā lako lakoampua pau ka hanauna.
- Ma ka polokalamu Intel Quartus Prime Pro Edition, wehe i ka papahana Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Hoʻoponopono i ka .qsf file e hāʻawi i nā pine e pili ana i kāu hāmeʻa.
- Ma ka papa kuhikuhi Processing, kaomi i ka Start Compilation.
- Ma hope o ka hōʻuluʻulu kūleʻa, a .sof file loaʻa maample_dir>/hardware_test_design/output_files papa kuhikuhi.
E hahai i kēia mau ʻanuʻu e hoʻolālā i ka hoʻolālā ʻenehana exampma ka mea hana Intel Agilex:
- Hoʻohui i ka Intel Agilex I-series Transceiver Signal Integrity Development Kit i ke kamepiula hoʻokipa.
'Ōlelo Aʻo: Ua hoʻonohonoho mua ʻia ka pahu hoʻomohala me nā alapine uaki pololei ma ke ʻano paʻamau. ʻAʻole pono ʻoe e hoʻohana i ka noi Clock Control e hoʻonohonoho i nā alapine. - Ma ka papa kuhikuhi Tools, kaomi Programmer.
- I ka Programmer, kaomi Hardware Setup.
- E koho i kahi lako polokalamu.
- E hōʻoia ua hoʻonohonoho ʻia ke ʻano iā JTAG.
- E koho i ka polokalamu Intel Agilex a kaomi i ka Add Device. Hōʻike ka Programmer i kahi kiʻi poloka o nā pilina ma waena o nā mea hana ma kāu papa.
- Ma ka lālani me kāu .sof, e nānā i ka pahu no ka .sof.
- E nānā i ka pahu ma ke kolamu Program/Configure.
- Kaomi hoʻomaka.
ʻIke pili
- Nā Kahe Hoʻolālā Hoʻokumu Paʻa
- Hoʻopololei i nā mea hana Intel FPGA
- Ka nānā 'ana a me ka Debugging Design me ka System Console
Ke ho'āʻo nei i ka Hoʻolālā Lako Paʻa Example
Ma hope o kou hōʻuluʻulu ʻana i ka F-Tile CPRI PHY Intel FPGA IP core design exampa hoʻonohonoho iā ia ma kāu polokalamu Intel Agilex, hiki iā ʻoe ke hoʻohana i ka System Console e hoʻolālā i ka IP core a me kāna PHY IP core registers.
E hoʻā i ka System Console a hoʻāʻo i ka hoʻolālā ʻenehana example, e hahai i kēia mau ʻanuʻu:
- Ma hope o ka hoʻolālā ʻenehana exampua hoʻonohonoho ʻia ma ka polokalamu Intel Agilex, ma ka polokalamu Intel Quartus Prime Pro Edition, ma ka papa kuhikuhi Tools, kaomi System Debugging Tools ➤ System Console.
- Ma ka ʻaoʻao Tcl Console, ʻano cd hwtest e hoʻololi i ka papa kuhikuhiample_dir>/hardware_test_design/hwtest_sl.
- Kākau i ke kumu main_script.tcl e wehe i kahi pilina i ka JTAG haku a hoʻomaka i ka hoʻāʻo.
Hoʻolālā Example Wehewehe
ʻO ka hoʻolālā exampe hōʻike ana i ka hana maʻamau o ka F-Tile CPRI PHY Intel FPGA IP core. Hiki iā ʻoe ke hana i ka hoʻolālā mai ka Example Design tab i ka F-Tile CPRI PHY Intel FPGA IP hoʻoponopono hoʻoponopono.
No ka hana ʻana i ka hoʻolālā exampʻAe, pono ʻoe e hoʻonohonoho mua i nā waiwai hoʻohālikelike no ka hoʻololi kumu IP āu i manaʻo ai e hana i kāu huahana hope. Hiki iā ʻoe ke koho e hana i ka hoʻolālā example me ka hiʻona RS-FEC a i ʻole. Loaʻa ka hiʻohiʻona RS-FEC me 10.1376, 12.1651 a me 24.33024 Gbps CPRI laina bit rates.
Papa 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
CPRI Line Bit Rate (Gbps) | Kākoʻo RS-FEC | Uaki Kuhikuhi (MHz) | Kākoʻo Latency Deterministic |
1.2288 | ʻAʻole | 153.6 | ʻAe |
2.4576 | ʻAʻole | 153.6 | ʻAe |
3.072 | ʻAʻole | 153.6 | ʻAe |
4.9152 | ʻAʻole | 153.6 | ʻAe |
6.144 | ʻAʻole | 153.6 | ʻAe |
9.8304 | ʻAʻole | 153.6 | ʻAe |
10.1376 | Me ka ʻole | 184.32 | ʻAe |
12.1651 | Me ka ʻole | 184.32 | ʻAe |
24.33024 | Me ka ʻole | 184.32 | ʻAe |
Nā hiʻohiʻona
- E hana i ka hoʻolālā example me ka hiʻona RS-FEC
- Nā mea hiki ke hoʻopaʻa packet maʻamau me ka helu latency huakaʻi puni
Hoʻolālā Hoʻohālikelike Example
ʻO ka F-Tile CPRI PHY Intel FPGA IP hoʻolālā exampLe hoʻopuka i kahi hōʻike hoʻohālikelike a me ka hoʻohālikelike files e hoʻomaka koke i ka F-Tile CPRI PHY Intel FPGA IP core ke koho ʻoe i ke koho Simulation.
Kiʻi 6. Papa Hana no 10.1316, 12.1651, a me 24.33024 Gbps (me ka RS-FEC a me ka ʻole)
Kiʻi 7. Paʻi Papa no 1.228, 2.4576, 3.072, 4.9152, 6.144, a me 9.8304 Gbps Line Rate
Ma kēia hoʻolālā exampʻO ia, hāʻawi ka simulation testbench i nā hana maʻamau e like me ka hoʻomaka ʻana a kali i ka laka, hoʻouna a loaʻa i nā ʻeke.
Hōʻike ka holo hoʻāʻo kūleʻa i ka hopena e hōʻoia ana i kēia ʻano hana:
- Hoʻoponopono ka loina o ka mea kūʻai aku i ke kumu IP.
- Ke kali nei ka loina o ka mea kūʻai aku i ka alignment datapath RX.
- Hoʻouna ka loiloi o ka mea kūʻai aku i nā hyperframes ma ka interface TX MII a kali i ʻelima hyperframes e loaʻa ma ka interface RX MII. Hoʻouna ʻia nā Hyperframes a loaʻa iā MII interface e like me nā kikoʻī CPRI v7.0.
Nānā: ʻO nā hoʻolālā CPRI e kuhikuhi ana i ka 1.2, 2.4, 3, 4.9, 6.1, a me 9.8 Gbps laina laina e hoʻohana i ka interface 8b/10b a me nā hoʻolālā e kuhikuhi ana i ka 10.1, 12.1 a me 24.3 Gbps (me a me ka ʻole RS-FEC) hoʻohana i ka interface MII. ʻO kēia hoʻolālā exampe komo pū ana me ka papa helu huakaʻi kaʻapuni e helu i ka latency huakaʻi kaʻapuni mai TX a i RX. - Heluhelu ka manaʻo o ka mea kūʻai aku i ka waiwai lancy huakaʻi pōʻai a nānā i ka ʻike a me ka pololei o ka ʻikepili hyperframes ma ka ʻaoʻao RX MII ke hoʻopau ka counter i ka helu latency huakaʻi puni.
ʻIke pili
- Nā kikoʻī CPRI
Hoʻolālā Lako Paʻa Example
Kiʻi 8. Hoʻolālā Lako Example Palapala Kii
Nānā
- Hoʻolālā ka CPRI me 2.4/4.9/9.8 Gbps CPRI laina laina e hoʻohana i ka interface 8b/10b a me nā hoʻolālā laina laina CPRI āpau e hoʻohana i ka interface MII.
- Pono nā hoʻolālā CPRI me 2.4/4.9/9.8 Gbps CPRI laina laina pono he 153.6 MHz transceiver reference clock a me nā laina laina CPRI ʻē aʻe he 184.32 MHz.
ʻO ka F-Tile CPRI PHY Intel FPGA IP core hardware design example e komo i keia mau mea.
- F-Tile CPRI PHY Intel FPGA IP kumu.
- Packet client logic block e hoʻopuka a loaʻa i nā kaʻa.
- Kaapuni kaapuni.
- IOPLL e hoopuka i sampling ka uaki no ka loina latency deterministic i loko o ka IP, a me ka mea hoʻohālikelike huakaʻi pōʻai ma ka testbench.
- Pūnaehana PLL e hoʻopuka i nā uaki ʻōnaehana no ka IP.
- ʻO Avalon®-MM address decoder e hoʻokaʻawale i ka wahi helu hoʻonohonoho hou no nā modula CPRI, Transceiver, a me Ethernet i ka wā o ka hoʻonohonoho hou ʻana.
- Nā kumu a me nā ʻimi no ka hōʻoia ʻana i ka hoʻihoʻi ʻana a me ka nānā ʻana i nā uaki a me kekahi mau kūlana kūlana.
- JTAG mea hoʻoponopono e kamaʻilio me ka System Console. Ke kamaʻilio nei ʻoe me ka loiloi mea kūʻai aku ma o System Console.
Nā hōʻailona Interface
Papa 5. Hoʻolālā Example Nā hōʻailona Interface
hōʻailona | Kuhikuhi | wehewehe |
ref_clk100MHz | Hookomo | Hoʻokomo i ka uaki no ke komo ʻana i ka CSR ma nā kikowaena hoʻonohonoho hou. Holoi ma 100 MHz. |
i_clk_ref[0] | Hookomo | Uaki kuhikuhi no System PLL. Holoi ma 156.25 MHz. |
i_clk_ref[1] | Hookomo | Uaki kuhikuhi Transceiver. Holoi ma
• 153.6 MHz no CPRI laina laina 1.2, 2.4, 3, 4.9, 6.1, a me 9.8 Gbps. • 184.32 MHz no CPRI laina laina 10.1,12.1, a me 24.3 Gbps me RS-FEC a me ka ole. |
i_rx_serial[n] | Hookomo | Hoʻokomo ʻo Transceiver PHY i ka ʻikepili serial. |
o_tx_serial[n] | Hoʻopuka | ʻO ka transceiver PHY hoʻopuka i ka ʻikepili serial. |
Hoʻolālā Example Kakau inoa
Papa 6. Hoʻolālā Example Kakau inoa
Helu Kanal | Wahi kumu (Byte Address) | ʻAno Kakau |
0 |
0x00000000 | Hoʻopaʻa inoa ʻia ʻo CPRI PHY no ka Channel 0 |
0x00100000 | Hoʻopaʻa inoa ʻo Ethernet Reconfiguration no Channel 0 | |
0x00200000 | Hoʻopaʻa inoa ʻo Transceiver Reconfiguration no Channel 0 | |
1(2) |
0x01000000 | Hoʻopaʻa inoa ʻia ʻo CPRI PHY no ka Channel 1 |
0x01100000 | Hoʻopaʻa inoa ʻo Ethernet Reconfiguration no Channel 1 | |
0x01200000 | Hoʻopaʻa inoa ʻo Transceiver Reconfiguration no Channel 1 | |
2(2) |
0x02000000 | Hoʻopaʻa inoa ʻia ʻo CPRI PHY no ka Channel 2 |
0x02100000 | Hoʻopaʻa inoa ʻo Ethernet Reconfiguration no Channel 2 | |
0x02200000 | Hoʻopaʻa inoa ʻo Transceiver Reconfiguration no Channel 2 | |
hoʻomau… |
Helu Kanal | Wahi kumu (Byte Address) | ʻAno Kakau |
3(2) |
0x03000000 | Hoʻopaʻa inoa ʻia ʻo CPRI PHY no ka Channel 3 |
0x03100000 | Hoʻopaʻa inoa ʻo Ethernet Reconfiguration no Channel 3 | |
0x03200000 | Hoʻopaʻa inoa ʻo Transceiver Reconfiguration no Channel 3 |
Mālama ʻia kēia mau papa inoa inā ʻaʻole hoʻohana ʻia ke kahawai.
F-Tile CPRI PHY Intel FPGA IP Design Example Nā waihona alakaʻi hoʻohana
Inā ʻaʻole i helu ʻia kahi mana IP core, pili ke alakaʻi mea hoʻohana no ka mana IP mua.
ʻO Intel Quartus Prime Version | Manaʻo IP Core | Ke alakaʻi hoʻohana |
21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design Example alakaʻi hoʻohana |
Moʻolelo Hoʻoponopono Hou no F-Tile CPRI PHY Intel FPGA IP Design Example alakaʻi hoʻohana
Palapala Palapala | ʻO Intel Quartus Prime Version | Manaʻo IP | Nā hoʻololi |
2021.10.04 | 21.3 | 3.0.0 |
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2021.06.21 | 21.2 | 2.0.0 | Hoʻokuʻu mua. |
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe.
* Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
Palapala / Punawai
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Ke alakaʻi hoʻohana F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, Hoʻolālā IP |