intel F-Tile CPRI PHY FPGA IP Design Example
Ntuziaka mmalite ngwa ngwa
F-Tile CPRI PHY Intel® FPGA IP isi na-enye testbench simulation na ngwaike imewe ex.ample nke na-akwado mkpokọta na nyocha ngwaike. Mgbe ị na-emepụta imewe example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta filedị mkpa iji megharịa, chịkọta, na nwalee imewe na ngwaike.
Intel na-enyekwa naanị mkpokọta example oru ngo nke ị nwere ike iji mee atụmatụ ngwa ngwa IP isi mpaghara na oge.
F-Tile CPRI PHY Intel FPGA IP core na-enye ike nke imepụta imewe examples maka nchikota niile akwadoro nke ọnụọgụ ọwa CPRI yana ọnụego bit ahịrị CPRI. The testbench na imewe exampna-akwado ọtụtụ ngwakọta paramita nke F-Tile CPRI PHY Intel FPGA IP core.
Ọgụgụ 1. Nzọụkwụ mmepe maka imewe Example
Ozi metụtara
- F-Tile CPRI PHY Intel FPGA IP ntuziaka onye ọrụ
- Maka ozi zuru ezu na F-tile CPRI PHY IP.
- F-Tile CPRI PHY Intel FPGA IP ndetu mwepụta
- Ihe ndetu mwepụta IP na-edepụta mgbanwe IP na otu ntọhapụ.
Achọrọ ngwaike na ngwanrọ
Iji nwalee exampiji chepụta, jiri ngwaike na ngwanrọ ndị a:
- Intel Quartus® Prime Pro Edition sọftụwia
- Sistemụ njikwa
- Ndị simulators akwadoro:
- Synopsys* VCS*
- Synopsis VCS MX
- Siemens* EDA ModelSim* SE ma ọ bụ Questa*— Questa-Intel FPGA Edition
Ịmepụta Nhazi
Ọgụgụ 2. Usoro
Nyocha 3. ỌpụampMepụta Tab na IP Parameter Editor
Iji mepụta ọrụ Intel Quartus Prime Pro Edition:
- Na Intel Quartus Prime Pro Edition, pịa File ➤ Ọkachamara Project ọhụrụ iji mepụta ọrụ Quartus Prime ọhụrụ, ma ọ bụ File ➤ Mepee Project ka imepe ọrụ Intel Quartus Prime dị ugbu a. Ọkachamara na-akpali gị ezipụta ngwaọrụ.
- Ezinụlọ ngwaọrụ Agilex (I-usoro) wee họrọ ngwaọrụ na-emezu ihe ndị a niile:
- Transceiver tile bụ F-tile
- Ọsọ ọsọ transceiver bụ -1 ma ọ bụ -2
- Isi ọsọ ọkwa bụ -1 ma ọ bụ -2 ma ọ bụ -3
- Pịa N'ikpeazụ.
Soro usoro ndị a ka ịmepụta F-Tile CPRI PHY Intel FPGA IP ngwaike imewe example na testbench:
- Na katalọgụ IP, chọta ma họrọ F-Tile CPRI PHY Intel FPGA IP. Window mgbanwe IP ọhụrụ na-egosi.
- Ezipụta aha ọkwa dị elu maka IP omenala gị iche. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .ip.
- Pịa OK. Ihe ndezi paramita na-egosi.
- Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
- Na Example Design tab, n'okpuru Example Design Files, họrọ nhọrọ Simulation iji mepụta testbench na ọrụ nchịkọta naanị. Họrọ nhọrọ Synthesis iji mepụta ngwaike imewe example. Ị ga-ahọrọ ma ọ dịkarịa ala otu n'ime nhọrọ Simulation na Synthesis iji mepụta ihe ngosi example.
- Na Exampna Kere taabụ, n'okpuru Emepụtara HDL Ụdị, họrọ Verilog HDL ma ọ bụ VHDL. Ọ bụrụ na ịhọrọ VHDL, ị ga-emerịrị testbench na simulator asụsụ agwakọtara. Ngwa a na-anwale na ex_ ndekọ bụ ụdị VHDL, mana isi testbench file bụ Verilog Sistemu file.
- Pịa n'ịwa Example Design bọtịnụ. Họrọ Example Imepụta windo ndekọ na-egosi.
- Ọ bụrụ na ị chọrọ ịgbanwe imewe exampụzọ ndekọ aha ma ọ bụ aha sitere na ndabara egosiri (cpriphy_ftile_0_example_design), chọgharịa n'ụzọ ọhụrụ wee pịnye ihe ọhụrụ ahụ exampaha ndekọ aha (ample_dir>).
Ọdịdị ndekọ
F-Tile CPRI PHY Intel FPGA IP isi imewe example file akwụkwọ ndekọ aha nwere ihe ndị a emepụtara files maka imewe example.
Ọgụgụ 4. Nhazi ndekọ aha nke emepụtara Example Design
Tebụl 1. Testbench File Nkọwa
| File Aha | Nkọwa |
| Key Testbench na Simulation Files | |
| <design_example_dir>/ example_testbench/basic_avl_tb_top.sv | testbench dị elu file. Testbench na-ewepụta ihe mkpuchi DUT ma na-arụ ọrụ Verilog HDL iji mepụta na ịnakwere ngwugwu. |
| <design_example_dir>/ example_testbench/ cpriphy_ftile_wrapper.sv | Ihe mkpuchi DUT nke na-ewepụta DUT na ihe ndị ọzọ testbench. |
| Ederede Testbench (1) | |
| <design_example_dir>/ example_testbench/run_vsim.do | Siemens EDA ModelSim SE ma ọ bụ Questa ma ọ bụ Questa-Intel FPGA Edition iji mee testbench. |
| <design_example_dir>/ example_testbench/run_vcs.sh | Edemede Synopsys VCS iji mee testbench. |
| <design_example_dir>/ example_testbench/run_vcsmx.sh | Edemede Synopsys VCS MX (jikọtara Verilog HDL na SystemVerilog na VHDL) iji mee testbench. |
Ileghara script simulator ọ bụla ọzọ naample_dir>/ example_testbench/ nchekwa.
Tebụl 2. Ihe nrụpụta ngwaike Example File Nkọwa
| File Aha | Nkọwa |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf | Intel Quartus Prime oru ngo file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.qsf | Ntọala ọrụ Intel Quartus Prime file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.sdc | Synopsys imewe mmachi files. Ị nwere ike idetuo ma gbanwee ndị a files maka imewe Intel Agilex™ nke gị. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_hw.v | Verilog HDL imewe nke kachasị eluample file. |
| <design_example_dir>/hardware_test_design/ cpriphy_ftile_wrapper.sv | Ihe mkpuchi DUT nke na-ewepụta DUT na ihe ndị ọzọ testbench. |
| <design_example_dir>/hardware_test_design/ hwtest_sl/main_script.tcl | Isi file maka ịnweta Sistemu Console. |
Ịmepụta atụmatụ Exampna Testbench
Ọgụgụ 5. Usoro
Soro usoro ndị a ka ịmee testbench:
- Na ngwa ngwa iwu, gbanwee gaa na ndekọ ndekọ simulation testbenchample_dir>/ example_testbench. cd / example_testbench
- Gbaa quartus_tlg n'ọrụ ewepụtara file: quartus_tlg cpriphy_ftile_hw
- Gbaa ip-setup-simulation: ip-setup-simulation –output-directory=./sim_script –use-relative-paths –quartus project=cpriphy_ftile_hw.qpf
- Gbaa script simulation maka simulator akwadoro nke nhọrọ gị. Edemede a na-achịkọta ma na-agba testbench na simulator. Rụtụ aka na tebụl Nzọụkwụ iji mee ka Testbench.
- Nyochaa nsonaazụ ya. testbench na-aga nke ọma nwetara hyperframes ise, wee gosi “PASSED”.
Tebụl 3. Nzọụkwụ iji megharịa Testbench na Synopsys VCS* Simulator
| Simulator | Ntuziaka | |
| VCS | N'ahịrị iwu, pịnye: | |
| sh run_vcs.sh | ||
| gara n'ihu… | ||
| Simulator | Ntuziaka | |
| VCS MX | N'ahịrị iwu, pịnye: | |
| sh run_vcsmx.sh | ||
| ModelSim SE ma ọ bụ Questa ma ọ bụ Questa-Intel FPGA Edition | N'ahịrị iwu, pịnye: | |
| vsim - mee run_vsim.do | ||
| Ọ bụrụ na-amasị gị ịme emume na-ebuliteghị GUI, pịnye: | ||
| vsim -c-do run_vsim.do | ||
Ndị na-esonụ sampMmepụta leta na-egosi nnwale ịme anwansị na-aga nke ọma maka 24.33024 Gbps yana ọwa CPRI 4:
Ịchịkọta ọrụ nchịkọta naanị
Iji chịkọta mkpokọta-naanị exampna project, soro usoro ndị a:
- Gbaa mbọ hụ na nhazi mkpokọta example ọgbọ agwụla.
- Na ngwanrọ Intel Quartus Prime Pro Edition, mepee ọrụ Intel Quartus Prime Pro Editionample_dir>/compilation_test_design/cpriphy_ftile.qpf.
- Na nhazi menu, pịa Malite Nchịkọta.
- Mgbe achịkọtachara nke ọma, akụkọ maka oge yana maka iji akụrụngwa dị na nnọkọ Intel Quartus Prime Pro Edition gị.
Ozi metụtara
Ngwongwo Nhazi dabere na ngọngọ
Ịchịkọta na Hazie Nhazi Exampna Hardware
Iji chịkọta nhazi ngwaike example wee hazie ya na ngwaọrụ Intel Agilex gị, soro usoro ndị a:
- Gbaa mbọ hụ na imepụta ngwaike example ọgbọ agwụla.
- Na ngwanrọ Intel Quartus Prime Pro Edition, mepee ọrụ Intel Quartus Primeample_dir>/hardware_test_design/ cpriphy_ftile_hw.qpf.
- Dezie .qsf file ikenye atụdo dabere na ngwaike gị.
- Na nhazi menu, pịa Malite Nchịkọta.
- Mgbe nchịkọta nke ọma gasịrị, .sof file dị naample_dir>/hardware_test_design/output_files ndekọ.
Soro usoro ndị a ka ịmebe ihe nhazi ngwaike exampna ngwaọrụ Intel Agilex:
- Jikọọ Intel Agilex I-usoro nke Transceiver Signal Integrity Development Kit na kọmputa onye ọbịa.
Mara: A na-ahazi ngwa mmepe ahụ site na ndabara nke ọma ugboro elekere. Ịkwesighi iji ngwa njikwa elekere ka ịtọ ugboro ugboro. - Na Ngwaọrụ menu, pịa Programmer.
- Na Programmer, pịa Hardware Mbido.
- Họrọ ngwaọrụ mmemme.
- Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
- Họrọ ngwaọrụ Intel Agilex wee pịa Tinye Ngwaọrụ. Onye mmemme na-egosiputa eserese mgbochi nke njikọ dị n'etiti ngwaọrụ dị na bọọdụ gị.
- N'ahịrị na .sof gị, lelee igbe maka .sof.
- Lelee igbe dị na kọlụm Mmemme/Hazie.
- Pịa Malite.
Ozi metụtara
- Ngwongwo Nhazi dabere na ngọngọ
- Ngwa ngwa Intel FPGA na-eme mmemme
- Iji Sistemụ Console nyochaa na imegharị atụmatụ
Nnwale ihe nrụpụta ngwaike Example
Mgbe ị chịkọtara F-Tile CPRI PHY Intel FPGA IP core design exampma hazie ya na ngwaọrụ Intel Agilex gị, ị nwere ike iji Sistemụ Console iji hazie IP core yana ndekọ isi IP PHY ya.
Ka ịgbanwuo Console Sistemu wee nwalee nhazi ngwaike example, soro usoro ndị a:
- Mgbe ngwaike imewe exampA na-ahazi le na ngwaọrụ Intel Agilex, na sọftụwia Intel Quartus Prime Pro Edition, na menu Ngwaọrụ, pịa Ngwaọrụ Debugging System ➤ System Console.
- Na pane Tcl Console, pịnye cd hwtest iji gbanwee ndekọ ka ọ bụrụample_dir>/hardware_test_design/hwtest_sl.
- Pịnye isi mmalite main_script.tcl iji mepee njikọ na JTAG nna ukwu wee malite ule.
Imepụta Example Nkọwa
Imewe example na-egosipụta isi ọrụ nke F-Tile CPRI PHY Intel FPGA IP core. Ị nwere ike ịmepụta imewe site na Exampma chepụta taabụ na F-Tile CPRI PHY Intel FPGA IP nchịkọta akụkọ paramita.
Iji mepụta imewe exampYa mere, ị ga-ebu ụzọ tọọ ụkpụrụ paramita maka mgbanwe isi IP nke ịchọrọ ịmepụta na ngwaahịa njedebe gị. Ị nwere ike ịhọrọ ịmepụta imewe exampnwere ma ọ bụ na-enweghị njirimara RS-FEC. Njirimara RS-FEC dị na 10.1376, 12.1651 na 24.33024 Gbps CPRI bit bit line.
Tebụl 4. F-Tile CPRI PHY Intel FPGA IP Core Feature Matrix
| Ọnụego ntanye ahịrị CPRI (Gbps) | Nkwado RS-FEC | Elekere ntụaka (MHz) | Nkwado Latency Deterministic |
| 1.2288 | Mba | 153.6 | Ee |
| 2.4576 | Mba | 153.6 | Ee |
| 3.072 | Mba | 153.6 | Ee |
| 4.9152 | Mba | 153.6 | Ee |
| 6.144 | Mba | 153.6 | Ee |
| 9.8304 | Mba | 153.6 | Ee |
| 10.1376 | Na na enweghị | 184.32 | Ee |
| 12.1651 | Na na enweghị | 184.32 | Ee |
| 24.33024 | Na na enweghị | 184.32 | Ee |
Atụmatụ
- Mepụta imewe example na njirimara RS-FEC
- Ike ịlele ngwugwu nke gụnyere ọnụ ọgụgụ latency njem okirikiri
Imepụta ihe ngosi Example
F-Tile CPRI PHY Intel FPGA IP imewe example na-emepụta simulation testbench na ịme anwansị files nke na-ewepụta F-Tile CPRI PHY Intel FPGA IP core mgbe ị họrọ nhọrọ Simulation.
Ọnụọgụ 6. Ihe nkpuchi ngọngọ maka 10.1316, 12.1651, na 24.33024 Gbps (ya na na-enweghị RS-FEC) Ọnụego ahịrị
Ọgụgụ 7. Ihe nkpuchi ngọngọ maka 1.228, 2.4576, 3.072, 4.9152, 6.144, na 9.8304 Gbps Line Rate
Na nke a imewe example, simulation testbench na-enye ọrụ bụ isi dị ka mmalite na ichere mkpọchi, nyefee na ịnata ngwugwu.
Nnwale na-aga nke ọma na-egosipụta mmepụta na-akwado omume ndị a:
- Ihe mgbagha nke ndị ahịa na-emegharị isi IP.
- Ihe mgbagha ndị ahịa na-eche maka nhazi data ụzọ RX.
- Ihe mgbagha nke ndị ahịa na-ebufe hyperframes na interface TX MII wee chere ka a nabata hyperframes ise na interface RX MII. A na-ebufe hyperframes ma nata na interface MII dịka nkọwa CPRI v7.0 siri dị.
Mara: CPRI chepụtara nke lekwasịrị anya 1.2, 2.4, 3, 4.9, 6.1, na 9.8 Gbps akara ọnụọgụ na-eji 8b/10b interface na atụmatụ ndị lekwasịrị anya 10.1, 12.1 na 24.3 Gbps (ya na na enweghị RS-FEC) jiri interface MII. Nke a imewe example gunyere counter njem okirikiri iji gụta latency njem okirikiri site na TX ruo RX. - Ihe mgbagha nke ndị ahịa na-agụ uru latency njem okirikiri wee lelee ọdịnaya na izi ezi nke data hyperframes n'akụkụ RX MII ozugbo counter mechara ọnụ ọgụgụ latency njem okirikiri.
Ozi metụtara
- Nkọwapụta CPRI
Nhazi ngwaike Example
Onyonyo 8. Akụrụngwa Nhazi Example Block eserese
Rịba ama
- Atụmatụ CPRI na 2.4/4.9/9.8 Gbps CPRI akara ọnụego na-eji 8b/10b interface na ndị ọzọ niile akara akara CPRI na-eji interface MII.
- Atụmatụ CPRI na 2.4/4.9/9.8 Gbps CPRI akara ọnụego chọrọ 153.6 MHz transceiver elekere na ọnụego akara CPRI ndị ọzọ chọrọ 184.32 MHz.
F-Tile CPRI PHY Intel FPGA IP isi ihe eji arụ ọrụ example gụnyere ihe ndị a:
- F-Tile CPRI PHY Intel FPGA IP isi.
- Ihe mgbochi mgbagha ndị ahịa na-ebute ma nata okporo ụzọ.
- Mkpesa njem okirikiri.
- IOPLL iji mepụta sampling ling clock for deterministic latency logic n'ime IP, na gburugburu njem counter akụrụngwa na testbench.
- Sistemu PLL iji mepụta clocks sistemụ maka IP.
- Avalon®-MM adreesị decoder iji dekọọ oghere adreesị nhazigharị maka CPRI, Transceiver, na modul Ethernet n'oge nnweta nhazigharị.
- Isi mmalite na nyocha maka nkwuputa nrụpụta na nyochaa elekere na obere ọkwa ọkwa.
- JTAG njikwa na-ekwurịta okwu na Sistemu Console. Ị na-ekwurịta okwu na mgbagha onye ahịa site na System Console.
Ihe nrịbama ihu
Tebụl 5. Imepụta Exampna akara ngosi interface
| Signal | Ntuziaka | Nkọwa |
| ref_clk100MHz | Ntinye | Elekere ntinye maka ịnweta CSR na ngbanwe nhazi niile. Ụgbọ ala na 100 MHz. |
| i_clk_ref[0] | Ntinye | Elekere ntụaka maka Sistemu PLL. Ụgbọ ala na 156.25 MHz. |
| i_clk_ref[1] | Ntinye | Elekere ntụgharị ntụgharị. Ụgbọala na
• 153.6 MHz maka ọnụego ahịrị CPRI 1.2, 2.4, 3, 4.9, 6.1, na 9.8 Gbps. • 184.32 MHz maka CPRI akara ọnụego 10.1,12.1, na 24.3 Gbps na na-enweghị RS-FEC. |
| i_rx_serial[n] | Ntinye | Ntinye data nsonye transceiver PHY. |
| o_tx_serial[n] | Mpụta | Oghere Usoro mmepụta PHY transceiver. |
Imepụta Exampna Ndebanye aha
Tebụl 6. Imepụta Exampna Ndebanye aha
| Nọmba ọwa | Adreesị ntọala (Adreesi Byte) | Ụdị aha |
|
0 |
0x00000000 | CPRI PHY ndebanye aha maka ọwa 0 |
| 0x00100000 | Edebanye aha nhazigharị Ethernet maka ọwa 0 | |
| 0x00200000 | Transceiver Reconfiguration na-edebanye aha maka ọwa 0 | |
|
1(2) |
0x01000000 | CPRI PHY ndebanye aha maka ọwa 1 |
| 0x01100000 | Edebanye aha nhazigharị Ethernet maka ọwa 1 | |
| 0x01200000 | Transceiver Reconfiguration na-edebanye aha maka ọwa 1 | |
|
2(2) |
0x02000000 | CPRI PHY ndebanye aha maka ọwa 2 |
| 0x02100000 | Edebanye aha nhazigharị Ethernet maka ọwa 2 | |
| 0x02200000 | Transceiver Reconfiguration na-edebanye aha maka ọwa 2 | |
| gara n'ihu… | ||
| Nọmba ọwa | Adreesị ntọala (Adreesi Byte) | Ụdị aha |
|
3(2) |
0x03000000 | CPRI PHY ndebanye aha maka ọwa 3 |
| 0x03100000 | Edebanye aha nhazigharị Ethernet maka ọwa 3 | |
| 0x03200000 | Transceiver Reconfiguration na-edebanye aha maka ọwa 3 |
A na-edobe ndekọ ndị a ma ọ bụrụ na ejighị ọwa.
F-Tile CPRI PHY Intel FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ
Ọ bụrụ na edepụtaghị ụdị isi IP, ntuziaka onye ọrụ maka ụdị IP isi gara aga na-emetụta.
| Intel Quartus Prime Version | Ụdị IP Core | Ntuziaka onye ọrụ |
| 21.2 | 2.0.0 | F-Tile CPRI PHY Intel FPGA IP Design Example ntuziaka onye ọrụ |
Akụkọ ngbanwe akwụkwọ maka F-Tile CPRI PHY Intel FPGA IP Design Example ntuziaka onye ọrụ
| Ụdị akwụkwọ | Intel Quartus Prime Version | Ụdị IP | Mgbanwe |
| 2021.10.04 | 21.3 | 3.0.0 |
|
| 2021.06.21 | 21.2 | 2.0.0 | Ntọhapụ mbụ. |
Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
* Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
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intel F-Tile CPRI PHY FPGA IP Design Example [pdf] Ntuziaka onye ọrụ F-Tile CPRI PHY FPGA IP Design Example, PHY FPGA IP Design Example, F-Tile CPRI IP Design Example, IP Design Example, IP Design |
