SYnOPSYS FPGA Synthesis Synplify Pro yeMicrosemi Edition IsiKhokelo somsebenzisi

I-Synopsys FPGA Synthesis-Synplify Pro yoHlelo lweMicrosemi
sisixhobo esibanzi sokuphunyezwa kweFPGA ngeendlela ezahlukeneyo
iimpawu eziyilelwe ukunceda abasebenzisi kwi-logic synthesis kunye noyilo
iyahamba.

Imiyalelo yokusetyenziswa kwemveliso

Isahluko 1: Intshayelelo

Esi sahluko sibonelela ngesipheloview yeSynopsys FPGA kunye
Iimveliso zePrototyping, iziXhobo zokuSebenza zeFPGA, kunye ne-Synopsys FPGA
Iimpawu zesixhobo.

Umda woxwebhu

Isethi yoxwebhu ibandakanya ulwazi malunga neempawu zemveliso
kwaye yenzelwe abasebenzisi abanomdla kwi-FPGA yokudibanisa kunye noyilo
iyahamba.

Ndiyaqalisa

Ukuqala ukusebenzisa isoftware, yindulule ngokulandela okunikiweyo
imiyalelo kwaye ubhekisele kwisikhokelo somsebenzisi ukuze ufumane uncedo.

Ujongano lomsebenzisi ngaphezuluview

Ziqhelanise nojongano lomsebenzisi ngokufanelekileyo
jonga kwiifitsha zesoftware.

Isahluko 2: FPGA Synthesis Design flows

Esi sahluko sichaza iLogic Synthesis Design Flow yeFPGA
udibaniso.

Isahluko sesi-3: Ukulungiselela iNgeniso

Funda indlela yokusebenzisa uMthombo woLwimi oluxubeneyo Files kunye noKunyuka
Umqokeleli wokulungiselela igalelo elisebenzayo.

Phawula: Kulumkele nakuphi na ukulinganiselwa okunxulumene noko
ngokusebenzisa uMqokeleli woNgeniso.

FAQ

Umbuzo: Ndingenza iikopi zamaxwebhu?

A: Ewe, isivumelwano selayisenisi siyakuvumela ukwenza iikopi zangaphakathi
sebenzisa kuphela ngophawu olufanelekileyo.

Umbuzo: Ndiyiqala njani isoftware?

A: Jonga icandelo elithi “Ukuqalisa” kwiSahluko 1 se
isikhokelo somsebenzisi semiyalelo eneenkcukacha yokuqalisa isoftwe.

Umbuzo: Ngoobani abaphulaphuli ekujoliswe kubo kwesi sikhokelo somsebenzisi?

A: Isikhokelo somsebenzisi sijolise kubantu abanomdla kwiFPGA
ukudibanisa kunye nokuhamba koyilo.

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Synopsys FPGA Synthesis
Synplify Pro kuHlelo lweMicrosemi
Isikhokelo somsebenzisi
Okthobha 2014

Isaziso selungelo lokushicilela kunye nolwazi lobunikazi
Ilungelo lokushicilela © 2014 Synopsy, Inc. Onke amalungelo agciniwe. Le software kunye namaxwebhu aqulathe ulwazi oluyimfihlo kunye nobunini obuyipropathi ye-Synopsys, Inc. Isoftware kunye namaxwebhu anikezelwe phantsi kwesivumelwano selayisenisi kwaye anokusetyenziswa okanye akhutshelwe kuphela ngokuhambelana nemiqathango yesivumelwano selayisensi. Akukho nxalenye yesoftware kunye namaxwebhu anokuthi aveliswe, agqithiswe, okanye aguqulelwe, ngayo nayiphi na indlela okanye ngayo nayiphi na indlela, i-elektroniki, oomatshini, ngesandla, i-optical, okanye ngenye indlela, ngaphandle kwemvume ebhaliweyo yangaphambili ye-Synopsys, Inc., okanye njengoko kubonelelwe ngokucacileyo sisivumelwano selayisensi.
Ilungelo lokukopa uxwebhu
Isivumelwano selayisenisi kunye ne-Synopsys sivumela umntu onikwe iphepha-mvume ukuba enze iikopi zamaxwebhu ukuze asetyenziswe ngaphakathi kuphela.
Ikopi nganye iya kubandakanya onke amalungelo okushicilela, iimpawu zorhwebo, iimpawu zenkonzo, kunye nezaziso zamalungelo obunini, ukuba zikhona. Umntu onikwe ilayisenisi kufuneka anike amanani alandelelanayo kuzo zonke iikopi. Ezi kopi ziya kuba nale legend ilandelayo kwiphepha leqweqwe:
“Olu xwebhu luphindwa kabini ngemvume yeSynopsy, Inc., ukuze lusetyenziswe kuphela ______________________________________________________ kunye nabasebenzi bayo. Le yinombolo yekopi __________."
Ingxelo Yolawulo Lwendawo
Yonke idatha yobugcisa equlethwe kolu papasho ixhomekeke kwimithetho yolawulo lokuthumela ngaphandle yase-United States of America. Ukubhengeza kubemi bamanye amazwe ngokuchasene nomthetho wase-United States akuvumelekanga. Luxanduva lomfundi ukumisela imimiselo esebenzayo aze ayithobele.
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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuzihlangula
I-SYNOPSYS, I-INC., KUNYE NABANTU BAYO IPHEPHA-MVUME ABENZA WARANTI YALO NALUPHI UHLOBO, LUCHAZAYO OKANYE LUCINGQIWEYO, NGOKUBHEKISELELE KOLU MTHETHO, KUHLANGANISA, KODWA AKUMDAWU, IZIQINISEKISO EZINGQIWEYO ZOKUTHENGISA NOKULUNGELA INXAXHEBA.
Iimpawu zoRhwebo ezibhalisiweyo (®)
Iisinopsy, AEON, AMPS, iAstro, iTekhnoloji yokuNxila i-Behavior, i-Cadabra, i-CATS, iQinisekisa, i-CHIPit, i-CoMET, iKHOWUDI V, i-Design Compiler, i-DesignWare, i-EMBED-IT!, i-Formality, i-Galaxy Custom Designer, i-Global Synthesis, i-HAPS, i-HapsTrak, i-HDL Analyst, i-HSIM, i-HSPICE, i-Lightify, i-MAST, i-Lightify, i-MAST NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, iziphumo eziNgcono nje, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, Synplicity logo, Synplify, Synplify Environmental, UMCS SYNCOME, UMCS SYNCOME, UMCS SYNCOME, UMCS UVera, kunye no-YIELUMlawuli ziimpawu zorhwebo ezibhalisiweyo ze-Synopsy, Inc.
Iimpawu zorhwebo (TM)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Professionalzer, DC HDly Design, Uyilo lweDFT MAXMAX, Uyilo lwe-DFT MAX, Uyilo lwe-DFT. Ukufikelela ngokuthe ngqo kwe-Silicon, ukuFumana, i-Eclypse, i-Encore, i-EPIC, i-Galaxy, i-HANEX, i-HDL Compiler, i-Hercules, i-Hierarchical Optimization Technology, i-High-performance ASIC Prototyping System, i-HSIMplus, i-Virtual Stepper, i-IICE, i-Sync, iN-Tandem, i-Intelli, iJupiter-TDP, iJupiter-XDP, iJupiter-XDP, i-SIC Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphaxer, Ripple-Ripple, Slicco, Ripple, Ripple, Ripple SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, kunye ne-Worksheet Buffer ziimpawu zorhwebo ze-Synopsys, Inc.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Amanqaku eNkonzo (sm)
I-MAP-in, i-SVP Café, kunye ne-TAP-in ziimpawu zenkonzo ze-Synopsys, Inc. I-SystemC luphawu lwentengiso lwe-Open SystemC Initiative kwaye isetyenziswa phantsi kwelayisensi. I-ARM kunye ne-AMBA ziimpawu zorhwebo ezibhalisiweyo ze-ARM Limited. I-Saber luphawu lwentengiso olubhalisiweyo lwe-SabreMark Limited Partnership kwaye isetyenziswa phantsi kwelayisensi. Zonke ezinye iimveliso okanye amagama enkampani anokuba ziimpawu zorhwebo zabanini bazo.
Ishicilelwe e-USA ngo-Oktobha 2014

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Imixholo

Isahluko 1: Intshayelelo
I-Synopsys FPGA kunye neeMveliso zePrototyping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FPGA Implementation Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-17 Synopsys FPGA Tool Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Umda woxwebhu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ISeti yoXwebhu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Abaphulaphuli. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ndiyaqalisa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ukuqalisa iSoftware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ukufumana Uncedo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ujongano lomsebenzisi ngaphezuluview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Isahluko 2: FPGA Synthesis Design flows
Ukuhamba koYilo lweNgcaciso yeNgcaciso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Isahluko sesi-3: Ukulungiselela iNgeniso
Ukumisela uMthombo weHDL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ukudala umthombo we-HDL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ukusebenzisa Umhleli Woncedo Lomxholo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Ukujonga umthombo weHDL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Ukuhlela uMthombo weHDL Files ngoMhleli wokubhaliweyo oKwakhelwe ngaphakathi. . . . . . . . . . . . . . . . . . . . 35 Ukusetha Iifestile Zokuhlela Ezikhethwayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Ukusebenzisa Umhleli Wombhalo Wangaphandle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Ukusebenzisa Izandiso zeThala leeNcwadi kwiThala leeNcwadi laseVerilog Files. . . . . . . . . . . . . . . . . . . . . . . 42
Ukusebenzisa uMthombo woLwimi oluxubeneyo Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ukusebenzisa uMqokeleli woKwandiswa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Imida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ukusebenzisa i-Structural Verilog Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Imida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukusebenza ngokuQinisekisa Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Ukusetyenziswa Nini Isithintelo Files ngaphezulu kweKhowudi yoMthombo. . . . . . . . . . . . . . . . . . . . . . . . 53 Ukusebenzisa Umhleli Wesicatshulwa kwisinyanzelo Files (Ilifa) . . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Izikhokelo zeSintaksi zoMnyanzelo Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Ukujonga uMnyanzelo Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis
Ukuseta iProjekthi Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ukudala iProjekthi File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ukuvula iProjekthi esele ikhona File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Ukwenza iiNguqu kwiProjekthi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Ukumisela iProjekthi View Bonisa Okukhethwayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Uhlaziyo lweVerilog lubandakanya iindlela kwiProjekthi yaBadala Files. . . . . . . . . . . . . . . . . . . . 65
Iprojekthi yokulawula File Uluhlu lwemigangatho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ukudala iiFolda ngokweSiko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 UkuLawula iiFolda zeProjekthi yesiNtu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Ukulawula Isiko Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Ukumisela izixhobo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ukusebenza ngoPhumezo oluninzi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Ukuseta iiNdlela zokuSebenza zokuSebenza ngeNgcaciso . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ukuseta Iinketho zesiXhobo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ukuseta iiKhetho zokuSebenza. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Ukuchaza ukuQhoba rhoqo kunye nokunyanzeliswa kweHlabathi Files. . . . . . . . . . . . . . . . . . . . . . 80 Ukuchaza uKhetho lweziphumo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Ukuchaza isiphumo seNgxelo yeXesha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Ukuseta iinketho zeVerilog kunye neVHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Ukuchaza iimpawu kunye nezikhokelo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Ukuchaza iimpawu kunye nezikhokelo kwi-VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Ukuchaza iimpawu kunye nezikhokelo kwiVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . 92 Ukuchaza iimpawu zokuSebenzisa umhleli woMHLABA . . . . . . . . . . . . . . . . . . . . . . . . . 93 Ukuchaza iimpawu kwimiqobo File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Iyakhangela Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ukuchonga i Files ukukhangela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Ukucoca i Files ukukhangela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Ukuqalisa Ukukhangela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Iziphumo zoPhando . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LO
Ugcino-nkcukacha Files kunye neeProjekthi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Gcina iProjekthi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Suka iProjekthi kuVimba. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Khuphela iProjekthi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Isahluko 5: Ukuchaza imiqobo
Ukusebenzisa Umhleli woMDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ukudala imiqobo kuMhleli we-SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ukudala imiqobo ngomyalelo wesakhelo se-FDC . . . . . . . . . . . . . . . . 116
Ukuchaza imiqobo yoMHLABA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-119 yokuNgena kunye nokuHlela uMthinteli woMda. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Ukumisela iwotshi kunye nemiqobo yeNdlela. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ukuchaza imiqobo yegalelo kunye neziphumo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-122 echaza iMigangatho ye-I / O Iintlobo zePad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Ukusebenzisa i-TCL View ye GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Izikhokelo zokuNgena kunye nokuHlela izithintelo. . . . . . . . . . . . . . . . . . . . . . . . 127
Ukuchaza IiNdlela eziKhethekileyo zeXesha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Ukuchaza ukusuka/Ukuya/NgeeNgcaciso zeXesha eliKhethekileyo. . . . . . . . . . . . . . . . . 130 Ukuchaza iindlela zeMulticycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Ukuchaza Iindlela Zobuxoki . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Ukufumana izinto nge-Tcl fumana kwaye wandise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Ukuchaza iipateni zoPhando lwe-Tcl fumana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Ukucoca i-Tcl Fumana iziphumo ngesihluzo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Ukusebenzisa i-Tcl Fumana Umyalelo wokuchaza iiNgqokelela. . . . . . . . . . . . . . . . . . . . . 138 Ukusebenzisa i-Tcl ukwandisa Umyalelo wokuchaza iiNgqokelela. . . . . . . . . . . . . . . . . . 140 Ukukhangela i-Tcl ukufumana kunye nokwandisa Iziphumo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Ukusebenzisa i-Tcl fumana kwaye wandise kwiMowudi yeBatshi. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Ukusebenzisa Iingqokelela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Ukuthelekiswa kweendlela zokuchaza iiNgqokelela. . . . . . . . . . . . . . . . . . . . . . . 144 Ukuyila nokusebenzisa iingqokelela ze-SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Ukwenza iingqokelela usebenzisa i-Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Viewing kunye nokuLawula iiNgqokelela kunye neMiyalelo yeTcl. . . . . . . . . . . . . . . 150
Ukuguqula iSDC ibe yiFDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Ukusebenzisa i-SCOPE Editor (Ilifa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Ukungena nokuHlela uMthinteli woMDA (Ilifa) . . . . . . . . . . . . . . . . . . . . . 157 Ukuchaza UMHLABA weMithintelo yeXesha (Ilifa) . . . . . . . . . . . . . . . . . . . . . . . 159 Ukungena kwiMiqobo eMiselweyo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Ukuseta iwotshi kunye nemiqobo yeNdlela. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Ukuchaza iiwotshi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Ukuchaza imiqobo yegalelo kunye neziphumo (iLifa) . . . . . . . . . . . . . . . . . . . . . . . 169 Ukuchaza Iindlela Zobuxoki (Ilifa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-6: Ukudibanisa kunye nokuHlalutywa kweZiphumo
Ukudibanisa Uyilo Lwakho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Ukuqhuba iNgcaciso yeNgcaciso. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Ukusebenzisa uHlolo oluhlaziyiweyo kuLawulo lweMisebenzi. . . . . . . . . . . . . . . . . . . . . . 174
Ijonga iLog File Iziphumo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Viewukudibanisa kunye nokusebenza ngeLog File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Ukufikelela kwiiNgxelo eziKhethekileyo ngokukhawuleza . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Ukufikelela kwiziphumo ukude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Ukuhlalutya Iziphumo Ngokusebenzisa Ilog File Iingxelo . . . . . . . . . . . . . . . . . . . . . . . . . 189 Ukusebenzisa Ifestile Yewotshi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Ukujonga ukuSetyenziswa kweZibonelelo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Ukuphatha Imiyalezo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ukuqwalaselwa kweZiphumo kuMyalezo Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ukuhluza iMiyalezo eMyalezo Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Ukuhluza iMiyalezo evela kumgca womyalelo. . . . . . . . . . . . . . . . . . . . . . . . . . 197 UkuziSebenzisa Ukuhluza uMyalezo ngeSikripthi seTcl. . . . . . . . . . . . . . . . . . . . . . . . 198 Ilog File Ulawulo lomyalezo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Ukuphatha Izilumkiso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Ukusebenzisa Qhubeka kwimpazamo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Ukusebenzisa Qhubeka kwimposiso yoQoqoshela iNdibanisela yeeNqaku . . . . . . . . . . . . . . . . . . . 203
Isahluko 7: Ukuhlalutya kunye noMhlalutyi we-HDL kunye neFSM Viewer
Ukusebenza kwiSkimu Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Ukwahlula phakathi koMhlalutyi we-HDL Views. . . . . . . . . . . . . . . . . . . . . . . . 209 Ukuvula i Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Viewing Iimpahla zeNgcaciso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Ukukhetha izinto kwi-RTL/Technology Views. . . . . . . . . . . . . . . . . . . . . . . 215 Ukusebenza nge-Multisheet Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Ukuhamba Phakathi Views kwifestile yeSicwangciso. . . . . . . . . . . . . . . . . . . . . . . 218 Ukuseta isicwangciso View Ezikhethwayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Ukulawula iiWindows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Ukuphonononga iCandelo loyilo loyilo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Uluhlu loyilo oluThatyathayo kunye neSikhangeli seHierarchy. . . . . . . . . . . . . . . . 222 Ukuphonononga Uluhlu Lwezinto Ngokutyhala/UkuPopa. . . . . . . . . . . . . . . . . . . . . . . 223 Ukuphonononga Uluhlu lweNgcaciso yeemeko ezingafihliyo . . . . . . . . . . . . . . . . . . . 228
Ukufumana Izinto . . . . . . . . . . . . .LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Ukukhangela ukukhangela izinto kwi-HDL Umhlalutyi Views. . . . . . . . . . . . . . . . . . . . . . . 230 Ukusebenzisa i-Fund for Hierarchical and Restricted Searches . . . . . . . . . . . . . . . . . . . . 232 Ukusebenzisa i-Wildcards kunye ne-Find Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukudibanisa ukuFumana kunye nokuHlunga ukuCoca uPhando . . . . . . . . . . . . . . . . . . . . . . 240 Ukusebenzisa iFumana ukuPhendla uMnatha weZiphumo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing ngaphakathi kwe-RTL/Tekhnoloji View . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing evela kwi-RTL/Tekhnoloji View . . . . . . . . . . . . . . . . . . . . . . . . . I-244 iCrossprobing ukusuka kwifestile yoMhleli wokubhaliweyo. . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Ukuxilonga kwiTcl Script Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Ukuxilonga ukusuka kwiFSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Ukuhlalutya Ngesixhobo soHlalutyi lwe-HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Viewing Uyilo loBume boBume kunye noMxholo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Izicwangciso zoHlulo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Ukwandisa i-Pin kunye ne-Net Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Ukwandisa kunye ViewUqhagamshelo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 UkuThwalaza kweSikimu soLawulo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Ukunciphisa ukusetyenziswa kweMemori ngelixa uhlalutya uYilo. . . . . . . . . . . . . . . . . . . 267
Ukusebenzisa iFSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Isahluko 8: Ukuhlalutya ixesha
Ukuhlalutya ixesha kwiSchematic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 ViewUlwazi Lwexesha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Ingcaciso yeXesha leNkcukacha kwiSkimu Views. . . . . . . . . . . . . . . . . . 275 Ukuhlalutya iMithi yewotshi kwi-RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 ViewIiNdlela Ezibalulekileyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Ukuphatha I-Negative Slack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Ukuvelisa iiNgxelo zeXesha leSiko nge-STA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Ukusebenzisa uhlalutyo lweMiqathango yoYilo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Iimeko ezingama-284 zokuSebenzisa ukuHlalutya uMthintelo woYilo. . . . . . . . . . . . . . . . . . . . . . 285 Ukudala i-ADC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Ukusebenzisa Amagama Ezinto Ngokuchanekileyo kwi-adc File . . . . . . . . . . . . . . . . . . . . . . . . . 290
Ukusebenzisa izithintelo ezizenzekelayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Iziphumo ze-291 zeZithintelo ze-Auto. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Isahluko 9: Ukuchaza iZinto ezikwiNqanaba eliPhezulu
Ukuchaza iiBhokisi eziMnyama zeNdibaniselwano . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-298 yokufaka iibhokisi eziMnyama kunye ne-I / Os kwi-Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . Iibhokisi ze-298 eziqinisekisayo eziMnyama kunye ne-I/Os kwi-VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . I-300 Yongeza izithintelo zexesha leBhokisi eliMnyama. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Ukongeza Ezinye iimpawu zeBhokisi eziMnyama. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza oomatshini boMbuso boDityaniso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Ukuchaza oomatshini boMbuso kwiVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Ukuchaza oomatshini boMbuso kwi-VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Ukuchaza iiFSM ezineempawu kunye nezikhokelo . . . . . . . . . . . . . . . . . . . . . . . . 309
Ukuchaza iiFSM eziKhuselekileyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Inkcazo ye-RAM ezenzekelayo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Block RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Iimpawu ze-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-315 Ibhloko ye-RAM ye-Inferring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Ukuqalisa ii-RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Ukuqalisa ii-RAM kwi-Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Ukuqalisa ii-RAMs kwi-VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Isahluko se-10: Ukuchaza uLungiso lweNqanaba loYilo
Iingcebiso zokuSebenzisa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Iingcebiso ze-330 zokuSebenzisa ngokubanzi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Ukulungiselela iNdawo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Ukulungiselela uKubeka Ixesha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Ukubuyisela ixesha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Ukulawula Ukubeka ixesha kwakhona . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Ukubeka kwakhona ixesha Eksample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Ingxelo yokuHlaziya ixesha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Indlela Ukugcina Ixesha Okusebenza Ngayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Ukugcina Izinto Ekulungiselelweni Ukude . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Ukusebenzisa i-syn_keep ukuGcina okanye ukuPhinda . . . . . . . . . . . . . . . . . . . . . . . 343 Ukulawula ukuThwatyiswa koBurhulumente . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Ukugcina Ulawulo Lolawulo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Ukuphucula iFanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Ukumisela imida yeFanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Ukulawula ukuBhafa nokuPhinda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Ukwabelana ngezixhobo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Kufakwa ii-I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Ukuphucula oomatshini boMbuso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Ukwenza isigqibo ngexesha lokuSebenzisa oomatshini boMbuso. . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Ukuqhuba i-FSM Compiler LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Ukuqhuba iFSM Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Ukufaka iiProbes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza iiProbe kwiKhowudi yoMthombo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Ukongeza iimpawu zeProbe ngokuSebenzayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Isahluko 11: Ukusebenza ngamanqaku oQoqoshelo
Qokelela iiNkalo ezisisiseko. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Advantages yoYilo lweNqaku loQoqosha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Manual Qokelela amanqaku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Amanqaku aqokelelweyo aqokelelweyo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Qokelela Iindidi zeengongoma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Qokelela iSiseko seNqaku leNdibaniselwano. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Qokelela uMnyanzelo weeNqaku Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IiModeli zeNgcaciso ze-Interface 375. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Ixesha leNdibaniselwano yokuHlanganisa amanqaku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Qokelela iNdibanisela yeeNqaku . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-381 yokuNyula iNdibanisela yeeNgcaciso zeNgcaciso. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Phambili-inkcazo yoQuquzelelo lweMithintelo yeXesha leNdawo. . . . . . . . . . . . . . . . 384
Ukudityaniswa kwamanqaku okuqokelela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 INcwadana yoQoqoshelo lweNqaku lokuPhuma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Ukudala imiqobo ekwiNqanaba eliphezulu File Ukuqokelela amanqaku . . . . . . . . . . . . . . . . 388 Ukuchazwa kweNcwadana yokuQumba amanqaku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Ukumisela imiqobo kwiNqanaba leNqanaba lokuQeqesha. . . . . . . . . . . . . . . . . . . . . . . . 391 Ukuhlalutya Ukuqulunqa iziphumo zeNgcaciso. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Ukusebenzisa iiNqaku zokuhlanganisa kunye nezinye iimpawu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Ukudibanisa amaNqaku oQoqoshelo kunye nokuSetyenziswa okuninzi. . . . . . . . . . . . . . . . . . . . . . . 396
Ukwenziwa ngokutsha ngoKwenyukayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Ukudityaniswa ngokutsha kwamanqaku ahlanganisayo ngokuNgxamisekileyo . . . . . . . . . . . . . . . . . . . . . . . . . 397
Isahluko 12: Ukusebenza nge-IP Input
Ukuvelisa i-IP nge-SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Ukuchaza iiFIFO ngeSYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Ukuchaza ii-RAM nge-SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-408 ichaza i-Byte-Vulela ii-RAM nge-SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . 416 Ukuchaza iiROM ngeSYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Ukuchaza iAdder/Subtractors ezineSYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . 427 Ukuchaza izinto zokubala ezineSYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
I-Synopsys FPGA IP Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Ngaphezuluview yeSynopsys FPGA IP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Uguqulelo oluntsonkothileyo kunye neNguqulelo entsonkothileyo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Ukusebenza nge-IP Efihliweyo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Uguqulela i-IP yakho ngokuntsonkothileyo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Ufihlo lwe-IP nge-encryptP1735.pl Script. . . . . . . . . . . . . . . . . . . . . . . . . 448 Uguqulelo oluntsonkothileyo lwe-IP kunye ne-EncryptIP Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Ukuxela iNdlela yokuPhuma yeSikripthi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Ukulungiselela iPhakeji ye-IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Ukusebenzisa i-Hyper Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Ukusebenzisa uMthombo we-Hyper wePrototyping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-460 isebenzisa i-Hyper Source yoYilo lwe-IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Iimpawu ze-460 zokuTrula Ngokusebenzisa i-Design Hierarchy ye-IP. . . . . . . . . . . . . . . 461
Isahluko 13: Ukuphucula Iinkqubo zeMveliso
Ukusebenzisa iMowudi yeBatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Ukubaleka iMowudi yeBatshi kwiProjekthi File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Ukubaleka iMowudi yeBatshi ngeSikripthi seTcl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 iiLayisenisi zokufola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Ukusebenza nge-Tcl Scripts kunye neMiyalelo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Ukusebenzisa i-Tcl Imiyalelo kunye neziBhalo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Ukuvelisa Incwadi Yomsebenzi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Ukumisela inani leMisebenzi eFanayo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Ukwenza iSibhalo seTcl Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Ukusebenzisa ii-Tcl eziguquguqukayo zokuZama iiFrekhwekhwenzi zekloko ezahlukileyo. . . . . . . . . . . . . . . . . . 476 Ukusebenzisa ii-Tcl eziguquguqukayo zokuzama iiTekhnoloji ezininzi ekujoliswe kuzo. . . . . . . . . . . . . . . . . 478 Ukubaleka eMazantsi-phezulu uHlanganiso ngeSikripthi. . . . . . . . . . . . . . . . . . . . . . . . . . . 479
UziBhalisa ngokuzenzekela nge synhooks.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Isahluko 14: Ukusebenzisa i-Multiprocessing
I-Multiprocessing Ngamanqaku Okuqokelela . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-484 Ukumisela Imisebenzi Eyeyona Iphakamileyo Ehambelanayo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Ukusetyenziswa kweeLayisensi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Isahluko 15: Ukulungiswa kweMicrosemi Designs
Ukuphucula uYilo lweMicrosemi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Ukusebenzisa iiBhokisi eziMnyama zeMicrosemi ezichazwe kwangaphambili. . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Ukusebenzisa i-Smartgen Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Ukusebenza ngeRadhard Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Ichaza i-syn_radhardlevel kwiKhowudi yoMthombo. . . . . . . . . . . . . . . . . . . . . . . 490 LO
Isahluko 16: Ukusebenza kunye neSiphumo seNdibaniselwano
Ukudlulisa ulwazi kwi-P&R Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza iiNdawo zePin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IiNdawo ezingama-494 ezichaza iiNdawo zeeBhasi zeMicrosemi. . . . . . . . . . . . . . . . . . . . . . . . . I-495 ichaza iMakhro kunye noBhaliso loBeko. . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Ukuvelisa isiphumo esiKhethekileyo soMthengisi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Isiphumo sokuJolisa kuMthengisi wakho. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Ukwenza ngokwezifiso iiFomathi zeNetlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Isahluko se-17: Ukuqhutywa kweMisebenzi ye-Post-Synthesis
Ukubaleka i-P&R ngokuzenzekelayo emva kwe-Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Ukusebenza kunye Chonga izixhobo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Ukuqaliswa kwi-Synplify Pro Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Ukuphatha Iingxaki ngokuQaliswa Chonga . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Ukusebenzisa Isixhobo Sokuchonga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Ukusebenzisa iiNqaku zoQoqoshelo ngesixhobo sokuchonga. . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Ukulinganisa ngesixhobo seVCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

ISAHLUKO 1
Intshayelelo
Le intshayelelo yesoftware yeSynplify Pro® ichaza oku kulandelayo:
· Synopsys FPGA kunye nePrototyping Products, kwiphepha 16 · Scope of the Document, kwiphepha 21 · Ukuqalisa, kwiphepha 22 · User Interface Overview, kwiphepha 24

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 1: Intshayelelo

I-Synopsys FPGA kunye neeMveliso zePrototyping

I-Synopsys FPGA kunye neeMveliso zePrototyping
Lo mfanekiso ulandelayo ubonisa iSynopsys FPGA kunye nePrototyping yosapho lweemveliso.

LO
Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

I-Synopsys FPGA kunye neeMveliso zePrototyping

Isahluko 1: Intshayelelo

Izixhobo zokuphumeza iFPGA
Iimveliso ze-Synplify Pro kunye ne-Synplify Premier zizixhobo ze-RTL ze-synthesis ngokukodwa ezilungiselelwe i-FPGAs (i-field programmable gate arrays) kunye ne-CPLDs (izixhobo eziyinkimbinkimbi ezicwangcisiweyo).

Synplify Pro Synthesis Software
I-Synplify Pro FPGA synthesis software ngumgangatho woshishino we-de facto wokuvelisa ukusebenza okuphezulu, ukuyila kweFPGA engabizi kakhulu. Yayo yodwa
I-Behaviour Extracting Synthesis Technology® (BEST) i-algorithms, yenza
ulungiselelo olukwinqanaba eliphezulu phambi kokudibanisa ikhowudi ye-RTL kwingqiqo ethile yeFPGA. Le ndlela ivumela ukwenziwa okungaphezulu kuyo yonke iFPGA, amaxesha okusebenza akhawulezayo, kunye nokukwazi ukuphatha uyilo olukhulu kakhulu. I-software ye-Synplify Pro isekela i-VHDL yamva nje kunye ne-Verilog yolwakhiwo lolwimi olubandakanya i-SystemVerilog kunye ne-VHDL 2008. Isixhobo sibuchwephesha obuzimeleyo obuvumela ukubuyisela ngokukhawuleza nokulula phakathi kwezixhobo ze-FPGA kunye nabathengisi beprojekthi yoyilo olulodwa.

Synplify Premier Synthesis Software
Ukusebenza kweNkulumbuso ye-Synplify yi-superset yesixhobo se-Synplify Pro, ebonelela ngokuphunyezwa kwe-FPGA yokugqibela kunye nokulungisa imeko. Ibandakanya uluhlu olubanzi lwezixhobo kunye nobuchwepheshe babayili beFPGA ephucukileyo, kwaye ikwasebenza njengenjini yokudibanisa yeeprotoyipu zeASIC ezijolise kwiiprototypes ezisekelwe kwiFPGA enye.
Imveliso ye-Synplify yeNkulumbuso ibonelela ngabayili beFPGA kunye neeprototyper ze-ASIC ezijolise kwii-FPGA enye ngeyona ndlela isebenzayo yomiliselo loyilo kunye nolungiso. Kwicala lokuphunyezwa koyilo, kubandakanya ukusebenza kokuvalwa kwexesha, ukuqinisekiswa kwengqiqo, ukusetyenziswa kwe-IP, ukuhambelana kwe-ASIC, kunye nokuphunyezwa kwe-DSP, kunye nokudibanisa okuqinileyo kunye ne-FPGA yomthengisi we-back-end tools. Kwicala le-debug, ibonelela ngokuqinisekiswa kwenkqubo ye-FPGAs ethi ikhawulezise inkqubo yolungiso, kwaye ibandakanya indlela ekhawulezayo neyonyukayo yokufumana iingxaki zoyilo oluntsokothileyo.

Iimpawu zeSixhobo ze-Synopsys FPGA
Le theyibhile yahlula phakathi komsebenzi omkhulu kwi-Synplify Pro, Synplify, Synplify Premier, kunye ne-Synplify Premier kunye neemveliso ze-Design Planner.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 1: Intshayelelo

I-Synopsys FPGA kunye neeMveliso zePrototyping

Synplify Synplify Pro

Ukusebenza

I-Synthesis yokukhupha ukuziphatha

ITekhnoloji® (BESTTM)

I-Core/IP eyenziwe ngumthengisi

Inkxaso (ubugcisa obuthile)

FSM Compiler

FSM Explorer

Uguqulo Lwewotshi eGated

Bhalisa iPipelining

Bhalisa Retimeing

SCOPE® uMnyanzelo woNgeno

Iimpawu ezithembekileyo eziphezulu

Indawo kunye nendlela edibeneyo

Uhlalutyo

Umhlalutyi we-HDL®

Ukhetho

Umhlalutyi wexesha

Yalatha-kwinqaku

FSM Viewer

Crossprobing

Indalo yeProbe Point

Identify® Instrumentor

Chonga iDebugger

Uhlalutyo lwamandla (SAIF)

Uyilo loMzimba

Isicwangciso soyilo File

Isabelo esinengqiqo kwiMimandla

Synplify iNkulumbuso
x
x
yesikisi
xx
xxxxx

Synplify iNkulumbuso DP
x
x
yesikisi
xx
xxxxx
xx

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

I-Synopsys FPGA kunye neeMveliso zePrototyping

Isahluko 1: Intshayelelo

Uqikelelo lweNdawo kunye neSabelo soMmandla weSikhoni sokuSebenziswa koMzimba uHlalutyi lwePhysical Synopsys DesignWare® iThala leeNcwadi leSiseko loRuntime Uyilo oluPhakamileyo Uyilo olomeleziweyo uLungiselelo oluKhawulezayo luDityaniswe kwimpazamo yeQela loYilo oluDityanisiweyo loYilo loLwimi oluQulutyayo Amanqaku okuYilwa kweHierarchical Designs Ilayisenisi yeBatch yoNyanelo iMode yeGQI kuphela IMode yeBatch P&R Inkcazo yangasemva yeP&R yoQinisekiso olusesikweni lweDatha

Synplify Synplify Pro

xxx

–

Chonga Udibaniso

Ilinganiselwe

Synplify iNkulumbuso
xxx
xxxx
xxx
x
x Imo yokudityaniswa kweNgqiqo x

Synplify iNkulumbuso DP
x
xxxx
xxxx
xxx
x
xx Imowudi yokudityaniswa kweNgqiqo
x

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 1: Intshayelelo

I-Synopsys FPGA kunye neeMveliso zePrototyping

Inkcazo ngasemva yeP&R Data Design Environment Text Editor View Ifestile yoMyalezo wefestile yeTcl Window yokuSetyenziswa okuninzi koMthengisi ngeTekhnoloji yeNkxaso yePrototyping Amanqaku exesha lokuqhuba Qokelela amanqaku eGated Clock yoGuquko Luhlanganisela kwimpazamo

Synplify Synplify Pro

Synplify iNkulumbuso
xxxx Ikhethiwe
xxx

Synplify iNkulumbuso DP
x
xxxx Ikhethiwe
xxx

LO
Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Umda woxwebhu

Isahluko 1: Intshayelelo

Umda woxwebhu
Oku kulandelayo kuchaza umda wolu xwebhu kunye nabantu ekujoliswe kubo.

ISeti yoXwebhu
Esi sikhokelo somsebenzisi yinxalenye yesethi yoxwebhu ebandakanya incwadi yesalathiso kunye nesifundo. Yenzelwe ukusetyenziswa namanye amaxwebhu akwiseti. Igxile ekuchazeni indlela yokusebenzisa iSynopsys FPGA isoftwe ukufezekisa imisebenzi eqhelekileyo. Oku kuthetha oku kulandelayo:
· Isikhokelo somsebenzisi sichaza kuphela ukhetho olufunekayo ukwenza imisebenzi eqhelekileyo
ichazwe kwincwadana. Ayichazi yonke imiyalelo ekhoyo kunye nokhetho. Ukufumana iinkcazo ezipheleleyo zazo zonke iinketho zomyalelo kunye nesintaksi, bhekisa kuMsebenzisi weNdibaniselwano ngaphezuluview isahluko kwi-Synopsys FPGA Synthesis Reference Manual.
· Isikhokelo somsebenzisi siqulathe ulwazi olusekwe kumsebenzi. Ngokwaphulwa kwe
indlela elungelelaniswa ngayo inkcazelo, funda incwadi ethi Ukufumana Uncedo, kwiphepha 22.

Abaphulaphuli
Isixhobo sesoftware yeSynplify Pro sijolise kumphuhlisi wenkqubo yeFPGA. Kucingelwa ukuba unolwazi malunga noku kulandelayo:
· Uqulunqo loyilo · RTL · FPGAs · Verilog/VHDL

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 1: Intshayelelo

Ndiyaqalisa

Ndiyaqalisa
Eli candelo likubonisa ukuba ungaqala njani nge-Synopsys FPGA synthesis software. Ichaza ezi zihloko zilandelayo, kodwa ayithathi indawo yolwazi kwimiyalelo yokuhlohla malunga nelayisensi kunye nofakelo:
· Ukuqala iSoftware, kwiphepha 22 · Ukufumana Uncedo, kwiphepha lama-22

Ukuqalisa iSoftware
1. Ukuba awukakwenzi oko, faka i-Synopsys FPGA synthesis software ngokwemiyalelo yokuhlohla.
2. Qala isoftware.
Ukuba usebenza kwiqonga leWindows, khetha
Iinkqubo-> I-Synopsy-> inguqulelo yemveliso ukusuka kwiqhosha lokuqala.
Ukuba usebenza kwiqonga le-UNIX, chwetheza ngokufanelekileyo
umyalelo kumgca womyalelo:
synplify_pro
· Umyalelo uqalisa isixhobo sokuhlanganisa, kwaye uvule iProjekthi yefestile. Ukuba
ukhe wasebenzisa isoftware ngaphambili, iwindow ibonisa iprojekthi yangaphambili. Ngolwazi oluthe vetshe malunga nojongano, bona i-User Interface Overview isahluko seNcwadana yeeNgcaciso.

Ukufumana Uncedo
Phambi kokuba ufowunele iSynopsys Support, jonga ulwazi olubhaliweyo. Ungafikelela kulwazi olukwi-intanethi kwimenyu yoNcedo, okanye ubhekisele kwinguqulelo yePDF. Le theyibhile ilandelayo ikubonisa indlela ulwazi olucwangciswe ngayo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ndiyaqalisa
Ukufumana uncedo nge... Ukusebenzisa iimpawu zesoftware Uzenza njani...
Ulwazi oluqukuqelayo
Imiyalezo yemposiso Iimpawu zonikezelo lwelayisensi kunye nezikhokelo Iimpawu zeNdibaniselwano Ulwimi kunye nesintaksi Tcl isivakalisi semiyalelo ye-Tcl synthesis Uhlaziyo lwemveliso

Isahluko 1: Intshayelelo
Jonga kwi... Synopsys FPGA Synthesis User Guide Synopsys FPGA Synthesis User Guide, amanqaku esicelo kwinkxaso web site Synopsys FPGA Synthesis User Guide, amanqaku isicelo kwinkxaso web indawo Uncedo lwe-Intanethi (khetha Uncedo->Imiyalezo yemposiso) Synopsys SolvNet Website Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Uncedo olukwi-Intanethi (khetha Uncedo->Tcl Uncedo) Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference ManualWeb imiyalelo yemenyu)

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 1: Intshayelelo

Ujongano lomsebenzisi ngaphezuluview

Ujongano lomsebenzisi ngaphezuluview
Ujongano lomsebenzisi (UI) luqulathe ifestile engundoqo, ebizwa ngokuba yiProjekthi view, kunye neefestile ezikhethekileyo okanye views kwimisebenzi eyahlukeneyo. Ukufumana iinkcukacha malunga nefitsha nganye, bona iSahluko sesi-2, isiNxulumanisi esiPheleleyoview yeSynopsys FPGA Synthesis Reference Manual.

Synplify Pro Interface

Iqhosha lePhaneli

Iprojekthi yeebar zesixhobo view

Ubume

Iziphumo zoPhumezo view

Iithebhu zokufikelela views

Tcl Script/iMiyalezo Window LO

Ifestile yokujonga

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

ISAHLUKO 2
I-FPGA yoYilo loQhagamshelwano luyahamba
Esi sahluko sichaza iLogic Synthesis Design Flow, kwiphepha lama-26.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 2: FPGA Synthesis Design flows

Logic Synthesis Design Flow

Izixhobo ze-Synopsys FPGA zidibanisa ingqiqo ngokuqala ngokuqulunqa umthombo we-RTL kwizakhiwo ezizimeleyo zetekhnoloji, kwaye emva koko ulungelelanisa kwaye wenze imephu ingqiqo kwizixhobo ezithe ngqo kubuchwepheshe. Emva kokuhlanganiswa kwengqiqo, isixhobo sivelisa uluhlu lwe-netlist olukhethekileyo kunye nomqobo. file onokuzisebenzisa njengamagalelo kwindawo-kunye-nendlela (P&R) isixhobo.
Lo mzobo ulandelayo ubonisa izigaba kunye nezixhobo ezisetyenzisiweyo kwi-logic synthesis kunye namanye amagalelo amakhulu kunye neziphumo. Ungasebenzisa i-Synplify Pro synthesis software kolu qukuqelo. Uhlalutyo lwexesha lokusebenzisana luyakhethwa. Nangona ukuhamba kubonisa umqobo womthengisi files njengamagalelo athe ngqo kwisixhobo seP&R, kufuneka udibanise ezi files ukuya kwiprojekthi yodibaniso ukwenzela ixesha iibhokisi ezimnyama.

Synopsys FPGA Tool

RTL

Ukuqulunqwa kwe-RTL

FDC

I-logic Synthesis

Uluhlu lwenethi oludityanisiweyo lwezithintelo Imiqobo yomthengisi
Isixhobo somthengisi
Indawo & Indlela

Inkqubo yoQhagamshelwano lweNgqiqo

Ukuhamba koyilo kunye nemiyalelo yesinyathelo-nge-nyathelo esekelwe kuyilo oluthile

data, khuphela isifundo kwi webindawo. La manyathelo alandelayo ashwankathela

inkqubo yokudibanisa uyilo, nayo iboniswe kwi

umfanekiso olandelayo.

1. Yenza iprojekthi.

2. Yongeza umthombo files kwiprojekthi.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Logic Synthesis Design Flow

Isahluko 2: FPGA Synthesis Design flows

3. Misela iimpawu kunye nemiqobo yoyilo.
4. Cwangcisa iinketho zophunyezo kwibhokisi yencoko yababini yeeKhetho zoPhumezo.
5. Cofa u-Run ukuze usebenzise i-logic synthesis.
6. Hlalutya iziphumo, usebenzisa izixhobo ezifana nelogi file, i-HDL Analyst schematic views, ifestile yoMyalezo kunye nefestile yokubukela.
Emva kokuba ugqibile uyilo, ungasebenzisa imveliso files ukuqhuba indawo-kunye-umzila kunye nesixhobo somthengisi kunye nokuphumeza i-FPGA.
Lo mfanekiso ulandelayo udwelisa amanyathelo aphambili ekuhambeni:

Yenza iProjekthi
Yongeza uMthombo Files
Misela imiqobo
Seta Iinketho
Qhuba iSoftware
Hlalutya Iziphumo Akukho manqaku Afikelelwe?
Ewe Indawo kunye neNdlela

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 2: FPGA Synthesis Design flows

Logic Synthesis Design Flow

LO
Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

ISAHLUKO 3
Ukulungiselela iNgeniso
Xa udibanisa uyilo, kufuneka usete iindidi ezimbini ze files: HDL fileezichaza uyilo lwakho, kunye neprojekthi files ukulawula uyilo. Esi sahluko sichaza iinkqubo zokuseka ezi files kunye neprojekthi. Ibandakanya oku kulandelayo:
· Ukumisela uMthombo weHDL Files, kwiphepha 30 · Ukusebenzisa uMthombo woLwimi oluxubeneyo Files, kwiphepha 44 · Ukusebenzisa i-Inremental Compiler, kwiphepha 49 · Ukusebenzisa i-Structural Verilog Flow, kwiphepha 51 · Ukusebenza ngokunyanzeliswa Files, kwiphepha 53

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

Ukumisela uMthombo weHDL Files
Eli candelo lichaza indlela yokuseta umthombo wakho files iprojekthi file ukuseta kuchazwe kwiProjekthi yokuSeta Files, kwiphepha 58. Umthombo files inokuba kwiVerilog okanye iVHDL. Ngolwazi malunga nolwakhiwo lwe files ukwenzela udibaniso, bhekisa kwiNcwadi yeeReferensi. Eli candelo lixoxa ngezi zihloko zilandelayo:
· Ukwenza uMthombo weHDL Files, kwiphepha 30 · Ukusebenzisa uMxholo woNcedo loMhleli, kwiphepha 32 · Ukujonga uMthombo weHDL Files, kwiphepha 34 · Ukuhlela Umthombo weHDL Files kunye noHlelo lweSibhalo esakhelwe-ngaphakathi, kwiphepha 35 · Ukusebenzisa umhleli weSibhalo saNgaphandle, kwiphepha 41 · Ukucwangcisa Okukhethwayo kwefestile, kwiphepha 39 · Ukusebenzisa Izandiso zeThala leeNcwadi kwiThala leeNcwadi leVerilog Files, kwiphepha 42

Ukudala uMthombo weHDL Files
Eli candelo lichaza indlela yokusebenzisa umhleli wokubhaliweyo owakhelwe-ngaphakathi ukwenza umthombo files, kodwa ayingeni kwiinkcukacha ze files ziqulathe. Ngeenkcukacha zezinto onokuthi uzibandakanye nongakwaziyo ukuzifaka, kunye nolwazi oluthe ngqo kumthengisi, jonga iReference Manual. Ukuba sele unayo umthombo files, ungasebenzisa umhleli wokubhaliweyo ukujonga isintaksi okanye ukuhlela i file (jonga ukujonga uMthombo weHDL Files, kwiphepha 34 kunye noHlelo lweHDL Source Files ngoMhleli weTeksti eyakhelwe-ngaphakathi, kwiphepha lama-35).
Ungasebenzisa iVerilog okanye iVHDL kumthombo wakho files. I files babe v (Verilog) okanye vhd (VHDL) file izandiso, ngokulandelelanayo. Ungasebenzisa iVerilog kunye neVHDL files kuyilo olufanayo. Ngolwazi malunga nokusebenzisa umxube we-Verilog kunye ne-VHDL yokufaka files, bona Ukusebenzisa uMthombo woLwimi oluxubeneyo Files, kwiphepha 44.
1. Ukwenza umthombo omtsha file nokuba ucofa i HDL file i icon ( ) okanye yenza oku kulandelayo:
Khetha File-> Entsha okanye cinezela Ctrl-n.
Kwibhokisi yencoko yababini Entsha, khetha uhlobo lomthombo file ufuna ukwenza,
Verilog okanye VHDL. NotLeOkuba ungasebenzisa uMhleli woNcedo loMxholo woyilo lweVerilog equlathe iSystemVerilog eyakha kumthombo

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukumisela uMthombo weHDL Files

Isahluko sesi-3: Ukulungiselela iNgeniso

file. Ngolwazi oluthe vetshe, jonga Ukusebenzisa Umhleli Woncedo Lomxholo, kwiphepha lama-32.
Ukuba usebenzisa ifomathi ye-Verilog 2001 okanye i-SystemVerilog, qiniseka ukuba wenze i-Verilog 2001 okanye i-System Verilog ukhetho phambi kokuba usebenzise i-synthesis (Iprojekthi-> IiNdlela zokuSebenza-> ithebhu ye-Verilog). I-Verilog engagqibekanga file ifomathi yeeprojekthi ezintsha yiSystemVerilog.

Chwetheza igama kunye nendawo ye file kwaye Cofa u-Kulungile. Ukuhlelwa okungenanto
ifestile ivula ngamanani emigca ekhohlo.
2. Chwetheza ulwazi lwemvelaphi kwifestile, okanye usike kwaye uncamathisele. Bona ukuhlela uMthombo weHDL Files ngoMhleli wokubhaliweyo oKwakhelwe-ngaphakathi, kwiphepha lama-35 ngolwazi oluthe kratya ekusebenzeni kwifestile yokuHlela.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

Ukufumana ezona ziphumo zilungileyo zokudibanisa, jonga iNcwadana yeReferensi kwaye uqinisekise ukuba usebenzisa ulwakhiwo olukhoyo kunye neempawu ezikhethekileyo zomthengisi kunye nemiyalelo ngokufanelekileyo.
3. Gcina ifayile ye file ngokukhetha File-> Gcina okanye i icon Gcina ( ).
Nje ukuba udale umthombo file, ungajonga ukuba une-syntax efanelekileyo, njengoko ichaziwe kuMthombo we-HDL Files, kwiphepha 34.

Ukusebenzisa uMhleli woNcedo lomxholo
Xa udala okanye uvula uyilo lweVerilog file, sebenzisa iNcedo loMxholo iqhosha eliboniswe ezantsi kwefestile ukukunceda ikhowudi ngeVerilog/SystemVerilog yakha kwimvelaphi file okanye Tcl imiyalelo yesithintelo kwi Tcl yakho file.
Ukusebenzisa uMhleli woNcedo loMxholo:
1. Cofa kwiqhosha loNcedo loMxholo ukubonisa lo mhleli wokubhaliweyo.

LO
Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukumisela uMthombo weHDL Files

Isahluko sesi-3: Ukulungiselela iNgeniso

2. Xa ukhetha ukwakha kwicala lasekhohlo lefestile, ingcaciso yoncedo lwe-intanethi yolwakhiwo iyaboniswa. Ukuba ulwakhiwo olukhethiweyo lunoluphawu lwenziwe, isihloko soncedo lwe-intanethi siboniswe phezulu kwefestile kwaye ikhowudi yegeneric okanye itemplate yomyalelo wolwakhiwo iboniswa ezantsi.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

3. Iqhosha elithi Faka iSakhelo seKhompyutha nalo livuliwe. Xa ucofa iqhosha elithi Faka iSakhelo seSakhelo, ikhowudi okanye umyalelo oboniswe kwifestile yetemplate ufakwe kweyakho file kwindawo yekhesa. Oku kukuvumela ukuba ufake ngokulula ikhowudi okanye umyalelo kwaye uyilungise kuyilo oza kulwenza.
4. Ukuba ufuna ukukhuphela kuphela iindawo zetemplate, khetha ikhowudi okanye umyalelo ofuna ukuwufaka uze ucofe Khuphela. Emva koko ungayincamathisela kweyakho file.

Ukujonga uMthombo weHDL Files

Isoftware ijonga ngokuzenzekelayo umthombo wakho weHDL files xa iziqokelela, kodwa ukuba ufuna ukukhangela ikhowudi yemvelaphi yakho phambi kokudityaniswa, sebenzisa le nkqubo ilandelayo. Kukho iindidi ezimbini zokuhlola ozenzayo kwi-software yodibaniso: i-syntax kunye ne-synthesis.

1. Khetha umthombo files ufuna ukujonga.
Ukukhangela yonke imvelaphi files kwiprojekthi, yeka ukukhetha zonke files kwi
uluhlu lweprojekthi, kwaye uqinisekise ukuba akukho nanye kwi files zivuliwe kwifestile esebenzayo. Ukuba unomthombo osebenzayo file, isoftwe ijonga kuphela esebenzayo file.
Ukujonga enye file, vula i file nge File-> Vula okanye ucofe kabini i
file kwiProjekthi yefestile. Ukuba ungaphezulu kwesinye file vula kwaye ufuna ukujonga enye yazo kuphela, beka ikhesa yakho kwindawo efanelekileyo file window ukuqinisekisa ukuba yifestile esebenzayo.

2. Ukujonga isintaksi, khetha u-Run->Syntax Jonga okanye ucinezele uShift+F7.

Isoftware ibona iimpazamo zesintaksi ezifana namagama angundoqo angachanekanga kunye neziphumlisi kwaye inike ingxelo naziphi na iimpazamo kwilogi eyahlukileyo. file (isintaksi.log). Ukuba akukho ziphoso zifunyenweyo, ujongo oluyimpumelelo lwesintaksi luxelwa emazantsi oku file.

3. Ukwenza uqwalaselo lwe-synthesis, khetha Qhuba->Synthesis Khangela okanye ucinezele uShift+F8.

Isoftware ibhaqa iimpazamo ezinxulumene nehardware njengekhowudi engalunganga

flip-flops kwaye uxele naziphi na iimpazamo kwilog eyahlukileyo file (isintaksi.log). Ukuba kukho

akukho ziphoso, ukhangelo lwe-syntax oluyimpumelelo luxelwe ezantsi koku

file.

4. hlekaview iimpazamo ngokuvula i-syntax.log file xa uyalelwa kwaye usebenzise Khangela ukufumana umyalezo wemposiso (khangela @E). Cofa kabini kwi

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukumisela uMthombo weHDL Files

Isahluko sesi-3: Ukulungiselela iNgeniso

Ikhowudi yempazamo yoonobumba aba-5 okanye ucofe kumbhalo womyalezo kwaye utyhale u-F1 ukubonisa uncedo lomyalezo wempazamo kwi-Intanethi.
5. Khangela inxalenye yekhowudi enoxanduva lwempazamo ngokunqakraza kabini kwisicatshulwa somyalezo kwi-syntax.log file. Ifestile yoMhleli wokubhaliweyo ivula imvelaphi efanelekileyo file kwaye iqaqambisa ikhowudi ebangele impazamo.
6. Phinda amanyathelo 4 kunye ne-5 de zonke iimpazamo zesintaksi kunye ne-synthesis zilungiswe.
Imiyalezo ingahlelwa njengeempazamo, izilumkiso, okanye amanqaku. Review yonke imiyalezo kunye nokusombulula naziphi na iimpazamo. Izilumkiso azibi kangako kuneempazamo, kodwa kufuneka uzifunde kwaye uziqonde nokuba awuzisombululi zonke. Amanqaku anolwazi kwaye akufuneki ukuba asonjululwe.

Ukuhlela uMthombo weHDL Files ngoMhleli wokubhaliweyo oKwakhelwe ngaphakathi
Umhleli wombhalo owakhelwe-ngaphakathi wenza kube lula ukwenza ikhowudi yomthombo wakho we-HDL, view ngayo, okanye uyihlele xa ufuna ukulungisa iimpazamo. Ukuba ufuna ukusebenzisa umhleli wokubhaliweyo wangaphandle, jonga Ukusebenzisa uHlelo lokubhaliweyo lwangaphandle, kwiphepha lama-41.
1. Yenza enye yezi zilandelayo ukuvula umthombo file ngenxa viewukulungisa okanye ukuhlela:
Ukuvula ngokuzenzekelayo eyokuqala file kuluhlu oluneempazamo, cofa F5.
Ukuvula ethile file, cofa kabini i file kwiProjekthi yefestile okanye
sebenzisa File-> Vula (Ctrl-o) kwaye ucacise umthombo file.
Ifestile yoMhleli wokubhaliweyo iyavula kwaye ibonise imvelaphi file. Imigca ineenombolo. Amagama angundoqo aluhlaza okwesibhakabhaka, kunye namazwana aluhlaza. Amaxabiso omtya abomvu. Ukuba ufuna ukuyitshintsha le mibala, jonga Ukucwangcisa Okukhethwayo kwefestile, kwiphepha 39.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

2. Ukuhlela a file, chwetheza ngqo kwifestile.
Le theyibhile ishwankathela imisebenzi yokuhlela eqhelekileyo onokuyisebenzisa. Ungasebenzisa kwakhona izibophelelo zebhodi yezitshixo endaweni yemiyalelo.

Uku...

Yenza...

Sika, khuphela, kwaye uncamathisele; Khetha umyalelo kwi popup (bamba phantsi hlehlisa, okanye wenze kwakhona intshukumo iqhosha lasekunene) okanye Hlela imenyu.

Yiya kumgca othile

Cofa u-Ctrl-g okanye ukhethe Hlela-> Yiya Ku, chwetheza inombolo yomgca, kwaye ucofe u-Kulungile.

Fumana umbhalo

Cofa Ctrl-f okanye ukhethe Hlela -> Fumana. Chwetheza umbhalo ofuna ukuwufumana, uze ucofe u-Kulungile.

Tshintsha umbhalo

Cofa u-Ctrl-h okanye ukhethe Hlela-> Buyisela. Chwetheza okubhaliweyo ofuna ukukufumana, kunye nombhalo ofuna ukuwubuyisela endaweni yawo. Cofa u-Kulungile.

Gqibezela igama elingundoqo

Chwetheza abalinganiswa abaneleyo ukuchonga ngokukodwa igama elingundoqo, kwaye ucinezele u-Esc.

Ukwalathisa umbhalo ekunene Khetha ibhloko, kwaye ucinezele i Tab. Ukwalathisa okubhaliweyo ekhohlo LSOkhetha ibhloko, kwaye ucinezele uShift-Tab.

Tshintshela konobumba abakhulu Khetha umbhalo, uze ukhethe Hlela->Okukwinqanaba Eliphambili->Onobumba abakhulu okanye ucinezele Ctrl-Shift-u.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukumisela uMthombo weHDL Files

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukuya… Tshintshela kunobumba omncinci Yongeza izimvo zebhlokhi
Hlela iikholamu

Yenza...
Khetha umbhalo, uze ukhethe Hlela->Ekuqhubekekayo->Onobumba abancinci okanye ucinezele Ctrl-u.
Beka ikhesa ekuqaleni kombhalo wezimvo, kwaye ukhethe Hlela->Ekukwinqanaba Eliphambili->Ikhowudi Yezimvo okanye ucinezele Alt-c.
Cinezela Alt, kwaye usebenzise iqhosha lemouse ekhohlo ukukhetha ikholamu. Kwamanye amaqonga, kufuneka usebenzise isitshixo apho ukusebenza kwe-Alt kufakwe kwimephu, njengeMeta okanye iqhosha ledayimane.

3. Ukusika kunye nokuncamathisela icandelo loxwebhu lwePDF, khetha i icon yokukhetha umbhalo omile okwe-T, gqamisa umbhalo owufunayo kwaye uyikopishe kwaye uyincamathisele kweyakho. file. I icon yokukhetha okubhaliweyo ikuvumela ukuba ukhethe iindawo zoxwebhu.
4. Ukwenza kunye nokusebenza ngeebhukhimakhi kwiyakho file, bona le theyibhile ilandelayo.
Iibhukhimaki yindlela efanelekileyo yokuhamba ixesha elide files okanye ukutsibela kumanqaku kwikhowudi obhekisa kuyo rhoqo. Ungasebenzisa ii-ayikhoni kwibar yesixhobo sokuHlela kule misebenzi. Ukuba awukwazi ukubona ibar yesixhobo ekunene kwefestile yakho, yenza ubungakanani kwezinye iibar zesixhobo.

Uku... Faka ibhukmakhi
Cima ibhukhimakhi
Cima zonke iibhukhimaksi

Yenza...
Cofa naphi na kumgca ofuna ukuwuphawula. Khetha Hlela->Guqula Amanqaku encwadi, cofa Ctrl-F2, okanye ukhethe i icon yokuqala kwibar yesixhobo sokuHlela. Inombolo yomgca igxininiswe ukubonisa ukuba kukho ibhukhimakhi ekuqaleni kwalo mgca.
Cofa naphina emgceni ngebhukhmakhi. Khetha Hlela->Guqula Amanqaku encwadi, cofa Ctrl-F2, okanye ukhethe i icon yokuqala kwibar yesixhobo sokuHlela. Inombolo yomgca ayisaphawulwa emva kokuba ibhukhimakhi icinyiwe.
Khetha Hlela-> Cima zonke iiBhukhimaki, cofa Ctrl-Shift-F2, okanye ukhethe i icon yokugqibela kwibar yesixhobo sokuHlela. Amanani omgca awasaphawulwa emva kokuba iibhukhimakhi zicinyiwe.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

Uku...
Khangela a file usebenzisa iibhukhimaksi

Yenza...
Sebenzisa iBhukhmaki Elandelayo (F2) kunye neBhukhmaki yangaphambili (Shift-F2) imiyalelo esuka kwi Hlela menu okanye ii-iyikhoni ezihambelanayo ukusuka kwibar yesixhobo sokuhlela ukuya kwibhukmaki oyifunayo.

5. Ukulungisa iimpazamo okanye kwakhonaview izilumkiso kwikhowudi yomthombo, yenza oku kulandelayo:
Vula i-HDL file ngempazamo okanye isilumkiso ngokunqakraza kabini i file
kuluhlu lweprojekthi.
Cofa u-F5 ukuya kwimpazamo yokuqala, isilumkiso, okanye inqaku kwi file. E
ezantsi kwe Ukuhlelwa kwefestile, ubona umyalezo obhaliweyo.
Ukuya kwimpazamo elandelayo, isilumkiso, okanye inqaku, khetha u-Baleka->Impazamo Elandelayo/Isilumkiso
okanye cinezela F5. Ukuba akusekho miyalezo kwi file, ubona umyalezo "Akusekho ziphoso/Izilumkiso/Amanqaku" emazantsi efestile yokuHlela. Khetha u-Run->Impazamo elandelayo/Isilumkiso okanye ucinezele u-F5 ukuya kwimpazamo, isilumkiso, okanye inqaku elilandelayo. file.
Ukubuyela umva kwimpazamo yangaphambili, isilumkiso, okanye inqaku, khetha
Qhuba->Imposiso/Isilumkiso sangaphambili okanye ucinezele uShift-F5.
6. Ukuzisa uncedo lomyalezo wemposiso kwinkcazo epheleleyo yempazamo, isilumkiso, okanye inqaku:
Vula ilog yefomati yokubhaliweyo file (cofa View Log) kwaye nokuba nqakraza kabini kuyo
ikhowudi yempazamo enabasebenzi aba-5 okanye ucofe kumbhalo womyalezo kwaye ucinezele F1.
Vula ilog yeHTML file kwaye ucofe ikhowudi yempazamo yabasebenzi aba-5.
Kwifestile ye-Tcl, cofa i Imiyalezo tab kwaye ucofe kwi-5-uonobumba
ikhowudi yemposiso kwikholamu ye-ID.
7. Ukunqumla ikhowudi yefestile yemvelaphi ukuya kwenye views, vula i view kwaye ukhethe isiqwenga sekhowudi. Jonga i-Crossprobing kwiWindow yoMhleli weSibhalo, kwiphepha lama-246 ngeenkcukacha.
8. Xa sele uzilungisile zonke iimpazamo, khetha File-> Gcina okanye ucofe i icon Gcina ukugcina i file.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

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Isahluko sesi-3: Ukulungiselela iNgeniso

Ukucwangcisa Iifestile Zokuhlela Ezikhethwayo
Uyakwazi ukwenza ngokusesikweni iifonti kunye nemibala esetyenziswa kwifestile yoHlelo lokubhaliweyo.
1. Khetha Khetha->Ukhetho loMhleli kunye nokuba Umhleli weSynopsys okanye uMhleli waNgaphandle. Ngolwazi oluthe vetshe malunga nomhleli wangaphandle, jonga Ukusebenzisa uHlelo lweSibhalo saNgaphandle, kwiphepha lama-41.
2. Emva koko kuxhomekeke kuhlobo lwe file uyavula, ungacwangcisa imvelaphi, umbala wesintaksi, kunye nokhetho lwefonti onokusetyenziswa nomhleli wokubhaliweyo.

Qaphela: Emva koko, ukhetho lokuhlela okubhaliweyo olumisela oku file iya kusebenza kubo bonke files loku file uhlobo.

Ifestile yoHlelo lokubhaliweyo ingasetyenziswa ukuseta izikhethwa zeprojekthi files, umthombo files (Verilog/VHDL), log files, Tcl files, umqobo files, okanye enye into engagqibekanga files ukusuka kwi Iinketho zoMhleli ibhokisi yencoko yababini.
3. Unokuseta imibala yesivakalisi kwezinye iinketho eziqhelekileyo zesintaksi, ezifana namagama angundoqo, imitya, kunye nezimvo. Umzekeloample kwilog file, izilumkiso kunye neempazamo zinokufakwa ngombala ukuze ziqondwe lula.
Cofa kwindawo yangaPhambili okanye yangasemva ukwenzela into ehambelanayo kwibala loMbala leSyntax ukubonisa umbala wombala.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

Unokukhetha imibala esisiseko okanye uchaze imibala yesiko kwaye uyongeze kwiphalethi yombala wakho. Ukukhetha umbala owufunayo cofa u-Kulungile.
4. Ukuseta ifonti kunye nobungakanani befonti kumhleli wokubhaliweyo, sebenzisa iimenyu zokutsalela phantsi.
5. Khangela Gcina iiTab ukwenza useto lwethebhu lusebenze, emva koko usete isithuba sesithuba usebenzisa utolo oluphezulu okanye olusezantsi lweSize yeTab.

LO 6. Cofa u-OK kwi-Editor Options form.
© 2014 Synopsy, Inc. 40

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

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Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa Umhleli Wombhalo Wangaphandle
Ungasebenzisa umhleli wokubhaliweyo wangaphandle njenge vi okanye emacs endaweni yomhleli wokubhaliweyo owakhelwe-ngaphakathi. Yenza oku kulandelayo ukuze uvule umhleli wokubhaliweyo wangaphandle. Ngolwazi malunga nokusebenzisa umhleli wokubhaliweyo owakhelwe-ngaphakathi, jonga uMthombo wokuHlela weHDL Files ngoMhleli weSibhalo esakhelwe ngaphakathi, kwiphepha lama-35.
1. Khetha Khetha-> IiKhetho zoMhleli kwaye uvule uHlelo lwaNgaphandle ukhetho.
2. Khetha umhleli wangaphandle, usebenzisa indlela efanelekileyo kwinkqubo yakho yokusebenza.
Ukuba usebenza kwiqonga leWindows, cofa i ...(Khangela) iqhosha
kwaye ukhethe umhleli wokubhaliweyo wangaphandle ophunyeziweyo.
Ukusuka kwi-UNIX okanye iqonga leLinux lomhleli wokubhaliweyo owenza eyakhe
window, cofa i ... Khangela iqhosha kwaye ukhethe umhleli wokubhaliweyo wangaphandle ophunyeziweyo.
Ukusuka kwiqonga le-UNIX lomhleli wokubhaliweyo ongenzi eyakhe
window, sukusebenzisa i … Iqhosha lokukhangela iincwadi. Endaweni yoko chwetheza u-xterm -e umhleli. Lo mfanekiso ulandelayo ubonisa i-VI echazwe njengomhleli wangaphandle.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukumisela uMthombo weHDL Files

Ukusuka kwiqonga leLinux, kumhleli wokubhaliweyo ongenzi eyakhe
window, sukusebenzisa i … Iqhosha lokukhangela iincwadi. Endaweni yoko, chwetheza i-gnome-terminal -x umhleli. Ukusebenzisa iimacs kwi-example, chwetheza i-gnome-terminal -x emacs.
Isoftware ivavanyiwe ngeemacs kunye nabahleli bombhalo we-vi.
3. Cofa Kulungile.

Ukusebenzisa Izandiso zeThala leeNcwadi kwiThala leeNcwadi leVerilog Files
Izandiso zethala leencwadi zinokongezwa kwithala leencwadi laseVerilog files ibandakanyiwe kuyilo lwakho lweprojekthi. Xa unikezela ngeendlela zophendlo kubalawuli abaqulathe ilayibrari yeVerilog files, ungakhankanya ezi zandiso zamathala amatsha kunye neVerilog kunye neSystemVerilog (.v kunye .sv) file izandiso.
Ukwenza oku:
1. Khetha iVerilog ithebhu ye Uphumezo Iinketho zolawulo.
2. Cacisa iindawo zeeLayibrari zeThala leeNcwadi zethala leencwadi laseVerilog files ukuba ibandakanywe kuyilo lwakho lweprojekthi.
3. Chaza uLwandiso lweThala leeNcwadi.
Naziphi na izandiso zethala leencwadi zinokuchazwa, ezifana .av, .bv, .cv, .xxx, .va, .vas (ukwahlula izandiso zethala leencwadi ezinesithuba).
Lo mfanekiso ulandelayo ubonisa ukuba ungangenisa phi na izandiso zethala leencwadi kwibhokisi yencoko yababini.

LO
Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

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Isahluko sesi-3: Ukulungiselela iNgeniso

I-Tcl elingana nale exampngulo myalelo ulandelayo:
set_option -libext .av .bv .cv .dv .ev
Ukufumana iinkcukacha, bona libext, kwiphepha 57 kwiReferensi yoMyalelo.
4. Emva kokuba uqokelele uyilo, unokuqinisekisa kwilog file ukuba ithala leencwadi files ngezi zandiso zalayishwa kwaye zafundwa. Umzekeloample:
@N: Ukusebenzisa iVerilog Compiler kwimowudi yeSystemVerilog @I::”C:dirtop.v” @N: CG1180 :”C:dirtop.v”:8:0:8:3|Iyalayisha file C:dirlib1sub1.av kuluhlu lwethala leencwadi elikhankanyiweyo C:dirlib1 @I::”C:dirlib1sub1.av” @N: CG1180 :”C:dirtop.v”:10:0:10:3|Iyalayisha file C:dirlib2sub2.bv kuluhlu lwethala leencwadi elikhankanyiweyo C:dirlib2 @I::”C:dirlib2sub2.bv” @N: CG1180 :”C:dirtop.v”:12:0:12:3|Iyalayisha file

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Ukusebenzisa uMthombo woLwimi oluxubeneyo Files

C:dirlib3sub3.cv kuluhlu lwethala leencwadi elikhankanyiweyo C:dirlib3 @I::”C:dirlib3sub3.cv” @N: CG1180 :”C:dirtop.v”:14:0:14:3|Iyalayisha file C:dirlib4sub4.dv kuluhlu lwethala leencwadi elikhankanyiweyo C:dirlib4 @I::”C:dirlib4sub4.dv” @N: CG1180 :”C:dirtop.v”:16:0:16:3|Iyalayisha file C:dirlib5sub5.ev kuluhlu lwethala leencwadi elikhankanyiweyo C:dirlib5 @I::”C:dirlib5sub5.ev” Itshekhi yesivakalisi yeVerilog iphumelele!

Ukusebenzisa uMthombo woLwimi oluxubeneyo Files
Ngesoftware yeSynplify Pro, ungasebenzisa umxube weVHDL kunye neVerilog input files kwiprojekthi yakho. Umzekeloampiiles zeVHDL kunye neVerilog files, bona iManuwali yoReferensi.
1. Khumbula ukuba iVerilog ayixhasi izibuko zeVHDL ezinganyanzelwanga kwaye zisete uyilo oluxubileyo lolwimi files ngokufanelekileyo.
2. Ukuba ufuna ukulungelelanisa iVerilog kunye neVHDL files kwiifolda ezahlukeneyo, khetha Khetha->Iprojekthi View Iinketho kwaye utshintshe kwi View Iprojekthi Files kwi Iifolda ukhetho.
Xa udibanisa i files kwiprojekthi, iVerilog kunye neVHDL files zikwiifolda ezahlukeneyo kwiProjekthi view.
3. Xa uvula iprojekthi okanye udala entsha, yongeza iVerilog kunye neVHDL files ngolu hlobo lulandelayo:
Khetha iProjekthi->Yongeza uMthombo File umyalelo okanye ucofe i Faka File iqhosha. Kwifom, setha Files yoHlobo ukuya kwi-HDL Files (*.vhd, *.vhdl, *.v). Khetha iVerilog kunye neVHDL files oyifunayo kwaye wongeze kweyakho
iprojekthi. Cofa u-Kulungile. Ngeenkcukacha malunga nokongeza files kwiprojekthi, bona Ukwenza iiNguqu kwiProjekthi, kwiphepha 62.
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Ukusebenzisa uMthombo woLwimi oluxubeneyo Files

Isahluko sesi-3: Ukulungiselela iNgeniso

I fileoyongezileyo ziboniswa kwiProjekthi view. Lo mfanekiso ubonisa i files zicwangciswe kwiifolda ezahlukeneyo.
4. Xa useta iinketho zesixhobo (Iqhosha leeNdlela zokuSebenza), khankanya imodyuli yomgangatho ophezulu. Ngolwazi oluthe vetshe malunga nokuseta iinketho zesixhobo, jonga Ukuseta iiNketho zoPhumezo lweNgcaciso yeNgcaciso, kwiphepha lama-75.
Ukuba imodyuli yomgangatho ophezulu yiVerilog, cofa iVerilog tab kwaye uchwetheze i
igama lemodyuli yomgangatho ophezulu.
Ukuba imodyuli ekwinqanaba eliphezulu yiVHDL, cofa ithebhu yeVHDL kwaye uchwetheze igama
yeziko elikwinqanaba eliphezulu. Ukuba imodyuli yomgangatho ophezulu ayifumanekanga kwilayibrari yomsebenzi engagqibekanga, kufuneka ukhankanye ithala leencwadi apho umqokeleli angayifumana khona imodyuli. Ukuze ufumane inkcazelo ngendlela yokwenza oku, bona iPhaneli yeVHDL, kwiphepha 200.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa uMthombo woLwimi oluxubeneyo Files

Kufuneka ukhankanye ngokuthe gca umphakamo ophezulu womnqongo, kuba sisiqalo apho umephu uvelisa uluhlu lomnatha oludityanisiweyo.
5. Khetha ithebhu yeZiphumo zokuSebenza kwifom efanayo kwaye ukhethe ifomathi ye-HDL yemveliso enye yemveliso files yenziwe yisoftware. Ngolwazi oluthe vetshe malunga nokuseta iinketho zesixhobo, jonga Ukuseta iiNketho zoPhumezo lweNgcaciso yeNgcaciso, kwiphepha lama-75.
Kuluhlu lwemveliso yeVerilog, khetha Bhala iVerilog Netlist. Kuluhlu lwemveliso yeVHDL, khetha Bhala i-Netlist yeVHDL. Seta naluphi na olunye ukhetho lwesixhobo kwaye ucofe u-Kulungile.
Ngoku ungadibanisa uyilo lwakho. Isoftware ifunda kwiifomati ezixubileyo zomthombo files kwaye yenza i-srs enye file esetyenziselwa ukudibanisa.
6. Ukuba ufumana iingxaki, jonga i-Troubleshooting Mixed Language Designs, kwiphepha lama-47 ngolwazi olongezelelweyo kunye neengcebiso.
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Ukusebenzisa uMthombo woLwimi oluxubeneyo Files

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukulungisa uYilo lweeLwimi eziDibeneyo
Eli candelo libonelela ngeengcebiso malunga nokusingatha iimeko ezithile ezinokuza noyilo oluxubeneyo lolwimi.

VHDL File Umyalelo
Kuyilo lwe-VHDL-kuphela okanye uyilo oluxubeneyo apho umgangatho ophezulu ungachazwanga, izixhobo ze-FPGA zodityaniso ziphinda zicwangcise ngokuzenzekelayo iVHDL. files ukwenzela ukuba iipakethe ze-VHDL zihlanganiswe ngolandelelwano oluchanekileyo.
Nangona kunjalo, ukuba unoyilo lolwimi oluxubeneyo apho uchaze inqanaba eliphezulu, kufuneka uchaze i-VHDL file iodolo yesixhobo. Kufuneka wenze oku kube kanye kuphela, ngokukhetha i Qhuba->Lungisa iVHDL files umyalelo. Ukuba awukwenzi oku, ufumana umyalezo wemposiso.

Iimpawu zeVHDL zehlabathi
Okwangoku, awukwazi ukuba neempawu ze-VHDL zehlabathi kuyilo oluxubeneyo lolwimi, kuba isixhobo siphumeza le miqondiso kuphela kuyilo lwe-VHDL kuphela.

Ukupasa VHDL Boolean Generics ukuya Verilog Parameters
Isixhobo sifaka ibhokisi emnyama yecandelo le-VHDL kunye ne-Boolean generics, ukuba elo candelo liqinisekisiwe kuyilo lweVerilog. Oku kungenxa yokuba iVerilog ayizazi iintlobo zedatha yeBoolean, ngoko ke ixabiso leBoolean kufuneka limelwe ngokuchanekileyo. Ukuba ixabiso le VHDL Boolean generic yi TRUE kwaye i Verilog literal imelwe ngu 1, umqokeleli we Verilog utolika oku njengebhokisi emnyama.
Ukunqanda ukuthoba ibhokisi emnyama, iVerilog literal ye VHDL Boolean generic iseti TRUE kufuneka ibeyi 1'b1, hayi 1. Ngokufanayo, ukuba iVHDL Boolean generic yi FALSE, iVerilog ehambelanayo mayibe ngu 1'b0, hayi 0.ampi-le ibonisa indlela yokumela i-Boolean generics ukuze bagqithe ngokuchanekileyo umda we-VHDL-Verilog, ngaphandle kokwenza ibhokisi emnyama.

Isibhengezo seQumrhu leVHDL

Verilog Instantiation

Iqumrhu abc sisiGeneric (
Number_Bits Divide_Bit );

: inani elipheleleyo: boolean

:= 0; := Bubuxoki;

abc #( .Number_Bits (16), .Divide_Bit (1'b0)
)

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Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa uMthombo woLwimi oluxubeneyo Files

Ukudlula iVHDL Generics Ngaphandle kokuTyala iBhokisi emnyama
Kwimeko apho iVerilog component parameter, (for example [0:0] RSR = 1'b0) ayihambelani nobukhulu becandelo le-VHDL elihambelanayo (RSR : integer := 0), isixhobo sifaka ibhokisi emnyama.
Ungasebenza malunga noku ngokususa ubhalo lobubanzi bebhasi ye [0:0] kwiVerilog files. Qaphela ukuba kufuneka usebenzise iVHDL yegeneric yodidi olupheleleyo kuba ezinye iindidi azikuvumeli ukubophelela okufanelekileyo kwecandelo leVerilog.

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Ukusebenzisa uMqokeleli woKwandiswa

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa uMqokeleli woKwandiswa
Sebenzisa i-Inremental Compiler flow ukuze unciphise kakhulu ixesha lokusebenza lomqokeleli kuyilo olukhulu. Isoftware iphinda iqokelele efanelekileyo kuphela files xa utshintsho loyilo lwenziwa kwaye luphinda lusebenzise isiseko sedatha yomqokeleli. Umqokeleli uhlaziya i-SRS file kuphela kwimodyuli echaphazelekayo kunye nemodyuli yangoku yabazali.
Ukwenza oku kuhamba, yenza oku kulandelayo:
1. Yongeza iVerilog okanye iVHDL files yoyilo.
2. Yenza i-Inremental Compile ukhetho kwi-Verilog okanye i-VHDL ithebhu yePhaneli yoKhetho loPhumezo.
I-SRS file yenzelwe imodyuli yoyilo nganye kulawulo lwe synwork.

3. Qhuba umqokeleli okokuqala.
4. Ukuba utshintsho loyilo lwenziwe, phinda usebenzise umqambi.
Umqambi uhlalutya isiseko sedatha kwaye umisela ukuba i-SRS files zisexesheni, emva koko kuphela iimodyuli ezitshintshileyo kwaye iimodyuli zangoku zabazali ziyahlaziywa. Oku kunokunceda ukuphucula ixesha lokusebenza kuyilo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa uMqokeleli woKwandiswa

Ukulinganiselwa
Umqokeleli olongezelelekileyo akaxhasi:
· Ulungelelwaniso files ibandakanywe nokuba kuqukuqelo lweVerilog okanye lweVHDL · Ukuhanjiswa kweHDL okuDityanisiweyo · Uyilo olunereferensi yemodyuli enqamlezayo (XMR)

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Ukusebenzisa i-Structural Verilog Flow

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa i-Structural Verilog Flow
Isixhobo se-synthesis samkela i-Verilog yesakhiwo files njengegalelo leprojekthi yakho yoyilo. Umqokeleli wobume be-Verilog wenza uhlolo lwe-syntax ye-semantic usebenzisa i-parser yayo yobunzima bokukhanya ukuphucula ixesha lokusebenza. Lo mqokeleli akenzi izinto ezintsonkothileyo zehardware okanye imisebenzi yokwandisa i-RTL, ke ngoko, isoftware iqhuba ngokukhawuleza ukuqokelelwa kweVerilog yolwakhiwo. files. Isoftware inokufunda oku kuveliswe kwi-Verilog yesakhiwo files, ukuba ziqulathe:
· Amanyathelo okuqala eteknoloji
· Nika iinkcazo ezilula
· Iimpawu ezichazwe kwiVerilog 2001 kunye neefomathi ezindala
· Zonke izakhiwo, ngaphandle kweempawu kufuneka zichazwe kwifomathi yeVerilog 95
Ukusebenzisa igalelo le-Verilog yesakhiwo files:
1. Kufuneka ucacise iVerilog yesakhiwo files ukubandakanya kuyilo lwakho. Ukwenza oku, yongeza i file kwiprojekthi usebenzisa enye yezi ndlela zilandelayo:
Iprojekthi->Yongeza uMthombo File okanye i Faka File iqhosha kwiProjekthi view Tcl umyalelo: yongeza_file -umakhi fileIgama
Oku kuhamba kungaqulatha i-Verilog yolwakhiwo kuphela files okanye i-HDL exutywe files (iVerilog/VHDL/EDF/SRS) kunye noluhlu lomnatha lweVerilog files. Nangona kunjalo, iimeko zeVerilog/VHDL/EDF/SRS azixhaswanga ngaphakathi kwemodyuli yeVerilog.
2. I-Verilog yolwakhiwo files zongezwa kwisiqulathi seefayili zeStructural Verilog kwiProjekthi view. Ungongeza kwakhona files kolu lawulo, xa usenza oku kulandelayo:
Khetha iVerilog yolwakhiwo file. Cofa ekunene kwaye ukhethe File Iinketho. Khetha i-Structural Verilog kwi File Chwetheza imenyu eyehlayo.
3. Run synthesis.
Isixhobo sokudibanisa senza i-vm okanye i-edf netlist file kuxhomekeke kwitekhnoloji echaziweyo. Le nkqubo iyafana nokuhamba kolungelelwaniso olungagqibekanga.

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Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenzisa i-Structural Verilog Flow

Ukulinganiselwa
Unyino lokuhamba kwe-Verilog yesakhiwo ayikuxhasi oku kulandelayo:
· Imizekelo ye-RTL yayo nayiphi na enye file iintlobo · Ulawulo lweprojekthi yeHierarchical (HPM) ukuhamba · Izabelo ezintsonkothileyo · Iimowudi ezithe ngqo zoMqulunqi kunye nokutshintsha

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Ukusebenza ngokuQinisekisa Files

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenza ngokuQinisekisa Files
Ukunyanzelwa files zisicatshulwa files eveliswa ngokuzenzekelayo lujongano lweSCOPE (bona Ukuchaza imiqobo yoMHLABA, kwiphepha 119), okanye oyidalayo ngesandla ngomhleli wokubhaliweyo. Ziqulathe imiyalelo ye-Tcl okanye iimpawu ezicinezela udibaniso lwentsebenzo. Kungenjalo, unokuseta imiqobo kwikhowudi yemvelaphi, kodwa le ayisiyiyo indlela ekhethwayo.
Eli candelo liqulethe ulwazi malunga
· Ukusetyenziswa nini isithintelo Files phezu kweKhowudi yoMthombo, kwiphepha lama-53
· Ukusebenzisa umhleli weTeksti kuMnyanzelo Files (Ilifa), kwiphepha 54
· IziKhokelo zeSintaksi zeTcl zoMnyanzelo Files, kwiphepha 55
· Ukujonga uMnyanzelo Files, kwiphepha 56
· Ukufumana iinkcukacha ngale ngxelo, jonga iNgxelo yokuJonga iConstraint, kwi
iphepha 270.leNcwadana eneembekiselo, kwiphepha 56

Ukusetyenziswa nini isithintelo Files ngaphezulu kweKhowudi yoMthombo
Unokongeza izithintelo kwisithintelo files (iveliswe lujongano lweSCOPE okanye ingeniswe kumhleli wokubhaliweyo) okanye kwikhowudi yemvelaphi. Ngokuqhelekileyo, kungcono ukusebenzisa ukunyanzeliswa files, kuba akufuneki uqokelele kwakhona ukuze imiqobo isebenze. Yenza kwakhona ikhowudi yakho yomthombo iphatheke ngakumbi. Jonga Ukusebenzisa uHlelo loMDA, kwiphepha le-112 ngolwazi oluthe vetshe.
Nangona kunjalo, ukuba unebhokisi yebhokisi emnyama yemiqobo efana ne-syn_tco, syn_tpd, kunye ne-syn_tsu, kufuneka uzifake njengezikhokelo kwikhowudi yomthombo. Ngokungafaniyo neempawu, izikhokelo zinokongezwa kuphela kwikhowudi yomthombo, kungekhona ukunyanzeliswa files. Jonga Iimpawu zoKuchaza iimpawu kunye neziKhokelo, kwiphepha lama-90 ngolwazi oluthe vetshe ngokongeza izikhokelo kwikhowudi yomthombo.

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Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenza ngokuQinisekisa Files

Ukusebenzisa Umhleli Wesicatshulwa kwisinyanzelo Files (Ilifa)
Ungasebenzisa umhleli weLifa SCOPE kwisithintelo seSDC files yenziwe ngaphambi kokukhululwa kwenguqulo G-2012.09. Nangona kunjalo, kuyacetyiswa ukuba uguqulele iSDC yakho files ukuya kwi-FDC files ukwenza uguqulelo lwamva nje lomhleli weSCOPE kunye nokusebenzisa uphatho lwesithintelo sexesha esongeziweyo kwisixhobo.
Ukuba ukhetha ukusebenzisa umhleli we-SCOPE welifa, eli candelo likubonisa indlela yokwenza ngesandla isithintelo se-Tcl file. Isoftware yenza oku ngokuzenzekelayo file ukuba usebenzisa umhleli we-SCOPE welifa ukufaka imiqobo. Umqobo we-Tcl file iqulathe kuphela imiqobo yexesha jikelele. Imiqobo yebhokisi emnyama kufuneka ifakwe kwikhowudi yemvelaphi. Ngolwazi olongezelelweyo, jonga Xa Usetyenziswa nini Isithintelo Files phezu kweKhowudi yoMthombo, kwiphepha lama-53.
1. Vula a file ukuhlela.
Qinisekisa ukuba uyivalile ifestile ye-SCOPE, okanye unako
bhala ngaphezulu imiqobo yangaphambili.
Ukwenza entsha file, khetha File-> Entsha, kwaye ukhethe uMnyanzelo File
(SCOPE) ukhetho. Chwetheza igama le file kwaye ucofe u-OK.
Ukuhlela esele ikhona file, khetha File-> Vula, seta i Files yoHlobo lokucoca ukuya
Ukunyanzelwa Files (sdc) kwaye uvule i file ufuna.
2. Landela izikhokelo zesintaksi kwiTcl Syntax Guidelines for Constraint Files, kwiphepha 55.
3. Faka imiqobo yexesha oyifunayo. Ngesintaksi, bona iManuwali yoReferensi. Ukuba unesithintelo sexesha lebhokisi emnyama, kufuneka uzingenise kwikhowudi yemvelaphi.
4. Unokongeza iimpawu ezikhethekileyo zomthengisi kwisithintelo file usebenzisa define_attribute. Jonga Iimpawu ezichazayo kwiMithintelo File, kwiphepha 97 ukuze ufumane inkcazelo engakumbi.
5. Gcina ifayile ye file.
6. Yongeza i file kwiprojekthi njengoko kuchaziwe kwi-Ukwenza iiNguqu kwiProjekthi, kwiphepha lama-62, kwaye uqhube ulungelelwaniso.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukusebenza ngokuQinisekisa Files

Isahluko sesi-3: Ukulungiselela iNgeniso

Tcl Izikhokelo zeSintaksi zoMnyanzelo Files
Eli candelo liquka izikhokelo jikelele zokusebenzisa i-Tcl kwisithintelo files:
· I-Tcl inovelwano lwemeko.
· Ekunikweni amagama ezinto: Igama lento kufuneka lingqinelane negama elikwikhowudi ye-HDL. Vala umzekelo kunye namagama ezibuko ngaphakathi curliibrayisi {}. Musa ukusebenzisa izithuba emagameni. Sebenzisa ichaphaza (.) ukwahlula amagama oluhlu. Kwiimodyuli zeVerilog, sebenzisa le syntax ilandelayo umzekelo, izibuko, kunye
amagama entsalela:
v:iseli [isimaphambili:]objectName
Apho iseli ligama lequmrhu loyilo, isimaphambili simaphambili ukuchonga izinto ezinegama elifanayo, intoName yindlela yomzekelo enechaphaza (.) umahluli. Isimaphambili sinokuba nayiphi na kwezi zilandelayo:

Isimaphambili (Unobumba omncinci) i: p: b: n:

Into Amagama omzekelo

Kwiimodyuli zeVHDL, sebenzisa le syntax ilandelayo umzekelo, izibuko, kunye net
amagama kwiimodyuli zeVHDL:
v:iseli [.view] [isimaphambili:]objectName
Apho v: ichaza njenge view into, lib ligama lethala leencwadi, iseli ligama lequmrhu loyilo, view ligama lolwakhiwo, isimaphambili simaphambili ukuchonga izinto ezinegama elifanayo, kwaye objectName yindlela yomzekelo enechaphaza (.) umahluli. View ifuneka kuphela ukuba kukho ngaphezu kwesinye isakhiwo soyilo. Jonga kwitheyibhile engasentla malunga nezimaphambili zezinto.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-3: Ukulungiselela iNgeniso

Ukusebenza ngokuQinisekisa Files

· Amagama athelekisekayo amakhadi asendle ngala * (iinkwenkwezi zihambelana naliphi na inani
abalinganiswa) kunye ? (inqaku lombuzo lihambelana nomlinganiswa omnye). Aba nobumba abahambelani namachaphaza asetyenziswa njengabahluli boluhlu. UmzekeloampLe, umtya olandelayo ichonga onke amasuntswana omzekelo westatereg kumnqongo wemodyuli yemodyuli:
mna:statemod.statereg[*]

Ukujonga uMnyanzelo Files
Unokujonga i-syntax kunye nolunye ulwazi olufanelekileyo kwisithintelo sakho files usebenzisa i Constraint Khangela umyalelo. Ukwenza ingxelo yesithintelo, yenza oku kulandelayo:
1. Yenza umqobo file kwaye uyongeze kwiprojekthi yakho.
2. Khetha Qhuba->Jonga isithintelo.
Lo myalelo uvelisa ingxelo ejonga uvakalelo kunye nokusetyenziswa kwemithintelo yexesha kwiFPGA synthesis constraint. files yeprojekthi yakho. Ingxelo ibhaliwe kwiprojekthiName_cck.rpt file kwaye idwelise olu lwazi lulandelayo:
Izithintelo ezingasetyenziswanga Izithintelo ezisebenzayo nezisebenzayo kuyilo lwandiso lwe-Wildcard kwizithinteli Izithintelo kwizinto ezingekhoyo.
Ukufumana iinkcukacha ngale ngxelo, jonga iNgxelo yokuJonga iConstraint, kwiphepha lama-270

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ISAHLUKO 4
Ukuseta iProjekthi yoQhagamshelwano loQoqosho
Xa udibanisa uyilo nge-Synopsys FPGA izixhobo zokuhlanganisa, kufuneka umise iprojekthi yoyilo lwakho. Oku kulandelayo kuchaza iinkqubo zokuseta iprojekthi yelogic synthesis:
· Ukumisela iProjekthi Files, kwiphepha 58 · Iprojekthi yoLawulo File Ulawulo lolawulo, kwiphepha 66 · Ukuseta ukuSetyenziswa, kwiphepha 72 · Ukuseta iiNdlela zokuSetyenziswa kweNgcaciso yeSingqinisiso, kwiphepha 75 · Ukucacisa iimpawu kunye nezikhokelo, kwiphepha 90 · Ukukhangela Files, kwiphepha 98 · Ukugcinwa koovimba Files kunye neeProjekthi, kwiphepha le-101

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuseta iProjekthi Files

Ukuseta iProjekthi Files
Eli candelo lichaza iziseko zendlela yokuseka nokulawula iprojekthi file kuyilo lwakho, kuquka olu lwazi lulandelayo:
· Ukwenza iProjekthi File, kwiphepha 58 · Ukuvulwa kweProjekthi Ekhoyo File, kwiphepha 61 · Ukwenza iiNguqu kwiProjekthi, kwiphepha 62 · Ukumisela iProjekthi View Bonisa Okukhethwayo, kwiphepha 63 · Ukuhlaziya i-Verilog iquka iindlela kwiProjekthi endala Files, kwiphepha 65
Kwi-ex ethileampngokuseta iprojekthi file, bhekisa kwisifundo sesixhobo osisebenzisayo.

Ukudala iProjekthi File
Kuya kufuneka wenze iprojekthi file kwiprojekthi nganye. Iprojekthi iqulethe idatha efunekayo kuyilo oluthile: uluhlu lomthombo files, iziphumo zodibaniso file, kunye nesethingi yokhetho lwesixhobo sakho. Le nkqubo ilandelayo ikubonisa indlela yokuseta iprojekthi file usebenzisa imiyalelo yomntu.
1. Qala ngokukhetha enye yezi zilandelayo: File-> Yakha iProjekthi, File-> Vula iProjekthi, okanye uphawu lweP. Cofa iProjekthi Entsha.
Ifestile yeProjekthi ibonisa iprojekthi entsha. Cofa i Yongeza File iqhosha, cofa F4, okanye khetha iProjekthi->Yongeza uMthombo File umyalelo. Yongeza Files ukuya kwiProjekthi yebhokisi yencoko yababini iyavula.
2. Yongeza umthombo files kwiprojekthi.
Qinisekisa ukuba iJonga kwibala eliphezulu lefom likhomba ekunene
ulawulo. I files zidweliswe kwibhokisi. Ukuba awuyiboni i files, khangela ukuba i Files of Indawo yodidi imiselwe ukubonisa echanekileyo file uhlobo. Ukuba udibanise igalelo files, landela inkqubo echazwe kukusebenzisa uMthombo woLwimi oluHlangeneyo Files, kwiphepha 44.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iProjekthi Files

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukongeza zonke files kulawulo kwangoko, cofa i Yongeza Konke iqhosha kwi
icala lasekunene lefom. Ukufaka files ngabanye, nqakraza kwi file kuluhlu kwaye emva koko ucofe i Yongeza iqhosha, okanye nqakraza kabini i file igama.
Unokongeza zonke files kulawulo kwaye emva koko susa ezo ongazifuniyo nge Susa iqhosha.
Ukuba wongeza iVHDL files, khetha ilayibrari efanelekileyo kwiVHDL Library popup menu. Ithala leencwadi olikhethileyo lisetyenziswa kuyo yonke iVHDL files xa ucofa u-Kulungile kwibhokisi yencoko yababini.
Ifestile yeprojekthi yakho ibonisa iprojekthi entsha file. Ukuba ucofa kuphawu lokudibanisa ecaleni kweprojekthi kwaye uyandise, ubona oku kulandelayo:
Ifolda (iifolda ezimbini zoyilo lweelwimi ezixubeneyo) ezinomthombo files.
Ukuba eyakho files azikho kwincwadi ephantsi kolawulo lweprojekthi, ungacwangcisa olu khetho ngokukhetha Iinketho->Iprojekthi View Iinketho kunye nokujonga i View iprojekthi files kwibhokisi yeefolda. Oku kwahlula uhlobo olunye file kwenye iProjekthi view ngokuwabeka kwiifolda ezahlukeneyo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuseta iProjekthi Files

Ukuphunyezwa, okubizwa ngokuba yi-rev_1 ngokwendalo. Ukuphunyezwa zi
uhlaziyo loyilo lwakho ngaphakathi kumxholo wesoftware yokudibanisa, kwaye ungathatheli indawo yangaphandle ikhowudi yolawulo lwesoftware kunye neenkqubo. Ukuphunyezwa okuninzi kukuvumela ukuba uguqule isixhobo kunye neenketho zokudibanisa ukujonga iinketho zoyilo. Unokuba nokuphunyezwa okuninzi kwi-Synplify Pro. Uzalisekiso ngalunye lunodityaniso lwalo kunye nokhetho lwesixhobo kunye neprojekthi yalo enxulumene neprojekthi files.

3. Yongeza nawaphi na amathala eencwadi owafunayo, usebenzisa indlela echazwe kwinyathelo langaphambili ukongeza iVerilog okanye ithala leencwadi leVHDL. file.
Kwiilayibrari ezikhethekileyo kumthengisi, yongeza ilayibrari efanelekileyo file kwi
iprojekthi. Qaphela ukuba kwezinye iintsapho, amathala eencwadi alayishwa ngokuzenzekelayo kwaye akukho mfuneko yokuba wongeze ngokucacileyo kwiprojekthi. file.
Ukongeza ithala leencwadi le-VHDL yomntu wesithathu, yongeza i-.vhd efanelekileyo file kuyilo, njengoko kuchaziwe kwinyathelo lesi-2. Cofa ekunene i file kwiProjekthi view kwaye ukhethe File Khetha, okanye khetha iProjekthi-> Seta ithala leencwadi leVHDL. Chaza igama lethala leencwadi elihambelana nezifanisi. Umzekeloample, MYLIB. Qinisekisa ukuba le phakheji yelayibrari iphambi koyilo lwenqanaba eliphezulu kuluhlu lwe files kwiProjekthi view.
Ngolwazi malunga nokuseta iVerilog kunye neVHDL file iinketho, bona Useto lweVerilog kunye neVHDL Iinketho, kwiphepha 84. Ungakwazi nokuseta ezi file iinketho kamva, phambi kokubaleka udibaniso.
Ukufumana ulwazi olongezelelweyo oluthe ngqo kumthengisi malunga nokusebenzisa iilayibrari ezinkulu zabathengisi kunye ne-black bLoOxes, bona Ukulungiswa kweMicrosemi Designs, kwiphepha le-487.
Kumacandelo ethekhinoloji yegeneric, unokongeza i
Ithala leencwadi leVerilog elizimeleyo ngobuchwephesha libonelelwe ngesoftware

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iProjekthi Files

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

(install_dir/lib/generic_ technology/gtech.v) kuyilo lwakho, okanye wongeze elakho ithala leencwadi elenziwe lafana nelo. Musa ukusebenzisa zombini kunye njengoko kunokubakho ukungqubana.
4. Khangela file ulandelelwano kwiProjekthi view. File iodolo ibaluleke kakhulu kwiVHDL files.
YeVHDL files, ungaodola ngokuzenzekelayo i files nge
ukhetha Qhuba-> Lungiselela iVHDL Files. Kungenjalo, hambisa ngesandla i files kwiProjekthi view. Iphakheji files kufuneka zibe ngowokuqala kuluhlu kuba ziqulunqwe phambi kokuba zisetyenziswe. Ukuba uneebhloko zoyilo ezisasazeke ngaphezulu kwabaninzi files, qiniseka ukuba unokulandelayo file umyalelo: i file equlathe iqumrhu kufuneka ibe yeyokuqala, ilandelwe yi-architecture file, kwaye ekugqibeleni i file ngoqwalaselo.
KwiProjekthi view, khangela ukuba okokugqibela file kwiProjekthi view Ingaba i
umthombo okumgangatho ophezulu file. Kungenjalo, ungakhankanya inqanaba eliphezulu file xa useta iinketho zesixhobo.
5. Khetha File-> Gcina, chwetheza igama leprojekthi, kwaye ucofe Gcina. Ifestile yeProjekthi ibonisa utshintsho lwakho.
6. Ukuvala iprojekthi file, khetha i Vala iProjekthi iqhosha okanye File->Vala iProjekthi.

Ukuvula iProjekthi ekhoyo File
Kukho iindlela ezimbini zokuvula iprojekthi file: iProjekthi eVulekileyo kunye nejenerikhi File -> Vula umyalelo.
1. Ukuba iprojekthi ofuna ukuyivula yile osebenze kuyo kutshanje, ungayikhetha ngokuthe ngqo: File-> IiProjekthi zakutsha nje-> Igama leprojekthi.
2. Sebenzisa enye yezi ndlela zilandelayo ukuvula nayiphi na iprojekthi file:

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuseta iProjekthi Files

Vula Umyalelo weProjekthi

File-> Vula Umyalelo

Khetha File-> Vula iProjekthi, cofa iqhosha leProjekthi evulekileyo kwicala lasekhohlo lefestile yeProjekthi, okanye ucofe i icon yeP.
Ukuvula iprojekthi yamva nje, cofa kabini kuluhlu lweeprojekthi zakutsha nje.
Kungenjalo, cofa iProjekthi ekhoyo iqhosha ukuvula i Vula ibhokisi yencoko yababini kwaye ukhethe iprojekthi.

Khetha File-> Vula.
Chaza uvimba weefayili ochanekileyo kwi-Look In: indawo.
Seta File yoHlobo lweProjekthi Files (*.prj). Ibhokisi idwelisa iprojekthi files.
Cofa kabini kwiprojekthi ofuna ukuyivula.

Iprojekthi ivula kwifestile yeProjekthi.

Ukwenza utshintsho kwiProjekthi
Ngokuqhelekileyo, uyongeza, ucime, okanye ubuyisele files.
1. Ukongeza umthombo okanye isithintelo files kwiprojekthi, khetha i Yongeza Files iqhosha okanye iProjekthi-> Yongeza uMthombo File ukuvula i Khetha Files ukuya Yongeza kwiProjekthi yebhokisi yencoko yababini. Jonga Ukwenza iProjekthi File, kwiphepha 58 ukuze ufumane iinkcukacha.
2. Ukucima i file ukusuka kwiprojekthi, cofa i file kwiProjekthi yefestile, kwaye ucinezele iqhosha elithi Cima.
3. Ukutshintsha a file kwiprojekthi,
Khetha i file ufuna ukutshintsha kwiProjekthi yefestile.
Cofa indawo ethi Guqula File iqhosha, okanye khetha iProjekthi-> Tshintsha File.
KuMthombo File ibhokisi yencoko yababini evulayo, cwangcisa Jonga kulawulo
apho entsha file ikhona. Entsha file kufuneka ibe yodidi olufanayo ne file ufuna ukubuyisela.
Ukuba awuboni eyakho file kuluhlu, khetha uhlobo lwe file udinga ukusuka
i Files of Indawo yodidi.
Cofa kabini i file. Entsha file ithatha indawo endala kwiprojekthi
uluhlu. LO
4. Ukuchaza indlela iprojekthi files zigcinwa kwiprojekthi, nqakraza ekunene kwi a file kwiProjekthi view kwaye ukhethe File Iinketho. Seta Gcina File inketho nokuba iNxulumana neProjekthi okanye iNdlela epheleleyo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iProjekthi Files

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

5. Ukukhangela ixesha stamp kwi file, nqakraza ekunene kwi file kwiProjekthi view kwaye ukhethe File Iinketho. Jonga ixesha ukuba i file yagqityelwa ukulungiswa. Cofa u-Kulungile.

Ukuseta iProjekthi View Bonisa Okukhethwayo
Unokwenza umbutho kunye nokuboniswa kweprojekthi files. 1. Khetha Khetha->Iprojekthi View Iinketho. Iprojekthi View Iifom zokhetho ziyavula.

2. Ukucwangcisa iintlobo ezahlukeneyo zegalelo files kwiincwadi ezineenkcukacha ezahlukeneyo, khangela View Iprojekthi Files kwiifolda.
Ukukhangela olu khetho kwenza abalawuli abahlukeneyo kwiProjekthi view ngenxa yokunyanzelwa files kunye nomthombo files.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuseta iProjekthi Files

3. Ukulawula file bonisa ngoku kulandelayo:
Bonisa ngokuzenzekelayo zonke ii files, ngokujonga Bonisa iThala leencwadi leProjekthi. Ukuba
oku akukhangelwa, iProjekthi view ayibonisi files de unqakraze kwisimboli yokudibanisa kwaye wandise i files kwifolda.
Khangela enye yeebhokisi kwiProjekthi File Igama lokubonisa icandelo le
ifomu ukugqiba ukuba njani fileamagama abonisiwe. Uyakwazi ukubonisa nje fileigama, indlela ehambelanayo, okanye indlela epheleleyo.
4. Ukuya view iprojekthi files kwiincwadi ezineenkcukacha ezilungiselelweyo, khangela View Iprojekthi Files kwiifolda zesiko. Ukufumana ulwazi oluthe xhaxhe, jonga Ukwenza iiFolda eziSiko, kwiphepha 66. Uhlobo lweefolda ziboniswa kuphela ukuba kukho iindidi ezininzi kwisiqulathi seefayili esilungiselelweyo.

Iifolda zesiko
© 2014 Synopsy, Inc. 64

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Ukuseta iProjekthi Files

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

5. Ukuvula umiliselo olungaphezulu kwesinye kwiProjekthi enye view, khangela Vumela iiProjekthi ezininzi ukuba zivulwe.
Iprojekthi ye-1

Iprojekthi ye-2

6. Lawula imveliso file bonisa ngoku kulandelayo:
Jonga uMboniso zonke Files kwibhokisi yeZiphumo zikavimba weefayili ukubonisa zonke iziphumo
files yenziwe emva kodibaniso.
Guqula imveliso file umbutho ngokunqakraza kwenye yebar zeheader
kwiziphumo zoPhumezo view. Ungadibanisa i files ngokohlobo okanye uzihlele ngokomhla ezigqitywe ukulungiswa.
7. Ukuya view file ulwazi, khetha i file kwiProjekthi view, cofa ekunene, kwaye ukhethe File Iinketho. Umzekeloample, ungajonga umhla a file yalungiswa.
Ukuhlaziya i-Verilog iquka iindlela kwiProjekthi yaBadala Files
Ukuba uneprojekthi file eyenziwe ngoguqulelo oludala lwesoftware (ngaphambi kwe8.1), iVerilog ibandakanya iindlela kule nto file zinxulumene nolawulo lweziphumo okanye umthombo file kunye `kubandakanya iingxelo. Ekukhutshweni emva kwe-8.1, iprojekthi file `kubandakanya iindlela zinxulumene neprojekthi file kuphela. I-GUI kukhupho lwamva nje ayiphuculi ngokuzenzekelayo i-prj endala fileukuhambelana nemithetho emitsha. Ukuphucula kunye nokusebenzisa iprojekthi endala file, yenza enye yezi zilandelayo:
· Hlela ngesandla i prj file kumhleli wokubhaliweyo kwaye wongeze oku kulandelayo kwi
umgca phambi kwesethi_yokhetho ngalunye -bandakanya_indlela:
set_option -project_relative_ibandakanya 1
· Qala iprojekthi entsha ngenguqulelo entsha yesoftware kwaye ucime i
iprojekthi endala. Oku kuya kwenza i-prj entsha file ukuthobela umthetho omtsha apho kubandakanywa kunxulumene ne-prj file.

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Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Iprojekthi yokulawula File Uluhlu lwemigangatho

Iprojekthi yokulawula File Uluhlu lwemigangatho
La macandelo alandelayo achaza ukuba ungenza njani kwaye ulawule iifolda ezilungiselelweyo kunye files kwiProjekthi view:
· Ukuyila iifolda zeSiko · Ukuguqula iifolda zeProjekthi yesiNtu · Ukuguqula iSiko Files

Ukuyila iifolda zesiko
Unokwenza iifolda ezinengqiqo kwaye wenze ngokwezifiso filekumaqela awohlukeneyo olawulo lweProjekthi yakho view. Ezi folda zinokuchazwa ngalo naliphi na igama okanye umgangatho woluhlu. UmzekeloampLe, ungangqinela inkqubo yakho yokusebenza ngokungenasizathu file ubume okanye HDL logic hierarchy. Iifolda eziqhelekileyo zohlulwa ngombala wazo ozuba.

Kukho iindlela ezininzi zokwenza iifolda zesiko kwaye wongeze files kubo kwiprojekthi. Sebenzisa enye yezi ndlela zilandelayo:

1. Cofa ekunene kwiprojekthi file okanye enye ifolda yesiko kwaye ukhethe Yongeza isiqulathi seefayili kwimenyu evelelayo. Emva koko yenza nayiphi na kwezi zilandelayo file imisebenzi:

Ukucofa ekunene kubonisa njalo

kuloo nto

fyioleuoLcrOafnileesitahnedr

khetha khetha

Beka kwisiqulathi seefayili. I-sub-menu ifolda esele ikhona okanye yenza

ifolda entsha.

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Iprojekthi yokulawula File Uluhlu lwemigangatho

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Qaphela ukuba ungabiza incwadi eneenkcukacha ngokungenasizathu, nangona kunjalo ungasebenzisi uphawu (/) kuba olu luphawu lomahluli woluhlu.
Ukuthiya ngokutsha ifolda, cofa ekunene kwifolda uze ukhethe okuthi Thiya kutsha kuyo
i popup menu. Ibhokisi yencoko yababini ethi Thiya kwakhona Isiqulathi seefayili iyavela; xela igama elitsha.
2. Sebenzisa i Faka Files ukuya kwiProjekthi yebhokisi yencoko yababini ukongeza imixholo epheleleyo yolawulo lwencwadi eneenkcukacha, kunye nendawo ekhethiweyo files kwiincwadi ezineenkcukacha zesiko elihambelana nenkqubo yolawulo ye-OS edweliswe kwibhokisi yencoko yababini ebonisiweyo.

Ukwenza oku, khetha Yongeza File iqhosha kwiProjekthi view.
Khetha naziphi na iincwadi ezineenkcukacha eziceliweyo njenge dsp ukusuka kwibhokisi yencoko yababini, ngoko
cofa i Yongeza iqhosha. Oku kubeka yonke indawo files ukusuka kuluhlu lwe dsp kulawulo lwesiko osanda kulwenza.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Iprojekthi yokulawula File Uluhlu lwemigangatho

Ukubeka ngokuzenzekelayo i files kwiincwadi ezineenkcukacha zesiko elihambelanayo
Uluhlu lwencwadi eneenkcukacha OS, khangela ukhetho olubizwa Yongeza Files ukuya kwiziqulathi zeefayili zesiko kwibhokisi yencoko yababini.
Ngokungagqibekanga, igama lesiqulathi seefayili likwaligama elifanayo nefolda
equlathe files okanye incwadi eneenkcukacha eza kongezwa kwiprojekthi. Nangona kunjalo, ungaguqula indlela amagama agciniweyo athiywa ngayo, ngokunqakraza kuKhetho lweefolda iqhosha. Ibhokisi yencoko yababini elandelayo iyaboniswa.

Ukusebenzisa:
Kuphela isiqulathi seefayili esiqulathe files yegama lesiqulathi seefayili, cofa ku Sebenzisa i-OS
Igama lesiqulathi seefayili.
Igama lendlela eya kwisilawulo esikhethiweyo ukumisela umgangatho we
Uluhlu lwemisebenzi lubonakaliswe kwindlela yesiqulathi seefayili.

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Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

3. Ungatsala kwaye ulahle files kunye neefolda ukusuka kwisicelo soMhloli we-OS kwiProjekthi view. Olu phawu luyafumaneka kwi-Windows kunye ne-Linux desktops eziqhuba i-KDE.
Xa utsala kwaye uwise a file, yongezwa ngokukhawuleza kwiprojekthi.
Ukuba akukho projekthi evulekileyo, isoftware idala iprojekthi.
Xa utsala kwaye uwise a file phezu kwencwadi eneenkcukacha, izakubekwa kulo
ifolda. Ekuqaleni, Yongeza Files ukuya kwiProjekthi yebhokisi yencoko yababini ibonisiwe icela ukuba uqinisekise i files iza kongezwa kwiprojekthi. Ungacofa u-Kulungile ukwamkela i files. Ukuba ufuna ukwenza utshintsho, unganqakraza i Susa Konke iqhosha kwaye uchaze icebo lokucoca elitsha okanye ukhetho.

Qaphela: Ukubonisa iziqulathi zeefayili ezilungiselelweyo kwiProjekthi view, khetha Khetha->Iprojekthi View Imenyu yokhetho, emva koko uvule/uvale ibhokisi yokukhangela View Iprojekthi Files kwiziqulathi zeefayili zesiko kwibhokisi yencoko yababini.

Ukulawula Iifolda zeProjekthi yesiNtu
Le nkqubo ilandelayo ichaza indlela onokuthi uyisuse ngayo files ukusuka kwincwadi eneenkcukacha, cima abalawuli, kwaye utshintshe ulawulo lwencwadi eneenkcukacha.
1. Ukususa a file ukusuka kwisiqulathi seefayili esilungiselelweyo, nokuba:
Tsala kwaye uyilahle kwenye incwadi okanye kwiprojekthi. Phawula i file, cofa ekunene kwaye ukhethe Susa kwisiqulathi seefayili kwi
popup menu.
Musa ukusebenzisa iqhosha le-Delete (DEL), njengoko oku kususa i file ukusuka kwiprojekthi.
2. Ukucima ifolda yesiko, yiqaqambise uze ucofe ekunene uze ukhethe Cima kwi-popup menu okanye ucinezele iqhosha le-DEL. Xa ucima ifolda, yenza enye yezi zinto zilandelayo:
Cofa Ewe ukucima ifolda kunye ne files equlethwe kulawulo olusuka
iprojekthi.
Cofa uHayi ukucima isiqulathi seefayili.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Iprojekthi yokulawula File Uluhlu lwemigangatho

3. Ukutshintsha ulawulo lwencwadi yesiko:
Tsala kwaye ulahle incwadi eneenkcukacha phakathi kwesinye isiqulathi seefayili ukuze sibe yi-sub-
incwadi eneenkcukacha okanye ngaphezulu kweprojekthi ukuyihambisa kumphakamo ophezulu.
Ukususa ulawulo lomgangatho ophezulu wesiqulathi seefayili esilungiselelweyo, tsala kwaye ulahle
inqanaba elisezantsi elifunwayo loluhlu lwemigangatho yeprojekthi. Emva koko cima uvimba weengcambu ongenanto wencwadi eneenkcukacha.
Umzekeloample, ukuba ulawulo lwencwadi yesiko ekhoyo lu:
/Eksamples/Verilog/RTL
Masithi ufuna inqanaba elinye leRTL yolawulo kuphela, tsala kwaye ulahle iRTL ngaphezulu kweprojekthi. Emva koko, unokucima i/Examples/Verilog directory.

Ukulawula Isiko Files
Ukongeza, unokwenza ezi ntlobo zilandelayo zesiko file imisebenzi:
1. Ukucinezela umboniso we files kwiincwadi ezineenkcukacha, cofa ekunene kwiProjekthi view kwaye ukhethe iProjekthi View Khetha okanye khetha Khetha->Iprojekthi View Iinketho. Khubaza ukhetho View Iprojekthi Files in Uhlobo lweencwadi ezineefayili kwibhokisi yencoko yababini.
2. Ukubonisa files ngolandelelwano lwealfabhethi endaweni yolandelelwano lweprojekthi, khangela i Hlela Files iqhosha kwiProjekthi view iphaneli yokulawula. Cofa isitshixo sotolo olusezantsi kwikona esezantsi-ekhohlo kwindawo yolawulo ukuguqulela kunye nokuvala indawo yolawulo.

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Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Iphaneli yokulawula iToggle
3. Ukutshintsha ulandelelwano lwe files kwiprojekthi:
Qinisekisa ukuba ukhubaza iifolda zesiko kunye nokuhlelwa files. Tsala kwaye ulahle a file kwindawo efunekayo kuluhlu lwe files.
4. Ukutshintsha i file chwetheza, tsala kwaye uyilahle kuhlobo olutsha ulawulo. Isoftware iya kukukhuthaza ukuba uqinisekiswe.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukumisela uMiselo

Ukumisela uMiselo
Ukuphunyezwa yinguqulelo yeprojekthi, ephunyezwe ngesethi ethile yezithintelo kunye nezinye izicwangciso. Iprojekthi inokuqulatha ukuphunyezwa okuninzi, nganye inesetingi zayo.

Ukusebenza ngoPhumezo oluninzi
Isixhobo se-Synplify Pro sikuvumela ukuba wenze ukuphunyezwa okuninzi koyilo olufanayo kwaye uthelekise iziphumo. Oku kukuvumela ukuba ulinge ngezicwangciso ezahlukeneyo zoyilo olufanayo. Ukuphunyezwa luhlaziyo loyilo lwakho ngaphakathi kumxholo wesoftware yokudibanisa, kwaye musa ukuthatha indawo yangaphandle yesoftware yolawulo lwekhowudi kunye neenkqubo.
1. Cofa i Yongeza uPhumezo iqhosha okanye khetha iProjekthi->UPhumezo olutsha kwaye usete iinketho zesixhobo esitsha (Isixhobo sesithuba), iinketho ezintsha (Ukhetho ithebhu), okanye isithintelo esitsha. file (Izithintelo tab).
Isoftware idala olunye ukuphunyezwa kwiprojekthi view. Ukuphunyezwa okutsha kunegama elifanayo nelidlulileyo, kodwa kunye nesimamva senani esahlukileyo. Lo mzobo ulandelayo ubonisa ukuphunyezwa okubini, i-rev1 kunye ne-rev2, kunye nokuphunyezwa kwangoku (okusebenzayo) kubonakalisiwe.

Ukuphunyezwa okutsha kusebenzisa ikhowudi yomthombo ofanayo files, kodwa iinketho zesixhobo ezahlukeneyo kunye nemithintelo. Ikhuphela ezinye files ukusuka kuzalisekiso lwangaphambili: ilog ye tlg file, uluhlu lomnatha lwe-srs RTL file, kunye noyilo_fsm.sdc file yenziwe ngu FSM Explorer. Isoftware igcina imbali ephindaphindwayo ye-synthesis ibaleka.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukumisela uMiselo

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

2. Qhuba i-synthesis kwakhona ngoseto olutsha.
Ukusebenzisa uphumezo lwangoku kuphela, cofa u-Eleka.
Ukwenza konke ukuphunyezwa kwiprojekthi, khetha u-Run-> Qhuba Konke
Ukuphunyezwa.
Ungasebenzisa uphumezo oluninzi ukuzama indawo eyahlukileyo okanye ulinge ngamaza ahlukeneyo. Jonga uSeto lweNgcaciso yeeNdlela zokuSebenza, kwiphepha lama-75 ngolwazi malunga nokhetho lokuseta.
Iprojekthi view ibonisa lonke uzalisekiso ngozalisekiso olusebenzayo oluphawulweyo kunye nesiphumo esihambelanayo files yenzelwe umiliselo olusebenzayo oluboniswe kwiZiphumo zoPhumezo view ngasekunene; ukutshintsha ukuphunyezwa okusebenzayo kutshintsha imveliso file umboniso. Ifestile yokuJonga ibeka esweni ukuphunyezwa okusebenzayo. Ukuba uqwalasela le festile ukubukela konke ukuphunyezwa, ukuphunyezwa okutsha kuhlaziywa ngokuzenzekelayo kwifestile.
3. Thelekisa iziphumo.
Sebenzisa ifestile yokuJonga ukuthelekisa iikhrayitheriya ezikhethiweyo. Qinisekisa ukuseta
uphumezo ofuna ukuthelekisa kunye noBumbeko lokuJonga umyalelo. Bona Ukusebenzisa Ifestile Yokubukela, kwiphepha 190 ukuze ufumane iinkcukacha.

Ukuthelekisa iinkcukacha, thelekisa ilogi file iziphumo.
4. Ukuthiya ngokutsha ukuphunyezwa, cofa iqhosha lasekunene lemouse kwigama lophumezo kwiprojekthi view, khetha Guqula iGama lokuSebenzisa kwi-popup menu, kwaye uchwetheze igama elitsha.
Qaphela ukuba i-UI yangoku ibhala ngaphezulu ukuphunyezwa; ukukhutshwa ngaphambi kwe-9.0 kugcina ukuphunyezwa ukuba kunikwe elinye igama.
5. Ukukopa ukuphunyezwa, cofa iqhosha lasekunene lemouse kwigama lomiliselo kwiprojekthi view, khetha Khuphela ukuphunyezwa kwimenyu evelelayo, kwaye uchwetheze igama elitsha lekopi.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukumisela uMiselo

6. Ukucima ukuphunyezwa, klikha iqhosha lasekunene lemouse kwigama lomiliselo kwiprojekthi view, kwaye ukhethe Susa ukuphunyezwa kwi popup menu.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso
Ukuseta iiNdlela zokuSebenza zeNgcaciso yeNgcaciso
Unokuseta iinketho zehlabathi zophunyezo lwakho lwe-synthesis, ezinye zazo zithe ngqo kwitekhnoloji. Eli candelo lichaza indlela yokuseta iinketho zehlabathi njengesixhobo, ulungiselelo, kunye file iinketho ngomyalelo weeNdlela zokuPhumeza. Ngolwazi malunga nokuseta imiqobo yophumezo, jonga Ukuchaza imiqobo yoMHLABA, kwiphepha le-119. Ngolwazi malunga nokugqwesa ukusetwa kwelizwe jikelele kunye neempawu zophawu okanye izikhokelo, jonga iimpawu zokuPhakamisa kunye neMikhombandlela, kwiphepha lama-90.
Eli candelo lixoxa ngezi zihloko zilandelayo:
· Ukuseta iiKhetho zeSixhobo, kwiphepha le-75 · Ukuseta iiKhetho zokuSebenza, kwiphepha le-78 · Ukucacisa ukuQwaqa kweHlabathi kunye nokunyanzeliswa Files, kwiphepha 80 · Ukukhankanya iiKhetho zeziphumo, kwiphepha lama-82 · Ukucacisa iNgxelo yeXesha leSiphumo, kwiphepha 84 · Ukuseta iiKhetho zeVerilog kunye neVHDL, kwiphepha 84
Ukuseta Iinketho zeSixhobo
Iinketho zesixhobo ziyinxalenye yokhetho lwehlabathi lonke onokuthi ulumisele ulwenziwo lwe-synthesis. Zibandakanya ukhetho lwenxalenye (iteknoloji, inxalenye kunye nebakala lesantya) kunye neenketho zokuphunyezwa (ufakelo lwe-I / O kunye ne- fanouts). Izinketho kunye nokuphunyezwa kwezi zikhetho zinokwahluka ukusuka kwiteknoloji ukuya kwiteknoloji, ngoko jonga izahluko zomthengisi we-Reference Manual ngolwazi malunga neenketho zakho zomthengisi.
1. Vula ifom yeeNdlela zokuSebenza ngokucofa iiNdlela zokuSebenza iqhosha okanye ukhethe iProjekthi->Iinketho zoPhumezo, kwaye ucofe iSixhobo tab phezulu ukuba ayikakhethwa.
2. Khetha iteknoloji, inxalenye, ipakethe, kunye nesantya. Iinketho ezikhoyo ziyahluka, kuxhomekeke kwitekhnoloji oyikhethayo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
3. Seta iinketho zokumaphu zesixhobo. Iinketho ziyahluka, kuxhomekeke kwitekhnoloji oyikhethayo.
Ukuba awuqinisekanga ukuba kuthetha ukuthini ukhetho, cofa kukhetho ukuze ubone
inkcazo kwibhokisi engezantsi. Ukufumana iinkcazo ezipheleleyo zokhetho, cofa u-F1 okanye ubhekisele kwisahluko esifanelekileyo somthengisi kwiNcwadi yeeReferensi.
Ukuseta ukhetho, chwetheza kwixabiso okanye khangela ibhokisi ukuze uyivule.
Ngolwazi oluthe kratya malunga nokucwangcisa imida ye fanout kunye nexesha kwakhona, bona Ukucwangcisa iMida yeFanout, kwiphepha 348, kunye noKubeka kwakhona ixesha, kwiphepha 334, ngokulandelelanayo. Ukufumana iinkcukacha malunga nolunye ukhetho oluthe ngqo kumthengisi, jonga kwisahluko esifanelekileyo somthengisi kunye nosapho lwetekhnoloji kwiManuwali yoReferensi.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso

4. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile.
5. Cofa iqhosha elithi Qhuba ukudibanisa uyilo. Isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.
6. Ukuseta iinketho zesixhobo ngescript, sebenzisa i-set_option Tcl umyalelo. Le theyibhile ilandelayo iqulathe uluhlu lwealfabhethi lokhetho lwesixhobo kwiSixhobo thebhu eboniswe kwimiyalelo yeTcl elinganayo. Ngenxa yokuba ukhetho luyiteknoloji- kunye nentsapho-based, zonke iinketho ezidweliswe kwitheyibhile zisenokungafumaneki kwiteknoloji ekhethiweyo. Yonke imiyalelo iqala ngo-set_option, ilandelwa yi-syntax kwikholamu njengoko kubonisiwe. Jonga iNcwadana yeReferensi yolona luhlu lubanzi lokhetho lomthengisi wakho.
Le theyibhile ilandelayo ibonisa uninzi lweenketho zesixhobo.

UKhetho lweePropathi ezichatshazelweyo zoMhlalutyi Khubaza i-I/O yokuFaka isiKhokelo seFanout

Tcl Umyalelo (set_option…) -run_prop_extract {1|0} -disable_io_insertion {1|0} -fanout_limit fanout_value

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso

Ukhetho

Tcl Umyalelo (set_option…)

Iphakheji

-iphakheji pkg_name

Inxalenye

-inxalenye yegama_igama

Sombulula abaqhubi abaxubeneyo

-resolve_multiple_driver {1|0}

Isantya

-speed_grade speed_grade

Iteknoloji

-igama elingundoqo letekhnoloji

Hlaziya Ukuqulunqa iDatha yexesha leNdawo -update_models_cp {0|1}

UkuVeliswa kweDatha ye-HDL yoHlalutyi -hdl_qload {1|0}

Ukuseta iiKhetho zokuSebenza
Iinketho zokuphucula ziyinxalenye yeenketho zehlabathi onokuthi uzibekele ukuphunyezwa. Eli candelo likuxelela ukuba ungaziseta njani iinketho ezinje ngokuphindaphindiweyo kunye nokukhethwa kwehlabathi jikelele njengokwabelana ngobutyebi. Ungakwazi ukuseta ezinye zezi iinketho ngamaqhosha afanelekileyo kwi-UI.
1. Vula ifom yeeNdlela zokuSebenza ngokucofa iiNdlela zokuSebenza iqhosha okanye ukhethe iProjekthi->Ukwenziwa kweeNdlela zokuSebenza, kwaye ucofe uKhetho isithuba phezulu.
2. Cofa iinketho zokulungiselela ozifunayo, nokuba kukwifomu okanye kwiProjekthi view. Ukhetho lwakho luyahluka, kuxhomekeke kwitekhnoloji. Ukuba ukhetho alukho kwitekhnoloji yakho, lukhutshiwe. Ukuseta ukhetho kwindawo enye kuyihlaziya ngokuzenzekelayo kwenye.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso

Iprojekthi View

IiNdlela zokuSebenza zokuSebenza-> Iinketho

Ngeenkcukacha malunga nokusebenzisa olu lungelelwaniso jonga kula macandelo alandelayo:

FSM Compiler FSM Explorer
Ukwabelwa ixesha kwakhona kweResource

Ukuphucula oomatshini boMbuso, kwiphepha 354
Ukuqhuba i-FSM Explorer, kwiphepha le-359 Qaphela: Kuphela iseti engaphantsi ye-Microsemi technologies exhasa ukhetho lweFSM Explorer. Sebenzisa iProjekthi-> IiNdlela zokuSebenza-> Iphaneli yokhetho ukujonga ukuba olu khetho luyaxhaswa kwisixhobo osikhankanye kwisixhobo sakho.
Ukwabelana ngeziBonelelo, kwiphepha lama-352
Ukuhlaziya ixesha, kwiphepha 334

Iinketho ezilinganayo zomyalelo we-Tcl set_option zezi zilandelayo:

Ukhetho lweFSM Compiler FSM Explorer Resource Sharing Retiming

set_option Tcl Command Option -symbolic_fsm_compiler {1|0} -use_fsm_explorer {1|0} -resource_sharing {1|0} -retiming {1|0}

3. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
4. Cofa iqhosha elithi Qhuba ukuqhuba ulungelelwaniso.
Isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.
IsiZukulwana seDatabase yoMhlalutyi we-HDL
Ngokungagqibekanga, isoftware ifunda uyilo lonke, yenza ulungelelwaniso lwengqiqo kunye nokusasazwa kwexesha, kwaye ibhala imveliso kuluhlu olunye (srs). Njengoko uyilo lusiya lukhula, ixesha lokubaleka kunye nokulungisa uyilo luba lucelomngeni ngakumbi.
Olu khetho luvumela umqokeleli ukwahlula kwangaphambili uyilo kwiimodyuli ezininzi ezibhalelwe ukwahlula i-netlist files (srs). Ukwenza olu khetho, khetha i-HDL Umhlalutyi weDatha yeSiveliso sebhokisi yokukhangela kwi Iinketho isithuba se Iinketho zoPhumezo ibhokisi yencoko yababini. Olu phawu luphucula ukusetyenziswa kwememori kakhulu kuyilo olukhulu.
Eli nqaku linokwenziwa ukuba lisebenze kwi-Tcl Script yefestile usebenzisa le set_option Tcl yomyalelo olandelayo:
set_option -hdl_qload 1
Emva kokuba i-HDL i-Database ye-Database ye-Database ye-option yenziwe yasebenza, sebenzisa i-Inremental Quick Load inketho kwisixhobo soHlalutyi lwe-HDL ukubonisa uyilo usebenzisa i-netlist eyodwa (srs) okanye i-netlist yemodyuli ye-RTL ephezulu (srs). Isixhobo sinokuthatha i-advantage yalo msebenzi ngokulayisha kuphela ulawulo loyilo oluchaphazelekayo. UmzekeloampLe, umkhangeli zincwadi wolawulo unokwandisa kuphela umgangatho osezantsi wolawulo njengoko kufuneka kumthwalo okhawulezayo. Inketho yoLondolozo oluKhawulezayo oLongezwayo ibekwe kwindawo yolawulo ngokubanzi yebhokisi yencoko yababini yoKhetho loMhlalutyi weHDL. Jonga iPhaneli ngokubanzi, kwiphepha lama-304.

Ukucacisa iFrequency kunye nokunyanzelwa kweHlabathi Files

Le nkqubo ikuxelela indlela yokuseta i-frequency jikelele kwaye uchaze umqobo files yokuphunyezwa.

1. Ukuseta iifrikhwensi zehlabathi, yenza enye yezi zilandelayo:

Chwetheza i-frequency jikelele kwiProjekthi view.

Vula ifom yeeNdlela zokuPhumeza ngokucofa uPhumezo

Iinketho iqhosha Izithinteli tab.

khethaLcOting

Iprojekthi->Ukuphunyezwa

Ukhetho,

kwaye

cofa

Umyalelo olinganayo weTcl set_option ngu-frequency frequencyValue.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso
Unako ukungayihoyi i-frequency jikelele kunye nemiqobo yasekhaya, njengoko kuchaziwe kwi-Specifying SCOPE Contrains, kwiphepha le-119. Kwisixhobo se-Synplify Pro, ungenza ngokuzenzekelayo imiqobo yewotshi kuyilo lwakho endaweni yokuseta amaza ehlabathi. Bona Ukusebenzisa Izithintelo Ezizenzekelayo, kwiphepha 291 ngeenkcukacha.
Iprojekthi yeGlobal Frequency kunye nezithintelo View
Iinketho Zokuphumeza-> Izithintelo

2. Ukuchaza umqobo files kuphunyezo, yenza enye yezi zilandelayo:
Khetha iProjekthi-> IiNdlela zokuSebenza-> Izithintelo. Jonga isithintelo
files ofuna ukuyisebenzisa kwiprojekthi.
Ukusuka kwiiKhetho zoPhumezo->Iphaneli yeZithintelo, unokucofa ku
yongeza isithintelo file.
Ngophumezo ofuna ukulusebenzisa olukhethiweyo, cofa Faka File kwi
Iprojekthi view, kwaye yongeza isithintelo files udinga.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
Ukwenza umqobo files, jonga Ukuchaza imiqobo yoMDA, kwiphepha 119.
3. Ukususa umqobo files ukusuka kuphunyezo, yenza enye yezi zilandelayo:
Khetha iProjekthi-> IiNdlela zokuSebenza-> Izithintelo. Cofa kwibhokisi yokukhangela
ecaleni kwe file igama.
KwiProjekthi view, cofa ekunene isithintelo file ukuba isuswe kwaye
khetha Susa kwiProjekthi.
Oku kususa umqobo file ukusuka ekuphunyezweni, kodwa ayiyicimi.
4. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile.
Xa udibanisa uyilo, isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.
Ukuchaza uKhetho lweziphumo
Eli candelo likubonisa indlela yokukhankanya iikhrayitheriya zemveliso yokwenziwa kodibaniso.
1. Vula ifom yeeNdlela zokuSebenza ngokucofa iiNdlela zokuSebenza iqhosha okanye ukhethe iProjekthi->Ukhetho loPhumezo, kwaye ucofe iZiphumo zoPhumezo thebhu phezulu.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso

2. Chaza isiphumo files ufuna ukwenza.
Ukuvelisa i-netlist enemaphu files, cofa Bhala i-Mapped Verilog Netlist okanye Bhala
Uluhlu lwe-Netlist lweVHDL olufakwe kwiMaphu.
Ukuvelisa umqobo okhethekileyo womthengisi file kwinkcazo yangaphambili,
nqakraza Bhala isithintelo somthengisi File. Jonga kwiinkcukacha ngale ngxelo, jonga iNgxelo yokuJonga iConstraint, kwiphepha lama-270.kwiNcwadi yeeReferensi, kwiphepha lama-56 ngolwazi oluthe vetshe.
3. Seta uvimba weefayili ofuna ukubhala kuwo iziphumo.
4. Cwangcisa ifomathi yemveliso file. Umyalelo olinganayo weTcl woshicilelo yiprojekthi -result_format format.
Ungafuna kwakhona ukuseta iimpawu zolawulo lwemaphu yamagama. Ukufumana iinkcukacha, jonga kwisahluko esifanelekileyo somthengisi kwiNcwadi yeeReferensi.
5. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile.
Xa udibanisa uyilo, isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
Ukucacisa iNgxelo yeNgxelo yeXesha
Unokugqiba ukuba yimalini echazwe kwingxelo yexesha ngokuseta ezi ndlela zilandelayo.
1. Ukukhetha iProjekthi-> IiNdlela zokuSebenza, kwaye ucofe ithebhu yeNgxelo yeXesha. 2. Seta inani leendlela ezibalulekileyo ofuna ukuba isoftware ixele.

3. Cacisa inani lamanqaku okuqalisa kunye nesiphelo ofuna ukuwabona axelwe kumacandelo endlela ebalulekileyo.
4. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile. Xa udibanisa uyilo, isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.
Ukuseta iinketho zeVerilog kunye neVHDL
Xa useta umthombo weVerilog kunye neVHDL files kwiprojekthi yakho, ungakhankanya iinketho ezithile zomqokeleli.
Ukumisela i-Verilog File Iinketho
Usete iVerilog file iinketho ngokukhetha nokuba yiProjekthi-> IiNdlela zoPhumezo-> I-Verilog, okanye uKhetho->Bumba iVerilog Compiler.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso

1. Cacisa ifomathi yeVerilog emayisetyenziswe.
Ukuseta umqokeleli kwihlabathi liphela kubo bonke files kwiprojekthi, khetha
Iprojekthi-> IiNdlela zokuSebenza-> I-Verilog. Ukuba usebenzisa iVerilog 2001 okanye iSystemVerilog, khangela iNcwadana yeReferensi yolwakhiwo oluxhaswayo.
Ukuchaza umqokeleli weVerilog kwi file isiseko, khetha i file kwi
Iprojekthi view. Cofa ekunene kwaye ukhethe File Iinketho. Khetha umqokeleli ofanelekileyo. I-Verilog engagqibekanga file ifomathi yeeprojekthi ezintsha yiSystemVerilog.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
2. Chaza imodyuli ekwinqanaba eliphezulu ukuba ubungakwenzi oku kwiProjekthi view.
3. Ukukhupha iiparamitha kwikhowudi yomthombo, yenza oku kulandelayo:
Cofa Khupha iiParameters. Ukubhala ngaphezulu kokungagqibekanga, ngenisa ixabiso elitsha leparameter.
Isoftware isebenzisa ixabiso elitsha ekuphunyezweni kwangoku kuphela. Qaphela ukuba utsalo lweparameter aluxhaswanga kuyilo oluxubeneyo.

4. Chwetheza isikhokhelo kwi-Compiler Directives, usebenzisa izithuba ukwahlula iinkcazo. Ungachwetheza kwizikhokelo oqhele ukuzifaka nge 'ifdef kwaye `chaza iinkcazo kwikhowudi. Umzekeloample, ABC=30 iziphumo kwisoftware ebhala ezi nkcazo zilandelayo kwiprojekthi file:
set_option -hdl_define -seta "ABC=30"
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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso
5. Kwi-Bandakanya uMyalelo weNdlela, khankanya iindlela zokukhangela eziquka imiyalelo yeVerilog fileezikwiprojekthi yakho. Sebenzisa amaqhosha akwikona ephezulu ngasekunene yebhokisi ukongeza, ukucima, okanye ukucwangcisa ngokutsha iindlela.
6. Kuluhlu lweeLayibrari zeThala leeNcwadi, khankanya indlela eya kuluhlu oluqulathe ithala leencwadi files yeprojekthi yakho. Sebenzisa amaqhosha akwikona ephezulu ngasekunene yebhokisi ukongeza, ukucima, okanye ukucwangcisa ngokutsha iindlela.
7. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile. Xa udibanisa uyilo, isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis yokuSeta iiNdlela zokuPhunyezwa kweNgcaciso yeNgcaciso
Ukucwangcisa iVHDL File Iinketho
Useta iVHDL file iinketho ngokukhetha nokuba yiProjekthi-> IiNdlela zokuPhumeza-> VHDL, okanye Iinketho-> Qwalasela uMhlanganisi weVHDL.

Kumthombo weVHDL, ungakhankanya iinketho ezichazwe ngezantsi.
1. Chaza imodyuli ekwinqanaba eliphezulu ukuba ubungakwenzi oku kwiProjekthi view. Ukuba imodyuli yomgangatho ophezulu ayifumanekanga kwilayibrari yomsebenzi engagqibekanga, kufuneka ukhankanye ithala leencwadi apho umqokeleli angayifumana khona imodyuli. Ukuze ufumane inkcazelo ngendlela yokwenza oku, bona iPhaneli yeVHDL, kwiphepha 200.
Ungasebenzisa kwakhona olu khetho kuyilo lolwimi oluxubeneyo okanye xa ufuna ukukhankanya imodyuli engeyiyo yokwenyani yomphakamo ophezulu okhoyo woMhlalutyi we HDL obonisayo kunye ne LdOebugging kwi schematic. views. 2. Xa ufuna ukufakwa kweekhowudi kumatshini wombuso ochazwe ngumsebenzisi, yenza oku kulandelayo:
Chaza uhlobo lwekhowudi ofuna ukuyisebenzisa.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuseta iiNdlela zokuSebenza eziNgqongileyo eziKhethekileyo kwiSahluko sesi-4: Ukuseta iProjekthi yoQhagamshelwano lweNgcaciso
Khubaza umqokeleli weFSM.
Xa udibanisa uyilo, isoftwe isebenzisa imiyalelo yomqokeleli oyibeka apha ukuze ifake ikhowudi koomatshini bakarhulumente kwaye ayiqhubeki umqokeleli weFSM, oya kubeka ngaphezulu imiyalelo yomqokeleli. Kungenjalo, ungachaza oomatshini bakarhulumente abanophawu lwe-sync_encoding, njengoko kuchaziwe kwi-Defining State Machines kwi-VHDL, kwiphepha lama-308.
3. Ukukhupha iigenerics kwikhowudi yemvelaphi, yenza oku:
Cofa ukukhupha iiConstant Generic. Ukubhala ngaphezulu kokungagqibekanga, ngenisa ixabiso elitsha legeneric.
Isoftware isebenzisa ixabiso elitsha ekuphunyezweni kwangoku kuphela. Qaphela ukuba awukwazi ukukhupha iigenerics ukuba unolwimi oluxubeneyo loyilo.

4. Ukutyhala iitristates ukunqumla inkqubo/ibhloko imida, khangela ukuba iPush Tristates yenziwe yasebenza. Ukufumana iinkcukacha, jonga i-Push Tristates Option, kwiphepha lama-212 kwiNcwadi yeeReferensi.
5. Qwalasela ukutolikwa kwemigaqo_yokudityaniswa kunye ne-synthesis_off:
Ukwenza umqokeleli atolike i-synthesis_on kunye ne-synthesis_off imiyalelo
njenge-translate_on/translate_off, yenza i-Synthesis On/Cima iMiselwe njenge-Translate_On/Cima ukhetho.
Ukungahoyi i-synthesis_on kunye ne-synthesis_off izikhokelo, qiniseka ukuba
olu khetho alukhangelwa. Jonga i-translate_off/translate_on, kwiphepha lama-226 kwi-Reference Manual ngolwazi oluthe vetshe.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuchaza iimpawu kunye nezikhokelo

6. Seta ezinye iinketho zophumezo njengoko zifuneka (jonga i-Setting Logic Synthesis Implementation Options, kwiphepha lama-75 ngoluhlu lwezinto onokukhetha kuzo). Cofa u-Kulungile.
Xa udibanisa uyilo, isoftware iqokelela kwaye imephu uyilo isebenzisa iinketho ozisetayo.

Ukuchaza iimpawu kunye nezikhokelo

Iimpawu kunye nemiyalelo yingcaciso owabele ukuyila izinto ukulawula indlela uyilo lwakho olucazululwa ngayo, luphuculwe, kwaye lufakwe kwimephu.
Iimpawu zilawula ukulungelelaniswa kwemephu kunye nezikhokelo zilawula ukulungelelaniswa komqokeleli. Ngenxa yalo mahluko, kufuneka ucacise izikhokelo kwikhowudi yemvelaphi. Le theyibhile ichaza iindlela ezikhoyo zokudala uphawu loyelelwano kunye neenkcukacha zomyalelo:

Imiqobo yoMhleli we-VHDL Verilog SCOPE File

Iimpawu Ewe Ewe Ewe Ewe Ewe

Izikhokelo Ewe Ewe Hayi Hayi

Kungcono ukukhankanya iimpawu kumhleli weSCOPE okanye imiqobo file, kuba akufuneki uqokelele uyilo kuqala. Kwimiyalelo, kufuneka uqulunqe uyilo ukuze lusebenze.
Ukuba SCOPE/izithintelo file kunye nekhowudi yomthombo we-HDL ichazwe kuyilo, imiqobo inokubaluleka xa kukho iingxabano.
Ngeenkcukacha ezithe vetshe, jonga koku kulandelayo:
· Ukuchaza iimpawu kunye nezikhokelo kwi-VHDL, kwiphepha 91 · Ukuchaza iimpawu kunye nezikhokelo kwi-Verilog, kwiphepha 92 · Ukuchaza iimpawu UsLiOng uMhleli we-SCOPE, kwiphepha 93 · Ukuchaza iimpawu kwiMithintelo. File, kwiphepha 97

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza iimpawu kunye nezikhokelo

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuchaza iimpawu kunye nezikhokelo kwi-VHDL
Ungasebenzisa ezinye iindlela ukongeza iimpawu kwizinto, njengoko zidweliswe kwiiMpawu zeMpawu kunye neziKhokelo, kwiphepha lama-90. Nangona kunjalo, ungakhankanya izikhokelo kuphela kwikhowudi yemvelaphi. Kukho iindlela ezimbini zokuchaza iimpawu kunye nezikhokelo kwi-VHDL:
· Ukusebenzisa iphakheji yeempawu ezichazwe kwangaphambili
· Ukubhengeza uphawu rhoqo xa lusetyenziswa
Ukufumana iinkcukacha ze-VHDL yophawu lwesintaksi, jonga uphawu lophawu lwe-VHDL kunye neSintaksi yoMgaqo, kwiphepha 561kwiNcwadana yoReferensi.

Ukusebenzisa iPhakeji yeempawu zeVHDL echazwe kwangaphambili
I-advantagUkusebenzisa iphakheji echazwe kwangaphambili kukuba unqanda ukuchaza kwakhona iimpawu kunye nemiyalelo ngexesha ngalinye uzifaka kwikhowudi yemvelaphi. I-disadvantage kukuba ikhowudi yakho yemvelaphi iphathwa kancinci. Impahla yeempawu ibekwe kwi-installDirectory/lib/vhd/synattr.vhd.
1. Ukusebenzisa iphakheji yeempawu ezichazwe kwangaphambili ezibandakanyiweyo kwilayibrari yesoftware, yongeza le migca kwisintaksi:
ithala leencwadi lidibanisa; sebenzisa synplify.attributes.all;
2. Yongeza uphawu okanye ulwalathiso olufunayo emva kokuchazwa kweyunithi yoyilo.
izibhengezo ; uphawu lophawu_igama lentoName : objectType lixabiso ;
Umzekeloample:
iqumrhu simpledff lizibuko (q: out bit_vector(7 downto 0); d: kwi bit_vector(7 downto 0); clk : kwi bit);
uphawu syn_noclockbuf ye clk : uphawu luyinyani;
Ukufumana iinkcukacha zemigaqo yesintaksi, jonga uphawu lweVHDL kunye neSintaksi yoMgaqo, kwiphepha 561 kwiNcwadana yoReferensi.
3. Yongeza umthombo file kwiprojekthi.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuchaza iimpawu kunye nezikhokelo

Ukubhengeza iimpawu zeVHDL kunye neziKhokelo
Ukuba awusebenzisi imveliso yeempawu, kufuneka uchaze kwakhona iimpawu ngexesha ngalinye uzibandakanya kwikhowudi yemvelaphi.
1. Ngalo lonke ixesha usebenzisa uphawu loyelelwano okanye isiyalelo, sichaze ngoko nangoko emva kokuba iyunithi yezibhengezo zeyunithi yoyilo usebenzisa le syntax ilandelayo:
design_unit_declaration ; uphawu lophawuName : uhlobo lwedatha ; uphawu lophawuIgama lentoName : objectType lixabiso ;
Umzekeloample:
iqumrhu simpledff lizibuko (q: out bit_vector(7 downto 0); d: kwi bit_vector(7 downto 0); clk : kwi bit);
uphawu syn_noclockbuf : boolean; uphawu syn_noclockbuf ye clk :signal yinyani;
2. Yongeza umthombo file kwiprojekthi.

Ukuchaza iimpawu kunye nezikhokelo kwiVerilog
Unokusebenzisa ezinye iindlela ukongeza iimpawu kwizinto, njengoko kuchaziwe kuLuhlu lweempawu kunye neziKhokelo, kwiphepha lama-90. Nangona kunjalo, ungakhankanya izikhokelo kuphela kwikhowudi yomthombo.
IVerilog ayinazo iimpawu zokudityaniswa ezichazwe kwangaphambili kunye nezikhokelo, ngoko ke kufuneka ubongeze njengezimvo. Uphawu loyelelwano okanye igama lomyalelo lilandelwa yi-keyword synthesis. Verilog files zinobuntununtunu, ngoko ke iimpawu kunye nezikhokelo mazicaciswe kanye njengoko zinikezelwe kwiinkcazelo zazo zesintaksi. Ngeenkcukacha zesintaksi, jonga uphawu lweVerilog kunye neSintaksi yoMgaqo, kwiphepha 363kwiNcwadi yoReferensi.
1. Ukongeza uphawu okanye umyalelo kwi-Verilog, sebenzisa umgca we-Verilog okanye i-block comment (i-C-style) i-syntax ilandela ngokuthe ngqo into yoyilo. Izimvo zebhlokhi kufuneka zandulele isemicolon, ukuba ikhona.
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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza iimpawu kunye nezikhokelo

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Verilog Block Comment Syntax
/* uphawu lwe-synthesisName = ixabiso */ /* isilawuli se-synthesisName = ixabiso */

Verilog Line Comment Syntax
// uphawu lwe-synthesisName = ixabiso // uluhlu lwe-synthesis directoryName = ixabiso

Ukufumana iinkcukacha zemigaqo yesintaksi, bona uphawu lweVerilog kunye neSintaksi yoMgaqo, kwiphepha lama-363 kwiNcwadana yoReferensi. Ezi zilandelayo zi-exampngaphantsi:
imodyuli fifo(ngaphandle, ngaphakathi) /* synthesis syn_hier = “nzima” */;
2. Ukuqhoboshela iimpawu ezininzi okanye izikhokelo kwinto enye, zihlukanise iimpawu ezinezithuba ezimhlophe, kodwa ungaphindi igama elingundoqo le-synthesis. Musa ukusebenzisa iikoma. Umzekeloample:
imeko yemeko /* udibaniso olupheleleyo_case parallel_case */;
3. Ukuba iirejista ezininzi zichazwe kusetyenziswa isitatimende esisodwa se-Verilog reg kwaye uphawu lusetyenziswa kubo, ngoko i-software ye-synthesis isebenzisa kuphela irejista yokugqibela echazwe kwi-reg statement. Umzekeloample:
reg [5:0] q, q_a, q_b, q_c, q_d /* synthesis syn_preserve=1 */;
Uphawu loyelelwano lwe-sync lusetyenziswa kuphela kwi-q_d. Le yindlela yokuziphatha elindelekileyo yezixhobo zokudibanisa. Ukusebenzisa olu phawu kuzo zonke iirejista, kufuneka usebenzise i-Verilog reg statement eyahlukileyo kwirejista nganye kwaye usebenzise uphawu.

Ukuchaza iimpawu zokuSebenzisa umhleli we-SCOPE
Ifestile ye-SCOPE ibonelela nge-interface ekulula ukuyisebenzisa ukongeza naluphi na uphawu. Awunakuyisebenzisela ukongeza izikhokelo, kuba kufuneka zongezwe kumthombo files. (Bona Iimpawu Ezichazayo Nezikhokelo kwiVHDL, kwiphepha 91 okanye Ukuchaza Iimpawu Nemigaqo kwiVerilog, kwiphepha 92). Le nkqubo ilandelayo ibonisa indlela yokongeza uphawu ngokuthe ngqo kwi- SCOPE yefestile.
1. Qala ngoyilo oluhlanganisiweyo kwaye uvule ifestile ye-SCOPE. Ukongeza iimpawu kuthintelo olukhoyo file, vula i SCOPE window ngokunqakraza kwekhoyo file kwiProjekthi view. Ukongeza iimpawu kwentsha fileNONE
2. Cofa i Iimpawu zesithuba ezantsi kwe SCOPE window.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Ukuchaza iimpawu kunye nezikhokelo

Ungakhetha into kuqala (inyathelo lesi-3) okanye uphawu lokuqala (inyathelo lesi-4).

3. Ukucacisa into, yenza enye yezi zilandelayo kwikholamu yeNjongo. Ukuba sele uluchazile uphawu, Uluhlu lweNto ludwelisa kuphela izinto ezikhethiweyo ezisebenzayo zophawu lophawu.
Khetha uhlobo lwento kuluhlu lweSihluzo seNto, uze ukhethe i
into kuluhlu lokhetho kuluhlu lweNto. Le yeyona ndlela ilungileyo yokuqinisekisa ukuba ukhankanya into efanelekileyo, ene-syntax echanekileyo.

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Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Ukuchaza iimpawu kunye nezikhokelo

Isahluko sesi-4: Ukuseta iProjekthi ye-Logic Synthesis

Tsala into ofuna ukuncamathela kuyo uphawu ukusuka kwi
RTL okanye iTekhnoloji views kuluhlu lweNto kwifestile ye-SCOPE. Kwezinye iimpawu, ukutsala kunye nokulahla kusenokungakhethi into eyiyo. Umzekeloample, ukuba ufuna ukuseta syn_hier kumnqongo okanye iziko elifana nesango, kufuneka uyibeke kwi view yaloo modyuli. Into izakuba nale syntax: v:moduleName kwiVerilog, okanye v:library.moduleName kwiVHDL, apho unokuba namathala eencwadi amaninzi.
Chwetheza igama lento kuluhlu lweNto. Ukuba awuyazi
igama, sebenzisa i Fumana umyalelo okanye i Object Filter column. Qinisekisa ukuchwetheza isimaphambili esifanelekileyo sento apho sifuneka khona. Umzekeloample, ukuseta uphawu kwi view, kufuneka udibanise i v: isimaphambili kwimodyuli okanye igama lequmrhu. KwiVHDL, kungafuneka uchaze ithala leencwadi kunye negama lemodyuli.
4. Ukuba ukhankanye into kuqala, ngoku ungakhankanya uphawu. Uluhlu lubonisa kuphela iimpawu ezisebenzayo zodidi lwento oyikhethileyo. Cacisa uphawu loyelelwano ngokubamba phantsi iqhosha le mouse kumhlathi wophawu kwaye ukhethe uphawu kuluhlu.

Ukuba ukhethe into kuqala, ukhetho olukhoyo luchongwa yinto ekhethiweyo kunye neteknoloji oyisebenzisayo. Ukuba ukhethe uphawu kuqala, ukhetho olukhoyo luchongwa bubuchwepheshe.
Xa ukhetha uphawu loyelelwano, iwindow ethi SCOPE ikuxelela uhlobo lwexabiso omawungenise kulo uphawu kwaye inikezela ngenkcazelo emfutshane yophawu. Ukuba ukhethe uphawu kuqala, qiniseka ukuba ubuyela umva kwaye uchaze into.
5. Gcwalisa ixabiso. Bamba phantsi iqhosha lemouse kuluhlu lwexabiso, kwaye ukhethe kuluhlu. Ungachwetheza kwakhona ixabiso.

Synplify Pro yeMicrosemi Edition User Guide ngo-Oktobha 2014

Isahluko 4: Ukuseta iLogic Sy

Amaxwebhu / Izibonelelo

I-SYnOPSYS FPGA Synthesis Synplify Pro yoHlelo lweMicrosemi [pdf] Isikhokelo somsebenzisi
I-FPGA Synthesis Synplify Pro yoHlelo lweMicrosemi, iSynthesis Synplify Pro yoHlelo lweMicrosemi, iSynplify Pro yoHlelo lweMicrosemi, iPro yoHlelo lweMicrosemi, uHlelo lweMicrosemi, uHlelo

Iimbekiselo

Incwadi yokusebenzisa

SYnOPSYS FPGA Synthesis Synplify Pro yeMicrosemi Edition IsiKhokelo somsebenzisi

I-FPGA Synthesis Synplify Pro yoHlelo lweMicrosemi

Iinkcukacha

Ulwazi lweMveliso

Imiyalelo yokusetyenziswa kwemveliso

Isahluko 1: Intshayelelo

Umda woxwebhu

Ndiyaqalisa

Ujongano lomsebenzisi ngaphezuluview

Isahluko 2: FPGA Synthesis Design flows

Isahluko sesi-3: Ukulungiselela iNgeniso

FAQ

Umbuzo: Ndingenza iikopi zamaxwebhu?

Umbuzo: Ndiyiqala njani isoftware?

Umbuzo: Ngoobani abaphulaphuli ekujoliswe kubo kwesi sikhokelo somsebenzisi?

Amaxwebhu / Izibonelelo

Iimbekiselo

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