SYnOPSYS FPGA Synthesis Synplify Pro for Microsemi Edition User Guide

Synopsys FPGA Synthesis - Synplify Pro ya Microsemi Edition
ndi chida chokwanira pakukhazikitsa FPGA ndi zosiyanasiyana
zida zopangidwa kuti zithandizire ogwiritsa ntchito popanga logic ndi kapangidwe
umayenda.

Malangizo Ogwiritsira Ntchito Zogulitsa

Mutu 1: Mawu Oyamba

Chaputala ichi chikupereka chomalizaview za Synopsys FPGA ndi
Prototyping Products, FPGA Implementation Tools, ndi Synopsys FPGA
Chida Features.

Kuchuluka kwa Document

Seti ya chikalatacho imaphatikizapo zambiri pazogulitsa
ndipo idapangidwira ogwiritsa ntchito omwe ali ndi chidwi ndi kaphatikizidwe ndi kapangidwe ka FPGA
umayenda.

Kuyambapo

Kuti muyambe kugwiritsa ntchito pulogalamuyo, yambani kutsatira zomwe zaperekedwa
malangizo ndi kutchula kalozera wogwiritsa ntchito kuti akuthandizeni.

User Interface Yathaview

Dziwani bwino mawonekedwe a ogwiritsa ntchito
yendani m'mapulogalamu.

Mutu 2: FPGA Synthesis Design Flows

Mutuwu umafotokoza za Logic Synthesis Design Flow ya FPGA
kaphatikizidwe.

Mutu 3: Kukonzekera Zolowetsa

Phunzirani momwe mungagwiritsire ntchito Mixed Language Source Files ndi Zowonjezera
Compiler pokonzekera zolowetsa bwino.

Zindikirani: Dziwani zoperewera zilizonse zomwe zikugwirizana nazo
pogwiritsa ntchito Incremental Compiler.

FAQ

Q: Kodi ndingapange makope a zolembedwazo?

A: Inde, mgwirizano wa laisensi umalola kupanga makope amkati
gwiritsani ntchito ndi chidziwitso choyenera.

Q: Kodi ndingayambe bwanji pulogalamuyo?

A: Onani gawo la “Chiyambi” mu Mutu 1 wa
kalozera wogwiritsa ntchito malangizo atsatanetsatane oyambira pulogalamuyo.

Q: Ndi anthu ati omwe akufuna kuti agwiritse ntchito bukhuli?

A: Buku la ogwiritsa ntchito limayang'ana anthu omwe ali ndi chidwi ndi FPGA
kaphatikizidwe ndi mapangidwe oyenda.

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Synopsys FPGA Synthesis
Synplify Pro ya Microsemi Edition
Wogwiritsa Ntchito
Okutobala 2014

Chidziwitso Chaumwini ndi Zambiri Zaumwini
Copyright © 2014 Synopsy, Inc. Ufulu wonse ndi wotetezedwa. Mapulogalamuwa ndi zolembedwazi zili ndi zinsinsi komanso zaumwini zomwe ndi katundu wa Synopsys, Inc. Mapulogalamuwa ndi zolemba zimaperekedwa pansi pa mgwirizano wa laisensi ndipo zitha kugwiritsidwa ntchito kapena kukopera molingana ndi pangano la layisensi. Palibe gawo la pulogalamuyo ndi zolembedwa zomwe zitha kupangidwanso, kufalitsidwa, kapena kumasuliridwa mwanjira iliyonse kapena mwanjira ina iliyonse, zamagetsi, zamakina, pamanja, zamaso, kapena mwanjira ina, popanda chilolezo cholembedwa ndi Synopsys, Inc., kapena monga momwe zaperekedwa ndi pangano lalayisensi.
Ufulu Wokopera Zolemba
Mgwirizano wa laisensi ndi Synopsys umalola yemwe ali ndi chilolezo kupanga makope a zolembazo kuti azigwiritsa ntchito mkati mwawo.
Kope lililonse liphatikizepo zokopera zonse, zizindikiritso, zizindikiro zautumiki, ndi zidziwitso za eni ake, ngati zilipo. Wopereka chilolezo ayenera kupereka manambala otsatizana kwa makope onse. Makope awa azikhala ndi nthano iyi patsamba loyamba:
"Chikalatachi chinabwerezedwa ndi chilolezo cha Synopsy, Inc., kuti chigwiritsidwe ntchito ndi ______________________________________________________ ndi antchito ake. Iyi ndi nambala yakope __________."
Chidziwitso Choyang'anira Kopita
Zonse zaukadaulo zomwe zili m'bukuli zili pansi pa malamulo oyendetsera katundu wa United States of America. Kuwulula kwa nzika zamayiko ena motsutsana ndi malamulo a United States ndikoletsedwa. Ndi udindo wa owerenga kudziwa malamulo omwe akugwiritsidwa ntchito ndikuwatsatira.
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Synplify Pro for Microsemi Edition User Guide October 2014

Chodzikanira
SYNOPSYS, INC., NDI OPEREKA ZIPHUNZITSI AKE PALIBE CHISINDIKIZO CHA MTIMA ULIWONSE, CHOCHITIKA KAPENA CHOCHITIKA, PAMODZI NDI CHINTHU IZI, KUPHATIKIZAPO, KOMA ZOSAKHALA MALIRE, ZIZINDIKIRO ZOFUNIKA KUCHITA NTCHITO NDI KUKHALA KWA NTCHITO.
Zizindikiro Zolembetsedwa (®)
Synopsy, AEON, AMPS, Astro, Behaviour Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, CODE V, Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, HSPICE, Identify, MesTool, Model, MAST NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, Zotsatira Zabwino Kwambiri, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Synplicity, Synplicity, Synplicity logo, Synplify, Synplify Environment, UMCS Contraints, UMX Vera, ndi YIELDirector ndi zizindikilo zolembetsedwa za Synopsys, Inc.
Zizindikiro (TM)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Katswiri, DC Professional, DC HD Ultra, DFTLMAX Design, Analyzer Design, Analyzer Design, Design Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Intelli, Jupiter-TDP, Jupiter-XDP, Jupiter-XDP, Jupiter-SIC Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Miciroid-Ripple, Satellite SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, ndi Worksheet Buffer ndi zizindikiro za Synopsys, Inc.

Synplify Pro for Microsemi Edition User Guide October 2014

Zizindikiro zautumiki (sm)
MAP-in, SVP Café, ndi TAP-in ndi zizindikiro za Synopsys, Inc. SystemC ndi chizindikiro cha Open SystemC Initiative ndipo amagwiritsidwa ntchito pansi pa laisensi. ARM ndi AMBA ndi zilembo zolembetsedwa za ARM Limited. Saber ndi chizindikiro cholembetsedwa cha SabreMark Limited Partnership ndipo imagwiritsidwa ntchito pansi pa layisensi. Mayina ena onse amalonda kapena akampani akhoza kukhala zizindikilo za eni ake.
Idasindikizidwa ku USA October 2014

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Synplify Pro for Microsemi Edition User Guide October 2014

Zamkatimu

Mutu 1: Mawu Oyamba
Synopsys FPGA ndi Prototyping Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FPGA Implementation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synopsys FPGA Tool Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Kuchuluka kwa Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Document Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Omvera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Kuyambapo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Kuyambitsa Mapulogalamu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Kupeza Thandizo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
User Interface Yathaview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mutu 2: FPGA Synthesis Design Flows
Logic Synthesis Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mutu 3: Kukonzekera Zolowetsa
Kupanga HDL Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Kupanga Gwero la HDL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Kugwiritsa Ntchito Context Help Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Kuyang'ana Gwero la HDL Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Kusintha Gwero la HDL Files ndi Built-in Text Editor. . . . . . . . . . . . . . . . . . . . 35 Kukhazikitsa Zokonda Zenera Zosintha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Kugwiritsa Ntchito Zolemba Zakunja. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Kugwiritsa Ntchito Zowonjezera Laibulale ya Laibulale ya Verilog Files. . . . . . . . . . . . . . . . . . . . . . . 42
Kugwiritsa Ntchito Chinenero Chosakanikirana Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Kugwiritsa Ntchito Zowonjezera Zowonjezera. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Zolepheretsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Kugwiritsa Ntchito Structural Verilog Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Zolepheretsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Synplify Pro for Microsemi Edition User Guide October 2014

Kugwira ntchito ndi Constraint Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Nthawi Yomwe Mungagwiritsire Ntchito Kuletsa Files over Source Code . . . . . . . . . . . . . . . . . . . . . . . . 53 Kugwiritsa Ntchito Text Editor Pazovuta Files (Cholowa). . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Syntax Guidelines for Constraint Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Kuwona Zoletsa Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Mutu 4: Kukhazikitsa Logic Synthesis Project
Kupanga Project Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Kupanga Ntchito File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Kutsegula Ntchito Yomwe ilipo File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Kusintha kwa Ntchito . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Kukhazikitsa Pulojekiti View Zokonda Zowonetsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Kusintha Verilog Phatikizani Njira mu Ntchito Yakale Files. . . . . . . . . . . . . . . . . . . . 65
Kuwongolera Ntchito File Utsogoleri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Kupanga Mafoda Amakonda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Kuwongolera Mafoda a Pulojekiti Yachizolowezi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Kusokoneza Mwambo Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Kukhazikitsa Zothandizira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Kugwira Ntchito Ndi Zambiri. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Kukhazikitsa Logic Synthesis Implementation Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Kukhazikitsa Zosankha Zachipangizo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Setting Optimization Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Kutchula Mafupipafupi ndi Zoletsa Padziko Lonse Files. . . . . . . . . . . . . . . . . . . . . . 80 Kutchula Zosankha Zotsatira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Kutchula Lipoti la Nthawi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Kukhazikitsa Zosankha za Verilog ndi VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Kufotokozera Makhalidwe ndi Malangizo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Kufotokozera Makhalidwe ndi Malangizo mu VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Kufotokozera Makhalidwe ndi Malangizo mu Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . 92 Kufotokozera Makhalidwe Kugwiritsa Ntchito SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . 93 Kutchula Makhalidwe mu Zoletsa File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Kufufuza Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Kuzindikira Files kuti Fufuzani . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Kusefa kwa Files kuti Fufuzani . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Kuyambitsa Kusaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Search Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LO
Kusunga zakale Files ndi Ntchito. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Sungani Ntchito Yosungidwa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Chotsani Ntchito Yosungidwa mu Archive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Synplify Pro for Microsemi Edition User Guide October 2014

Koperani Ntchito. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Mutu 5: Kutchula Zopinga
Kugwiritsa ntchito SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Kupanga Zolepheretsa mu SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Kupanga Zopinga Ndi FDC Template Command. . . . . . . . . . . . . . . . 116
Kutchula Zolepheretsa SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Zolepheretsa Kulowetsa ndi Kusintha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Kukhazikitsa Koloko ndi Zolepheretsa Panjira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Kufotokozera Zolepheretsa Kulowetsa ndi Kutulutsa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Kutchula Mitundu Ya Padi ya I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Kugwiritsa ntchito TCL View ya SCOPE GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Malangizo Olowera ndi Kusintha Zolepheretsa. . . . . . . . . . . . . . . . . . . . . . . . 127
Kutchula Kupatula Nthawi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Kufotokozera Kuchokera/Kupita/Kupyolera M'Mfundo Zosankha Nthawi . . . . . . . . . . . . . . . . . 130 Kufotokozera Njira Zochita Zambiri. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Kufotokozera Njira Zonama . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Kupeza Zinthu ndi Tcl pezani ndikukulitsa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Kutchula Zitsanzo Zosaka za Tcl kupeza. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Refining Tcl Pezani Zotsatira ndi -sefa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Kugwiritsa Ntchito Tcl Pezani Lamulo Kufotokozera Zosonkhanitsidwa. . . . . . . . . . . . . . . . . . . . . 138 Kugwiritsa Ntchito Tcl kulitsa Lamulo Kufotokozera Zosonkhanitsidwa. . . . . . . . . . . . . . . . . . 140 Kuyang'ana Tcl pezani ndikukulitsa Zotsatira. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Pogwiritsa ntchito Tcl pezani ndikukulitsa mu Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Kugwiritsa Ntchito Zosonkhanitsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Kufananiza Njira Zofotokozera Zosonkhanitsira. . . . . . . . . . . . . . . . . . . . . . . 144 Kupanga ndi Kugwiritsa Ntchito Zosonkhanitsira SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Kupanga Zosonkhanitsira pogwiritsa ntchito Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Viewing ndi Kuwongolera Zosonkhanitsidwa ndi Tcl Commands. . . . . . . . . . . . . . . 150
Kusintha SDC kukhala FDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Kugwiritsa ntchito SCOPE Editor (Cholowa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Kulowetsa ndi Kusintha Zolepheretsa KULIMBIKITSA (Cholowa) . . . . . . . . . . . . . . . . . . . . . 157 Kutchula KULIMBITSA Zolepheretsa Nthawi (Cholowa) . . . . . . . . . . . . . . . . . . . . . . . 159 Kulowetsa Zopinga Zosasinthika. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Kukhazikitsa Koloko ndi Zopinga za Panjira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Kufotokozera Mawotchi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Kufotokozera Zolepheretsa Kulowetsa ndi Kutulutsa (Cholowa) . . . . . . . . . . . . . . . . . . . . . . . 169 Kufotokozera Njira Zabodza (Cholowa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 6: Kupanga ndi Kusanthula Zotsatira
Kupanga Mapangidwe Anu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Kuthamanga kwa logic kaphatikizidwe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Kugwiritsa Ntchito Zofufuza Zaposachedwa za Kasamalidwe ka Ntchito . . . . . . . . . . . . . . . . . . . . . . 174
Kuwona Logi File Zotsatira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ViewKugwira ntchito ndi Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Kupeza Malipoti Achindunji Mwachangu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Kupeza Zotsatira Patali . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Kusanthula Zotsatira Pogwiritsa Ntchito Lolemba File Malipoti . . . . . . . . . . . . . . . . . . . . . . . . . 189 Kugwiritsa Ntchito Zenera la Ulonda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Kuyang'ana Kugwiritsa Ntchito Zida. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Kusamalira Mauthenga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Kuyang'ana Zotsatira mu Uthenga Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Kusefa Mauthenga mu Uthenga Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Kusefa Mauthenga kuchokera pa Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Kusintha Mauthenga Kusefa ndi Tcl Script. . . . . . . . . . . . . . . . . . . . . . . . 198 Chithunzi File Maulamuliro a Mauthenga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Kugwira Machenjezo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Kugwiritsa Ntchito Pitirizani Kulakwitsa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Kugwiritsa Ntchito Pitirizani Pa Kulakwitsa Pakuphatikiza Mfundo Zophatikiza. . . . . . . . . . . . . . . . . . . 203
Mutu 7: Kusanthula ndi HDL Analyst ndi FSM Viewer
Kugwira ntchito mu Schematic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Kusiyanitsa Pakati pa HDL Analyst Views. . . . . . . . . . . . . . . . . . . . . . . . 209 Kutsegula kwa Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Viewing Katundu Wazinthu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Kusankha Zinthu mu RTL/Technology Views. . . . . . . . . . . . . . . . . . . . . . . 215 Kugwira ntchito ndi Multisheet Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Kusuntha Pakati Views mu Zenera la Schematic. . . . . . . . . . . . . . . . . . . . . . . 218 Kukhazikitsa dongosolo View Zokonda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Kuwongolera Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Kuwona Mapangidwe Apamwamba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Traversing Design Hierarchy ndi Hierarchy Browser. . . . . . . . . . . . . . . . 222 Kuwunika Ulamuliro Wazinthu Mwakukankha/Kudumpha. . . . . . . . . . . . . . . . . . . . . . . 223 Kuwunika Zinthu Zoyang'anira Zinthu Zowonekera. . . . . . . . . . . . . . . . . . . 228
Kupeza Zinthu . . . . . . . . . . . . .LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Kusakatula Kuti Mupeze Zinthu mu HDL Analyst Views. . . . . . . . . . . . . . . . . . . . . . . 230 Kugwiritsa Ntchito Search for Hierarchical and Restrict Searches . . . . . . . . . . . . . . . . . . . . 232 Kugwiritsa Ntchito Wildcards ndi Pezani Lamulo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Synplify Pro for Microsemi Edition User Guide October 2014

Kuphatikiza Pezani ndi Sefa kuti Mukonze Zosaka . . . . . . . . . . . . . . . . . . . . . . 240 Kugwiritsa Ntchito Fufuzani Kuti Mufufuze Mauthenga Otuluka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing mkati mwa RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing kuchokera ku RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 244 Crossprobing kuchokera pawindo la Text Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Crossprobing kuchokera pawindo la Tcl Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Crossprobing kuchokera ku FSM Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Kusanthula ndi Chida cha HDL Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Viewing Design Hierarchy ndi Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Sefa Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Kukulitsa Pin ndi Net Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Kukulitsa ndi Viewndi Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Flattening Schematic Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Kuchepetsa Kugwiritsa Ntchito Memory Pamene Mukusanthula Mapangidwe. . . . . . . . . . . . . . . . . . . 267
Kugwiritsa ntchito FSM Viewndi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Mutu 8: Kusanthula Nthawi
Kusanthula Nthawi mu Schematic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Viewing Information Nthawi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Chidziwitso cha Nthawi mu Schematic Views. . . . . . . . . . . . . . . . . . 275 Kusanthula Mitengo ya Clock mu RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Viewing Njira Zovuta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Kuthana ndi Ulesi Woipa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Kupanga Malipoti Anthawi Yake ndi STA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Kugwiritsa Ntchito Zoletsa Zopangira Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Zochitika Zogwiritsa Ntchito Zoletsa Zopangira Analysis. . . . . . . . . . . . . . . . . . . . . . 285 Kupanga ADC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Kugwiritsa Ntchito Mayina Azinthu Molondola mu adc File . . . . . . . . . . . . . . . . . . . . . . . . . 290
Kugwiritsa Ntchito Auto Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Zotsatira za Zoletsa Magalimoto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Mutu 9: Kutengera Zinthu Zapamwamba
Kufotokozera Mabokosi Akuda a kaphatikizidwe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Box ndi I/Os ku Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Box ndi I/Os mu VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 300 Kuwonjezera Zoletsa Zanthawi ya Black Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Kuonjeza Zina Zina Zabokosi Lakuda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Synplify Pro for Microsemi Edition User Guide October 2014

Kufotokozera Makina a Boma a Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Kufotokozera Makina a Boma ku Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Kufotokozera Makina a Boma mu VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Kutchula ma FSM okhala ndi Makhalidwe ndi Malangizo. . . . . . . . . . . . . . . . . . . . . . . . 309
Kufotokozera Ma FSM otetezeka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Automatic RAM Inference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 block RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Makhalidwe a RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Inferring Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Kuyambitsa ma RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Kuyambitsa ma RAM ku Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Kuyambitsa ma RAM mu VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Chaputala 10: Kutchula Zokonda Zopangira
Malangizo Owonjezera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Malangizo a 330 General Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Kukometsa Malo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Kukonzekeletsa Nthawi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Kubwereza nthawi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Kuwongolera Kusunga Nthawi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Kubwezeretsa Nthawi Eksample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Retiming Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Momwe Kubwezeretsa Nthawi Kumagwirira Ntchito . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Kusunga Zinthu Kuti Zisamakozedwe Kutali . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Kugwiritsa ntchito syn_keep posungira kapena kubwereza. . . . . . . . . . . . . . . . . . . . . . . 343 Kulamulira Kuphwanyika kwa Utsogoleri Waukulu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Kusunga Utsogoleri Waukulu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Konzani Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Kukhazikitsa Malire a Fanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Kuwongolera Kuyimitsa ndi Kubwereza. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Kugawana Zothandizira . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Kuyika ma I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Kupititsa patsogolo Makina a Boma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Kusankha Nthawi Yokonzekera Makina a Boma. . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Kuyendetsa FSM Compiler LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Kuthamanga kwa FSM Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Kulowetsa Zofufuza . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Synplify Pro for Microsemi Edition User Guide October 2014

Kufotokozera Zofufuza mu Code Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Kuwonjezera Mawonekedwe a Probe Molumikizana. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Mutu 11: Kugwira Ntchito ndi Kusonkhanitsa Mfundo
Lembani Zoyambira Zoyambira. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Advantagndi Compile Point Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Pamanja Lembani Mfundo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Nested Compile Mfundo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Phatikizani Mitundu ya Mfundo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Sungani Zoyambira Zoyambira. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Phatikizani Zoletsa Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Interface Logic Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Interface Nthawi Yophatikiza Mfundo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Phatikizani Kaphatikizidwe ka Mfundo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Zowonjezera Zophatikiza Zophatikiza Mfundo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Ndemanga za Patsogolo Zoletsa Kusunga Nthawi . . . . . . . . . . . . . . . . 384
Kupanga Mfundo Zophatikiza . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Mayendedwe A Buku Lophatikiza Mfundo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Kupanga Zopinga Zapamwamba File za Kusonkhanitsa Mfundo . . . . . . . . . . . . . . . . 388 Kufotokozera Mfundo Zophatikiza Buku. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Kukhazikitsa Zolepheretsa Pagulu Lophatikiza Mfundo . . . . . . . . . . . . . . . . . . . . . . . . 391 Kusanthula Zotsatira Zophatikiza Mfundo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Kugwiritsa Ntchito Zophatikiza Zophatikiza ndi Zina. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Kuphatikiza Kuphatikiza Mfundo ndi Multiprocessing. . . . . . . . . . . . . . . . . . . . . . . 396
Resynthesizing Mochulukira. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Kukonzanso Kuphatikiza Mfundo Mochulukira . . . . . . . . . . . . . . . . . . . . . . . . . 397
Mutu 12: Kugwira ntchito ndi IP Input
Kupanga IP ndi SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Kutchula ma FIFO okhala ndi SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Kufotokozera ma RAM okhala ndi SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Kufotokozera ma Byte-Enable RAMs okhala ndi SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . 416 Kutchula ma ROM okhala ndi SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Kutchula Adder/Subtractors okhala ndi SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Kufotokozera Zowerengera ndi SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
The Synopsys FPGA IP Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Tsopanoview za Synopsys FPGA IP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Encryption ndi Decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Kugwira ntchito ndi Encrypted IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Synplify Pro for Microsemi Edition User Guide October 2014

Kubisa IP Yanu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Encrypting IP ndi encryptP1735.pl Script. . . . . . . . . . . . . . . . . . . . . . . . . 448 Encrypting IP ndi encryptIP Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Kufotokozera Njira Zotulutsa Zolemba. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Kukonzekera Phukusi la IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Kugwiritsa ntchito Hyper Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Kugwiritsa Ntchito Hyper Source kwa Prototyping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Kugwiritsa Ntchito Hyper Source ya IP Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Kuwombera Zizindikiro Kupyolera mu Mapangidwe Apamwamba a IP. . . . . . . . . . . . . . . 461
Mutu 13: Kukometsa Njira Zopangira Zopanga
Kugwiritsa Ntchito Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Running Batch Mode pa Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Running Batch Mode yokhala ndi Tcl Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Zilolezo Zamzere. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Kugwira ntchito ndi Tcl Scripts ndi Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Kugwiritsa Ntchito Malamulo a Tcl ndi Zolemba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Kupanga Zolemba za Ntchito. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Kukhazikitsa Nambala ya Ntchito Zofanana. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Kupanga Tcl Synthesis Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Kugwiritsa Ntchito Zosintha za Tcl Kuyesa Mawotchi Osiyanasiyana. . . . . . . . . . . . . . . . . . 476 Kugwiritsa Ntchito Zosintha za Tcl Kuyesa Matekinoloje Angapo A Target. . . . . . . . . . . . . . . . . 478 Kuthamanga Pansi-mmwamba kaphatikizidwe ndi Script . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Automating Flows ndi synhooks.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Mutu 14: Kugwiritsa Ntchito Multiprocessing
Multiprocessing With Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Kukhazikitsa Ntchito Zofanana Kwambiri . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Kugwiritsa Ntchito License. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Mutu 15: Kukonzekera kwa Microsemi Designs
Kupititsa patsogolo Mapangidwe a Microsemi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Kugwiritsa Ntchito Mabokosi Akuda a Microsemi Black. . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Kugwiritsa Smartgen Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Kugwira Ntchito ndi Radhard Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Kutchula syn_radhardlevel mu Khodi Yochokera. . . . . . . . . . . . . . . . . . . . . . . 490 LO
Mutu 16: Kugwira Ntchito ndi Zotulutsa Zophatikiza
Kutumiza Zambiri ku P&R Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Synplify Pro for Microsemi Edition User Guide October 2014

Kufotokozera Malo a Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Kutchula Malo Oyendera Mabasi a Microsemi . . . . . . . . . . . . . . . . . . . . . . . . . 495 Kufotokozera Macro ndi Kuyika Kaundula. . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Kupanga Zotulutsa Zapadera Zaogulitsa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Kutsata Kutulutsa Kwa Wogulitsa Wanu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Kusintha Mawonekedwe a Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Mutu 17: Kuthamanga kwa Post-Synthesis Operations
Kuthamanga P&R Mwachangu pambuyo Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Kugwira ntchito ndi Dziwani Zida. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Kukhazikitsa kuchokera ku Synplify Pro Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Kuthana ndi Mavuto ndi Kukhazikitsa Dziwani . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Kugwiritsa Ntchito Chida Chozindikiritsa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Kugwiritsa Ntchito Kuphatikiza Mfundo ndi Chida Chozindikiritsa. . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Kuyerekeza ndi Chida cha VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Synplify Pro for Microsemi Edition User Guide October 2014

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Synplify Pro for Microsemi Edition User Guide October 2014

MUTU 1
Mawu Oyamba
Mawu oyamba awa a pulogalamu ya Synplify Pro® akufotokoza izi:
· Synopsys FPGA and Prototyping Products, patsamba 16 · Scope of the Document, patsamba 21 · Kuyamba, patsamba 22 · User Interface Overview, patsamba 24

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 1: Mawu Oyamba

Synopsys FPGA ndi Prototyping Products

Synopsys FPGA ndi Prototyping Products
Chithunzi chotsatira chikuwonetsa Synopsys FPGA ndi Prototyping banja lazinthu.

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Synplify Pro for Microsemi Edition User Guide October 2014

Synopsys FPGA ndi Prototyping Products

Mutu 1: Mawu Oyamba

FPGA Implementation Zida
Zogulitsa za Synplify Pro ndi Synplify Premier ndi zida zophatikizira za RTL makamaka zopangidwira ma FPGAs (zosanjikiza zam'munda) ndi ma CPLD (zida zovuta zofikira).

Synplify Pro Synthesis Software
Synplify Pro FPGA synthesis software ndiye mulingo wamakampani opanga zinthu zapamwamba komanso zotsika mtengo za FPGA. Zake zapadera
Behaviour Extracting Synthesis Technology® (BEST) ma aligorivimu, chitani
kukhathamiritsa kwapamwamba musanaphatikize kachidindo ka RTL kukhala malingaliro enieni a FPGA. Njirayi imalola kukhathamiritsa kwapamwamba kudera lonse la FPGA, kuthamanga kwachangu, komanso kuthekera kogwiritsa ntchito mapangidwe akulu kwambiri. Pulogalamu ya Synplify Pro imathandizira chilankhulo chaposachedwa cha VHDL ndi Verilog kuphatikiza SystemVerilog ndi VHDL 2008. Chidachi ndi ukadaulo wodziyimira pawokha kulola kuyambiranso mwachangu komanso kosavuta pakati pa zida za FPGA ndi ogulitsa kuchokera ku polojekiti imodzi yokha.

Synplify Premier Synthesis Software
Magwiridwe a Synplify Premier ndi chida chapamwamba cha Synplify Pro, chomwe chimapereka mwayi womaliza wa FPGA ndikuwongolera chilengedwe. Zimaphatikizanso zida zambiri ndi matekinoloje a opanga apamwamba a FPGA, komanso amagwiranso ntchito ngati injini yophatikizira ma prototypers a ASIC omwe amayang'ana ma prototypes amodzi a FPGA.
Chogulitsa cha Synplify Premier chimapereka onse opanga ma FPGA ndi ma prototypers a ASIC omwe amayang'ana ma FPGA amodzi omwe ali ndi njira yabwino kwambiri yokhazikitsira ndi kukonza zolakwika. Kumbali yokhazikitsa mapangidwe, kumaphatikizapo magwiridwe antchito a kutseka kwanthawi, kutsimikizira malingaliro, kugwiritsa ntchito IP, kuyanjana kwa ASIC, ndi kukhazikitsa kwa DSP, komanso kuphatikiza kolimba ndi zida zomaliza za FPGA ogulitsa. Kumbali yochotsa zolakwika, imapereka kutsimikizika kwadongosolo kwa FPGAs komwe kumathandizira kwambiri kukonza zolakwika, ndikuphatikizanso njira yofulumira komanso yowonjezereka yopezera zovuta zamapangidwe.

Chida cha Synopsys FPGA Chida
Gome ili limasiyanitsa magwiridwe antchito mu Synplify Pro, Synplify, Synplify Premier, ndi Synplify Premier yokhala ndi zinthu za Design Planner.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 1: Mawu Oyamba

Synopsys FPGA ndi Prototyping Products

Synplify Synplify Pro

Kachitidwe

Kaphatikizidwe Wotulutsa Khalidwe

Technology® (BESTTM)

Core/IP Yopangidwa ndi Vendor

Thandizo (matekinoloje ena)

Wopanga FSM

FSM Explorer

Kutembenuka kwa Gated Clock

SCOPE® Constraint Entry

Mkulu kudalirika mbali

Malo ophatikizika ndi njira

Kusanthula

HDL Analyst®

Njira

Nthawi Analyzer

Mfundo ndi mfundo

Mtengo wa FSM Viewer

Crossprobing

Probe Point Creation

Identify® Instrumentor

Dziwani Debugger

Kusanthula mphamvu (SAIF)

Mapangidwe Athupi

Design Plan File

Kugawa kwa logic ku zigawo

Synplify Premier
x
x
xxxxxx
xx
xxxx

Synplify Premier DP
x
x
xxxxxx
xx
xxxx
xx

Synplify Pro for Microsemi Edition User Guide October 2014

Synopsys FPGA ndi Prototyping Products

Mutu 1: Mawu Oyamba

Kuyerekeza kwa Dera ndi Chigawo Chakuthekera kwa Pini Yopatsa Kukhathamiritsa Kwathupi Kaphatikizidwe Kathupi Katswiri Synopsys DesignWare® Foundation Library Runtime Hierarchical Design Kupititsa patsogolo Kukonzekera Kwachangu Kuphatikizira Kuphatikiza Pazolakwika Mapangidwe a Gulu Lophatikiza Zinenero Kapangidwe Kophatikiza Mfundo Zopangira Mapangidwe Otsogola License Yowona Batch GUI (Floating License) Floating Mode (Floating Mode) Batch Mode P&R Back-innotation ya P&R Data Formal Verification

Synplify Synplify Pro

xxx

–

Dziwani Kuphatikizika

Zochepa

Synplify Premier
xxx
xxxx
xxx
x
x logic synthesis mode x

Synplify Premier DP
x
xxxx
xxxx
xxx
x
xx Logic synthesis mode
x

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 1: Mawu Oyamba

Synopsys FPGA ndi Prototyping Products

Ndemanga zakumbuyo za P&R Data Design Environment Text Editor View Onerani Window Message Window Tcl Window Multiple Implementations Vendor Technology Support Prototyping Features Zomwe Zimagwira Ntchito Nthawi Yokonzekera Phatikizani Mfundo Zosintha za Gated Clock Pankhani Yolakwika

Synplify Synplify Pro

Synplify Premier
xxxx Wasankhidwa
xxx

Synplify Premier DP
x
xxxx Wasankhidwa
xxx

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Synplify Pro for Microsemi Edition User Guide October 2014

Kuchuluka kwa Document

Mutu 1: Mawu Oyamba

Kuchuluka kwa Document
Zotsatirazi zikufotokozera kukula kwa chikalatachi ndi anthu omwe akufuna.

Document Set
Bukuli ndi gawo la zolemba zomwe zili ndi buku lofotokozera komanso maphunziro. Amapangidwa kuti agwiritsidwe ntchito ndi zolemba zina zomwe zili mu seti. Imayang'ana kwambiri kufotokozera momwe mungagwiritsire ntchito pulogalamu ya Synopsys FPGA kuti mukwaniritse ntchito zanthawi zonse. Izi zikutanthauza kuti:
· Buku logwiritsa ntchito limangofotokozera zomwe mungachite kuti mugwire ntchito zomwe zimafanana
zafotokozedwa mu bukhuli. Sichimalongosola lamulo lililonse ndi njira yomwe ilipo. Kuti mumve mafotokozedwe athunthu amitundu yonse yamalamulo ndi mawu ofotokozera, onani User Interface Overview mutu mu Synopsys FPGA Synthesis Reference Manual.
· Buku la ogwiritsa ntchito lili ndi zidziwitso zozikidwa pa ntchito. Za kusweka kwa
mmene chidziŵitso chimalinganizidwira, onani Getting Help, patsamba 22.

Omvera
Chida cha pulogalamu ya Synplify Pro chalunjika kwa wopanga makina a FPGA. Zimaganiziridwa kuti mumadziwa izi:
· Kaphatikizidwe kamangidwe · RTL · FPGAs · Verilog/VHDL

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 1: Mawu Oyamba

Kuyambapo

Kuyambapo
Gawoli likukuwonetsani momwe mungayambitsire pulogalamu ya Synopsys FPGA synthesis. Imalongosola mitu yotsatirayi, koma sikuposa zomwe zili mu malangizo oyika okhudza kupereka zilolezo ndi kukhazikitsa:
· Kuyambitsa Mapulogalamu, patsamba 22 · Kupeza Thandizo, patsamba 22

Kuyambira Software
1. Ngati simunatero, ikani pulogalamu ya Synopsys FPGA kaphatikizidwe malinga ndi malangizo oyika.
2. Yambitsani mapulogalamu.
Ngati mukugwira ntchito pa nsanja ya Windows, sankhani
Mapulogalamu-> Synopsy-> mtundu wazinthu kuchokera pa batani loyambira.
Ngati mukugwira ntchito pa nsanja ya UNIX, lembani zoyenera
lamula pamzere wolamula:
synplify_pro
· Lamulo akuyamba chida kaphatikizidwe, ndi kutsegula Project zenera. Ngati
mwayendetsa pulogalamuyo kale, zenera likuwonetsa polojekiti yapitayi. Kuti mudziwe zambiri za mawonekedwe, onani User Interface Overview mutu wa Buku Lothandizira.

Kupeza Thandizo
Musanayimbire Synopsys Support, yang'anani zomwe zalembedwa. Mutha kupeza zambiri pa intaneti kuchokera pa menyu Thandizo, kapena onani mtundu wa PDF. Gome ili m’munsili likusonyeza mmene mfundozo zimasanjidwira.

Synplify Pro for Microsemi Edition User Guide October 2014

Kuyambapo
Kuti muthandizidwe ndi... Kugwiritsa ntchito mawonekedwe a mapulogalamu Momwe munga...
Zambiri zoyenda
Mauthenga olakwika Mawonekedwe a Layisensi ndi malangizo Kaphatikizidwe Zinenero ndi mawu a Tcl syntax Tcl synthesis imalamula Zosintha zamalonda

Mutu 1: Mawu Oyamba
Onani ku… Synopsys FPGA Synthesis User Guide Synopsys FPGA Synthesis User Guide, zolemba zothandizira pa chithandizo. web site Synopsys FPGA Synthesis User Guide, zolemba za ntchito pa chithandizo web Thandizo pa intaneti (sankhani Thandizo-> Mauthenga Olakwika) Synopsy SolvNet Website Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Thandizo pa intaneti (sankhani Thandizo-> Thandizo la Tcl) Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual (Web menyu malamulo)

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 1: Mawu Oyamba

User Interface Yathaview

User Interface Yathaview
Mawonekedwe a ogwiritsa ntchito (UI) amakhala ndi zenera lalikulu, lotchedwa Project view, ndi mazenera apadera kapena views ntchito zosiyanasiyana. Kuti mumve zambiri za chilichonse mwazinthuzi, onani Mutu 2, User Interface Overview ya Synopsys FPGA Synthesis Reference Manual.

Synplify Pro Interface

Dinani batani

Toolbar Project view

Mkhalidwe

Zotsatira za Kukhazikitsa view

Ma tabu oti mufike views

Tcl Script/Mauthenga Zenera LO

Penyani Zenera

Synplify Pro for Microsemi Edition User Guide October 2014

MUTU 2
FPGA Synthesis Design Imayenda
Mutuwu ukufotokoza za Logic Synthesis Design Flow, patsamba 26.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 2: FPGA Synthesis Design Flows

Logic Synthesis Design Flow

Zida za Synopsys FPGA zimapanga malingaliro poyambitsa kaye gwero la RTL kukhala zopanga zodziyimira pawokha paukadaulo, kenako kukhathamiritsa ndi kupanga mapu amalingaliro kuzinthu zaukadaulo. Pambuyo pa kaphatikizidwe ka logic, chidacho chimapanga mndandanda wazinthu zotsatizana ndi ogulitsa ndi zopinga. file zomwe mungagwiritse ntchito ngati zolowetsa ku chida cha malo-ndi-njira (P&R).
Chithunzi chotsatirachi chikuwonetsa magawo ndi zida zomwe zimagwiritsidwa ntchito popanga malingaliro ndi zina mwazolowera ndi zotuluka. Mutha kugwiritsa ntchito pulogalamu ya Synplify Pro synthesis pakuyenda uku. Kusanthula kwa nthawi yolumikizana ndikosankha. Ngakhale mayendedwe akuwonetsa kuletsa kwa ogulitsa files monga zolowera mwachindunji ku chida cha P&R, muyenera kuwonjezera izi files ku projekiti ya kaphatikizidwe yowerengera nthawi mabokosi akuda.

Chida cha Synopsys FPGA

Mtengo RTL

Kupanga kwa RTL

FDC

Logic Synthesis

Synthesized netlist Synthesis zopinga Zoletsa za ogulitsa
Chida Chogulitsa
Malo & Njira

Logic Synthesis Procedure

Kwa mapangidwe oyenda ndi malangizo a sitepe ndi sitepe potengera mapangidwe enieni

data, koperani maphunziro kuchokera ku webmalo. Masitepe otsatirawa afotokoze mwachidule

njira synthesizing kamangidwe, amenenso zikusonyezedwa mu

chithunzi chotsatira.

1. Pangani polojekiti.

2. Onjezani gwero files ku polojekiti.

Synplify Pro for Microsemi Edition User Guide October 2014

Logic Synthesis Design Flow

Mutu 2: FPGA Synthesis Design Flows

3. Khazikitsani mawonekedwe ndi zopinga pakupanga.
4. Khazikitsani zosankha za kukhazikitsa mu bokosi la Implementation Options dialog.
5. Dinani Thamangani kuti mugwiritse ntchito logic synthesis.
6. Unikani zotsatira, pogwiritsa ntchito zida monga chipika file, HDL Analyst schematic views, zenera la Mauthenga ndi Window Yoyang'anira.
Mukamaliza kupanga, mutha kugwiritsa ntchito zotulutsa files kuyendetsa malo-ndi-njira ndi chida cha ogulitsa ndikukhazikitsa FPGA.
Chithunzi chotsatirachi chikuwonetsa masitepe akulu mumayendedwe:

Pangani Project
Onjezani Gwero Files
Khazikitsani Zoletsa
Khazikitsani Zosankha
Kuthamanga Mapulogalamu
Kusanthula Zotsatira Palibe Zolinga Zomwe Zakwaniritsidwa?
Inde Malo ndi Njira

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 2: FPGA Synthesis Design Flows

Logic Synthesis Design Flow

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Synplify Pro for Microsemi Edition User Guide October 2014

MUTU 3
Kukonzekera Zolowetsa
Mukapanga mapangidwe, muyenera kukhazikitsa mitundu iwiri ya filendi: HDL filezomwe zimafotokoza kapangidwe kanu, ndi ntchito files kuyang'anira mapangidwe. Mutuwu ukufotokoza njira zokhazikitsira izi files ndi polojekiti. Zimakhudza izi:
· Kukhazikitsa Gwero la HDL Files, patsamba 30 · Kugwiritsa Ntchito Magwero a Zinenero Zosakanikirana Files, patsamba 44 · Kugwiritsa Ntchito Zowonjezera Zophatikiza, patsamba 49 · Kugwiritsa Ntchito Structural Verilog Flow, patsamba 51 Files, patsamba 53

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kupanga HDL Source Files

Kupanga HDL Source Files
Gawoli likufotokoza momwe mungakhazikitsire gwero lanu files; polojekiti file kukhazikitsidwa kumafotokozedwa mu Setting Up Project Files, patsamba 58. Gwero files ikhoza kukhala mu Verilog kapena VHDL. Kuti mudziwe zambiri zokhudza kupanga files kuti kaphatikizidwe, tchulani Buku Lofotokozera. Gawoli likukamba za mitu iyi:
· Kupanga Gwero la HDL Files, patsamba 30 · Kugwiritsa Ntchito Context Help Editor, patsamba 32 · Kuyang'ana Gwero la HDL Files, patsamba 34 · Kusintha Gwero la HDL Files ndi Built-in Text Editor, patsamba 35 · Kugwiritsa Ntchito Mkonzi Wamalemba Wakunja, patsamba 41 · Kukhazikitsa Zokonda Zazenera, patsamba 39 Files, patsamba 42

Kupanga HDL Source Files
Gawoli likufotokoza momwe mungagwiritsire ntchito cholembera chokhazikika kuti mupange gwero files, koma sapita mwatsatanetsatane za zomwe files muli. Kuti mumve zambiri za zomwe mungathe komanso zomwe simungaphatikizepo, komanso zambiri zokhudzana ndi ogulitsa, onani Buku Lothandizira. Ngati muli ndi source files, mutha kugwiritsa ntchito mkonzi wamawu kuti muwone mawuwo kapena kusintha file (onani Kuwona Gwero la HDL Files, patsamba 34 ndi Kusintha kwa HDL Source Files ndi Built-in Text Editor, patsamba 35).
Mutha kugwiritsa ntchito Verilog kapena VHDL gwero lanu files. The files ali ndi v (Verilog) kapena vhd (VHDL) file zowonjezera, motero. Mutha kugwiritsa ntchito Verilog ndi VHDL files mumapangidwe omwewo. Kuti mudziwe zambiri za kugwiritsa ntchito kusakaniza kwa Verilog ndi VHDL files, onani Kugwiritsa Ntchito Magwero a Zinenero Zosakanikirana Files, patsamba 44.
1. Kupanga gwero latsopano file mwina dinani HDL file icon ( ) kapena chitani zotsatirazi:
Sankhani File-> Chatsopano kapena dinani Ctrl-n.
Mu bokosi la zokambirana Latsopano, sankhani mtundu wa gwero file mukufuna kupanga,
Verilog kapena VHDL. NotLeOkuti mutha kugwiritsa ntchito Context Help Editor pamapangidwe a Verilog omwe ali ndi SystemVerilog amamanga gwero.

Synplify Pro for Microsemi Edition User Guide October 2014

Kupanga HDL Source Files

Mutu 3: Kukonzekera Zolowetsa

file. Kuti mudziwe zambiri, onani Kugwiritsa Ntchito Context Help Editor, patsamba 32.
Ngati mukugwiritsa ntchito mtundu wa Verilog 2001 kapena SystemVerilog, onetsetsani kuti mwayambitsa njira ya Verilog 2001 kapena System Verilog musanagwiritse ntchito kaphatikizidwe (Project-> Implementation Options-> Verilog tab). Verilog yokhazikika file mtundu wama projekiti atsopano ndi SystemVerilog.

Lembani dzina ndi malo a file ndi Dinani Chabwino. Kusintha kopanda kanthu
zenera limatsegula ndi manambala a mzere kumanzere.
2. Lembani gwero pa zenera, kapena kudula ndi kumata izo. Onani Kusintha kwa HDL Source Files ndi Built-in Text Editor, patsamba 35 kuti mudziwe zambiri pakugwira ntchito pawindo la Editing.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kupanga HDL Source Files

Kuti mupeze zotsatira zabwino kwambiri za kaphatikizidwe, yang'anani Buku Lothandizira ndikuwonetsetsa kuti mukugwiritsa ntchito zomanga zomwe zilipo komanso malingaliro ndi malangizo a ogulitsa bwino.
3. Sungani file posankha File-> Sungani kapena Sungani chithunzi ( ).
Mukapanga gwero file, mutha kuwona kuti muli ndi mawu olondola, monga momwe tafotokozera mu Checking HDL Source Files, patsamba 34.

Kugwiritsa Ntchito Context Help Editor
Mukapanga kapena kutsegula mapangidwe a Verilog file, gwiritsani ntchito batani Thandizo la Context lomwe likuwonetsedwa pansi pawindo kuti likuthandizeni khodi ndi Verilog/SystemVerilog constructs mu gwero file kapena Tcl constraint commands mu Tcl yanu file.
Kuti mugwiritse ntchito Context Help Editor:
1. Dinani batani la Context Help kuti muwonetse mawu osintha.

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Synplify Pro for Microsemi Edition User Guide October 2014

Kupanga HDL Source Files

Mutu 3: Kukonzekera Zolowetsa

2. Mukasankha chomanga kumanzere kwa zenera, kufotokozera kwapaintaneti kothandizira pakumanga kumawonekera. Ngati zomwe mwasankha zili ndi izi, mutu wothandizira pa intaneti ukuwonetsedwa pamwamba pa zenera ndipo code generic kapena template yamalamulo amapangidwewo amawonetsedwa pansi.

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Kupanga HDL Source Files

3. Batani la Insert Template limayatsidwanso. Mukadina batani la Insert Template, code kapena lamulo lomwe likuwonetsedwa pawindo la template limayikidwa mu yanu file pa malo a cholozera. Izi zimakuthandizani kuti muyike kachidindo kapena kulamula mosavuta ndikuisintha pamapangidwe omwe mukupanga.
4. Ngati mukufuna kukopera zigawo zokha za template, sankhani kachidindo kapena lamulo lomwe mukufuna kuyika ndikudina Copy. Kenako mukhoza kuziyika pamutu wanu file.

Kuwona Gwero la HDL Files

Pulogalamuyo imangoyang'ana gwero lanu la HDL files ikawaphatikiza, koma ngati mukufuna kuwona gwero lanu musanaphatikizidwe, gwiritsani ntchito njira zotsatirazi. Pali mitundu iwiri yamacheke yomwe mumachita mu pulogalamu yophatikizira: syntax ndi kaphatikizidwe.

1. Sankhani gwero filemukufuna kufufuza.
Kuti muwone gwero lonse files mu projekiti, sankhani zonse files mu
mndandanda wa polojekiti, ndipo onetsetsani kuti palibe mwa files amatsegulidwa pawindo logwira ntchito. Ngati muli ndi gwero yogwira file, mapulogalamu amangoyang'ana omwe akugwira ntchito file.
Kuti muwone imodzi file, tsegulani file ndi File-> Tsegulani kapena dinani kawiri
file pawindo la Project. Ngati muli ndi zambiri file tsegulani ndipo mukufuna kuyang'ana imodzi yokha, ikani cholozera chanu pamalo oyenera file zenera kuti muwonetsetse kuti ndi zenera logwira ntchito.

2. Kuti muwone masinthidwe, sankhani Thamangani->Syntax Check kapena dinani Shift+F7.

Pulogalamuyi imazindikira zolakwika za syntax monga mawu osakira ndi zizindikiro zopumira ndikuwonetsa zolakwika zilizonse mu chipika chosiyana. file (syntax.log). Ngati palibe zolakwika zomwe zapezeka, cheke chochita bwino cha syntax chimanenedwa pansi pa izi file.

3. Kuti muyendetse cheke cha kaphatikizidwe, sankhani Thamangani->Kaphatikizidwe Fufuzani kapena dinani Shift+F8.

Pulogalamuyi imazindikira zolakwika zokhudzana ndi hardware monga zolembedwa molakwika

flip-flops ndikuwonetsa zolakwika zilizonse mu chipika chosiyana file (syntax.log). Ngati alipo

palibe zolakwika, cheke chochita bwino cha syntax chimanenedwa pansi pa izi

file.

4. kusekaview zolakwikazo potsegula syntax.log file mukafunsidwa ndikugwiritsa ntchito Pezani kuti mupeze uthenga wolakwika (sakani @E). Dinani kawiri pa

Synplify Pro for Microsemi Edition User Guide October 2014

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Mutu 3: Kukonzekera Zolowetsa

Khodi yolakwika ya zilembo 5 kapena dinani mawuwo ndikukankhira F1 kuti muwonetse thandizo lauthenga wolakwika pa intaneti.
5. Pezani gawo la code lomwe lachititsa cholakwikacho podina kawiri pa mawu a uthenga mu syntax.log file. Zenera la Text Editor limatsegula gwero loyenera file ndikuwunikira code yomwe idayambitsa cholakwika.
6. Bwerezani masitepe 4 ndi 5 mpaka zolakwika zonse za syntax ndi kaphatikizidwe zitakonzedwa.
Mauthenga akhoza kugawidwa ngati zolakwika, machenjezo, kapena zolemba. Review mauthenga onse ndi kuthetsa zolakwika zilizonse. Machenjezo ndi ocheperako poyerekeza ndi zolakwika, koma muyenera kuziwerenga ndikuzimvetsetsa ngakhale osathetsa zonse. Zolemba ndi zothandiza ndipo siziyenera kuthetsedwa.

Kusintha kwa HDL Source Files ndi Built-in Text Editor
Zolemba zomangidwira zimapangitsa kukhala kosavuta kupanga code yanu ya HDL, view izo, kapena sinthani pamene mukufuna kukonza zolakwika. Ngati mukufuna kugwiritsa ntchito cholembera chakunja, onani Kugwiritsa Ntchito Mkonzi Wamalemba Wakunja, patsamba 41.
1. Chitani chimodzi mwa izi kuti mutsegule gwero file za viewkukonza kapena kukonza:
Kuti mutsegule choyamba file pamndandanda wokhala ndi zolakwika, dinani F5.
Kuti mutsegule zenizeni file, dinani kawiri pa file pawindo la Project kapena
ntchito File-> Tsegulani (Ctrl-o) ndipo tchulani gwero file.
Zenera la Text Editor limatsegula ndikuwonetsa gwero file. Mizere imawerengedwa. Mawu osakira ali mu buluu, ndi ndemanga zobiriwira. Zingwe zili zofiira. Ngati mukufuna kusintha mitundu iyi, onani Kukhazikitsa Zokonda Zenera Losintha, patsamba 39.

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Kupanga HDL Source Files

2. Kusintha a file, lembani mwachindunji pawindo.
Tebuloli likufotokozera mwachidule zochitika zomwe mungagwiritse ntchito. Mukhozanso kugwiritsa ntchito njira zazifupi za kiyibodi m'malo mwa malamulo.

Ku…

Kodi…

Dulani, koperani, ndi kumata; Sankhani lamulo kuchokera pa mphukira (gwirani pansi sinthani, kapena chitaniponso kanthu pa batani lakumanja la mbewa) kapena Sinthani menyu.

Pitani ku mzere wina

Dinani Ctrl-g kapena sankhani Sinthani-> Pitani Ku, lembani nambala ya mzere, ndikudina Chabwino.

Pezani mawu

Dinani Ctrl-f kapena sankhani Sinthani -> Pezani. Lembani mawu omwe mukufuna kupeza, ndikudina Chabwino.

Sinthani mawu

Dinani Ctrl-h kapena sankhani Sinthani-> Bwezerani. Lembani mawu omwe mukufuna kupeza, ndi mawu omwe mukufuna kuwasintha. Dinani Chabwino.

Malizitsani mawu osakira

Lembani zilembo zokwanira kuti muzindikire mwapadera mawu osakira, ndikudina Esc.

Lowetsani mawu kumanja Sankhani chipikacho, ndikudina Tab. Lowetsani mawu kumanzere LSOSankhani chipikacho, ndikudina Shift-Tab.

Sinthani zilembo zazikulu Sankhani mawuwo, kenako sankhani Sinthani-> Zapamwamba -> Zolemba zazikulu kapena dinani Ctrl-Shift-u.

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Ku… Sinthani kukhala zilembo zochepa Onjezani chipika ndemanga
Sinthani mizati

Kodi…
Sankhani mawuwo, kenako sankhani Sinthani-> Zotsogola -> Zing'onozing'ono kapena dinani Ctrl-u.
Ikani cholozera kumayambiriro kwa mawu a ndemanga, ndikusankha Sinthani-> Advanced-> Comment Code kapena dinani Alt-c.
Dinani Alt, ndipo gwiritsani ntchito batani lakumanzere kuti musankhe ndime. Pamapulatifomu ena, muyenera kugwiritsa ntchito kiyi yomwe mawonekedwe a Alt amajambulidwa, monga kiyi ya Meta kapena diamondi.

3. Kuti mudule ndi kumata gawo la chikalata cha PDF, sankhani chizindikiro cha T-shaped Text Select, sonyezani zomwe mukufuna ndikuzikopera ndikuziyika m'bokosi lanu. file. Chizindikiro cha Text Select chimakulolani kusankha mbali za chikalatacho.
4. Kupanga ndi kugwira ntchito ndi ma bookmark anu file, onani tebulo lotsatirali.
Mabukumaki ndi njira yabwino yoyendera nthawi yayitali files kapena kulumphira ku mfundo zomwe mumazitchula nthawi zambiri. Mutha kugwiritsa ntchito zithunzi zomwe zili pazida za Sinthani pazochita izi. Ngati simungathe kuwona Zida za Sinthani kumanja kwa zenera lanu, sinthaninso mipiringidzo ina.

Ku… Ikani chizindikiro
Chotsani chizindikiro
Chotsani zosungira zonse

Kodi…
Dinani paliponse pamzere womwe mukufuna kuyika chizindikiro. Sankhani Sinthani-> Sinthani Zikhomo, dinani Ctrl-F2, kapena sankhani chizindikiro choyamba pazida zosinthira. Nambala ya mzere imawunikiridwa kusonyeza kuti pali chizindikiro kumayambiriro kwa mzerewo.
Dinani paliponse pamzere ndi chizindikiro. Sankhani Sinthani-> Sinthani Zikhomo, dinani Ctrl-F2, kapena sankhani chizindikiro choyamba pazida zosinthira. Nambala ya mzere siyiwonetsedwanso chizindikirochi chikachotsedwa.
Sankhani Sinthani-> Chotsani Zosungira Zonse, dinani Ctrl-Shift-F2, kapena sankhani chizindikiro chomaliza pazida zosinthira. Manambala a mzere samawonetsedwanso zizindikiro zosungira zichotsedwa.

Synplify Pro for Microsemi Edition User Guide October 2014

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Kupanga HDL Source Files

Ku…
Yendani a file pogwiritsa ntchito ma bookmark

Kodi…
Gwiritsani Ntchito Mabukumaki Otsatira (F2) ndi Makakimaki Am'mbuyo (Shift-F2) kuchokera pa menyu ya Sinthani kapena zithunzi zofananira kuchokera pazida za Edit kuti mupite ku bookmark yomwe mukufuna.

5. Kukonza zolakwika kapena kukonzansoview machenjezo mu code source, chitani zotsatirazi:
Tsegulani HDL file ndi cholakwika kapena chenjezo podina kawiri pa file
m'ndandanda wa polojekiti.
Dinani F5 kuti mupite ku cholakwika choyamba, chenjezo, kapena cholembera mu fayilo file. Pa
pansi pa Kusintha zenera, inu mukuwona uthenga lemba.
Kuti mupite ku cholakwika chotsatira, chenjezo, kapena cholembera, sankhani Kuthamanga-> Cholakwika Chotsatira/Chenjezo
kapena dinani F5. Ngati palibenso mauthenga mu file, mukuwona uthenga "Palibenso Zolakwa / Machenjezo / Zolemba" pansi pawindo la Kusintha. Sankhani Kuthamanga-> Cholakwika Chotsatira / Chenjezo kapena dinani F5 kuti mupite ku zolakwika, chenjezo, kapena zindikirani lotsatira. file.
Kuti mubwerere ku cholakwika cham'mbuyo, chenjezo, kapena cholembera, sankhani
Thamangani-> Cholakwika Cham'mbuyo/Chenjezo kapena dinani Shift-F5.
6. Kubweretsa thandizo la uthenga wolakwika kuti mufotokozere zolakwika, chenjezo, kapena cholembera:
Tsegulani chipika chamtundu wa malemba file (dinani View Log) ndipo dinani kawiri
nambala yolakwika ya zilembo 5 kapena dinani mawuwo ndikudina F1.
Tsegulani chipika cha HTML file ndikudina pa code yolakwika ya zilembo 5.
Pazenera la Tcl, dinani Mauthenga tabu ndikudina pa zilembo 5
khodi yolakwika mu ID.
7. Kuti crossprobe kuchokera gwero code zenera kupita ena views, tsegulani view ndikusankha chidutswa cha code. Onani Crossprobing kuchokera pawindo la Text Editor, patsamba 246 kuti mumve zambiri.
8. Mukakonza zolakwika zonse, sankhani File-> Sungani kapena dinani Save icon kuti musunge file.

Synplify Pro for Microsemi Edition User Guide October 2014

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Mutu 3: Kukonzekera Zolowetsa

Kukhazikitsa Zokonda Zosintha Zawindo
Mutha kusintha mafonti ndi mitundu yomwe imagwiritsidwa ntchito pawindo la Kusintha kwa Text.
1. Sankhani Zosankha-> Zosintha Zosintha ndi Synopsys Editor kapena Mkonzi Wakunja. Kuti mudziwe zambiri za mkonzi wakunja, onani Kugwiritsa Ntchito External Text Editor, patsamba 41.
2. Ndiye malingana ndi mtundu wa file mumatsegula, mutha kuyika maziko, mtundu wa ma syntax, ndi zokonda zamafonti kuti mugwiritse ntchito ndi cholembera.

Zindikirani: Pambuyo pake, zokonda zosintha zomwe mwakhazikitsa za izi file idzagwira ntchito kwa onse files izi file mtundu.

Zenera la Text Editing lingagwiritsidwe ntchito kukhazikitsa zokonda za polojekiti files, gwero files (Verilog/VHDL), log files, tcl files, kuletsa files, kapena kusakhazikika kwina files kuchokera mu bokosi la Editor Options dialog.
3. Mungathe kuyika mitundu ya kalembedwe ka mawu omveka bwino, monga mawu ofunika, zingwe, ndi ndemanga. Za example mu log file, machenjezo ndi zolakwika zimatha kulembedwa mitundu kuti zizindikire mosavuta.
Dinani pa Patsogolo kapena Pambuyo gawo la chinthu chofananira mu Syntax Colouring field kuti muwonetse mtunduwo.

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Kupanga HDL Source Files

Mutha kusankha mitundu yoyambira kapena kutanthauzira mitundu yokhazikika ndikuyiwonjezera papaleti yamtundu wanu. Kuti musankhe mtundu womwe mukufuna dinani OK.
4. Kuti muyike makulidwe a font ndi makulidwe a mkonzi wa mawu, gwiritsani ntchito mindandanda yotsitsa.
5. Chongani Sungani Ma Tabs kuti mutsegule zosintha za tabu, kenako ikani masitayilo a tabu pogwiritsa ntchito muvi wopita mmwamba kapena pansi wa Kukula kwa Tab.

LO 6. Dinani Chabwino pa mawonekedwe a Editor Options.
© 2014 Synopsy, Inc. 40

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Kugwiritsa Ntchito External Text Editor
Mutha kugwiritsa ntchito cholembera chakunja ngati vi kapena emacs m'malo mwazolemba zomangidwa. Chitani zotsatirazi kuti mutsegule zolemba zakunja. Kuti mumve zambiri za kugwiritsa ntchito cholembera chokhazikika, onani Kusintha kwa HDL Source Files ndi Built-in Text Editor, patsamba 35.
1. Sankhani Zosankha-> Zosintha Zosintha ndikuyatsa njira ya Mkonzi Wakunja.
2. Sankhani mkonzi wakunja, pogwiritsa ntchito njira yoyenera kumayendedwe anu opangira.
Ngati mukugwira ntchito papulatifomu ya Windows, dinani ... (Sakatulani) batani
ndikusankha mkonzi wakunja womwe ungakwaniritsidwe.
Kuchokera pa nsanja ya UNIX kapena Linux yolemba zolemba zomwe zimapanga zake
zenera, dinani batani la ... Sakatulani ndikusankha mkonzi wamawu wakunja womwe ungakwaniritsidwe.
Kuchokera pa nsanja ya UNIX yolemba zolemba zomwe sizipanga zake
zenera, osagwiritsa ntchito ... batani la Sakatulani. M'malo mwake lembani xterm -e editor. Chithunzi chotsatira chikuwonetsa VI wotchulidwa ngati mkonzi wakunja.

Synplify Pro for Microsemi Edition User Guide October 2014

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Kupanga HDL Source Files

Kuchokera pa nsanja ya Linux, kwa mkonzi wamawu omwe sapanga okha
zenera, osagwiritsa ntchito ... batani la Sakatulani. M'malo mwake, lembani gnome-terminal -x editor. Kugwiritsa ntchito emacs kwa example, lembani gnome-terminal -x emacs.
Pulogalamuyi yayesedwa ndi emacs ndi vi text editors.
3. Dinani OK.

Kugwiritsa Ntchito Zowonjezera Library kwa Verilog Library Files
Zowonjezera laibulale zitha kuwonjezeredwa ku library ya Verilog filezikuphatikizidwa m'mapangidwe anu a polojekitiyi. Mukapereka njira zosakira kumakanema omwe ali ndi laibulale ya Verilog files, mukhoza kufotokoza zowonjezera laibulale yatsopanoyi komanso Verilog ndi SystemVerilog (.v ndi .sv) file zowonjezera.
Kuchita izi:
1. Sankhani Verilog tabu ya Implementation Mungasankhe gulu.
2. Tchulani malo a Library Directories a laibulale ya Verilog files kuti ziphatikizidwe mumapangidwe anu a polojekitiyi.
3. Tchulani Zowonjezera Library.
Zowonjezera laibulale iliyonse zitha kutchulidwa, monga .av, .bv, .cv, .xxx, .va, .vas (zowonjezera laibulale zokhala ndi malo).
Chithunzi chotsatira chikukuwonetsani komwe mungalowemo zowonjezera laibulale pa bokosi la zokambirana.

LO
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Chofanana ndi Tcl cha example ndi lamulo ili:
set_option -libext .av .bv .cv .dv .ev
Kuti mudziwe zambiri, onani libext, patsamba 57 mu Command Reference.
4. Mukamaliza kupanga mapangidwe, mutha kutsimikizira mu chipikacho file kuti laibulale files ndi zowonjezera izi zidakwezedwa ndikuwerengedwa. Za exampLe:
@N: Kuthamanga Verilog Compiler mu SystemVerilog mode @I::”C:dirtop.v” @N: CG1180 :”C:dirtop.v”:8:0:8:3|Kutsegula file C:dirlib1sub1.av kuchokera ku laibulale yodziwika bwino C:dirlib1 @I::”C:dirlib1sub1.av” @N: CG1180 :”C:dirtop.v”:10:0:10:3|Ikutsegula file C:dirlib2sub2.bv kuchokera ku laibulale yodziwika bwino C:dirlib2 @I::”C:dirlib2sub2.bv” @N: CG1180 :”C:dirtop.v”:12:0:12:3|Ikutsegula file

Synplify Pro for Microsemi Edition User Guide October 2014

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Kugwiritsa Ntchito Chinenero Chosakanikirana Files

C:dirlib3sub3.cv kuchokera ku laibulale yodziwika bwino C:dirlib3 @I::”C:dirlib3sub3.cv” @N: CG1180 :”C:dirtop.v”:14:0:14:3|Ikutsegula file C:dirlib4sub4.dv kuchokera ku laibulale yodziwika bwino C:dirlib4 @I::”C:dirlib4sub4.dv” @N: CG1180 :”C:dirtop.v”:16:0:16:3|Ikutsegula file C:dirlib5sub5.ev kuchokera ku laibulale yodziwika bwino C:dirlib5 @I::"C:dirlib5sub5.ev" Chekeni cha syntax ya Verilog yapambana!

Kugwiritsa Ntchito Chinenero Chosakanikirana Files
Ndi pulogalamu ya Synplify Pro, mutha kugwiritsa ntchito zosakaniza za VHDL ndi Verilog files mu polojekiti yanu. Za exampma VHDL ndi Verilog files, onani Buku Lothandizira.
1. Kumbukirani kuti Verilog sichirikiza madoko a VHDL osamangika ndikukhazikitsa chilankhulo chosakanikirana files motero.
2. Ngati mukufuna kukonza Verilog ndi VHDL files m'mafoda osiyanasiyana, sankhani Zosankha-> Ntchito View Zosankha ndi kusintha pa View Ntchito Files mu Folders mwina.
Pamene mukuwonjezera files ku polojekiti, Verilog ndi VHDL files ali m'mafoda osiyana mu Project view.
3. Mukatsegula pulojekiti kapena kupanga yatsopano, onjezani Verilog ndi VHDL files motere:
Sankhani Project-> Add Source File lamula kapena dinani Add File batani. Pa fomu, ikani Files a Type mpaka HDL Files (*.vhd, *.vhdl, *.v). Sankhani Verilog ndi VHDL filezomwe mukufuna ndikuziwonjezera ku zanu
polojekiti. Dinani Chabwino. Kuti mudziwe zambiri za kuwonjezera files ku projekiti, onani Kupanga Zosintha pa Ntchito, patsamba 62.
LO

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The filezomwe mwawonjezera zikuwonetsedwa mu Project view. Chithunzi ichi chikuwonetsa files amapangidwa mu zikwatu zosiyana.
4. Mukayika zosankha za chipangizo (batani la Implementation Options), tchulani gawo lapamwamba. Kuti mumve zambiri zokhuza zosankha za chipangizocho, onani Kukhazikitsa Zosankha za Logic Synthesis Implementation, patsamba 75.
Ngati gawo lapamwamba kwambiri ndi Verilog, dinani tabu ya Verilog ndikulemba
dzina la module yapamwamba.
Ngati gawo lapamwamba kwambiri ndi VHDL, dinani tabu ya VHDL ndikulemba dzinalo
a bungwe lapamwamba. Ngati gawo lapamwamba silinapezeke mulaibulale yantchito yosasinthika, muyenera kufotokoza laibulale komwe wophatikiza angapeze gawolo. Kuti mudziwe zambiri zamomwe mungachitire izi, onani Gulu la VHDL, patsamba 200.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa Ntchito Chinenero Chosakanikirana Files

Muyenera kufotokoza momveka bwino gawo lapamwamba, chifukwa ndi poyambira pomwe mapper amapanga mndandanda wophatikiza.
5. Sankhani tabu ya Implementation Results pa mawonekedwe omwewo ndikusankha mtundu umodzi wa HDL wotuluka files yopangidwa ndi pulogalamuyo. Kuti mumve zambiri zokhuza zosankha za chipangizocho, onani Kukhazikitsa Zosankha za Logic Synthesis Implementation, patsamba 75.
Kwa Verilog linanena bungwe netlist, kusankha Lembani Verilog Netlist. Kwa VHDL linanena bungwe netlist, kusankha Lembani VHDL Netlist. Khazikitsani njira zina za chipangizo ndikudina Chabwino.
Tsopano mutha kupanga mapangidwe anu. Pulogalamuyi imawerengedwa mumitundu yosakanikirana ya gwero files ndipo imapanga srs imodzi file zomwe zimagwiritsidwa ntchito popanga.
6. Ngati mukukumana ndi mavuto, onani Kuthetsa Zosakaniza Zosakaniza Zinenero, patsamba 47 kuti mudziwe zambiri ndi malangizo.
LO

Synplify Pro for Microsemi Edition User Guide October 2014

Kugwiritsa Ntchito Chinenero Chosakanikirana Files

Mutu 3: Kukonzekera Zolowetsa

Kuthetsa Mavuto Ophatikiza Zinenero Zosakanikirana
Chigawochi chimapereka malangizo okhudza momwe angachitire zinthu zinazake zomwe zingabwere ndi zinenero zosiyanasiyana.

Chithunzi cha VHDL File Order
Kwa mapangidwe a VHDL-okha kapena mapangidwe osakanizika pomwe mulingo wapamwamba sunatchulidwe, zida zophatikizira za FPGA zimangokonzanso VHDL. files kotero kuti mapaketi a VHDL asonkhanitsidwe mwatsatanetsatane.
Komabe, ngati muli ndi chilankhulo chosakanikirana pomwe mwatchulapo gawo lapamwamba, muyenera kufotokoza VHDL file dongosolo kwa chida. Muyenera kuchita izi kamodzi kokha, posankha Kuthamanga-> Konzani VHDL files lamulo. Ngati simuchita izi, mumalandira uthenga wolakwika.

VHDL Global Signals
Pakalipano, simungakhale ndi zizindikiro zapadziko lonse za VHDL pamapangidwe osakanikirana a zinenero, chifukwa chidachi chimangogwiritsa ntchito zizindikirozi pamapangidwe a VHDL okha.

Kudutsa VHDL Boolean Generics kupita ku Verilog Parameters
Chidacho chimalowetsa bokosi lakuda la gawo la VHDL ndi ma generic a Boolean, ngati gawolo lidakhazikitsidwa pamapangidwe a Verilog. Izi ndichifukwa choti Verilog samazindikira mitundu ya data ya Boolean, kotero mtengo wa Boolean uyenera kuyimiridwa moyenera. Ngati mtengo wa VHDL Boolean generic ndi TRUE ndipo Verilog yeniyeni imayimiridwa ndi 1, Verilog compiler amatanthauzira izi ngati bokosi lakuda.
Pofuna kupewa kutengera bokosi lakuda, Verilog yeniyeni ya VHDL Boolean generic yokhazikitsidwa kuti TRUE iyenera kukhala 1'b1, osati 1. Mofananamo, ngati VHDL Boolean generic ndi FALSE, Verilog yogwirizana iyenera kukhala 1'b0, osati 0. Zotsatira zotsatiraziample akuwonetsa momwe angaimire ma generic a Boolean kuti adutse malire a VHDL-Verilog, osatchula bokosi lakuda.

VHDL Entity Declaration

Verilog Instantiation

Entity abc is Generic (
Number_Bits Divide_Bit );

: chiwerengero : boolean

:= 0; := Zabodza;

abc #( .Number_Bits (16), .Gawani_Pang'ono (1'b0)
)

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa Ntchito Chinenero Chosakanikirana Files

Kudutsa VHDL Generics Popanda Kudumpha Bokosi Lakuda
Pankhani yomwe gawo la Verilog gawo, (mwachitsanzoample [0:0] RSR = 1'b0) sagwirizana ndi kukula kwa VHDL chigawo cha generic (RSR : integer := 0), chidachi chimalowetsa bokosi lakuda.
Mutha kuthana ndi izi pochotsa m'lifupi mwa basi [0:0] mu Verilog files. Dziwani kuti muyenera kugwiritsa ntchito VHDL generic ya mtundu wa integer chifukwa mitundu inayo siyilola kumangirira koyenera kwa gawo la Verilog.

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Synplify Pro for Microsemi Edition User Guide October 2014

Kugwiritsa Ntchito Zowonjezera Zowonjezera

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa Ntchito Zowonjezera Zowonjezera
Gwiritsani ntchito kuthamanga kwa Incremental Compiler kuti muchepetse nthawi yothamangira pamapangidwe akulu. The mapulogalamu recompiles okha zogwirizana files pamene kusintha kwapangidwe kupangidwa ndikugwiritsanso ntchito nkhokwe ya compiler. Wopangayo amakonzanso SRS file kwa gawo lomwe lakhudzidwa komanso gawo lapanthawi yomweyo la makolo.
Kuti muchite izi, chitani zotsatirazi:
1. Onjezani Verilog kapena VHDL files kwa mapangidwe.
2. Yambitsani njira Yowonjezera Yowonjezera kuchokera pa tsamba la Verilog kapena VHDL la gulu la Implementation Options.
Iye SRS file imapangidwira gawo lililonse lazopanga muzolembera za synwork.

3. Thamangani chojambulira koyamba.
4. Ngati kusintha kwapangidwe kunapangidwa, yambitsaninso compiler.
Wopangayo amasanthula nkhokwe ndikuzindikira ngati SRS files ndi zaposachedwa, ndiye ma module okha omwe asintha ndipo ma module apanthawi yomweyo amapangidwanso. Izi zingathandize kukonza nthawi yogwiritsira ntchito popanga.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa Ntchito Zowonjezera Zowonjezera

Zolepheretsa
The incremental compiler sichikuthandizira:
· Kusintha files akuphatikizidwa mumayendedwe a Verilog kapena VHDL · Mayendedwe osakanikirana a HDL · Mapangidwe okhala ndi ma cross module (XMR)

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Synplify Pro for Microsemi Edition User Guide October 2014

Kugwiritsa ntchito Structural Verilog Flow

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa ntchito Structural Verilog Flow
Chida chophatikizira chimavomereza Verilog yokhazikika files monga chothandizira pulojekiti yanu yopangira. Kapangidwe ka Verilog compiler imapanga macheke a syntax semantic pogwiritsa ntchito chowerengera chopepuka kuti chiwongolere nthawi yothamanga. Wophatikizira uyu samachita zovuta zamtundu wa hardware kapena ntchito zokhathamiritsa za RTL, chifukwa chake, pulogalamuyo imayendetsa mwachangu kuphatikiza kwa Verilog yokhazikika. files. Pulogalamuyi imatha kuwerenga izi zopangidwa ndi Verilog files, ngati ali ndi:
‣ Zidziwitso zamaukadaulo akale
· Kugawa mawu osavuta
· Makhalidwe ofotokozedwa mu Verilog 2001 ndi mawonekedwe akale
· Zomanga zonse, kupatula zikhalidwe ziyenera kufotokozedwa mu mtundu wa Verilog 95
Kuti mugwiritse ntchito zolowetsa za Verilog files:
1. Muyenera kufotokozera Verilog yokhazikika files kuphatikiza mu kapangidwe kanu. Kuti muchite izi, yonjezerani file ku polojekiti pogwiritsa ntchito imodzi mwa njira izi:
Pulojekiti-> Onjezani Gwero File kapena Add File batani mu Project view Tcl lamulo: add_file - wopanga fileDzina
Kuthamanga uku kumatha kukhala ndi Verilog yokhazikika files kapena HDL yosakanikirana files (Verilog/VHDL/EDF/SRS) pamodzi ndi mndandanda wamtundu wa Verilog files. Komabe, zochitika za Verilog/VHDL/EDF/SRS sizimathandizidwa mkati mwa gawo la Verilog.
2. Verilog yokhazikika files amawonjezedwa ku foda ya Structural Verilog mu Project view. Mukhozanso kuwonjezera files ku bukhu ili, mukachita izi:
Sankhani structural Verilog file. Dinani kumanja ndikusankha File Zosankha. Sankhani Structural Verilog kuchokera ku File Lembani menyu otsika.
3. Thamanga kaphatikizidwe.
Chida chophatikizira chimapanga vm kapena edf netlist file kutengera ukadaulo wotchulidwa. Njirayi ikufanana ndi kayendedwe ka kaphatikizidwe kosasintha.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwiritsa ntchito Structural Verilog Flow

Zolepheretsa
Zochepa za kayendedwe ka Verilog sizigwirizana ndi izi:
· Ma RTL ena aliwonse file mitundu · Hierarchical project management (HPM) ikuyenda · Ntchito zovuta · Mitundu ndi masiwichi ophatikizira

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Synplify Pro for Microsemi Edition User Guide October 2014

Kugwira ntchito ndi Constraint Files

Mutu 3: Kukonzekera Zolowetsa

Kugwira ntchito ndi Constraint Files
Kukakamiza files ndi text files omwe amapangidwa okha ndi mawonekedwe a SCOPE (onani Kutchula SCOPE Constraints, patsamba 119), kapena zomwe mumapanga pamanja ndi mkonzi wamawu. Ali ndi malamulo a Tcl kapena zikhumbo zomwe zimalepheretsa kaphatikizidwe kameneka. Kapenanso, mutha kuyika zopinga mu code source, koma iyi si njira yomwe mumakonda.
Gawoli lili ndi zambiri za
· Nthawi Yomwe Mungagwiritsire Ntchito Zoletsa Files over Source Code, patsamba 53
· Kugwiritsa Ntchito Text Editor for Constraint Files (Cholowa), patsamba 54
· Tcl Syntax Guidelines for Constraint Files, patsamba 55
· Kuwunika Kuletsa Files, patsamba 56
· Kuti mudziwe zambiri za lipotili, onani Constraint Checking Report, pa
tsamba 270. la Buku Lothandizira, patsamba 56

Nthawi Yomwe Mungagwiritsire Ntchito Constraint Files pa Source Code
Mutha kuwonjezera zopinga pazovuta files (yopangidwa ndi mawonekedwe a SCOPE kapena yolowetsedwa m'mawu olembera) kapena mu code source. Nthawi zambiri, ndi bwino kugwiritsa ntchito contraindication files, chifukwa simuyenera kubwezeretsanso kuti zopingazo ziyambe kugwira ntchito. Zimapangitsanso code yanu yoyambira kukhala yonyamula. Onani Kugwiritsa Ntchito SCOPE Editor, patsamba 112 kuti mudziwe zambiri.
Komabe, ngati muli ndi zoletsa za nthawi yamabokosi akuda monga syn_tco, syn_tpd, ndi syn_tsu, muyenera kuziyika monga malangizo pamasinthidwe. Mosiyana ndi mawonekedwe, malangizo amatha kuwonjezeredwa ku code source, osati kukakamiza files. Onani Kufotokozera Makhalidwe ndi Maupangiri, patsamba 90 kuti mumve zambiri pakuwonjeza maupangiri ku code code.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwira ntchito ndi Constraint Files

Kugwiritsa Ntchito Text Editor for Constraint Files (Cholowa)
Mutha kugwiritsa ntchito mkonzi wa Legacy SCOPE pazovuta za SDC fileidapangidwa isanatulutsidwe mtundu wa G-2012.09. Komabe, tikulimbikitsidwa kuti mumasulire SDC yanu fileku FDC files kuti mutsegule mtundu waposachedwa wa SCOPE mkonzi ndikugwiritsa ntchito njira yolimbikitsira yoletsa nthawi mu chida.
Ngati mungasankhe kugwiritsa ntchito cholowa cha SCOPE mkonzi, gawoli likuwonetsani momwe mungapangire pamanja choletsa cha Tcl. file. Mapulogalamu amangopanga izi file ngati mugwiritsa ntchito cholembera cha SCOPE kuti mulowetse zopinga. Mtengo wa Tcl file zili ndi zoletsa nthawi zonse. Zoletsa za Black box ziyenera kulowetsedwa mu code source. Kuti mumve zambiri, onani Nthawi Yogwiritsa Ntchito Constraint Files over Source Code, patsamba 53.
1. Tsegulani a file za kusintha.
Onetsetsani kuti mwatseka zenera la SCOPE, kapena mungathe
lembani zoletsa zam'mbuyomu.
Kupanga latsopano file, sankhani File-> Chatsopano, ndikusankha Constraint File
(SCOPE) njira. Lembani dzina la file ndikudina Chabwino.
Kusintha zomwe zilipo file, sankhani File-> Tsegulani, ikani Files ya Type fyuluta kuti
Kukakamiza Files (sdc) ndikutsegula file mukufuna.
2. Tsatirani malangizo a syntax mu Tcl Syntax Guidelines for Constraint Files, patsamba 55.
3. Lowetsani zoletsa zomwe mukufuna. Kuti mumve mawu, onani Buku Lothandizira. Ngati muli ndi zoletsa nthawi yamabokosi akuda, muyenera kuziyika mu code source.
4. Mukhozanso kuwonjezera makhalidwe enieni ogulitsa pazovuta file pogwiritsa ntchito define_attribute. Onani Kufotokozera Makhalidwe mu Zoletsa File, patsamba 97 kuti mudziwe zambiri.
5. Sungani file.
6. Onjezani file ku pulojekiti monga momwe zafotokozedwera mu Kupanga Zosintha ku Pulojekiti, patsamba 62, ndikuyendetsa kaphatikizidwe.

Synplify Pro for Microsemi Edition User Guide October 2014

Kugwira ntchito ndi Constraint Files

Mutu 3: Kukonzekera Zolowetsa

Tcl Syntax Guidelines for Constraint Files
Gawoli lili ndi malangizo ogwiritsira ntchito Tcl pazovuta files:
· Tcl ndizovuta kwambiri.
· Pakutchula zinthu: Dzina la chinthu liyenera kufanana ndi dzina la HDL code. Phatikizanipo mayina ndi madoko mkati mwa curly mabatani {}. Osagwiritsa ntchito mipata m'maina. Gwiritsani ntchito kadontho (.) kuti mulekanitse mayina otsogola. M'ma module a Verilog, gwiritsani ntchito mawu otsatirawa mwachitsanzo, port, ndi
Net names:
v:cell [prefix:]objectName
Kumene selo ndilo dzina la kapangidwe kake, chiwongolero ndi chiyambi chozindikiritsa zinthu zomwe zili ndi dzina lomwelo, objectName ndi njira yachitsanzo yokhala ndi cholekanitsa madontho (.). Chiyambi chikhoza kukhala chilichonse mwa izi:

Chiyambi (chochepa) i: p: b: n:

Maina achinthu Mayina adoko (doko lonse) Kagawo kakang'ono ka doko Mayina a ukonde

M'ma module a VHDL, gwiritsani ntchito mawu otsatirawa mwachitsanzo, port, ndi net
mayina muma module a VHDL:
v: selo [.view] [prefix:]objectName
Kumene v: amazindikiritsa ngati a view chinthu, lib ndi dzina la library, cell ndi dzina la kapangidwe kake, view ndi dzina la kamangidwe, prefix ndi prefix yozindikiritsa zinthu zomwe zili ndi dzina lomwelo, ndipo objectName ndi njira yachitsanzo yokhala ndi kadontho (.) cholekanitsa. View zimangofunika ngati pali zomanga zoposa chimodzi za mapangidwe. Onani tebulo ili pamwamba pa ma prefixes a zinthu.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 3: Kukonzekera Zolowetsa

Kugwira ntchito ndi Constraint Files

* Makhadi ofananira ndi mayina ndi * (nyenyezi ikufanana ndi nambala iliyonse ya
zilembo) ndi? (chizindikirocho chikufanana ndi munthu m'modzi). Zilembozi sizikugwirizana ndi madontho omwe amagwiritsidwa ntchito ngati olekanitsa magulu. Za example, chingwe chotsatirachi chikuwonetsa zigawo zonse za statereg mu module ya statemod:
ine:statemod.statereg[*]

Kuyang'ana Constraint Files
Mutha kuyang'ana ma syntax ndi zidziwitso zina zokhudzana ndizovuta zanu files pogwiritsa ntchito lamulo la Constraint Check. Kuti mupange lipoti loletsa, chitani izi:
1. Pangani cholepheretsa file ndikuwonjezera ku polojekiti yanu.
2. Sankhani Kuthamanga-> Kuletsa Kufufuza.
Lamuloli limapanga lipoti lomwe limayang'ana kaphatikizidwe ndi kuthekera kwa zovuta zanthawi mu FPGA synthesis constraint. files za polojekiti yanu. Lipotilo lalembedwa ku projectName_cck.rpt file ndikulemba izi:
Zoletsa zomwe sizikugwiritsidwa ntchito Zoletsa zomwe zili zovomerezeka komanso zogwiritsidwa ntchito pakupanga kukulitsa kwa Wildcard pazoletsa Zoletsa pa zinthu zomwe kulibe
Kuti mumve zambiri za lipotili, onani Lipoti Loyang'ana Zoletsa, patsamba 270. la Buku Lothandizira

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Synplify Pro for Microsemi Edition User Guide October 2014

MUTU 4
Kukhazikitsa Logic Synthesis Project
Mukapanga mapangidwe ndi zida zophatikizira za Synopsys FPGA, muyenera kukhazikitsa pulojekiti yamapangidwe anu. Zotsatirazi zikufotokozera njira zokhazikitsira polojekiti ya logic synthesis:
· Kukhazikitsa Project Files, patsamba 58 · Kuwongolera Ntchito File Utsogoleri, patsamba 66 · Kukhazikitsa Zothandizira, patsamba 72 · Kukhazikitsa Zosankha Zogwiritsa Ntchito Logic Synthesis, patsamba 75 · Kutchula Makhalidwe ndi Malangizo, patsamba 90 · Kusaka Files, patsamba 98 · Archive Files ndi Ntchito, patsamba 101

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kupanga Project Files

Kupanga Project Files
Gawoli likufotokoza zofunikira za momwe mungakhazikitsire ndi kuyang'anira ntchito file pakupanga kwanu, kuphatikiza izi:
· Kupanga Pulojekiti File, patsamba 58 · Kutsegula Ntchito Yakale File, patsamba 61 · Kupanga Zosintha pa Ntchito, patsamba 62 · Kukhazikitsa Ntchito View Zokonda Zowonetsa, patsamba 63 · Kusintha Verilog Phatikizani Njira mu Ntchito Yakale Files, patsamba 65
Kwa ex yeniyeniampndi kukhazikitsa polojekiti file, onetsani ku phunziro la chida chomwe mukugwiritsa ntchito.

Kupanga Ntchito File
Muyenera kukhazikitsa polojekiti file pa projekiti iliyonse. Pulojekiti imakhala ndi deta yofunikira pamapangidwe enaake: mndandanda wa gwero files, zotsatira za kaphatikizidwe file, ndi zokonda pa chipangizo chanu. Njira yotsatirayi ikuwonetsani momwe mungakhazikitsire polojekiti file kugwiritsa ntchito malamulo payekha.
1. Yambani posankha imodzi mwa izi: File-> Ntchito yomanga, File-> Open Project, kapena chithunzi cha P. Dinani Ntchito Yatsopano.
Zenera la Project likuwonetsa polojekiti yatsopano. Dinani Add File batani, dinani F4, kapena sankhani Project-> Add Source File lamula. The Add Files to Project dialog box imatsegulidwa.
2. Onjezani gwero files ku polojekiti.
Onetsetsani kuti Kuyang'ana m'munda womwe uli pamwamba pa fomuyo ukulozera kumanja
directory. The files zalembedwa m'bokosi. Ngati simukuwona files, onani kuti Files of Type field yakhazikitsidwa kuti iwonetse zolondola file mtundu. Ngati muli ndi malingaliro osiyanasiyana files, tsatirani njira yolongosoledwa mu Kugwiritsa Ntchito Magwero a Zinenero Zosakanikirana Files, patsamba 44.

Synplify Pro for Microsemi Edition User Guide October 2014

Kupanga Project Files

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kuti muwonjezere zonse files m'ndandanda nthawi yomweyo, dinani batani la Add All
mbali yakumanja ya mawonekedwe. Kuwonjezera files payekha, alemba pa file m'ndandanda ndiyeno dinani Add batani, kapena dinani kawiri file dzina.
Mutha kuwonjezera zonse files m'ndandanda ndikuchotsa zomwe simukuzifuna ndi batani la Chotsani.
Ngati mukuwonjezera VHDL files, sankhani laibulale yoyenera kuchokera pa menyu ya VHDL Library. Laibulale yomwe mwasankha imayikidwa pa VHDL yonse files mukadina Chabwino mu bokosi la zokambirana.
Zenera la polojekiti yanu likuwonetsa polojekiti yatsopano file. Mukadina chizindikiro chowonjezera pafupi ndi polojekiti ndikuyikulitsa, mukuwona zotsatirazi:
Foda (mafoda awiri amitundu yosiyanasiyana ya zilankhulo) yokhala ndi gwero files.
Ngati wanu files sizili mufoda pansi pa chikwatu cha polojekiti, mutha kuyika zomwe mukufuna posankha Zosankha-> Ntchito View Zosankha ndi kufufuza za View polojekiti files mu zikwatu bokosi. Izi zimalekanitsa mtundu umodzi wa file kuchokera kwa wina mu Project view poziika m’zikwatu zosiyana.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kupanga Project Files

Kukhazikitsa, komwe kumatchedwa rev_1 mwachisawawa. Zokhazikitsa ndi
kukonzanso kapangidwe kanu mkati mwa pulogalamu ya kaphatikizidwe, ndipo musalowe m'malo mwa pulogalamu yowongolera ma code source ndi njira. Kukhazikitsa kangapo kumakupatsani mwayi wosintha zida ndi zosankha za kaphatikizidwe kuti mufufuze zosankha zamapangidwe. Mutha kukhala ndi machitidwe angapo mu Synplify Pro. Kukhazikitsa kulikonse kumakhala ndi kaphatikizidwe kake ndi zosankha za chipangizocho komanso zokhudzana ndi polojekiti files.

3. Onjezani malaibulale aliwonse omwe mungafune, pogwiritsa ntchito njira yomwe tafotokozera m'mbuyomu kuti muwonjezere laibulale ya Verilog kapena VHDL file.
Pamalaibulale okhudzana ndi ogulitsa, onjezani laibulale yoyenera file ku ku
polojekiti. Zindikirani kuti kwa mabanja ena, malaibulale amadzazidwa okha ndipo simuyenera kuwawonjezera mwatsatanetsatane pulojekitiyi. file.
Kuti muwonjezere laibulale ya phukusi la gulu lachitatu la VHDL, onjezani .vhd yoyenera file ku kamangidwe, monga tafotokozera mu sitepe 2. Dinani pomwe pa file mu Project view ndi kusankha File Zosankha, kapena sankhani Project-> Khazikitsani laibulale ya VHDL. Tchulani dzina la library lomwe likugwirizana ndi zoyeserera. Za exampndi, MYLIB. Onetsetsani kuti laibulale ya phukusili ili patsogolo pa mapangidwe apamwamba pamndandanda wa files mu Project view.
Kuti mudziwe zambiri za kukhazikitsa Verilog ndi VHDL file zosankha, onani Setting Verilog ndi VHDL Options, patsamba 84. Mukhozanso kukhazikitsa izi file zosankha pambuyo pake, musanayendetse kaphatikizidwe.
Kuti mudziwe zambiri zokhudzana ndi kugwiritsa ntchito malaibulale akuluakulu ogulitsa ndi ma bLoOxes akuda, onani Kukonzekera kwa Microsemi Designs, patsamba 487.
Pazinthu zamakono zamakono, mukhoza kuwonjezera
Laibulale yodziyimira payokha ya Verilog yoperekedwa ndi pulogalamuyi

Synplify Pro for Microsemi Edition User Guide October 2014

Kupanga Project Files

Mutu 4: Kukhazikitsa Logic Synthesis Project

(install_dir/lib/generic_ technology/gtech.v) pamapangidwe anu, kapena onjezani laibulale yanu yamtundu wina. Osagwiritsa ntchito zonse pamodzi chifukwa pangakhale mikangano.
4. Onani file dongosolo mu Project view. File kuyitanitsa ndikofunikira kwambiri kwa VHDL files.
Kwa VHDL files, mutha kuyitanitsa basi files ndi
kusankha Kuthamanga-> Konzani VHDL Files. Kapenanso, pamanja kusuntha files mu Project view. Phukusi files ayenera kukhala oyamba pamndandanda chifukwa amapangidwa asanagwiritsidwe ntchito. Ngati muli ndi midadada yopangidwira yofalikira pambiri files, onetsetsani kuti muli ndi zotsatirazi file oda: ndi file zomwe zili ndi bungwe ziyenera kukhala zoyamba, zotsatiridwa ndi zomangamanga file, ndipo potsiriza file ndi kasinthidwe.
Mu Project view, fufuzani kuti chomaliza file mu Project view ndi
gwero lapamwamba file. Kapenanso, mutha kufotokoza zapamwamba file mukakhazikitsa zosankha za chipangizo.
5. Sankhani File-> Sungani, lembani dzina la polojekitiyo, ndikudina Sungani. Zenera la Project likuwonetsa zosintha zanu.
6. Kutseka ntchito file, sankhani batani la Close Project kapena File-> Tsekani Pulojekiti.

Kutsegula Ntchito Yakale File
Pali njira ziwiri zotsegulira polojekiti file: Open Project ndi generic File -> Tsegulani lamulo.
1. Ngati polojekiti yomwe mukufuna kutsegula ndi yomwe mwagwirapo posachedwa, mutha kusankha mwachindunji: File-> Ntchito Zaposachedwa-> ProjectName.
2. Gwiritsani ntchito imodzi mwa njira zotsatirazi kuti mutsegule polojekiti iliyonse file:

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kupanga Project Files

Tsegulani Project Command

File-> Open Command

Sankhani File-> Open Project, dinani Open Project batani kumanzere kwa Project zenera, kapena dinani chizindikiro P.
Kuti mutsegule pulojekiti yaposachedwa, dinani kawiri kuchokera pamndandanda wamapulojekiti aposachedwa.
Apo ayi, dinani Project yomwe ilipo batani kuti mutsegule Tsegulani bokosi la zokambirana ndikusankha polojekitiyo.

Sankhani File->Otsegula.
Tchulani chikwatu choyenera mu Look In: field.
Khalani File ya Type to Project Files (*.prj). Bokosilo limatchula ntchitoyo files.
Dinani kawiri pa polojekiti yomwe mukufuna kutsegula.

Ntchitoyi imatsegulidwa pawindo la Project.

Kusintha kwa Project
Nthawi zambiri, mumawonjezera, kuchotsa, kapena kusintha files.
1. Kuonjezera gwero kapena cholepheretsa files ku polojekiti, sankhani Add Files batani kapena Project-> Add Source File kutsegula Sankhani Files ku Add to Project dialog box. Onani Kupanga Ntchito File, patsamba 58 kuti mumve zambiri.
2. Kuchotsa a file kuchokera ku polojekiti, dinani batani file pawindo la Project, ndikusindikiza batani Chotsani.
3. Kusintha a file mu polojekiti,
Sankhani a file mukufuna kusintha pa Project zenera.
Dinani Kusintha File batani, kapena sankhani Project-> Sinthani File.
Mu Gwero File dialog box yomwe imatsegula, ikani Look In ku chikwatu
kumene kwatsopano file ili. Chatsopano file ayenera kukhala amtundu wofanana ndi wa file mukufuna kusintha.
Ngati simukuwona yankho file zolembedwa, sankhani mtundu wa file muyenera kuchokera
ndi Files of Type field.
Dinani kawiri pa file. Chatsopano file m'malo mwa yakale mu polojekitiyi
mndandanda. LO
4. Kufotokoza momwe polojekiti files amasungidwa mu polojekiti, dinani pomwepa a file mu Project view ndi kusankha File Zosankha. Khazikitsani Save File kusankha kwa Relative to Project kapena Absolute Path.

Synplify Pro for Microsemi Edition User Guide October 2014

Kupanga Project Files

Mutu 4: Kukhazikitsa Logic Synthesis Project

5. Kuwona nthawi stamp pa a file, dinani pomwe pa a file mu Project view ndi kusankha File Zosankha. Onani nthawi yomweyo file idasinthidwa komaliza. Dinani Chabwino.

Kukhazikitsa Project View Onetsani Zokonda
Mutha kusintha makonda ndi mawonekedwe a polojekiti files. 1. Sankhani Zosankha-> Pulojekiti View Zosankha. The Project View Fomu yosankha imatsegulidwa.

2. Kukonza zolowetsa zosiyanasiyana files m'mafoda osiyana, fufuzani View Ntchito Files mu Folders.
Kuwona izi kumapanga zikwatu zosiyana mu Project view kwa kukakamizidwa files ndi gwero files.

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Mutu 4: Kukhazikitsa Logic Synthesis Project

Kupanga Project Files

3. Kulamulira file kuwonetsa ndi izi:
Onetsani zonse zokha files, poyang'ana Show Project Library. Ngati
izi sizinayendetsedwe, Project view sichimawonetsa files mpaka mutadina chizindikiro chowonjezera ndikukulitsa files mu chikwatu.
Chongani chimodzi mwa mabokosi mu Project File Dzina Lowonetsera gawo la
fomu kuti mudziwe bwanji filemayina akuwonetsedwa. Mutha kuwonetsa nokha filedzina, njira yachibale, kapena njira yeniyeni.
4. Kuti view polojekiti files m'mafoda osinthidwa makonda, fufuzani View Ntchito Files mu Custom Folders. Kuti mumve zambiri, onani Kupanga Mafoda Amakonda, patsamba 66. Mafoda amtundu amawonetsedwa ngati pali mitundu ingapo mufoda yokhazikika.

Mafoda Amakonda
© 2014 Synopsy, Inc. 64

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Kupanga Project Files

Mutu 4: Kukhazikitsa Logic Synthesis Project

5. Kutsegula njira zingapo zoyendetsera polojekiti imodzi view, fufuzani Lolani Ma projekiti Angapo Kuti Atsegulidwe.
Pulogalamu ya 1

Pulogalamu ya 2

6. Kulamulira linanena bungwe file kuwonetsa ndi izi:
Onani Chiwonetsero chonse Files m'bokosi la Results Directory kuti muwonetse zotuluka zonse
files kwaiye pambuyo kaphatikizidwe.
Sinthani zotuluka file kupanga bungwe podina pamutu umodzi wamutu
mu Zotsatira za Kukhazikitsa view. Mutha kupanga magulu a files ndi mtundu kapena kusanja malinga ndi tsiku lomwe adasinthidwa komaliza.
7. Kuti view file zambiri, sankhani file mu Project view, dinani kumanja, ndikusankha File Zosankha. Za example, mukhoza kuyang'ana tsiku a file zidasinthidwa.
Kusintha Verilog Phatikizani Njira mu Ntchito Yakale Files
Ngati muli ndi polojekiti file idapangidwa ndi mtundu wakale wa pulogalamuyo (isanafike 8.1), Verilog imaphatikizapo njira mu izi file zimagwirizana ndi bukhu lazotsatira kapena gwero file ndi `kuphatikizapo ziganizo. Zotulutsidwa pambuyo pa 8.1, polojekitiyi file `kuphatikiza njira zimagwirizana ndi polojekiti file kokha. GUI pazotulutsa zaposachedwa sizimangokweza prj yakale files kutsatira malamulo atsopano. Kupititsa patsogolo ndi kugwiritsa ntchito polojekiti yakale file, chitani chimodzi mwa izi:
· Sinthani pamanja prj file mu text editor ndikuwonjezera zotsatirazi pa
mzere pamaso pa set_option iliyonse -include_path:
set_option -project_relative_includes 1
· Yambitsani pulojekiti yatsopano ndi pulogalamu yatsopano ndikuchotsa
projekiti yakale. Izi zipangitsa prj yatsopano file mverani lamulo latsopano pomwe zikuphatikiza zikugwirizana ndi prj file.

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Kuwongolera Ntchito File Utsogoleri

Kuwongolera Ntchito File Utsogoleri
Magawo otsatirawa akufotokoza momwe mungapangire ndikuwongolera mafoda osinthidwa ndi files mu Project view:
· Kupanga Mafoda Amwambo · Kuwongolera Mafoda Amapulojekiti Amakonda · Kuwongolera Mwambo Files

Kupanga Mafoda Amakonda
Mutha kupanga zikwatu zomveka ndikusintha mwamakonda filem'magulu osiyanasiyana otsogola mkati mwa Project yanu view. Mafodawa amatha kutchulidwa ndi dzina lililonse kapena mulingo wowongolera. Za exampLero, mutha kufananiza makina anu ogwiritsira ntchito mosasamala file kapangidwe kapena HDL logic hierarchy. Mafoda achikhalidwe amasiyanitsidwa ndi mtundu wawo wabuluu.

Pali njira zingapo zopangira zikwatu zomwe mumakonda ndikuwonjezera files kwa iwo mu polojekiti. Gwiritsani ntchito imodzi mwa njira izi:

1. Dinani kumanja pa polojekiti file kapena chikwatu china chotsatira ndikusankha Add Foda kuchokera pa menyu yoyambira. Kenako chitani chilichonse mwa izi file ntchito:

Dinani kumanja zikuwonetsa choncho

pa kuti

fyioleuoLcrOafnileesitahnedr

sankhani kusankha

Ikani mu Foda. A sub-menu chikwatu alipo kapena pangani

foda yatsopano.

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Kuwongolera Ntchito File Utsogoleri

Mutu 4: Kukhazikitsa Logic Synthesis Project

Zindikirani kuti mutha kutchula fodayo mosasamala, koma musagwiritse ntchito (/) chifukwa ichi ndi chizindikiro cha olekanitsa.
Kuti mutchulenso chikwatu, dinani kumanja pa chikwatucho ndikusankha Rename kuchokera
menyu popup. The Rename Folder dialog box likuwonekera; tchulani dzina latsopano.
2. Gwiritsani ntchito Add Files to Project dialog box kuti muwonjezere zonse zomwe zili mufoda, ndikuyika mwakufuna files mu zikwatu zomwe zimagwirizana ndi zolemba za foda ya OS zomwe zalembedwa mu bokosi la zokambirana.

Kuti muchite izi, sankhani Add File batani mu Project view.
Sankhani zikwatu zilizonse zomwe mwapemphedwa monga dsp kuchokera m'bokosi la zokambirana, ndiye
dinani Add batani. Izi zimayika zonse files kuchokera ku dsp hierarchy kulowa mufoda yomwe mwangopanga kumene.

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Mutu 4: Kukhazikitsa Logic Synthesis Project

Kuwongolera Ntchito File Utsogoleri

Kuyika basi files mu zikwatu zomwe zimagwirizana ndi
paulamuliro wa chikwatu cha OS, yang'anani njira yotchedwa Add Files ku Custom Folders pa dialog box.
Mwachikhazikitso, dzina lachikwatu lachikwatu ndi dzina lofanana ndi chikwatu
muli files kapena chikwatu kuti muwonjezere ku polojekiti. Komabe, mutha kusintha momwe mafoda amatchulidwira, podina batani la Folders Option. Bokosi lotsatirali likuwonetsedwa.

Kugwiritsa ntchito:
Chikwatu chomwe chili ndi files pa dzina la chikwatu, dinani Gwiritsani Ntchito OS
Dzina lachikwatu.
Dzina lanjira ku chikwatu chosankhidwa kuti mudziwe mulingo wa
utsogoleri umasonyezedwa panjira ya chikwatu.

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Kuwongolera Ntchito File Utsogoleri

Mutu 4: Kukhazikitsa Logic Synthesis Project

3. Mutha kukoka ndikugwetsa files ndi zikwatu kuchokera ku pulogalamu ya OS Explorer kulowa mu Project view. Izi zimapezeka pamakompyuta a Windows ndi Linux omwe akuyendetsa KDE.
Mukakoka ndikugwetsa a file, nthawi yomweyo amawonjezedwa ku polojekitiyi.
Ngati palibe pulojekiti yotseguka, pulogalamuyo imapanga polojekiti.
Mukakoka ndikugwetsa a file pa chikwatu, chidzaikidwa mmenemo
chikwatu. Poyamba, kuwonjezera Files to Project dialog box ikuwonetsedwa ndikukufunsani kuti mutsimikizire files kuti awonjezedwe ku polojekiti. Mukhoza alemba bwino kuvomereza files. Ngati mukufuna kusintha, mutha kudina batani Chotsani Zonse ndikutchula fyuluta yatsopano kapena kusankha.

Zindikirani: Kuti muwonetse zikwatu zomwe zili mu Project view, sankhani Zosankha-> Pulojekiti View Zosankha menyu, kenako yambitsani / zimitsani bokosi loyang'ana View Ntchito Files mu Custom Folders pa dialog box.

Kuwongolera Mafoda a Project Mwambo
Njira yotsatirayi ikufotokoza momwe mungachotsere files kuchokera pamafoda, chotsani zikwatu, ndikusintha utsogoleri wamafoda.
1. Kuchotsa a file kuchokera mufoda yokhazikika, mwina:
Kokani ndikuponya mufoda ina kapena pulojekitiyi. Unikani za file, dinani kumanja ndikusankha Chotsani ku Foda kuchokera ku
menyu popup.
Osagwiritsa ntchito kiyi ya Delete (DEL), chifukwa izi zimachotsa file kuchokera ku polojekiti.
2. Kuti mufufute foda yomwe mwakonda, iwonetseni ndiyeno dinani kumanja ndikusankha Chotsani kuchokera pamenyu yoyambira kapena dinani batani la DEL. Mukachotsa chikwatu, pangani chimodzi mwazosankha izi:
Dinani Inde kuchotsa chikwatu ndi files zomwe zili mufoda kuchokera
polojekiti.
Dinani Ayi kuti mungochotsa chikwatucho.

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Mutu 4: Kukhazikitsa Logic Synthesis Project

Kuwongolera Ntchito File Utsogoleri

3. Kusintha mawonekedwe a chikwatu chomwe mwamakonda:
Kokani ndikugwetsa chikwatu mkati mwa chikwatu china kuti chikhale sub-
foda kapena kupitilira pulojekitiyo kuti musunthire pamlingo wapamwamba.
Kuti muchotse utsogoleri wapamwamba wa chikwatu chomwe mwakonda, kokerani ndikugwetsa
kagawo kakang'ono komwe kakufunika pantchitoyo. Kenako chotsani chikwatu chopanda kanthu cha chikwatucho.
Za example, ngati chikwatu chikwatu chomwe chilipo ndi:
/Eksamples/Verilog/RTL
Tiyerekeze kuti mukufuna otsogolera a RTL a mulingo umodzi wokha, kenako kokerani ndikugwetsa RTL pa projekitiyo. Pambuyo pake, mutha kufufuta /Examples/Verilog directory.

Kuwongolera Mwambo Files
Kuphatikiza apo, mutha kuchita izi mwachizolowezi file ntchito:
1. Kupondereza chiwonetsero cha files mu Type zikwatu, dinani kumanja mu Project view ndi kusankha Project View Zosankha kapena sankhani Zosankha-> Pulojekiti View Zosankha. Letsani njira View Ntchito Files mu Type Folders pa dialog box.
2. Kuwonetsa files mu dongosolo la zilembo m'malo mwa dongosolo la polojekiti, fufuzani Mtundu Files batani mu Project view gawo lowongolera. Dinani muvi wapansi pansi pakona yakumanzere kwa gulu kuti mutsegule ndi kuzimitsa gulu lowongolera.

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Kuwongolera Ntchito File Utsogoleri

Mutu 4: Kukhazikitsa Logic Synthesis Project

Control Panel Toggle
3. Kusintha dongosolo la files mu polojekiti:
Onetsetsani kuti mwayimitsa zikwatu zomwe mwasankha ndikusankha files. Kokani ndikuponya a file ku malo ofunidwa pamndandanda wa files.
4. Kusintha file lembani, kokerani ndikugwetsa ku foda yamtundu watsopano. Pulogalamuyi idzakupangitsani kuti mutsimikizire.

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Mutu 4: Kukhazikitsa Logic Synthesis Project

Kukhazikitsa Zothandizira

Kukhazikitsa Zothandizira
Kukhazikitsa ndi mtundu wa projekiti, yokhazikitsidwa ndi zopinga zinazake ndi zoikamo zina. Pulojekiti ikhoza kukhala ndi machitidwe angapo, iliyonse ili ndi zoikamo zake.

Kugwira ntchito ndi Zambiri Zambiri
Chida cha Synplify Pro chimakupatsani mwayi wopanga machitidwe angapo amapangidwe omwewo ndikuyerekeza zotsatira. Izi zimakupatsani mwayi kuyesa zosintha zosiyanasiyana zamapangidwe omwewo. Kukhazikitsa ndikukonzanso kapangidwe kanu mkati mwa pulogalamu ya kaphatikizidwe, ndipo osalowa m'malo mwa mapulogalamu ndi njira zowongolera ma code source.
1. Dinani batani la Add Implementation kapena sankhani Project-> New Implementation ndikukhazikitsa zosankha zatsopano za chipangizo (Chipangizo cha Chipangizo), zosankha zatsopano (Zosankha), kapena chopinga chatsopano. file (Zopinga tabu).
Pulogalamuyi imapanga kukhazikitsidwa kwina mu polojekitiyi view. Kukhazikitsa kwatsopano kuli ndi dzina lofanana ndi lakale, koma lokhala ndi nambala yoyambira. Chithunzi chotsatirachi chikuwonetsa kukhazikitsidwa kuwiri, rev1 ndi rev2, ndikukhazikitsa kwapano (yogwira) kuwonekera.

Kukhazikitsa kwatsopano kumagwiritsa ntchito code yofanana files, koma zosankha zosiyanasiyana za chipangizo ndi zopinga. Imakopera zina files kuchokera pakukhazikitsa koyambirira: tlg log file, mndandanda wa srs RTL file, ndi design_fsm.sdc file yopangidwa ndi FSM Explorer. Mapulogalamu amasunga repeatable mbiri ya kaphatikizidwe amathamanga.

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Kukhazikitsa Zothandizira

Mutu 4: Kukhazikitsa Logic Synthesis Project

2. Thamangani kaphatikizidwe kachiwiri ndi zoikamo zatsopano.
Kuti mugwiritse ntchito panokha, dinani Thamangani.
Kuti mugwiritse ntchito zonse zomwe polojekitiyi ikuchita, sankhani Run-> Run All
Kukhazikitsa.
Mutha kugwiritsa ntchito zingapo kuyesa gawo lina kapena kuyesa ma frequency osiyanasiyana. Onani Zosankha Zokhazikitsa Logic Synthesis Implementation, patsamba 75 kuti mudziwe zambiri za zosankha.
The Project view kuwonetsa zonse zomwe zakhazikitsidwa zomwe zikuwonetsedweratu ndi zomwe zikugwirizana nazo files zopangidwira kuti zigwiritsidwe ntchito zomwe zikuwonetsedwa muzotsatira za Implementation view kumanja; kusintha ntchito yogwira kumasintha zotsatira file chiwonetsero. Zenera la Watch limayang'anira zomwe zikuchitika. Ngati mukonza zenera ili kuti muwone zonse zomwe zachitika, kukhazikitsa kwatsopano kumangosinthidwa pazenera.
3. Fananizani zotsatira.
Gwiritsani ntchito zenera la Watch kuti mufananize zomwe mwasankha. Onetsetsani kukhazikitsa
zomwe mukufuna kufananitsa ndi Configure Watch Watch. Onani Kugwiritsa Ntchito Zenera Loyang’anira, patsamba 190 kuti mumve zambiri.

Kuti mufananize zambiri, yerekezerani chipikacho file zotsatira.
4. Kuti mutchulenso kukhazikitsa, dinani batani lakumanja la mbewa pa dzina lokhazikitsa polojekiti view, sankhani Sinthani Dzina Lothandizira kuchokera pa menyu yoyambira, ndikulemba dzina latsopano.
Zindikirani kuti UI yapano imachotsa kukhazikitsidwa; zotulutsidwa zisanachitike 9.0 zimasunga kukhazikitsidwa kuti kutchulidwenso.
5. Kuti mukopere zomwe zachitika, dinani batani lakumanja la mbewa pa dzina lokhazikitsa polojekitiyo view, sankhani Copy Implementation kuchokera pa menyu yoyambira, ndikulemba dzina latsopano la kukoperako.

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Mutu 4: Kukhazikitsa Logic Synthesis Project

Kukhazikitsa Zothandizira

6. Kuti mufufute kukhazikitsidwa, dinani batani lakumanja la mbewa pa dzina la kukhazikitsa mu polojekiti view, ndi kusankha Chotsani Kukhazikitsa kuchokera pa mphukira menyu.

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Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project
Kukhazikitsa Logic Synthesis Implementation Options
Mutha kukhazikitsa zosankha zapadziko lonse lapansi pazokhazikitsa zanu, zina mwazotengera luso laukadaulo. Gawoli likufotokoza momwe mungakhazikitsire zosankha zapadziko lonse lapansi monga chipangizo, kukhathamiritsa, ndi file zosankha ndi lamulo la Implementation Options. Kuti mudziwe zambiri za kukhazikitsa zolepheretsa kuti mukwaniritse, onani Kutchula SCOPE Constraints, patsamba 119. Kuti mumve zambiri za kupitilira makonda adziko lonse ndi malingaliro kapena malangizo, onani Kutchula Makhalidwe ndi Directive, patsamba 90.
Gawoli likukamba za mitu iyi:
· Kukhazikitsa Zosankha za Chipangizo, patsamba 75 · Kukhazikitsa Zosankha Zowonjezera, patsamba 78 · Kutchula Ma frequency ndi Kuletsa Files, patsamba 80 · Kutchula Zosankha Zazotsatira, patsamba 82 · Kutchula Lipoti la Nthawi, patsamba 84 · Kukhazikitsa Zosankha za Verilog ndi VHDL, patsamba 84
Kukhazikitsa Zosankha Zachipangizo
Zosankha pazida ndi gawo lazosankha zapadziko lonse lapansi zomwe mungakhazikitse pakutha kwa kaphatikizidwe. Zimaphatikizapo kusankha kwa gawo (ukadaulo, gawo ndi kalasi yothamanga) ndi njira zoyendetsera (kuyika kwa I/O ndi fanouts). Zosankha ndi kukhazikitsidwa kwa zosankhazi zingasiyane kuchokera kuukadaulo kupita kuukadaulo, kotero yang'anani mitu ya ogulitsa mu Buku Lothandizira kuti mudziwe zambiri za zosankha zanu mavenda.
1. Tsegulani mawonekedwe a Implementation Options podina batani la Implementation Options kapena kusankha Project->Implementation Options, ndipo dinani Chipangizo tabu pamwamba ngati sichinasankhidwe kale.
2. Sankhani luso, gawo, phukusi, ndi liwiro. Zosankha zomwe zilipo zimasiyanasiyana, kutengera luso lomwe mwasankha.

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Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
3. Khazikitsani zosankha za mapu a chipangizo. Zosankha zimasiyanasiyana, kutengera luso lomwe mwasankha.
Ngati simukutsimikiza kuti njirayo ikutanthauza chiyani, dinani batani kuti muwone
kufotokoza m'bokosi pansipa. Kuti mudziwe zambiri za zomwe mungasankhe, dinani F1 kapena tchulani mutu woyenerera wa ogulitsa mu Buku Lothandizira.
Kuti muyike njira, lembani mtengo kapena chongani bokosi kuti muwatsegule.
Kuti mumve zambiri za kukhazikitsa malire a fanout ndi kubweza nthawi, onani Kukhazikitsa Malire a Fanout, patsamba 348, ndi Retiming, patsamba 334, motsatana. Kuti mudziwe zambiri za zosankha zina za ogulitsa, onani mutu woyenerera wa ogulitsa ndi banja laukadaulo mu Reference Manual.

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4. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino.
5. Dinani Thamanga batani kuti synthesize mapangidwe. Pulogalamuyi imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.
6. Kuti muyike zosankha za chipangizo ndi script, gwiritsani ntchito lamulo la set_option Tcl. Gome lotsatirali lili ndi mndandanda wa zilembo za zosankha za chipangizo pa Chipangizo chojambulidwa ndi malamulo ofanana a Tcl. Chifukwa zosankhazo ndi zamakono- komanso zochokera kubanja, zonse zomwe zalembedwa patebulo sizingakhalepo muukadaulo wosankhidwa. Malamulo onse amayamba ndi set_option, ndikutsatiridwa ndi syntax muzanja monga momwe zasonyezedwera. Yang'anani Buku Lothandizira kuti muwone mndandanda wazomwe mungachite kwa wogulitsa wanu.
Gome lotsatirali likuwonetsa zambiri mwazosankha za chipangizocho.

Zosankha Zofotokozera za Analyst Letsani I/O Insertion Fanout Guide

Tcl Lamulo (set_option…) -run_prop_extract {1|0} -disable_io_insertion {1|0} -fanout_limit fanout_value

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Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options

Njira

Tcl Lamulo (set_option…)

Phukusi

-paketi pkg_name

Gawo

-gawo gawo_dzina

Konzani Madalaivala Osakanikirana

-resolve_multiple_driver {1|0}

Liwiro

-speed_grade speed_grade

Zamakono

-Tekinoloje mawu ofunika

Sinthani Kuphatikiza Data Yanthawi -update_models_cp {0|1}

HDL Analyst Database Generation -hdl_qload {1|0}

Kukhazikitsa Zosankha Zowonjezera
Zosankha zokhathamiritsa ndi gawo lazosankha zapadziko lonse lapansi zomwe mungakhazikitse kuti mukwaniritse. Gawoli likukuuzani momwe mungakhazikitsire zosankha monga pafupipafupi komanso kukhathamiritsa kwapadziko lonse lapansi monga kugawana zinthu. Mutha kukhazikitsanso zina mwazosankhazi ndi mabatani oyenera pa UI.
1. Tsegulani mawonekedwe a Implementation Options podina batani la Implementation Options kapena kusankha Project->Implementation Options, ndikudina Zosankha pamwamba.
2. Dinani kukhathamiritsa zomwe mukufuna, kaya pa fomu kapena mu Project view. Zosankha zanu zimasiyanasiyana, malinga ndi luso lamakono. Ngati palibe njira yopezera ukadaulo wanu, imachotsedwa. Kukhazikitsa njira pamalo amodzi kumangosintha malo ena.

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Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project

Ntchito View

Zosankha Zowonjezera Zosankha-> Zosankha

Kuti mudziwe zambiri pakugwiritsa ntchito kukhathamiritsa uku onani magawo otsatirawa:

FSM Compiler FSM Explorer
Kusintha kwa Resource Sharing Retiming

Kupititsa patsogolo Makina a Boma, patsamba 354
Kuthamanga kwa FSM Explorer, patsamba 359 Chidziwitso: Kagawo kakang'ono kokha ka matekinoloje a Microsemi ndi omwe amathandizira njira ya FSM Explorer. Gwiritsani ntchito Project-> Implementation Options-> Zosankha gulu kuti muwone ngati njirayi imathandizidwa ndi chipangizo chomwe mwatchula mu chida chanu.
Kugawana Zinthu, patsamba 352
Kubwereza, patsamba 334

Zofanana za lamulo la Tcl set_option ndi izi:

Njira FSM Compiler FSM Explorer Resource Sharing Retiming

set_option Tcl Command Option -symbolic_fsm_compiler {1|0} -use_fsm_explorer {1|0} -resource_sharing {1|0} -retiming {1|0}

3. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
4. Dinani Thamanga batani kuthamanga kaphatikizidwe.
Pulogalamuyi imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.
HDL Analyst Database Generation
Mwachikhazikitso, pulogalamuyo imawerenga kapangidwe kake, imachita kukhathamiritsa kwanzeru komanso kufalitsa nthawi, ndikulemba zotuluka ku netlist imodzi (srs). Pamene mapangidwe akukulirakulira, nthawi yoyendetsa ndikuwongolera mapangidwewo amakhala ovuta kwambiri.
Zosankha izi zimalola wopanga kugawanitsa mapangidwewo kukhala ma module angapo omwe amalembedwa kuti alekanitse netlist filendi (srs). Kuti muchite izi, sankhani bokosi loyang'ana la HDL Analyst Database Generation pa Zosankha tabu la Implementation Options dialog box. Izi zimakulitsa kugwiritsa ntchito kukumbukira kwambiri pamapangidwe akulu.
Izi zitha kuthandizidwanso pazenera la Tcl Script pogwiritsa ntchito set_option Tcl lamulo ili:
set_option -hdl_qload 1
Njira ya HDL Analyst Database Generation ikayatsidwa, gwiritsani ntchito njira ya Incremental Quick Load mu chida cha HDL Analyst kuti muwonetse kapangidwe kake pogwiritsa ntchito netlist imodzi (srs) kapena ma module angapo apamwamba a RTL (srs). Chidacho chikhoza kutenga advantage za izi potsegula mwachisawawa okhawo omwe akhudzidwa. Za exampLero, msakatuli wolozerana akhoza kukulitsa utsogoleri wocheperako momwe ungafunikire kuti achuluke mwachangu. Njira Yowonjezera Yowonjezera Mwamsanga ili pagawo la General la HDL Analyst Options dialog box. Onani General Panel, patsamba 304.

Kufotokozera Kuchuluka Kwapadziko Lonse ndi Zoletsa Files

Njirayi imakuwuzani momwe mungakhazikitsire ma frequency apadziko lonse lapansi ndikuwonetsa zoletsa files kuti akwaniritse.

1. Kuti mukhazikitse ma frequency padziko lonse lapansi, chitani chimodzi mwa izi:

Lembani pafupipafupi padziko lonse lapansi mu Project view.

Tsegulani mawonekedwe a Implementation Options podina Kukhazikitsa

Zosankha batani Constraints tabu.

seleLcOting

Ntchito-> Kukhazikitsa

Zosankha,

ndi

dinani

ndi

Lamulo lofanana la Tcl set_option ndi -frequency frequencyValue.

Synplify Pro for Microsemi Edition User Guide October 2014

Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project
Mutha kupitilira kuchulukirachulukira kwapadziko lonse lapansi ndi zoletsa zakomweko, monga zafotokozedwera mu Kutchula SCOPE Constraints, patsamba 119. Mu chida cha Synplify Pro, mutha kupanga zopinga za wotchi pamapangidwe anu m'malo mokhazikitsa ma frequency adziko lonse lapansi. Onani Kugwiritsa Ntchito Zoletsa Magalimoto, patsamba 291 kuti mumve zambiri.
Global Frequency and Constraints Project View
Zosankha Zokhazikitsa-> Zoletsa

2. Kufotokozera choletsa files kuti mukwaniritse, chitani chimodzi mwa izi:
Sankhani Pulojekiti-> Zosankha Zothandizira-> Zolepheretsa. Yang'anani cholepheretsa
filezomwe mukufuna kugwiritsa ntchito polojekitiyi.
Kuchokera pa Kukhazikitsa Zosankha-> Zoletsa, mutha kudinanso kuti
onjezerani choletsa file.
Ndi kukhazikitsa komwe mukufuna kugwiritsa ntchito kosankhidwa, dinani Add File mu
Ntchito view, ndi kuwonjezera choletsa files muyenera.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
Kupanga zopinga files, onani Kutchula SCOPE Constraints, patsamba 119.
3. Kuchotsa zopinga files kuchokera pakukhazikitsa, chitani chimodzi mwa izi:
Sankhani Pulojekiti-> Zosankha Zothandizira-> Zolepheretsa. Dinani pachongani bokosi
pafupi ndi file dzina.
Mu Project view, dinani kumanja koletsa file kuchotsedwa ndi
sankhani Chotsani ku Project.
Izi zimachotsa zopinga file kuchokera pakukhazikitsa, koma sichichotsa.
4. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino.
Mukapanga kapangidwe kake, pulogalamuyo imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.
Kutchula Zosankha Zazotsatira
Gawoli likukuwonetsani momwe mungatchulire zofunikira zomwe zimatuluka pa kaphatikizidwe kameneka.
1. Tsegulani mawonekedwe a Implementation Options podina batani la Implementation Options kapena kusankha Project->Implementation Options, ndipo dinani Zotsatira Zotsatira pamwamba.

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Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project

2. Tchulani zotsatira filemukufuna kupanga.
Kuti mupange netlist yojambulidwa files, dinani Lembani Mapped Verilog Netlist kapena Lembani
Mapu a VHDL Netlist.
Kupanga choletsa chokhudzana ndi ogulitsa file kwa chidziwitso choyambirira,
dinani Lembani Zoletsa Zogulitsa File. Onani Zambiri pa lipotili, onani Constraint Checking Report, patsamba 270.of the Reference Manual, patsamba 56 kuti mudziwe zambiri.
3. Khazikitsani chikwatu chomwe mukufuna kulemba zotsatira.
4. Khazikitsani mtundu wa linanena bungwe file. Lamulo lofanana la Tcl lolemba ndi project -result_format format.
Mwinanso mungafune kukhazikitsa zosintha kuti ziwongolere kupanga mapu. Kuti mudziwe zambiri, onani mutu woyenerera wa ogulitsa mu Buku Lothandizira.
5. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino.
Mukapanga kapangidwe kake, pulogalamuyo imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
Kufotokozera Kutulutsa Lipoti la Nthawi
Mukhoza kudziwa kuchuluka kwa zomwe zanenedwa mu lipoti la nthawi mwa kukhazikitsa njira zotsatirazi.
1. Kusankha Project-> Implementation Options, ndi kumadula Lipoti la Nthawi tabu. 2. Khazikitsani kuchuluka kwa njira zovuta zomwe mukufuna kuti pulogalamuyo inene.

3. Tchulani chiwerengero cha mfundo zoyambira ndi zomaliza zomwe mukufuna kuziwona m'magawo ovuta.
4. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino. Mukapanga kapangidwe kake, pulogalamuyo imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.
Kukhazikitsa Zosankha za Verilog ndi VHDL
Mukakhazikitsa gwero la Verilog ndi VHDL files mu pulojekiti yanu, mutha kufotokozeranso zosankha zina zophatikiza.
Kukhazikitsa Verilog File Zosankha
Mwakhazikitsa Verilog file zosankha posankha Project-> Njira Zothandizira-> Verilog, kapena Options-> Konzani Verilog Compiler.

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Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project

1. Tchulani mtundu wa Verilog woti mugwiritse ntchito.
Kukhazikitsa compiler padziko lonse lapansi kwa onse files mu polojekiti, sankhani
Pulojekiti-> Zosankha Zothandizira-> Verilog. Ngati mukugwiritsa ntchito Verilog 2001 kapena SystemVerilog, yang'anani Buku Lothandizira pazomanga zothandizidwa.
Kufotokozera Verilog compiler pa per file maziko, kusankha file mu
Ntchito view. Dinani kumanja ndikusankha File Zosankha. Sankhani chojambulira choyenera. Verilog yokhazikika file mtundu wama projekiti atsopano ndi SystemVerilog.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
2. Tchulani gawo lapamwamba ngati simunachite izi mu Project view.
3. Kuti mutenge magawo kuchokera ku code code, chitani zotsatirazi:
Dinani Kutulutsa Parameters. Kuti muchotse zosasinthika, lowetsani mtengo watsopano wa parameter.
Pulogalamuyi imagwiritsa ntchito mtengo watsopano pakukhazikitsa komweko kokha. Dziwani kuti kutulutsa kwa parameter sikuthandizidwa pamitundu yosakanikirana.

4. Lembani malangizo mu Compiler Directives, pogwiritsa ntchito mipata kulekanitsa ziganizozo. Mutha kulemba malangizo omwe mungalowe nawo ndi 'ifdef ndi` define statements in code. Za example, ABC=30 imabweretsa pulogalamuyo kulemba mawu otsatirawa ku polojekiti file:
set_option -hdl_define -khazikitsa "ABC = 30"
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Synplify Pro for Microsemi Edition User Guide October 2014

Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project
5. Mu Phatikizanipo Path Order, tchulani njira zofufuzira zomwe zikuphatikizapo malamulo a Verilog filezomwe zili mu polojekiti yanu. Gwiritsani ntchito mabatani omwe ali pakona yakumanja kwa bokosilo kuti muwonjezere, kufufuta, kapena kuyitanitsanso njira.
6. M'mabuku a Library, tchulani njira yopita ku chikwatu chomwe chili ndi laibulale files za polojekiti yanu. Gwiritsani ntchito mabatani omwe ali pakona yakumanja kwa bokosilo kuti muwonjezere, kufufuta, kapena kuyitanitsanso njira.
7. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino. Mukapanga kapangidwe kake, pulogalamuyo imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project Setting Logic Synthesis Implementation Options
Kupanga VHDL File Zosankha
Mumakhazikitsa VHDL file zosankha posankha Project-> Implementation Options-> VHDL, or Options-> Configure VHDL Compiler.

Kwa gwero la VHDL, mutha kufotokoza zomwe zafotokozedwa pansipa.
1. Tchulani gawo lapamwamba ngati simunachite izi mu Project view. Ngati gawo lapamwamba kwambiri silikupezeka mulaibulale yantchito yosasinthika, muyenera kufotokozera laibulale komwe wopanga angapeze gawolo. Kuti mudziwe zambiri zamomwe mungachitire izi, onani Gulu la VHDL, patsamba 200.
Mutha kugwiritsanso ntchito njirayi pamapangidwe osakanikirana a zilankhulo kapena mukafuna kufotokoza gawo lomwe silili gawo lapamwamba la HDL Analyst kuwonetsa ndi LdOebugging pamachitidwe. views. 2. Pa kabisidwe ka makina a boma, chitani izi:
Tchulani mtundu wa encoding womwe mukufuna kugwiritsa ntchito.

Synplify Pro for Microsemi Edition User Guide October 2014

Kukhazikitsa Logic Synthesis Implementation Options Mutu 4: Kukhazikitsa Logic Synthesis Project
Letsani compiler ya FSM.
Mukapanga kapangidwe kake, pulogalamuyo imagwiritsa ntchito malangizo ophatikiza omwe mwawayika pano kuti asungire makina aboma ndipo samayendetsa makina a FSM, omwe angapambane ndi malangizo a compiler. Kapenanso, mutha kufotokozera makina aboma omwe ali ndi syn_encoding, monga tafotokozera mu Defining State Machines mu VHDL, patsamba 308.
3. Kuti mutenge ma generics kuchokera ku code code, chitani izi:
Dinani Tingafinye Generic Constants. Kuti muchotse zosasinthika, lowetsani mtengo watsopano wageneric.
Pulogalamuyi imagwiritsa ntchito mtengo watsopano pakukhazikitsa komweko kokha. Dziwani kuti simungathe kuchotsa ma generic ngati muli ndi chilankhulo chosakanikirana.

4. Kukankhira ma tristates kudutsa malire a ndondomeko/block, onetsetsani kuti Push Tristates ndiyoyatsidwa. Kuti mudziwe zambiri, onani Push Tristates Option, patsamba 212 mu Buku Lofotokozera.
5. Dziwani matanthauzidwe a malangizo a synthesis_on and synthesis_off:
Kupangitsa wolembayo kutanthauzira synthesis_on ndi synthesis_off malangizo
monga translate_on/translate_off, yang'anirani kaphatikizidwe On/Off Kukhazikitsidwa ngati Kumasulira Kuyatsa/Kuzimitsa.
Kunyalanyaza malangizo a synthesis_on ndi synthesis_off, onetsetsani kuti
njira iyi sinafufuzidwe. Onani translate_off/translate_on, patsamba 226 mu Buku Lolozera kuti mudziwe zambiri.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kufotokozera Makhalidwe ndi Malangizo

6. Khazikitsani njira zina zogwirira ntchito ngati zikufunika (onani Zosankha Zokhazikitsa Logic Synthesis, patsamba 75 kuti mupeze mndandanda wa zosankha). Dinani Chabwino.
Mukapanga kapangidwe kake, pulogalamuyo imaphatikiza ndi kupanga mapu pogwiritsa ntchito zomwe mwasankha.

Kufotokozera Makhalidwe ndi Malangizo

Mawonekedwe ndi malangizo ndizomwe mumagawira kuti mupange zinthu kuti ziwongolere momwe mapangidwe anu amasankhidwira, kukhathamiritsa, ndi mapu.
Makhalidwe amawongolera kukhathamiritsa kwa mapu ndi malangizo amawongolera kukhathamiritsa kwa ma compiler. Chifukwa cha kusiyana kumeneku, muyenera kufotokozera malangizo omwe ali mu code source. Gome ili likufotokoza njira zomwe zilipo zopangira mawonekedwe ndi malangizo:

Zoletsa za VHDL Verilog SCOPE Editor File

Makhalidwe Inde Inde Inde Inde

Malangizo Inde Inde Ayi Ayi

Ndibwino kuti mutchule zomwe zili mu SCOPE editor kapena zopinga file, chifukwa simuyenera kukonzanso kapangidwe kaye. Kwa malangizo, muyenera kupanga mapangidwe kuti agwire ntchito.
Ngati SCOPE/zoletsa file ndipo code code ya HDL imatchulidwa kuti ipangidwe, zolepheretsa zimakhala zofunikira pakakhala mikangano.
Kuti mudziwe zambiri, onani zotsatirazi:
· Kutchula Makhalidwe ndi Malangizo mu VHDL, patsamba 91 · Kutchula Makhalidwe ndi Malangizo ku Verilog, patsamba 92 · Kutchula Makhalidwe UsLiOng Mkonzi wa SCOPE, patsamba 93 File, patsamba 97

Synplify Pro for Microsemi Edition User Guide October 2014

Kufotokozera Makhalidwe ndi Malangizo

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kufotokozera Makhalidwe ndi Malangizo mu VHDL
Mungagwiritse ntchito njira zina kuti muwonjezere zizindikiro ku zinthu, monga momwe zalembedwera mu Kutchula Makhalidwe ndi Malangizo, patsamba 90. Pali njira ziwiri zofotokozera zikhumbo ndi malangizo mu VHDL:
· Kugwiritsa ntchito zomwe zafotokozedweratu
· Kulengeza za chikhalidwe nthawi iliyonse yomwe ikugwiritsidwa ntchito
Kuti mudziwe zambiri za kalembedwe ka VHDL, onani VHDL Attribute ndi Directive Syntax, patsamba 561 mu Buku Lofotokozera.

Pogwiritsa ntchito Phukusi la Predefined VHDL Attributes
AdvantagKugwiritsa ntchito phukusi losankhidwiratu ndikuti mumapewa kufotokozeranso zomwe zanenedwazo ndi malangizo nthawi iliyonse mukawaphatikiza mu code code. The disadvantage ndikuti khodi yanu yoyambira ndiyosavuta kunyamula. Phukusi la mawonekedwe lili mu installDirectory/lib/vhd/synattr.vhd.
1. Kuti mugwiritse ntchito zinthu zomwe zafotokozedweratu zomwe zaphatikizidwa mu laibulale ya mapulogalamu, yonjezerani mizere iyi ku syntax:
library synplify; gwiritsani ntchito synplify.attributes.all;
2. Onjezani malingaliro kapena malangizo omwe mukufuna pambuyo pa chilengezo cha kapangidwe kake.
zolengeza; attribute attribute_name of objectName : objectType ndi mtengo;
Za exampLe:
chinthu simpledff ndi doko (q: out bit_vector(7 downto 0); d: mu bit_vector(7 downto 0); clk: pang'ono);
chizindikiro syn_noclockbuf cha clk : chizindikiro ndi chowona;
Kuti mumve zambiri za kalembedwe ka mawu, onani VHDL Attribute and Directive Syntax, patsamba 561 mu Buku Lofotokozera.
3. Onjezani gwero file ku polojekiti.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kufotokozera Makhalidwe ndi Malangizo

Kulengeza Makhalidwe a VHDL ndi Malangizo
Ngati simugwiritsa ntchito phukusi, muyenera kutanthauziranso mawonekedwe nthawi iliyonse mukawaphatikiza mu code code.
1. Nthawi iliyonse mukamagwiritsa ntchito mawu kapena malangizo, tanthauzirani mawuwo mukangomaliza kulengeza pogwiritsa ntchito mawu awa:
design_unit_declaration ; attribute attributeName : dataType ; attribute attributeName of objectName : objectType is value ;
Za exampLe:
chinthu simpledff ndi doko (q: out bit_vector(7 downto 0); d: mu bit_vector(7 downto 0); clk: pang'ono);
chizindikiro syn_noclockbuf : boolean; chizindikiro syn_noclockbuf ya clk :signal ndi yowona;
2. Onjezani gwero file ku polojekiti.

Kufotokozera Makhalidwe ndi Malangizo ku Verilog
Mungagwiritse ntchito njira zina kuti muwonjezere zizindikiro za zinthu, monga momwe zafotokozedwera mu Kutchula Makhalidwe ndi Malangizo, patsamba 90.
Verilog ilibe mawonekedwe ndi malangizo omwe adafotokozedweratu, chifukwa chake muyenera kuwawonjezera ngati ndemanga. Dzina lachidziwitso kapena chilangizo limatsogozedwa ndi mawu osakira. Verilog files ndizovuta kwambiri, kotero mawonekedwe ndi malangizo akuyenera kufotokozedwa ndendende momwe amafotokozera m'mawu awo. Kuti mudziwe zambiri za kalembedwe ka mawu, onani Verilog Attribute and Directive Syntax, patsamba 363 mu Buku Lofotokozera.
1. Kuti muwonjezere chikhumbo kapena malangizo mu Verilog, gwiritsani ntchito mzere wa Verilog kapena block comment (C-style) motsatira ndondomeko yachindunji. Ndemanga za block ziyenera kutsogola semicolon, ngati ilipo.
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Synplify Pro for Microsemi Edition User Guide October 2014

Kufotokozera Makhalidwe ndi Malangizo

Mutu 4: Kukhazikitsa Logic Synthesis Project

Verilog Block Comment Syntax
/* synthesis attributeName = mtengo *//* kaphatikizidwe directoryName = mtengo */

Verilog Line Comment Syntax
// synthesis attributeName = mtengo // kaphatikizidwe directoryName = mtengo

Kuti mudziwe zambiri za malamulo a kalembedwe ka mawu, onani Verilog Attribute and Directive Syntax, patsamba 363 mu Buku Lofotokozera. Otsatirawa ndi akaleampzochepa:
gawo fifo(kunja, mkati) /* synthesis syn_hier = "yolimba" */;
2. Kuti muphatikize zizindikiro zambiri kapena malangizo ku chinthu chomwecho, siyanitsani makhalidwewo ndi mipata yoyera, koma musabwereze mawu ofunika kwambiri. Osagwiritsa ntchito koma. Za exampLe:
vuto /* kaphatikizidwe full_case parallel_case */;
3. Ngati zolembera zambiri zimatanthauzidwa pogwiritsa ntchito mawu amodzi a Verilog reg ndipo chidziwitso chikugwiritsidwa ntchito kwa iwo, ndiye kuti pulogalamu ya kaphatikizidwe imangogwiritsa ntchito kaundula womaliza wolengezedwa mu reg statement. Za exampLe:
reg [5:0] q, q_a, q_b, q_c, q_d /* synthesis syn_preserve=1 */;
Chizindikiro cha syn_preserve chimangogwiritsidwa ntchito ku q_d. Izi ndizomwe zikuyembekezeka pazida zophatikizira. Kuti mugwiritse ntchito izi pamakaundula onse, muyenera kugwiritsa ntchito mawu osiyana a Verilog reg pa kaundula aliyense ndikugwiritsa ntchito mawonekedwewo.

Kufotokozera Makhalidwe Kugwiritsa Ntchito SCOPE Editor
Zenera la SCOPE limapereka mawonekedwe osavuta kugwiritsa ntchito kuwonjezera mawonekedwe aliwonse. Simungagwiritse ntchito powonjezera malangizo, chifukwa ayenera kuwonjezeredwa kugwero files. (Onani Specifying Attributes and Directives mu VHDL, patsamba 91 kapena Specifying Attributes and Directives in Verilog, patsamba 92). Mchitidwe wotsatirawu ukuwonetsa momwe mungawonjezere mawonekedwe pazenera la SCOPE.
1. Yambani ndi mapangidwe opangidwa ndikutsegula zenera la SCOPE. Kuti muwonjezere zomwe zili pazovuta zomwe zilipo file, tsegulani zenera la SCOPE podina zomwe zilipo file mu Project view. Kuti muwonjezere mawonekedwe ku chatsopano file, dinani chizindikiro cha SCOPE ndikudina Initialize kuti mutsegule zenera la SCOPE.
2. Dinani Makhalidwe tabu pansi pa zenera la SCOPE.

Synplify Pro for Microsemi Edition User Guide October 2014

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kufotokozera Makhalidwe ndi Malangizo

Mukhoza kusankha chinthu choyamba (gawo 3) kapena chikhalidwe choyamba (gawo 4).

3. Kuti mufotokoze chinthucho, chitani chimodzi mwa zotsatirazi mu gawo la Object. Ngati mudatchula kale zachinthu, ndime ya Object imangotchula zosankha zolondola za chinthucho.
Sankhani mtundu wa chinthu mugawo la Object Selter, ndiyeno sankhani a
chinthu kuchokera pamndandanda wazosankha mugawo la Object. Iyi ndi njira yabwino kwambiri yowonetsetsa kuti mukutchula chinthu choyenera, ndi mawu olondola.

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Kufotokozera Makhalidwe ndi Malangizo

Mutu 4: Kukhazikitsa Logic Synthesis Project

Kokani chinthu chomwe mukufuna kulumikiza nacho chochokera ku
RTL kapena Technology views ku gawo la Object pawindo la SCOPE. Kwa zina, kukokera ndi kuponya sikungasankhe chinthu choyenera. Za example, ngati mukufuna kuyika syn_hier pa gawo kapena gulu ngati ndi chipata, muyenera kuyiyika pa view za module imeneyo. Chinthucho chingakhale ndi mawu awa: v:moduleName mu Verilog, kapena v:library.moduleName mu VHDL, komwe mungakhale ndi malaibulale angapo.
Lembani dzina la chinthucho mugawo lachinthu. Ngati simukudziwa
dzina, gwiritsani ntchito Pezani lamulo kapena gawo la Object Filter. Onetsetsani kuti mwalemba choyambirira choyenera cha chinthu chomwe chikufunika. Za example, kukhazikitsa chikhalidwe pa a view, muyenera kuwonjezera v: prefix ku gawo kapena dzina lachinthu. Kwa VHDL, mungafunike kufotokoza laibulale komanso dzina la gawo.
4. Ngati mwatchula chinthu choyamba, mukhoza tsopano kufotokoza chikhalidwecho. Mndandandawu umangowonetsa zovomerezeka za mtundu wa chinthu chomwe mwasankha. Tchulani khalidwelo pogwira batani la mbewa mu gawo la Attribute ndikusankha khalidwe kuchokera pamndandanda.

Ngati mwasankha chinthu choyamba, zosankha zomwe zilipo zimatsimikiziridwa ndi chinthu chosankhidwa ndi teknoloji yomwe mukugwiritsa ntchito. Ngati mwasankha chikhumbo choyamba, zosankha zomwe zilipo zimatsimikiziridwa ndi luso lamakono.
Mukasankha chikhalidwe, zenera la SCOPE limakuuzani mtundu wamtengo wapatali womwe muyenera kuyikapo ndikufotokozera mwachidule za chikhalidwecho. Ngati mwasankha chikhumbo choyamba, onetsetsani kuti mwabwereranso ndikulongosola chinthucho.
5. Lembani mtengo wake. Gwirani pansi batani la mbewa mugawo la Value, ndikusankha pamndandandawo. Mukhozanso kulemba mtengo.

Synplify Pro for Microsemi Edition User Guide October 2014

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SYnOPSYS FPGA Synthesis Synplify Pro ya Microsemi Edition [pdf] Buku Logwiritsa Ntchito
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SYnOPSYS FPGA Synthesis Synplify Pro for Microsemi Edition User Guide

FPGA Synthesis Synplify Pro ya Microsemi Edition

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