SYnOPSYS FPGA Synthesis Synplify Pro for Microsemi Edition User Guide

The Synopsys FPGA Synthesis – Synplify Pro for Microsemi Edition
is a comprehensive tool for FPGA implementation with various
features designed to assist users in logic synthesis and design
flows.

Product Usage Instructions

Chapter 1: Introduction

This chapter provides an overview of the Synopsys FPGA and
Prototyping Products, FPGA Implementation Tools, and Synopsys FPGA
Tool Features.

Scope of the Document

The document set includes information on the product features
and is intended for users interested in FPGA synthesis and design
flows.

Getting Started

To start using the software, launch it following the provided
instructions and refer to the user guide for assistance.

User Interface Overview

Familiarize yourself with the user interface to efficiently
navigate through the software features.

Chapter 2: FPGA Synthesis Design Flows

This chapter details the Logic Synthesis Design Flow for FPGA
synthesis.

Chapter 3: Preparing the Input

Learn how to use Mixed Language Source Files and the Incremental
Compiler for efficient input preparation.

Note: Be aware of any limitations associated
with using the Incremental Compiler.

FAQ

Q: Can I make copies of the documentation?

A: Yes, the license agreement permits making copies for internal
use only with proper attribution.

Q: How do I start the software?

A: Refer to the “Getting Started” section in Chapter 1 of the
user guide for detailed instructions on starting the software.

Q: What is the intended audience for this user guide?

A: The user guide is aimed at individuals interested in FPGA
synthesis and design flows.

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Synopsys FPGA Synthesis
Synplify Pro for Microsemi Edition
User Guide
October 2014

Copyright Notice and Proprietary Information
Copyright © 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.
Right to Copy Documentation
The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only.
Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page:
“This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.”
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.
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Synplify Pro for Microsemi Edition User Guide October 2014

Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Registered Trademarks (®)
Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, CHIPit, CoMET, CODE V, Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, HSPICE, Identify, Leda, LightTools, MAST, METeor, ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, the Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, UMRBus, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc.
Trademarks (TM)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Intelli, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, and Worksheet Buffer are trademarks of Synopsys, Inc.

Synplify Pro for Microsemi Edition User Guide October 2014

Service Marks (sm)
MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc. SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners.
Printed in the U.S.A October 2014

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Synplify Pro for Microsemi Edition User Guide October 2014

Contents

Chapter 1: Introduction
Synopsys FPGA and Prototyping Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FPGA Implementation Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synopsys FPGA Tool Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Scope of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 The Document Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
User Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 2: FPGA Synthesis Design Flows
Logic Synthesis Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 3: Preparing the Input
Setting Up HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Creating HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Using the Context Help Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Checking HDL Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Editing HDL Source Files with the Built-in Text Editor . . . . . . . . . . . . . . . . . . . . 35 Setting Editing Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Using an External Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Using Library Extensions for Verilog Library Files . . . . . . . . . . . . . . . . . . . . . . . 42
Using Mixed Language Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Using the Incremental Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Using the Structural Verilog Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Synplify Pro for Microsemi Edition User Guide October 2014

Working with Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 When to Use Constraint Files over Source Code . . . . . . . . . . . . . . . . . . . . . . . . 53 Using a Text Editor for Constraint Files (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Syntax Guidelines for Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Checking Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Chapter 4: Setting up a Logic Synthesis Project
Setting Up Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Creating a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Opening an Existing Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Making Changes to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Setting Project View Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Updating Verilog Include Paths in Older Project Files . . . . . . . . . . . . . . . . . . . . 65
Managing Project File Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Creating Custom Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Manipulating Custom Project Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Manipulating Custom Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Setting Up Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Working with Multiple Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Setting Logic Synthesis Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Setting Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Setting Optimization Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Specifying Global Frequency and Constraint Files . . . . . . . . . . . . . . . . . . . . . . 80 Specifying Result Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Specifying Timing Report Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Setting Verilog and VHDL Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Specifying Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Specifying Attributes and Directives in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Specifying Attributes and Directives in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Specifying Attributes Using the SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . 93 Specifying Attributes in the Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Searching Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Identifying the Files to Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Filtering the Files to Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Initiating the Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Search Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LO
Archiving Files and Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Archive a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Un-Archive a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Synplify Pro for Microsemi Edition User Guide October 2014

Copy a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Chapter 5: Specifying Constraints
Using the SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Creating Constraints in the SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Creating Constraints With the FDC Template Command . . . . . . . . . . . . . . . . 116
Specifying SCOPE Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Entering and Editing Scope Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Setting Clock and Path Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Defining Input and Output Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Specifying Standard I/O Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Using the TCL View of SCOPE GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Guidelines for Entering and Editing Constraints . . . . . . . . . . . . . . . . . . . . . . . . 127
Specifying Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Defining From/To/Through Points for Timing Exceptions . . . . . . . . . . . . . . . . . 130 Defining Multicycle Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Defining False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Finding Objects with Tcl find and expand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Specifying Search Patterns for Tcl find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Refining Tcl Find Results with -filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Using the Tcl Find Command to Define Collections . . . . . . . . . . . . . . . . . . . . . 138 Using the Tcl expand Command to Define Collections . . . . . . . . . . . . . . . . . . 140 Checking Tcl find and expand Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Using Tcl find and expand in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Using Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Comparison of Methods for Defining Collections . . . . . . . . . . . . . . . . . . . . . . . 144 Creating and Using SCOPE Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Creating Collections using Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Viewing and Manipulating Collections with Tcl Commands . . . . . . . . . . . . . . . 150
Converting SDC to FDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Using the SCOPE Editor (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Entering and Editing SCOPE Constraints (Legacy) . . . . . . . . . . . . . . . . . . . . . 157 Specifying SCOPE Timing Constraints (Legacy) . . . . . . . . . . . . . . . . . . . . . . . 159 Entering Default Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Setting Clock and Path Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Defining Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Defining Input and Output Constraints (Legacy) . . . . . . . . . . . . . . . . . . . . . . . 169 Defining False Paths (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 6: Synthesizing and Analyzing the Results
Synthesizing Your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Running Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Using Up-to-date Checking for Job Management . . . . . . . . . . . . . . . . . . . . . . 174
Checking Log File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Viewing and Working With the Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Accessing Specific Reports Quickly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Accessing Results Remotely . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Analyzing Results Using the Log File Reports . . . . . . . . . . . . . . . . . . . . . . . . . 189 Using the Watch Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Checking Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Handling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Checking Results in the Message Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Filtering Messages in the Message Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Filtering Messages from the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Automating Message Filtering with a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . 198 Log File Message Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Handling Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Using Continue on Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Using Continue on Error for Compile Point Synthesis . . . . . . . . . . . . . . . . . . . 203
Chapter 7: Analyzing with HDL Analyst and FSM Viewer
Working in the Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Differentiating Between the HDL Analyst Views . . . . . . . . . . . . . . . . . . . . . . . . 209 Opening the Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Viewing Object Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Selecting Objects in the RTL/Technology Views . . . . . . . . . . . . . . . . . . . . . . . 215 Working with Multisheet Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Moving Between Views in a Schematic Window . . . . . . . . . . . . . . . . . . . . . . . 218 Setting Schematic View Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Managing Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Exploring Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Traversing Design Hierarchy with the Hierarchy Browser . . . . . . . . . . . . . . . . 222 Exploring Object Hierarchy by Pushing/Popping . . . . . . . . . . . . . . . . . . . . . . . 223 Exploring Object Hierarchy of Transparent Instances . . . . . . . . . . . . . . . . . . . 228
Finding Objects . . . . . . . . . . . . .L.O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Browsing to Find Objects in HDL Analyst Views . . . . . . . . . . . . . . . . . . . . . . . 230 Using Find for Hierarchical and Restricted Searches . . . . . . . . . . . . . . . . . . . . 232 Using Wildcards with the Find Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Synplify Pro for Microsemi Edition User Guide October 2014

Combining Find with Filtering to Refine Searches . . . . . . . . . . . . . . . . . . . . . . 240 Using Find to Search the Output Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing within an RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing from the RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 244 Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Crossprobing from the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Analyzing With the HDL Analyst Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Viewing Design Hierarchy and Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Filtering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Expanding Pin and Net Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Expanding and Viewing Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Flattening Schematic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Minimizing Memory Usage While Analyzing Designs . . . . . . . . . . . . . . . . . . . 267
Using the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Chapter 8: Analyzing Timing
Analyzing Timing in Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Viewing Timing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Annotating Timing Information in the Schematic Views . . . . . . . . . . . . . . . . . . 275 Analyzing Clock Trees in the RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Viewing Critical Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Handling Negative Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Generating Custom Timing Reports with STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Using Analysis Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Scenarios for Using Analysis Design Constraints . . . . . . . . . . . . . . . . . . . . . . 285 Creating an ADC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Using Object Names Correctly in the adc File . . . . . . . . . . . . . . . . . . . . . . . . . 290
Using Auto Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Results of Auto Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Chapter 9: Inferring High-Level Objects
Defining Black Boxes for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Boxes and I/Os in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Boxes and I/Os in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Adding Black Box Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Adding Other Black Box Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Synplify Pro for Microsemi Edition User Guide October 2014

Defining State Machines for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Defining State Machines in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Defining State Machines in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Specifying FSMs with Attributes and Directives . . . . . . . . . . . . . . . . . . . . . . . . 309
Specifying Safe FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Automatic RAM Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 RAM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Inferring Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Initializing RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Initializing RAMs in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Initializing RAMs in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Chapter 10: Specifying Design-Level Optimizations
Tips for Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 General Optimization Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Optimizing for Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Optimizing for Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Controlling Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Retiming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Retiming Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 How Retiming Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Preserving Objects from Being Optimized Away . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Using syn_keep for Preservation or Replication . . . . . . . . . . . . . . . . . . . . . . . 343 Controlling Hierarchy Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Preserving Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Optimizing Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Setting Fanout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Controlling Buffering and Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Sharing Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Inserting I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Optimizing State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Deciding when to Optimize State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Running the FSM Compiler L.O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Running the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Inserting Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Synplify Pro for Microsemi Edition User Guide October 2014

Specifying Probes in the Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Adding Probe Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Chapter 11: Working with Compile Points
Compile Point Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Advantages of Compile Point Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Manual Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Nested Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Compile Point Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Compile Point Synthesis Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Compile Point Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Interface Logic Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Interface Timing for Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Compile Point Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Incremental Compile Point Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Forward-annotation of Compile Point Timing Constraints . . . . . . . . . . . . . . . . 384
Synthesizing Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 The Manual Compile Point Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Creating a Top-Level Constraints File for Compile Points . . . . . . . . . . . . . . . . 388 Defining Manual Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Setting Constraints at the Compile Point Level . . . . . . . . . . . . . . . . . . . . . . . . 391 Analyzing Compile Point Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Using Compile Points with Other Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Combining Compile Points with Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . 396
Resynthesizing Incrementally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Resynthesizing Compile Points Incrementally . . . . . . . . . . . . . . . . . . . . . . . . . 397
Chapter 12: Working with IP Input
Generating IP with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Specifying FIFOs with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Specifying RAMs with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Specifying Byte-Enable RAMs with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . 416 Specifying ROMs with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Specifying Adder/Subtractors with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Specifying Counters with SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
The Synopsys FPGA IP Encryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Overview of the Synopsys FPGA IP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Encryption and Decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Working with Encrypted IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Synplify Pro for Microsemi Edition User Guide October 2014

Encrypting Your IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Encrypting IP with the encryptP1735.pl Script . . . . . . . . . . . . . . . . . . . . . . . . . 448 Encrypting IP with the encryptIP Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Specifying the Script Output Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Preparing the IP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Using Hyper Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Using Hyper Source for Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Using Hyper Source for IP Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Threading Signals Through the Design Hierarchy of an IP . . . . . . . . . . . . . . . 461
Chapter 13: Optimizing Processes for Productivity
Using Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Running Batch Mode on a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Running Batch Mode with a Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Queuing Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Working with Tcl Scripts and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Using Tcl Commands and Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Generating a Job Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Setting Number of Parallel Jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Creating a Tcl Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Using Tcl Variables to Try Different Clock Frequencies . . . . . . . . . . . . . . . . . . 476 Using Tcl Variables to Try Several Target Technologies . . . . . . . . . . . . . . . . . 478 Running Bottom-up Synthesis with a Script . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Automating Flows with synhooks.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Chapter 14: Using Multiprocessing
Multiprocessing With Compile Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Setting Maximum Parallel Jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 License Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Chapter 15: Optimizing for Microsemi Designs
Optimizing Microsemi Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Using Predefined Microsemi Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Using Smartgen Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Working with Radhard Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Specifying syn_radhardlevel in the Source Code . . . . . . . . . . . . . . . . . . . . . . . 490 LO
Chapter 16: Working with Synthesis Output
Passing Information to the P&R Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Synplify Pro for Microsemi Edition User Guide October 2014

Specifying Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Specifying Locations for Microsemi Bus Ports . . . . . . . . . . . . . . . . . . . . . . . . . 495 Specifying Macro and Register Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Generating Vendor-Specific Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Targeting Output to Your Vendor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Customizing Netlist Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Chapter 17: Running Post-Synthesis Operations
Running P&R Automatically after Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Working with the Identify Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Launching from the Synplify Pro Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Handling Problems with Launching Identify . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Using the Identify Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Using Compile Points with the Identify Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Simulating with the VCS Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Synplify Pro for Microsemi Edition User Guide October 2014

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Synplify Pro for Microsemi Edition User Guide October 2014

CHAPTER 1
Introduction
This introduction to the Synplify Pro® software describes the following:
· Synopsys FPGA and Prototyping Products, on page 16 · Scope of the Document, on page 21 · Getting Started, on page 22 · User Interface Overview, on page 24

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 1: Introduction

Synopsys FPGA and Prototyping Products

Synopsys FPGA and Prototyping Products
The following figure displays the Synopsys FPGA and Prototyping family of products.

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Synplify Pro for Microsemi Edition User Guide October 2014

Synopsys FPGA and Prototyping Products

Chapter 1: Introduction

FPGA Implementation Tools
The Synplify Pro and Synplify Premier products are RTL synthesis tools especially designed for FPGAs (field programmable gate arrays) and CPLDs (complex programmable logic devices).

Synplify Pro Synthesis Software
The Synplify Pro FPGA synthesis software is the de facto industry standard for producing high-performance, cost-effective FPGA designs. Its unique
Behavior Extracting Synthesis Technology® (B.E.S.T.) algorithms, perform
high-level optimizations before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimizations across the FPGA, fast runtimes, and the ability to handle very large designs. The Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The tool is technology independent allowing quick and easy retargeting between FPGA devices and vendors from a single design project.

Synplify Premier Synthesis Software
The Synplify Premier functionality is a superset of the Synplify Pro tool, providing the ultimate FPGA implementation and debug environment. It includes a comprehensive suite of tools and technologies for advanced FPGA designers, and also serves as the synthesis engine for ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier product offers both FPGA designers and ASIC prototypers targeting single FPGAs with the most efficient method of design implementation and debug. On the design implementation side, it includes functionality for timing closure, logic verification, IP usage, ASIC compatibility, and DSP implementation, as well as a tight integration with FPGA vendor back-end tools. On the debug side, it provides for in-system verification of FPGAs which dramatically accelerates the debug process, and also includes a rapid and incremental method for finding elusive design problems.

Synopsys FPGA Tool Features
This table distinguishes between the major functionality in Synplify Pro, Synplify, Synplify Premier, and Synplify Premier with Design Planner products.

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 1: Introduction

Synopsys FPGA and Prototyping Products

Synplify Synplify Pro

Performance

Behavior Extracting Synthesis

Technology® (BESTTM)

Vendor-Generated Core/IP

Support (certain technologies)

FSM Compiler

FSM Explorer

Gated Clock Conversion

SCOPE® Constraint Entry

High reliability features

Integrated place-and-route

Analysis

HDL Analyst®

Option

Timing Analyzer

Point-to-point

FSM Viewer

Crossprobing

Probe Point Creation

Identify® Instrumentor

Identify Debugger

Power analysis (SAIF)

Physical Design

Design Plan File

Logic Assignment to Regions

Synplify Premier
x
x
x x x x x x x x
x x
x x x x x x

Synplify Premier DP
x
x
x x x x x x x x
x x
x x x x x x
x x

Synplify Pro for Microsemi Edition User Guide October 2014

Synopsys FPGA and Prototyping Products

Chapter 1: Introduction

Area Estimation and Region Capacity Pin Assignment Physical Optimizations Physical Synthesis Physical Analyst Synopsys DesignWare® Foundation Library Runtime Hierarchical Design Enhanced Optimization Fast Synthesis Multiprocessing Compile on Error Team Design Mixed Language Design Compile Points Hierarchical Design True Batch Mode (Floating licenses only) GUI Batch Mode (Floating licenses) Batch Mode P&R Back-annotation of P&R Data Formal Verification

Synplify Synplify Pro

x x x x

–

Identify Integration

Limited

Synplify Premier
x x x
x x x x x
x x x x
x
x Logic synthesis mode x

Synplify Premier DP
x
x x x x x
x x x x x
x x x x
x
x x Logic synthesis mode
x

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 1: Introduction

Synopsys FPGA and Prototyping Products

Back-annotation of P&R Data Design Environment Text Editor View Watch Window Message Window Tcl Window Multiple Implementations Vendor Technology Support Prototyping Features Runtime features Compile Points Gated Clock Conversion Compile on Error

Synplify Synplify Pro

Synplify Premier
x x x x x Selected
x x x x

Synplify Premier DP
x
x x x x x Selected
x x x x

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Synplify Pro for Microsemi Edition User Guide October 2014

Scope of the Document

Chapter 1: Introduction

Scope of the Document
The following explain the scope of this document and the intended audience.

The Document Set
This user guide is part of a document set that includes a reference manual and a tutorial. It is intended for use with the other documents in the set. It concentrates on describing how to use the Synopsys FPGA software to accomplish typical tasks. This implies the following:
· The user guide only explains the options needed to do the typical tasks
described in the manual. It does not describe every available command and option. For complete descriptions of all the command options and syntax, refer to the User Interface Overview chapter in the Synopsys FPGA Synthesis Reference Manual.
· The user guide contains task-based information. For a breakdown of
how information is organized, see Getting Help, on page 22.

Audience
The Synplify Pro software tool is targeted towards the FPGA system developer. It is assumed that you are knowledgeable about the following:
· Design synthesis · RTL · FPGAs · Verilog/VHDL

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 1: Introduction

Getting Started

Getting Started
This section shows you how to get started with the Synopsys FPGA synthesis software. It describes the following topics, but does not supersede the information in the installation instructions about licensing and installation:
· Starting the Software, on page 22 · Getting Help, on page 22

Starting the Software
1. If you have not already done so, install the Synopsys FPGA synthesis software according to the installation instructions.
2. Start the software.
If you are working on a Windows platform, select
Programs->Synopsys->product version from the Start button.
If you are working on a UNIX platform, type the appropriate
command at the command line:
synplify_pro
· The command starts the synthesis tool, and opens the Project window. If
you have run the software before, the window displays the previous project. For more information about the interface, see the User Interface Overview chapter of the Reference Manual.

Getting Help
Before you call Synopsys Support, look through the documented information. You can access the information online from the Help menu, or refer to the PDF version. The following table shows you how the information is organized.

Synplify Pro for Microsemi Edition User Guide October 2014

Getting Started
For help with… Using software features How to…
Flow information
Error messages Licensing Attributes and directives Synthesis features Language and syntax Tcl syntax Tcl synthesis commands Product updates

Chapter 1: Introduction
Refer to the… Synopsys FPGA Synthesis User Guide Synopsys FPGA Synthesis User Guide, application notes on the support web site Synopsys FPGA Synthesis User Guide, application notes on the support web site Online help (select Help->Error Messages) Synopsys SolvNet Website Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Online help (select Help->Tcl Help) Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual (Web menu commands)

Synplify Pro for Microsemi Edition User Guide October 2014

Chapter 1: Introduction

User Interface Overview

User Interface Overview
The user interface (UI) consists of a main window, called the Project view, and specialized windows or views for different tasks. For details about each of the features, see Chapter 2, User Interface Overview of the Synopsys FPGA Synthesis Reference Manual.

Synplify Pro Interface

Button Panel

Toolbars Project view

Status

Implementation Results view

Tabs to access views

Tcl Script/Messages Window LO

Watch Window

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CHAPTER 2
FPGA Synthesis Design Flows
This chapter describes the Logic Synthesis Design Flow, on page 26.

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Chapter 2: FPGA Synthesis Design Flows

Logic Synthesis Design Flow

The Synopsys FPGA tools synthesize logic by first compiling the RTL source into technology-independent logic structures, and then optimizing and mapping the logic to technology-specific resources. After logic synthesis, the tool generates a vendor-specific netlist and constraint file that you can use as inputs to the place-and-route (P&R) tool.
The following figure shows the phases and the tools used for logic synthesis and some of the major inputs and outputs. You can use the Synplify Pro synthesis software for this flow. The interactive timing analysis is optional. Although the flow shows the vendor constraint files as direct inputs to the P&R tool, you should add these files to the synthesis project for timing black boxes.

Synopsys FPGA Tool

RTL

RTL Compilation

FDC

Logic Synthesis

Synthesized netlist Synthesis constraints Vendor constraints
Vendor Tool
Place & Route

Logic Synthesis Procedure

For a design flow with step-by-step instructions based on specific design

data, download the tutorial from the website. The following steps summarize

the procedure for synthesizing the design, which is also illustrated in the

figure that follows.

1. Create a project.

2. Add the source files to the project.

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Logic Synthesis Design Flow

Chapter 2: FPGA Synthesis Design Flows

3. Set attributes and constraints for the design.
4. Set options for the implementation in the Implementation Options dialog box.
5. Click Run to run logic synthesis.
6. Analyze the results, using tools like the log file, the HDL Analyst schematic views, the Message window and the Watch Window.
After you have completed the design, you can use the output files to run place-and-route with the vendor tool and implement the FPGA.
The following figure lists the main steps in the flow:

Create Project
Add Source Files
Set Constraints
Set Options
Run the Software
Analyze Results No Goals Met?
Yes Place and Route

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Logic Synthesis Design Flow

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CHAPTER 3
Preparing the Input
When you synthesize a design, you need to set up two kinds of files: HDL files that describe your design, and project files to manage the design. This chapter describes the procedures to set up these files and the project. It covers the following:
· Setting Up HDL Source Files, on page 30 · Using Mixed Language Source Files, on page 44 · Using the Incremental Compiler, on page 49 · Using the Structural Verilog Flow, on page 51 · Working with Constraint Files, on page 53

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Setting Up HDL Source Files

Setting Up HDL Source Files
This section describes how to set up your source files; project file setup is described in Setting Up Project Files, on page 58. Source files can be in Verilog or VHDL. For information about structuring the files for synthesis, refer to the Reference Manual. This section discusses the following topics:
· Creating HDL Source Files, on page 30 · Using the Context Help Editor, on page 32 · Checking HDL Source Files, on page 34 · Editing HDL Source Files with the Built-in Text Editor, on page 35 · Using an External Text Editor, on page 41 · Setting Editing Window Preferences, on page 39 · Using Library Extensions for Verilog Library Files, on page 42

Creating HDL Source Files
This section describes how to use the built-in text editor to create source files, but does not go into details of what the files contain. For details of what you can and cannot include, as well as vendor-specific information, see the Reference Manual. If you already have source files, you can use the text editor to check the syntax or edit the file (see Checking HDL Source Files, on page 34 and Editing HDL Source Files with the Built-in Text Editor, on page 35).
You can use Verilog or VHDL for your source files. The files have v (Verilog) or vhd (VHDL) file extensions, respectively. You can use Verilog and VHDL files in the same design. For information about using a mixture of Verilog and VHDL input files, see Using Mixed Language Source Files, on page 44.
1. To create a new source file either click the HDL file icon ( ) or do the following:
Select File->New or press Ctrl-n.
In the New dialog box, select the kind of source file you want to create,
Verilog or VHDL. NotLeOthat you can use the Context Help Editor for Verilog designs that contain SystemVerilog constructs in the source

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file. For more information, see Using the Context Help Editor, on page 32.
If you are using Verilog 2001 format or SystemVerilog, make sure to enable the Verilog 2001 or System Verilog option before you run synthesis (Project->Implementation Options->Verilog tab). The default Verilog file format for new projects is SystemVerilog.

Type a name and location for the file and Click OK. A blank editing
window opens with line numbers on the left.
2. Type the source information in the window, or cut and paste it. See Editing HDL Source Files with the Built-in Text Editor, on page 35 for more information on working in the Editing window.

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Setting Up HDL Source Files

For the best synthesis results, check the Reference Manual and ensure that you are using the available constructs and vendor-specific attributes and directives effectively.
3. Save the file by selecting File->Save or the Save icon ( ).
Once you have created a source file, you can check that you have the right syntax, as described in Checking HDL Source Files, on page 34.

Using the Context Help Editor
When you create or open a Verilog design file, use the Context Help button displayed at the bottom of the window to help you code with Verilog/SystemVerilog constructs in the source file or Tcl constraint commands into your Tcl file.
To use the Context Help Editor:
1. Click on the Context Help button to display this text editor.

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2. When you select a construct in the left-side of the window, the online help description for the construct is displayed. If the selected construct has this feature enabled, the online help topic is displayed on the top of the window and a generic code or command template for that construct is displayed at the bottom.

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Setting Up HDL Source Files

3. The Insert Template button is also enabled. When you click the Insert Template button, the code or command shown in the template window is inserted into your file at the location of the cursor. This allows you to easily insert the code or command and modify it for the design that you are going to synthesize.
4. If you want to copy only parts of the template, select the code or command you want to insert and click Copy. You can then paste it into your file.

Checking HDL Source Files

The software automatically checks your HDL source files when it compiles them, but if you want to check your source code before synthesis, use the following procedure. There are two kinds of checks you do in the synthesis software: syntax and synthesis.

1. Select the source files you want to check.
To check all the source files in a project, deselect all files in the
project list, and make sure that none of the files are open in an active window. If you have an active source file, the software only checks the active file.
To check a single file, open the file with File->Open or double-click the
file in the Project window. If you have more than one file open and want to check only one of them, put your cursor in the appropriate file window to make sure that it is the active window.

2. To check the syntax, select Run->Syntax Check or press Shift+F7.

The software detects syntax errors such as incorrect keywords and punctuation and reports any errors in a separate log file (syntax.log). If no errors are detected, a successful syntax check is reported at the bottom of this file.

3. To run a synthesis check, select Run->Synthesis Check or press Shift+F8.

The software detects hardware-related errors such as incorrectly coded

flip-flops and reports any errors in a separate log file (syntax.log). If there

are no errors, a successful syntax check is reported at the bottom of this

file.

4. Review the errors by opening the syntax.log file when prompted and use Find to locate the error message (search for @E). Double-click on the

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5-character error code or click on the message text and push F1 to display online error message help.
5. Locate the portion of code responsible for the error by double-clicking on the message text in the syntax.log file. The Text Editor window opens the appropriate source file and highlights the code that caused the error.
6. Repeat steps 4 and 5 until all syntax and synthesis errors are corrected.
Messages can be categorized as errors, warnings, or notes. Review all messages and resolve any errors. Warnings are less serious than errors, but you must read through and understand them even if you do not resolve all of them. Notes are informative and do not need to be resolved.

Editing HDL Source Files with the Built-in Text Editor
The built-in text editor makes it easy to create your HDL source code, view it, or edit it when you need to fix errors. If you want to use an external text editor, see Using an External Text Editor, on page 41.
1. Do one of the following to open a source file for viewing or editing:
To automatically open the first file in the list with errors, press F5.
To open a specific file, double-click the file in the Project window or
use File->Open (Ctrl-o) and specify the source file.
The Text Editor window opens and displays the source file. Lines are numbered. Keywords are in blue, and comments in green. String values are in red. If you want to change these colors, see Setting Editing Window Preferences, on page 39.

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Setting Up HDL Source Files

2. To edit a file, type directly in the window.
This table summarizes common editing operations you might use. You can also use the keyboard shortcuts instead of the commands.

To…

Do…

Cut, copy, and paste; Select the command from the popup (hold down undo, or redo an action the right mouse button) or Edit menu.

Go to a specific line

Press Ctrl-g or select Edit->Go To, type the line number, and click OK.

Find text

Press Ctrl-f or select Edit ->Find. Type the text you want to find, and click OK.

Replace text

Press Ctrl-h or select Edit->Replace. Type the text you want to find, and the text you want to replace it with. Click OK.

Complete a keyword

Type enough characters to uniquely identify the keyword, and press Esc.

Indent text to the right Select the block, and press Tab. Indent text to the left LSOelect the block, and press Shift-Tab.

Change to upper case Select the text, and then select Edit->Advanced ->Uppercase or press Ctrl-Shift-u.

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To… Change to lower case Add block comments
Edit columns

Do…
Select the text, and then select Edit->Advanced ->Lowercase or press Ctrl-u.
Put the cursor at the beginning of the comment text, and select Edit->Advanced->Comment Code or press Alt-c.
Press Alt, and use the left mouse button to select the column. On some platforms, you have to use the key to which the Alt functionality is mapped, like the Meta or diamond key.

3. To cut and paste a section of a PDF document, select the T-shaped Text Select icon, highlight the text you need and copy and paste it into your file. The Text Select icon lets you select parts of the document.
4. To create and work with bookmarks in your file, see the following table.
Bookmarks are a convenient way to navigate long files or to jump to points in the code that you refer to often. You can use the icons in the Edit toolbar for these operations. If you cannot see the Edit toolbar on the far right of your window, resize some of the other toolbars.

To… Insert a bookmark
Delete a bookmark
Delete all bookmarks

Do…
Click anywhere in the line you want to bookmark. Select Edit->Toggle Bookmarks, press Ctrl-F2, or select the first icon in the Edit toolbar. The line number is highlighted to indicate that there is a bookmark at the beginning of that line.
Click anywhere in the line with the bookmark. Select Edit->Toggle Bookmarks, press Ctrl-F2, or select the first icon in the Edit toolbar. The line number is no longer highlighted after the bookmark is deleted.
Select Edit->Delete all Bookmarks, press Ctrl-Shift-F2, or select the last icon in the Edit toolbar. The line numbers are no longer highlighted after the bookmarks are deleted.

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Setting Up HDL Source Files

To…
Navigate a file using bookmarks

Do…
Use the Next Bookmark (F2) and Previous Bookmark (Shift-F2) commands from the Edit menu or the corresponding icons from the Edit toolbar to navigate to the bookmark you want.

5. To fix errors or review warnings in the source code, do the following:
Open the HDL file with the error or warning by double-clicking the file
in the project list.
Press F5 to go to the first error, warning, or note in the file. At the
bottom of the Editing window, you see the message text.
To go to the next error, warning, or note, select Run->Next Error/Warning
or press F5. If there are no more messages in the file, you see the message “No More Errors/Warnings/Notes” at the bottom of the Editing window. Select Run->Next Error/Warning or press F5 to go to the the error, warning, or note in the next file.
To navigate back to a previous error, warning, or note, select
Run->Previous Error/Warning or press Shift-F5.
6. To bring up error message help for a full description of the error, warning, or note:
Open the text-format log file (click View Log) and either double click on
the 5-character error code or click on the message text and press F1.
Open the HTML log file and click on the 5-character error code.
In the Tcl window, click the Messages tab and click on the 5-character
error code in the ID column.
7. To crossprobe from the source code window to other views, open the view and select the piece of code. See Crossprobing from the Text Editor Window, on page 246 for details.
8. When you have fixed all the errors, select File->Save or click the Save icon to save the file.

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Setting Editing Window Preferences
You can customize the fonts and colors used in a Text Editing window.
1. Select Options->Editor Options and either Synopsys Editor or External Editor. For more information about the external editor, see Using an External Text Editor, on page 41.
2. Then depending on the type of file you open, you can to set the background, syntax coloring, and font preferences to use with the text editor.

Note: Thereafter, text editing preferences you set for this file will apply to all files of this file type.

The Text Editing window can be used to set preferences for project files, source files (Verilog/VHDL), log files, Tcl files, constraint files, or other default files from the Editor Options dialog box.
3. You can set syntax colors for some common syntax options, such as keywords, strings, and comments. For example in the log file, warnings and errors can be color-coded for easy recognition.
Click in the Foreground or Background field for the corresponding object in the Syntax Coloring field to display the color palette.

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You can select basic colors or define custom colors and add them to your custom color palette. To select your desired color click OK.
4. To set font and font size for the text editor, use the pull-down menus.
5. Check Keep Tabs to enable tab settings, then set the tab spacing using the up or down arrow for Tab Size.

LO 6. Click OK on the Editor Options form.
© 2014 Synopsys, Inc. 40

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Using an External Text Editor
You can use an external text editor like vi or emacs instead of the built-in text editor. Do the following to enable an external text editor. For information about using the built-in text editor, see Editing HDL Source Files with the Built-in Text Editor, on page 35.
1. Select Options->Editor Options and turn on the External Editor option.
2. Select the external editor, using the method appropriate to your operating system.
If you are working on a Windows platform, click the …(Browse) button
and select the external text editor executable.
From a UNIX or Linux platform for a text editor that creates its own
window, click the … Browse button and select the external text editor executable.
From a UNIX platform for a text editor that does not create its own
window, do not use the … Browse button. Instead type xterm -e editor. The following figure shows VI specified as the external editor.

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Setting Up HDL Source Files

From a Linux platform, for a text editor that does not create its own
window, do not use the … Browse button. Instead, type gnome-terminal -x editor. To use emacs for example, type gnome-terminal -x emacs.
The software has been tested with the emacs and vi text editors.
3. Click OK.

Using Library Extensions for Verilog Library Files
Library extensions can be added to Verilog library files included in your design for the project. When you provide search paths to the directories that contain the Verilog library files, you can specify these new library extensions as well as the Verilog and SystemVerilog (.v and .sv) file extensions.
To do this:
1. Select the Verilog tab of the Implementation Options panel.
2. Specify the locations of the Library Directories for the Verilog library files to be included in your design for the project.
3. Specify the Library Extensions.
Any library extensions can be specified, such as .av, .bv, .cv, .xxx, .va, .vas (separate library extensions with a space).
The following figure shows you where to enter the library extensions on the dialog box.

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The Tcl equivalent for this example is the following command:
set_option -libext .av .bv .cv .dv .ev
For details, see libext, on page 57 in the Command Reference.
4. After you compile the design, you can verify in the log file that the library files with these extensions were loaded and read. For example:
@N: Running Verilog Compiler in SystemVerilog mode @I::”C:dirtop.v” @N: CG1180 :”C:dirtop.v”:8:0:8:3|Loading file C:dirlib1sub1.av from specified library directory C:dirlib1 @I::”C:dirlib1sub1.av” @N: CG1180 :”C:dirtop.v”:10:0:10:3|Loading file C:dirlib2sub2.bv from specified library directory C:dirlib2 @I::”C:dirlib2sub2.bv” @N: CG1180 :”C:dirtop.v”:12:0:12:3|Loading file

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Using Mixed Language Source Files

C:dirlib3sub3.cv from specified library directory C:dirlib3 @I::”C:dirlib3sub3.cv” @N: CG1180 :”C:dirtop.v”:14:0:14:3|Loading file C:dirlib4sub4.dv from specified library directory C:dirlib4 @I::”C:dirlib4sub4.dv” @N: CG1180 :”C:dirtop.v”:16:0:16:3|Loading file C:dirlib5sub5.ev from specified library directory C:dirlib5 @I::”C:dirlib5sub5.ev” Verilog syntax check successful!

Using Mixed Language Source Files
With the Synplify Pro software, you can use a mixture of VHDL and Verilog input files in your project. For examples of the VHDL and Verilog files, see the Reference Manual.
1. Remember that Verilog does not support unconstrained VHDL ports and set up the mixed language design files accordingly.
2. If you want to organize the Verilog and VHDL files in different folders, select Options->Project View Options and toggle on the View Project Files in Folders option.
When you add the files to the project, the Verilog and VHDL files are in separate folders in the Project view.
3. When you open a project or create a new one, add the Verilog and VHDL files as follows:
Select the Project->Add Source File command or click the Add File button. On the form, set Files of Type to HDL Files (*.vhd, *.vhdl, *.v). Select the Verilog and VHDL files you want and add them to your
project. Click OK. For details about adding files to a project, see Making Changes to a Project, on page 62.
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The files you added are displayed in the Project view. This figure shows the files arranged in separate folders.
4. When you set device options (Implementation Options button), specify the top-level module. For more information about setting device options, see Setting Logic Synthesis Implementation Options, on page 75.
If the top-level module is Verilog, click the Verilog tab and type the
name of the top-level module.
If the top-level module is VHDL, click the VHDL tab and type the name
of the top-level entity. If the top-level module is not located in the default work library, you must specify the library where the compiler can find the module. For information on how to do this, see VHDL Panel, on page 200.

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You must explicitly specify the top-level module, because it is the starting point from which the mapper generates a merged netlist.
5. Select the Implementation Results tab on the same form and select one output HDL format for the output files generated by the software. For more information about setting device options, see Setting Logic Synthesis Implementation Options, on page 75.
For a Verilog output netlist, select Write Verilog Netlist. For a VHDL output netlist, select Write VHDL Netlist. Set any other device options and click OK.
You can now synthesize your design. The software reads in the mixed formats of the source files and generates a single srs file that is used for synthesis.
6. If you run into problems, see Troubleshooting Mixed Language Designs, on page 47 for additional information and tips.
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Troubleshooting Mixed Language Designs
This section provides tips on handling specific situations that might come up with mixed language designs.

VHDL File Order
For VHDL-only designs or mixed designs where the top level is not specified, the FPGA synthesis tools automatically re-arrange the VHDL files so that the VHDL packages are compiled in the correct order.
However, if you have a mixed-language design where you have specified the top level, you must specify the VHDL file order for the tool. You only need to do this once, by selecting the Run->Arrange VHDL files command. If you do not do this, you get an error message.

VHDL Global Signals
Currently, you cannot have VHDL global signals in mixed language designs, because the tool only implements these signals in VHDL-only designs.

Passing VHDL Boolean Generics to Verilog Parameters
The tool infers a black box for a VHDL component with Boolean generics, if that component is instantiated in a Verilog design. This is because Verilog does not recognize Boolean data types, so the Boolean value must be represented correctly. If the value of the VHDL Boolean generic is TRUE and the Verilog literal is represented by a 1, the Verilog compiler interprets this as a black box.
To avoid inferring a black box, the Verilog literal for the VHDL Boolean generic set to TRUE must be 1’b1, not 1. Similarly, if the VHDL Boolean generic is FALSE, the corresponding Verilog literal must be 1’b0, not 0. The following example shows how to represent Boolean generics so that they correctly pass the VHDL-Verilog boundary, without inferring a black box.

VHDL Entity Declaration

Verilog Instantiation

Entity abc is Generic (
Number_Bits Divide_Bit );

: integer : boolean

:= 0; := False;

abc #( .Number_Bits (16), .Divide_Bit (1’b0)
)

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Passing VHDL Generics Without Inferring a Black Box
In the case where a Verilog component parameter, (for example [0:0] RSR = 1’b0) does not match the size of the corresponding VHDL component generic (RSR : integer := 0), the tool infers a black box.
You can work around this by removing the bus width notation of [0:0] in the Verilog files. Note that you must use a VHDL generic of type integer because the other types do not allow for the proper binding of the Verilog component.

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Using the Incremental Compiler

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Using the Incremental Compiler
Use the Incremental Compiler flow to significantly reduce compiler runtime for large designs. The software recompiles only relevant files when a design change is made and reuses the compiler database. The compiler regenerates the SRS file only for the affected module and immediate parent module.
To run this flow, perform the following:
1. Add the Verilog or VHDL files for the design.
2. Enable the Incremental Compile option from the Verilog or VHDL tab of the Implementation Options panel.
An SRS file is created for each design module in the synwork directory.

3. Run the compiler for the first time.
4. If a design change was made, re-run the compiler.
The compiler analyzes the database and determines whether the SRS files are up-to-date, then only modules that have changed and the immediate parent modules are regenerated. This can help improve the runtime for the design.

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Using the Incremental Compiler

Limitations
The incremental compiler does not support:
· Configuration files included in either the Verilog or VHDL flow · Mixed HDL flows · Designs with cross module referencing (XMR)

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Using the Structural Verilog Flow
The synthesis tool accepts structural Verilog files as input for your design project. The structural Verilog compiler performs syntax semantic checks using its light-weight parser to improve runtime. This compiler does not perform complex hardware extractions or RTL optimization operations, therefore, the software runs fast compilation of the structural Verilog files. The software can read these generated structural Verilog files, if they contain:
· Instantiations of technology primitives
· Simple assign statements
· Attributes specified in Verilog 2001 and older formats
· All constructs, except attributes must be specified in Verilog 95 format
To use structural Verilog input files:
1. You must specify the structural Verilog files to include in your design. To do this, add the file to the project using one of the following methods:
Project->Add Source File or the Add File button in the Project view Tcl command: add_file -structver fileName
This flow can contain only structural Verilog files or mixed HDL files (Verilog/VHDL/EDF/SRS) along with structural Verilog netlist files. However, Verilog/VHDL/EDF/SRS instances are not supported within a structural Verilog module.
2. The structural Verilog files are added to the Structural Verilog folder in the Project view. You can also add files to this directory, when you perform the following:
Select the structural Verilog file. Right-click and select File Options. Choose Structural Verilog from the File Type drop-down menu.
3. Run synthesis.
The synthesis tool generates a vm or edf netlist file depending on the technology specified. This process is similar to the default synthesis flow.

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Limitations
Limitations of the structural Verilog flow does not support the following:
· RTL instances for any other file types · Hierarchical project management (HPM) flows · Complex assignments · Compiler-specific modes and switches

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Working with Constraint Files
Constraint files are text files that are automatically generated by the SCOPE interface (see Specifying SCOPE Constraints, on page 119), or which you create manually with a text editor. They contain Tcl commands or attributes that constrain the synthesis run. Alternatively, you can set constraints in the source code, but this is not the preferred method.
This section contains information about
· When to Use Constraint Files over Source Code, on page 53
· Using a Text Editor for Constraint Files (Legacy), on page 54
· Tcl Syntax Guidelines for Constraint Files, on page 55
· Checking Constraint Files, on page 56
· For details on this report, see Constraint Checking Report, on
page 270.of the Reference Manual, on page 56

When to Use Constraint Files over Source Code
You can add constraints in constraint files (generated by SCOPE interface or entered in a text editor) or in the source code. In general, it is better to use constraint files, because you do not have to recompile for the constraints to take effect. It also makes your source code more portable. See Using the SCOPE Editor, on page 112 for more information.
However, if you have black box timing constraints like syn_tco, syn_tpd, and syn_tsu, you must enter them as directives in the source code. Unlike attributes, directives can only be added to the source code, not to constraint files. See Specifying Attributes and Directives, on page 90 for more information on adding directives to source code.

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Working with Constraint Files

Using a Text Editor for Constraint Files (Legacy)
You can use the Legacy SCOPE editor for the SDC constraint files created before release version G-2012.09. However, it is recommended that you translate your SDC files to FDC files to enable the latest version of the SCOPE editor and to utilize the enhanced timing constraint handling in the tool.
If you choose to use the legacy SCOPE editor, this section shows you how to manually create a Tcl constraint file. The software automatically creates this file if you use the legacy SCOPE editor to enter the constraints. The Tcl constraint file only contains general timing constraints. Black box constraints must be entered in the source code. For additional information, see When to Use Constraint Files over Source Code, on page 53.
1. Open a file for editing.
Make sure you have closed the SCOPE window, or you could
overwrite previous constraints.
To create a new file, select File->New, and select the Constraint File
(SCOPE) option. Type a name for the file and click OK.
To edit an existing file, select File->Open, set the Files of Type filter to
Constraint Files (sdc) and open the file you want.
2. Follow the syntax guidelines in Tcl Syntax Guidelines for Constraint Files, on page 55.
3. Enter the timing constraints you need. For the syntax, see the Reference Manual. If you have black box timing constraints, you must enter them in the source code.
4. You can also add vendor-specific attributes in the constraint file using define_attribute. See Specifying Attributes in the Constraints File, on page 97 for more information.
5. Save the file.
6. Add the file to the project as described in Making Changes to a Project, on page 62, and run synthesis.

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Tcl Syntax Guidelines for Constraint Files
This section covers general guidelines for using Tcl for constraint files:
· Tcl is case-sensitive.
· For naming objects: The object name must match the name in the HDL code. Enclose instance and port names within curly braces { }. Do not use spaces in names. Use the dot (.) to separate hierarchical names. In Verilog modules, use the following syntax for instance, port, and
net names:
v:cell [prefix:]objectName
Where cell is the name of the design entity, prefix is a prefix to identify objects with the same name, objectName is an instance path with the dot (.) separator. The prefix can be any of the following:

Prefix (Lower-case) i: p: b: n:

Object Instance names Port names (entire port) Bit slice of a port Net names

In VHDL modules, use the following syntax for instance, port, and net
names in VHDL modules:
v:cell [.view] [prefix:]objectName
Where v: identifies it as a view object, lib is the name of the library, cell is the name of the design entity, view is a name for the architecture, prefix is a prefix to identify objects with the same name, and objectName is an instance path with the dot (.) separator. View is only needed if there is more than one architecture for the design. See the table above for the prefixes of objects.

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Working with Constraint Files

· Name matching wildcards are * (asterisk matches any number of
characters) and ? (question mark matches a single character). These characters do not match dots used as hierarchy separators. For example, the following string identifies all bits of the statereg instance in the statemod module:
i:statemod.statereg[*]

Checking Constraint Files
You can check syntax and other pertinent information on your constraint files using the Constraint Check command. To generate a constraint report, do the following:
1. Create a constraint file and add it to your project.
2. Select Run->Constraint Check.
This command generates a report that checks the syntax and applicability of the timing constraints in the FPGA synthesis constraint files for your project. The report is written to the projectName_cck.rpt file and lists the following information:
Constraints that are not applied Constraints that are valid and applicable to the design Wildcard expansion on the constraints Constraints on objects that do not exist
For details on this report, see Constraint Checking Report, on page 270.of the Reference Manual

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CHAPTER 4
Setting up a Logic Synthesis Project
When you synthesize a design with the Synopsys FPGA synthesis tools, you must set up a project for your design. The following describe the procedures for setting up a project for logic synthesis:
· Setting Up Project Files, on page 58 · Managing Project File Hierarchy, on page 66 · Setting Up Implementations, on page 72 · Setting Logic Synthesis Implementation Options, on page 75 · Specifying Attributes and Directives, on page 90 · Searching Files, on page 98 · Archiving Files and Projects, on page 101

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Setting Up Project Files

Setting Up Project Files
This section describes the basics of how to set up and manage a project file for your design, including the following information:
· Creating a Project File, on page 58 · Opening an Existing Project File, on page 61 · Making Changes to a Project, on page 62 · Setting Project View Display Preferences, on page 63 · Updating Verilog Include Paths in Older Project Files, on page 65
For a specific example on setting up a project file, refer to the tutorial for the tool you are using.

Creating a Project File
You must set up a project file for each project. A project contains the data needed for a particular design: the list of source files, the synthesis results file, and your device option settings. The following procedure shows you how to set up a project file using individual commands.
1. Start by selecting one of the following: File->Build Project, File->Open Project, or the P icon. Click New Project.
The Project window shows a new project. Click the Add File button, press F4, or select the Project->Add Source File command. The Add Files to Project dialog box opens.
2. Add the source files to the project.
Make sure the Look in field at the top of the form points to the right
directory. The files are listed in the box. If you do not see the files, check that the Files of Type field is set to display the correct file type. If you have mixed input files, follow the procedure described in Using Mixed Language Source Files, on page 44.

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To add all the files in the directory at once, click the Add All button on
the right side of the form. To add files individually, click on the file in the list and then click the Add button, or double-click the file name.
You can add all the files in the directory and then remove the ones you do not need with the Remove button.
If you are adding VHDL files, select the appropriate library from the the VHDL Library popup menu. The library you select is applied to all VHDL files when you click OK in the dialog box.
Your project window displays a new project file. If you click on the plus sign next to the project and expand it, you see the following:
A folder (two folders for mixed language designs) with the source files.
If your files are not in a folder under the project directory, you can set this preference by selecting Options->Project View Options and checking the View project files in folders box. This separates one kind of file from another in the Project view by putting them in separate folders.

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The implementation, named rev_1 by default. Implementations are
revisions of your design within the context of the synthesis software, and do not replace external source code control software and processes. Multiple implementations let you modify device and synthesis options to explore design options. You can have multiple implementations in Synplify Pro. Each implementation has its own synthesis and device options and its own project-related files.

3. Add any libraries you need, using the method described in the previous step to add the Verilog or VHDL library file.
For vendor-specific libraries, add the appropriate library file to the
project. Note that for some families, the libraries are loaded automatically and you do not need to explicitly add them to the project file.
To add a third-party VHDL package library, add the appropriate .vhd file to the design, as described in step 2. Right click the file in the Project view and select File Options, or select Project-> Set VHDL library. Specify a library name that is compatible with the simulators. For example, MYLIB. Make sure that this package library is before the toplevel design in the list of files in the Project view.
For information about setting Verilog and VHDL file options, see Setting Verilog and VHDL Options, on page 84. You can also set these file options later, before running synthesis.
For additional vendor-specific information about using vendor macro libraries and black bLoOxes, see Optimizing for Microsemi Designs, on page 487.
For generic technology components, you can either add the
technology-independent Verilog library supplied with the software

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(install_dir/lib/generic_ technology/gtech.v) to your design, or add your own generic component library. Do not use both together as there may be conflicts.
4. Check file order in the Project view. File order is especially important for VHDL files.
For VHDL files, you can automatically order the files by
selecting Run->Arrange VHDL Files. Alternatively, manually move the files in the Project view. Package files must be first on the list because they are compiled before they are used. If you have design blocks spread over many files, make sure you have the following file order: the file containing the entity must be first, followed by the architecture file, and finally the file with the configuration.
In the Project view, check that the last file in the Project view is the
top-level source file. Alternatively, you can specify the top-level file when you set the device options.
5. Select File->Save, type a name for the project, and click Save. The Project window reflects your changes.
6. To close a project file, select the Close Project button or File->Close Project.

Opening an Existing Project File
There are two ways to open a project file: the Open Project and the generic File ->Open command.
1. If the project you want to open is one you worked on recently, you can select it directly: File->Recent Projects-> projectName.
2. Use one of the following methods to open any project file:

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Setting Up Project Files

Open Project Command

File->Open Command

Select File->Open Project, click the Open Project button on the left side of the Project window, or click the P icon.
To open a recent project, doubleclick it from the list of recent projects.
Otherwise, click the Existing Project button to open the Open dialog box and select the project.

Select File->Open.
Specify the correct directory in the Look In: field.
Set File of Type to Project Files (*.prj). The box lists the project files.
Double-click on the project you want to open.

The project opens in the Project window.

Making Changes to a Project
Typically, you add, delete, or replace files.
1. To add source or constraint files to a project, select the Add Files button or Project->Add Source File to open the Select Files to Add to Project dialog box. See Creating a Project File, on page 58 for details.
2. To delete a file from a project, click the file in the Project window, and press the Delete key.
3. To replace a file in a project,
Select the file you want to change in the Project window.
Click the Change File button, or select Project->Change File.
In the Source File dialog box that opens, set Look In to the directory
where the new file is located. The new file must be of the same type as the file you want to replace.
If you do not see your file listed, select the type of file you need from
the Files of Type field.
Double-click the file. The new file replaces the old one in the project
list. LO
4. To specify how project files are saved in the project, right click on a file in the Project view and select File Options. Set the Save File option to either Relative to Project or Absolute Path.

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5. To check the time stamp on a file, right click on a file in the Project view and select File Options. Check the time that the file was last modified. Click OK.

Setting Project View Display Preferences
You can customize the organization and display of project files. 1. Select Options->Project View Options. The Project View Options form opens.

2. To organize different kinds of input files in separate folders, check View Project Files in Folders.
Checking this option creates separate folders in the Project view for constraint files and source files.

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Setting Up Project Files

3. Control file display with the following:
Automatically display all the files, by checking Show Project Library. If
this is unchecked, the Project view does not display files until you click on the plus symbol and expand the files in a folder.
Check one of the boxes in the Project File Name Display section of the
form to determine how filenames are displayed. You can display just the filename, the relative path, or the absolute path.
4. To view project files in customized custom folders, check View Project Files in Custom Folders. For more information, see Creating Custom Folders, on page 66. Type folders are only displayed if there are multiple types in a custom folder.

Custom Folders
© 2014 Synopsys, Inc. 64

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5. To open more than one implementation in the same Project view, check Allow Multiple Projects to be Opened.
Project 1

Project 2

6. Control the output file display with the following:
Check the Show all Files in Results Directory box to display all the output
files generated after synthesis.
Change output file organization by clicking in one of the header bars
in the Implementation Results view. You can group the files by type or sort them according to the date they were last modified.
7. To view file information, select the file in the Project view, right-click, and select File Options. For example, you can check the date a file was modified.
Updating Verilog Include Paths in Older Project Files
If you have a project file created with an older version of the software (prior to 8.1), the Verilog include paths in this file are relative to the results directory or the source file with the `include statements. In releases after 8.1, the project file `include paths are relative to the project file only. The GUI in the more recent releases does not automatically upgrade the older prj files to conform to the newer rules. To upgrade and use the old project file, do one of the following:
· Manually edit the prj file in a text editor and add the following on the
line before each set_option -include_path:
set_option -project_relative_includes 1
· Start a new project with a newer version of the software and delete the
old project. This will make the new prj file obey the new rule where includes are relative to the prj file.

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Managing Project File Hierarchy

Managing Project File Hierarchy
The following sections describe how you can create and manage customized folders and files in the Project view:
· Creating Custom Folders · Manipulating Custom Project Folders · Manipulating Custom Files

Creating Custom Folders
You can create logical folders and customize files in various hierarchy groupings within your Project view. These folders can be specified with any name or hierarchy level. For example, you can arbitrarily match your operating system file structure or HDL logic hierarchy. Custom folders are distinguished by their blue color.

There are several ways to create custom folders and then add files to them in a project. Use one of the following methods:

1. Right-click on a project file or another custom folder and select Add Folder from the popup menu. Then perform any of the following file operations:

Right-click displays so

on a that

fyioleuoLcrOafnileesitahnedr

select select

Place in Folder. A sub-menu an existing folder or create

new folder.

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Note that you can arbitrarily name the folder, however do not use the character (/) because this is a hierarchy separator symbol.
To rename a folder, right-click on the folder and select Rename from
the popup menu. The Rename Folder dialog box appears; specify a new name.
2. Use the Add Files to Project dialog box to add the entire contents of a folder hierarchy, and optionally place files into custom folders corresponding to the OS folder hierarchies listed in the dialog box display.

To do this, select the Add File button in the Project view.
Select any requested folders such as dsp from the dialog box, then
click the Add button. This places all the files from the dsp hierarchy into the custom folder you just created.

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Managing Project File Hierarchy

To automatically place the files into custom folders corresponding to
the OS folder hierarchy, check the option called Add Files to Custom Folders on the dialog box.
By default, the custom folder name is the same name as the folder
containing files or folder to be added to the project. However, you can modify how folders are named, by clicking on the Folders Option button. The following dialog box is displayed.

To use:
Only the folder containing files for the folder name, click on Use OS
Folder Name.
The path name to the selected folder to determine the level of
hierarchy reflected for the custom folder path.

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3. You can drag and drop files and folders from an OS Explorer application into the Project view. This feature is available on Windows and Linux desktops running KDE.
When you drag and drop a file, it is immediately added to the project.
If no project is open, the software creates a project.
When you drag and drop a file over a folder, it will be placed in that
folder. Initially, the Add Files to Project dialog box is displayed asking you to confirm the files to be added to the project. You can click OK to accept the files. If you want to make changes, you can click the Remove All button and specify a new filter or option.

Note: To display custom folders in the Project view, select the Options->Project View Options menu, then enable/disable the check box for View Project Files in Custom Folders on the dialog box.

Manipulating Custom Project Folders
The following procedure describes how you can remove files from folders, delete folders, and change the folder hierarchy.
1. To remove a file from a custom folder, either:
Drag and drop it into another folder or onto the project. Highlight the file, right-click and select Remove from Folder from the
popup menu.
Do not use the Delete (DEL) key, as this removes the file from the project.
2. To delete a custom folder, highlight it then right-click and select Delete from the popup menu or press the DEL key. When you delete a folder, make one of the following choices:
Click Yes to delete the folder and the files contained in the folder from
the project.
Click No to just delete the folder.

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Managing Project File Hierarchy

3. To change the hierarchy of the custom folder:
Drag and drop the folder within another folder so that it is a sub-
folder or over the project to move it to the top-level.
To remove the top-level hierarchy of a custom folder, drag and drop
the desired sub-level of hierarchy over the project. Then delete the empty root directory for the folder.
For example, if the existing custom folder directory is:
/Examples/Verilog/RTL
Suppose you want a single-level RTL hierarchy only, then drag and drop RTL over the project. Thereafter, you can delete the /Examples/Verilog directory.

Manipulating Custom Files
Additionally, you can perform the following types of custom file operations:
1. To suppress the display of files in the Type folders, right-click in the Project view and select Project View Options or select Options->Project View Options. Disable the option View Project Files in Type Folders on the dialog box.
2. To display files in alphabetical order instead of project order, check the Sort Files button in the Project view control panel. Click the down arrow key in the bottom-left corner of the panel to toggle the control panel on and off.

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Control Panel Toggle
3. To change the order of files in the project:
Make sure to disable custom folders and sorting files. Drag and drop a file to the desired position in the list of files.
4. To change the file type, drag and drop it to the new type folder. The software will prompt you for verification.

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Setting Up Implementations

Setting Up Implementations
An implementation is a version of a project, implemented with a specific set of constraints and other settings. A project can contain multiple implementations, each one with its own settings.

Working with Multiple Implementations
The Synplify Pro tool lets you create multiple implementations of the same design and then compare results. This lets you experiment with different settings for the same design. Implementations are revisions of your design within the context of the synthesis software, and do not replace external source code control software and processes.
1. Click the Add Implementation button or select Project->New Implementation and set new device options (Device tab), new options (Options tab), or a new constraint file (Constraints tab).
The software creates another implementation in the project view. The new implementation has the same name as the previous one, but with a different number suffix. The following figure shows two implementations, rev1 and rev2, with the current (active) implementation highlighted.

The new implementation uses the same source code files, but different device options and constraints. It copies some files from the previous implementation: the tlg log file, the srs RTL netlist file, and the design_fsm.sdc file generated by FSM Explorer. The software keeps a repeatable history of the synthesis runs.

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2. Run synthesis again with the new settings.
To run the current implementation only, click Run.
To run all the implementations in a project, select Run->Run All
Implementations.
You can use multiple implementations to try a different part or experiment with a different frequency. See Setting Logic Synthesis Implementation Options, on page 75 for information about setting options.
The Project view shows all implementations with the active implementation highlighted and the corresponding output files generated for the active implementation displayed in the Implementation Results view on the right; changing the active implementation changes the output file display. The Watch window monitors the active implementation. If you configure this window to watch all implementations, the new implementation is automatically updated in the window.
3. Compare the results.
Use the Watch window to compare selected criteria. Make sure to set
the implementations you want to compare with the Configure Watch command. See Using the Watch Window, on page 190 for details.

To compare details, compare the log file results.
4. To rename an implementation, click the right mouse button on the implementation name in the project view, select Change Implementation Name from the popup menu, and type a new name.
Note that the current UI overwrites the implementation; releases prior to 9.0 preserve the implementation to be renamed.
5. To copy an implementation, click the right mouse button on the implementation name in the project view, select Copy Implementation from the popup menu, and type a new name for the copy.

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Setting Up Implementations

6. To delete an implementation, click the right mouse button on the implementation name in the project view, and select Remove Implementation from the popup menu.

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Setting Logic Synthesis Implementation Options
You can set global options for your synthesis implementations, some of them technology-specific. This section describes how to set global options like device, optimization, and file options with the Implementation Options command. For information about setting constraints for the implementation, see Specifying SCOPE Constraints, on page 119. For information about overriding global settings with individual attributes or directives, see Specifying Attributes and Directives, on page 90.
This section discusses the following topics:
· Setting Device Options, on page 75 · Setting Optimization Options, on page 78 · Specifying Global Frequency and Constraint Files, on page 80 · Specifying Result Options, on page 82 · Specifying Timing Report Output, on page 84 · Setting Verilog and VHDL Options, on page 84
Setting Device Options
Device options are part of the global options you can set for the synthesis run. They include the part selection (technology, part and speed grade) and implementation options (I/O insertion and fanouts). The options and the implementation of these options can vary from technology to technology, so check the vendor chapters of the Reference Manual for information about your vendor options.
1. Open the Implementation Options form by clicking the Implementation Options button or selecting Project->Implementation Options, and click the Device tab at the top if it is not already selected.
2. Select the technology, part, package, and speed. Available options vary, depending on the technology you choose.

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3. Set the device mapping options. The options vary, depending on the technology you choose.
If you are unsure of what an option means, click on the option to see
a description in the box below. For full descriptions of the options, click F1 or refer to the appropriate vendor chapter in the Reference Manual.
To set an option, type in the value or check the box to enable it.
For more information about setting fanout limits and retiming, see Setting Fanout Limits, on page 348, and Retiming, on page 334, respectively. For details about other vendor-specific options, refer to the appropriate vendor chapter and technology family in the Reference Manual.

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4. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK.
5. Click the Run button to synthesize the design. The software compiles and maps the design using the options you set.
6. To set device options with a script, use the set_option Tcl command. The following table contains an alphabetical list of the device options on the Device tab mapped to the equivalent Tcl commands. Because the options are technology- and family-based, all of the options listed in the table may not be available in the selected technology. All commands begin with set_option, followed by the syntax in the column as shown. Check the Reference Manual for the most comprehensive list of options for your vendor.
The following table shows a majority of the device options.

Option Annotated Properties for Analyst Disable I/O Insertion Fanout Guide

Tcl Command (set_option…) -run_prop_extract {1|0} -disable_io_insertion {1|0} -fanout_limit fanout_value

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Option

Tcl Command (set_option…)

Package

-package pkg_name

Part

-part part_name

Resolve Mixed Drivers

-resolve_multiple_driver {1|0}

Speed

-speed_grade speed_grade

Technology

-technology keyword

Update Compile Point Timing Data -update_models_cp {0|1}

HDL Analyst Database Generation -hdl_qload {1|0}

Setting Optimization Options
Optimization options are part of the global options you can set for the implementation. This section tells you how to set options like frequency and global optimization options like resource sharing. You can also set some of these options with the appropriate buttons on the UI.
1. Open the Implementation Options form by clicking the Implementation Options button or selecting Project->Implementation Options, and click the Options tab at the top.
2. Click the optimization options you want, either on the form or in the Project view. Your choices vary, depending on the technology. If an option is not available for your technology, it is greyed out. Setting the option in one place automatically updates it in the other.

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Project View

Optimization Options Implementation Options->Options

For details about using these optimizations refer to the following sections:

FSM Compiler FSM Explorer
Resource Sharing Retiming

Optimizing State Machines, on page 354
Running the FSM Explorer, on page 359 Note: Only a subset of the Microsemi technologies support the FSM Explorer option. Use the Project->Implementation Options->Options panel to determine if this option is supported for the device you specify in your tool.
Sharing Resources, on page 352
Retiming, on page 334

The equivalent Tcl set_option command options are as follows:

Option FSM Compiler FSM Explorer Resource Sharing Retiming

set_option Tcl Command Option -symbolic_fsm_compiler {1|0} -use_fsm_explorer {1|0} -resource_sharing {1|0} -retiming {1|0}

3. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK.

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4. Click the Run button to run synthesis.
The software compiles and maps the design using the options you set.
HDL Analyst Database Generation
By default, the software reads the entire design, performs logic optimizations and timing propagation, and writes output to a single netlist (srs). As designs get larger, the time to run and debug the design becomes more challenging.
This options allows the compiler to pre-partition the design into multiple modules that are written to separate netlist files (srs). To enable this option, select the HDL Analyst Database Generation checkbox on the Options tab of the Implementation Options dialog box. This feature improves memory usage significantly for large designs.
This feature can also be enabled from the Tcl Script window using the following set_option Tcl command:
set_option -hdl_qload 1
Once the HDL Analyst Database Generation option is enabled, use the Incremental Quick Load option in the HDL Analyst tool to display the design using either a single netlist (srs) or multiple top-level RTL module netlists (srs). The tool can take advantage of this feature by dynamically loading only the affected design hierarchy. For example, the hierarchy browser can expand only the lowerlevel hierarchy as needed for quick load. The Incremental Quick Load option is located on the General panel of the HDL Analyst Options dialog box. See General Panel, on page 304.

Specifying Global Frequency and Constraint Files

This procedure tells you how to set the global frequency and specify the constraint files for the implementation.

1. To set a global frequency, do one of the following:

Type a global frequency in the Project view.

Open the Implementation Options form by clicking the Implementation

Options button Constraints tab.

seleLcOting

Project->Implementation

Options,

and

click

the

The equivalent Tcl set_option command is -frequency frequencyValue.

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You can override the global frequency with local constraints, as described in Specifying SCOPE Constraints, on page 119. In the Synplify Pro tool, you can automatically generate clock constraints for your design instead of setting a global frequency. See Using Auto Constraints, on page 291 for details.
Global Frequency and Constraints Project View
Implementation Options->Constraints

2. To specify constraint files for an implementation, do one of the following:
Select Project->Implementation Options->Constraints. Check the constraint
files you want to use in the project.
From the Implementation Options->Constraints panel, you can also click to
add a constraint file.
With the implementation you want to use selected, click Add File in the
Project view, and add the constraint files you need.

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To create constraint files, see Specifying SCOPE Constraints, on page 119.
3. To remove constraint files from an implementation, do one of the following:
Select Project->Implementation Options->Constraints. Click off the checkbox
next to the file name.
In the Project view, right-click the constraint file to be removed and
select Remove from Project.
This removes the constraint file from the implementation, but does not delete it.
4. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK.
When you synthesize the design, the software compiles and maps the design using the options you set.
Specifying Result Options
This section shows you how to specify criteria for the output of the synthesis run.
1. Open the Implementation Options form by clicking the Implementation Options button or selecting Project->Implementation Options, and click the Implementation Results tab at the top.

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2. Specify the output files you want to generate.
To generate mapped netlist files, click Write Mapped Verilog Netlist or Write
Mapped VHDL Netlist.
To generate a vendor-specific constraint file for forward annotation,
click Write Vendor Constraint File. See For details on this report, see Constraint Checking Report, on page 270.of the Reference Manual, on page 56 for more information.
3. Set the directory to which you want to write the results.
4. Set the format for the output file. The equivalent Tcl command for scripting is project -result_format format.
You might also want to set attributes to control name-mapping. For details, refer to the appropriate vendor chapter in the Reference Manual.
5. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK.
When you synthesize the design, the software compiles and maps the design using the options you set.

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Specifying Timing Report Output
You can determine how much is reported in the timing report by setting the following options.
1. Selecting Project->Implementation Options, and click the Timing Report tab. 2. Set the number of critical paths you want the software to report.

3. Specify the number of start and end points you want to see reported in the critical path sections.
4. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK. When you synthesize the design, the software compiles and maps the design using the options you set.
Setting Verilog and VHDL Options
When you set up the Verilog and VHDL source files in your project, you can also specify certain compiler options.
Setting Verilog File Options
You set Verilog file options by selecting either Project->Implementation Options-> Verilog, or Options->Configure Verilog Compiler.

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1. Specify the Verilog format to use.
To set the compiler globally for all the files in the project, select
Project->Implementation Options->Verilog. If you are using Verilog 2001 or SystemVerilog, check the Reference Manual for supported constructs.
To specify the Verilog compiler on a per file basis, select the file in the
Project view. Right-click and select File Options. Select the appropriate compiler. The default Verilog file format for new projects is SystemVerilog.

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Chapter 4: Setting up a Logic Synthesis Project Setting Logic Synthesis Implementation Options
2. Specify the top-level module if you did not already do this in the Project view.
3. To extract parameters from the source code, do the following:
Click Extract Parameters. To override the default, enter a new value for a parameter.
The software uses the new value for the current implementation only. Note that parameter extraction is not supported for mixed designs.

4. Type in the directive in Compiler Directives, using spaces to separate the statements. You can type in directives you would normally enter with ‘ifdef and `define statements in the code. For example, ABC=30 results in the software writing the following statements to the project file:
set_option -hdl_define -set “ABC=30”
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5. In the Include Path Order, specify the search paths for the include commands for the Verilog files that are in your project. Use the buttons in the upper right corner of the box to add, delete, or reorder the paths.
6. In the Library Directories, specify the path to the directory which contains the library files for your project. Use the buttons in the upper right corner of the box to add, delete, or reorder the paths.
7. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK. When you synthesize the design, the software compiles and maps the design using the options you set.

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Chapter 4: Setting up a Logic Synthesis Project Setting Logic Synthesis Implementation Options
Setting VHDL File Options
You set VHDL file options by selecting either Project->Implementation Options->VHDL, or Options->Configure VHDL Compiler.

For VHDL source, you can specify the options described below.
1. Specify the top-level module if you did not already do this in the Project view. If the top-level module is not located in the default work library, you must specify the library where the compiler can find the module. For information on how to do this, see VHDL Panel, on page 200.
You can also use this option for mixed language designs or when you want to specify a module that is not the actual top-level entity for HDL Analyst displaying and LdOebugging in the schematic views. 2. For user-defined state machine encoding, do the following:
Specify the kind of encoding you want to use.

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Disable the FSM compiler.
When you synthesize the design, the software uses the compiler directives you set here to encode the state machines and does not run the FSM compiler, which would override the compiler directives. Alternatively, you can define state machines with the syn_encoding attribute, as described in Defining State Machines in VHDL, on page 308.
3. To extract generics from the source code, do this:
Click Extract Generic Constants. To override the default, enter a new value for a generic.
The software uses the new value for the current implementation only. Note that you cannot extract generics if you have a mixed language design.

4. To push tristates across process/block boundaries, check that Push Tristates is enabled. For details, see Push Tristates Option, on page 212in the Reference Manual.
5. Determine the interpretation of the synthesis_on and synthesis_off directives:
To make the compiler interpret synthesis_on and synthesis_off directives
like translate_on/translate_off, enable the Synthesis On/Off Implemented as Translate On/Off option.
To ignore the synthesis_on and synthesis_off directives, make sure that
this option is not checked. See translate_off/translate_on, on page 226 in the Reference Manual for more information.

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Specifying Attributes and Directives

6. Set other implementation options as needed (see Setting Logic Synthesis Implementation Options, on page 75 for a list of choices). Click OK.
When you synthesize the design, the software compiles and maps the design using the options you set.

Specifying Attributes and Directives

Attributes and directives are specifications that you assign to design objects to control the way your design is analyzed, optimized, and mapped.
Attributes control mapping optimizations and directives control compiler optimizations. Because of this difference, you must specify directives in the source code. This table describes the methods that are available to create attribute and directive specifications:

VHDL Verilog SCOPE Editor Constraints File

Attributes Yes Yes Yes Yes

Directives Yes Yes No No

It is better to specify attributes in the SCOPE editor or the constraints file, because you do not have to recompile the design first. For directives, you must compile the design for them to take effect.
If SCOPE/constraints file and the HDL source code are specified for a design, the constraints has priority when there are conflicts.
For further details, refer to the following:
· Specifying Attributes and Directives in VHDL, on page 91 · Specifying Attributes and Directives in Verilog, on page 92 · Specifying Attributes UsLiOng the SCOPE Editor, on page 93 · Specifying Attributes in the Constraints File, on page 97

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Specifying Attributes and Directives in VHDL
You can use other methods to add attributes to objects, as listed in Specifying Attributes and Directives, on page 90. However, you can specify directives only in the source code. There are two ways of defining attributes and directives in VHDL:
· Using the predefined attributes package
· Declaring the attribute each time it is used
For details of VHDL attribute syntax, see VHDL Attribute and Directive Syntax, on page 561in the Reference Manual.

Using the Predefined VHDL Attributes Package
The advantage to using the predefined package is that you avoid redefining the attributes and directives each time you include them in source code. The disadvantage is that your source code is less portable. The attributes package is located in installDirectory/lib/vhd/synattr.vhd.
1. To use the predefined attributes package included in the software library, add these lines to the syntax:
library synplify; use synplify.attributes.all;
2. Add the attribute or directive you want after the design unit declaration.
declarations ; attribute attribute_name of objectName : objectType is value ;
For example:
entity simpledff is port (q: out bit_vector(7 downto 0); d : in bit_vector(7 downto 0); clk : in bit);
attribute syn_noclockbuf of clk : signal is true;
For details of the syntax conventions, see VHDL Attribute and Directive Syntax, on page 561 in the Reference Manual.
3. Add the source file to the project.

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Specifying Attributes and Directives

Declaring VHDL Attributes and Directives
If you do not use the attributes package, you must redefine the attributes each time you include them in source code.
1. Every time you use an attribute or directive, define it immediately after the design unit declarations using the following syntax:
design_unit_declaration ; attribute attributeName : dataType ; attribute attributeName of objectName : objectType is value ;
For example:
entity simpledff is port (q: out bit_vector(7 downto 0); d : in bit_vector(7 downto 0); clk : in bit);
attribute syn_noclockbuf : boolean; attribute syn_noclockbuf of clk :signal is true;
2. Add the source file to the project.

Specifying Attributes and Directives in Verilog
You can use other methods to add attributes to objects, as described in Specifying Attributes and Directives, on page 90. However, you can specify directives only in the source code.
Verilog does not have predefined synthesis attributes and directives, so you must add them as comments. The attribute or directive name is preceded by the keyword synthesis. Verilog files are case sensitive, so attributes and directives must be specified exactly as presented in their syntax descriptions. For syntax details, see Verilog Attribute and Directive Syntax, on page 363in the Reference Manual.
1. To add an attribute or directive in Verilog, use Verilog line or block comment (C-style) syntax directly following the design object. Block comments must precede the semicolon, if there is one.
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Verilog Block Comment Syntax
/* synthesis attributeName = value */ /* synthesis directoryName = value */

Verilog Line Comment Syntax
// synthesis attributeName = value // synthesis directoryName = value

For details of the syntax rules, see Verilog Attribute and Directive Syntax, on page 363 in the Reference Manual. The following are examples:
module fifo(out, in) /* synthesis syn_hier = “hard” */;
2. To attach multiple attributes or directives to the same object, separate the attributes with white spaces, but do not repeat the synthesis keyword. Do not use commas. For example:
case state /* synthesis full_case parallel_case */;
3. If multiple registers are defined using a single Verilog reg statement and an attribute is applied to them, then the synthesis software only applies the last declared register in the reg statement. For example:
reg [5:0] q, q_a, q_b, q_c, q_d /* synthesis syn_preserve=1 */;
The syn_preserve attribute is only applied to q_d. This is the expected behavior for the synthesis tools. To apply this attribute to all registers, you must use a separate Verilog reg statement for each register and apply the attribute.

Specifying Attributes Using the SCOPE Editor
The SCOPE window provides an easy-to-use interface to add any attribute. You cannot use it for adding directives, because they must be added to the source files. (See Specifying Attributes and Directives in VHDL, on page 91 or Specifying Attributes and Directives in Verilog, on page 92). The following procedure shows how to add an attribute directly in the SCOPE window.
1. Start with a compiled design and open the SCOPE window. To add the attributes to an existing constraint file, open the SCOPE window by clicking on the existing file in the Project view. To add the attributes to a new file, click the SCOPE icon and click Initialize to open the SCOPE window.
2. Click the Attributes tab at the bottom of the SCOPE window.

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Specifying Attributes and Directives

You can either select the object first (step 3) or the attribute first (step 4).

3. To specify the object, do one of the following in the Object column. If you already specified the attribute, the Object column lists only valid object choices for that attribute.
Select the type of object in the Object Filter column, and then select an
object from the list of choices in the Object column. This is the best way to ensure that you are specifying an object that is appropriate, with the correct syntax.

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Drag the object to which you want to attach the attribute from the
RTL or Technology views to the Object column in the SCOPE window. For some attributes, dragging and dropping may not select the right object. For example, if you want to set syn_hier on a module or entity like an and gate, you must set it on the view for that module. The object would have this syntax: v:moduleName in Verilog, or v:library.moduleName in VHDL, where you can have multiple libraries.
Type the name of the object in the Object column. If you do not know
the name, use the Find command or the Object Filter column. Make sure to type the appropriate prefix for the object where it is needed. For example, to set an attribute on a view, you must add the v: prefix to the module or entity name. For VHDL, you might have to specify the library as well as the module name.
4. If you specified the object first, you can now specify the attribute. The list shows only the valid attributes for the type of object you selected. Specify the attribute by holding down the mouse button in the Attribute column and selecting an attribute from the list.

If you selected the object first, the choices available are determined by the selected object and the technology you are using. If you selected the attribute first, the available choices are determined by the technology.
When you select an attribute, the SCOPE window tells you the kind of value you must enter for that attribute and provides a brief description of the attribute. If you selected the attribute first, make sure to go back and specify the object.
5. Fill out the value. Hold down the mouse button in the Value column, and select from the list. You can also type in a value.

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Chapter 4: Setting up a Logic Sy

Documents / Resources

SYnOPSYS FPGA Synthesis Synplify Pro for Microsemi Edition [pdf] User Guide
FPGA Synthesis Synplify Pro for Microsemi Edition, Synthesis Synplify Pro for Microsemi Edition, Synplify Pro for Microsemi Edition, Pro for Microsemi Edition, Microsemi Edition, Edition

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User Manual

SYnOPSYS FPGA Synthesis Synplify Pro for Microsemi Edition User Guide

FPGA Synthesis Synplify Pro for Microsemi Edition

Specifications

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Product Usage Instructions

Chapter 1: Introduction

Scope of the Document

Getting Started

User Interface Overview

Chapter 2: FPGA Synthesis Design Flows

Chapter 3: Preparing the Input

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