SYnOPSYS FPGA Synthesis Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi

Synopsys FPGA Synthesis - Synplify Pro maka mbipụta Microsemi
bụ ngwa ọrụ zuru oke maka mmejuputa FPGA dị iche iche
atụmatụ emebere iji nyere ndị ọrụ aka n'ịkọwapụta mgbagha na imewe
aga.

Ntuziaka ojiji ngwaahịa

Isi nke 1: Okwu Mmalite

Isiakwụkwọ a na-enye nfeview nke Synopsys FPGA na
Ngwaahịa prototyping, Ngwa mmejuputa FPGA, yana Synopsys FPGA
Njirimara ngwaọrụ.

Oke akwụkwọ ahụ

Ntọala akwụkwọ ahụ gụnyere ozi na njirimara ngwaahịa
ma ezubere maka ndị ọrụ nwere mmasị na njikọ na imewe FPGA
aga.

Na-amalite

Iji malite iji ngwanro ahụ, malite ya na-eso nke enyere
ntuziaka ma rụtụ aka na ntuziaka onye ọrụ maka enyemaka.

Ihe nlebanya onye ọrụ gafereview

Mara onwe gị na interface ọrụ nke ọma
gaa site na njirimara ngwanrọ.

Isi nke 2: FPGA Synthesis Eserese Na-aga

Isiakwụkwọ a na-akọwapụta usoro nhazi ihe mgbagha maka FPGA
njikọ.

Isi nke 3: Ịkwadebe ntinye

Mụta ka esi eji Isi mmalite Asụsụ agwakọta Files na mmụba
Ngwakọta maka nkwadebe ntinye nke ọma.

Mara: Mara mmachi ọ bụla metụtara
site na iji Mgbakwunye Compiler.

FAQ

Ajụjụ: Enwere m ike ịmegharị akwụkwọ ahụ?

A: Ee, nkwekọrịta ikike na-enye ohere ịme nnomi maka ime
jiri naanị na njiri mara mma.

Ajụjụ: Kedu ka m ga-esi malite ngwa ngwa?

A: Rụtụ aka na ngalaba “ịmalite” n'Isi nke 1 nke
ntuziaka onye ọrụ maka nkọwa zuru ezu na ịmalite ngwa ngwa.

Ajụjụ: Gịnị bụ ndị echere maka ntuziaka onye ọrụ a?

A: Ntuziaka onye ọrụ bụ maka ndị nwere mmasị na FPGA
njikọ na imewe aga.

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Synopsys FPGA Synthesis
Synplify Pro maka mbipụta Microsemi
Ntuziaka onye ọrụ
Ọktoba 2014

Ozi nwebisiinka na ozi nwebisiinka
Nwebiisinka © 2014 Synopsys, Inc. Ikike niile echekwabara. Akụrụngwa na akwụkwọ nwere ozi nzuzo na nke nwe ya bụ ihe onwunwe Synopsys, Inc. Enyere ngwanro na akwụkwọ n'okpuru nkwekọrịta ikike, enwere ike iji ya ma ọ bụ depụtaghachi ya naanị dịka usoro nke nkwekọrịta ikike siri dị. Enweghị akụkụ nke ngwanrọ na akwụkwọ enwere ike ịmegharị, bufee, ma ọ bụ tụgharịa asụsụ, n'ụdị ọ bụla ma ọ bụ n'ụzọ ọ bụla, eletrọnịkị, nrụzi, akwụkwọ ntuziaka, ngwa anya, ma ọ bụ nke ọzọ, na-enweghị ikike ederede tupu Synopsys, Inc., ma ọ bụ dị ka nkwekọrịta ikike nyere.
Ikike idetu akwụkwọ
Nkwekọrịta ikike na Synopsys na-enye ndị nwe ikikere ikike ịme nnomi akwụkwọ maka naanị ime ya.
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"Ejigharịrị akwụkwọ a site na ikike nke Synopsys, Inc., maka iji naanị __________________________________________ na ndị ọrụ ya. Nke a bụ nọmba nnomi __________."
Nkwupụta njikwa ebe
Data teknụzụ niile dị n'akwụkwọ a bụ n'okpuru iwu njikwa mbupụ nke United States of America. Amachibidoro ikpughere ụmụ amaala obodo ọzọ megidere iwu United States. Ọ bụ ọrụ onye na-agụ ya ikpebi iwu ndị dị na ịgbaso ha.
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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Nkwuputa
SYNOPSYS, INC., na ndị nyere ya ikike enweghị ikike n'ụdị ọ bụla, Kpọpụtaara ma ọ bụ metụtara, gbasara ihe a, gụnyere, mana ọnweghị oke na, ikike akwadoro maka ịzụ ahịa na ohere.
Edebara aha ụghalaahịa (®)
Synopsys, AEON, AMPS, Astro, Nkà na ụzụ Na-ewepụta Omume, Cadabra, CATS, Asambodo, CHIPit, CoMET, CODE V, Design Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Global Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, HSPICE, LightTool, LeToolsTes,Model NanoSim, NOVeA, OpenVera, ORA, PathMill, Physical Compiler, PrimeTime, SCOPE, Nanị Nsonaazụ Ka Mma, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory Sistemu, Syndicated, Synplicity, Synplicity logo, Synplify, Synplify Pro, Optimment Constraint, OptimMAX Constraint VCS, Vera, na YIELDirector bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Synopsys, Inc.
Akara ahia (TM)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Ọkachamara, DC Ọkachamara, DC Ultra, Design Analyzer, Design Max, DirectPower D. Nchọpụta, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Technology Optimization Technology, High- Performance ASIC Prototyping System, HSIMplus, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Intelli, Jupiter, Jupiter-DP, Liberty Jupiter-DP, Jupiter-DP Libra-Passport, Ọbá akwụkwọ Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Saccoi-Rippled. SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, na Worksheet Buffer bụ ụghalaahịa nke Synopsys, Inc.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Akara ọrụ (sm)
MAP-in, SVP Café, na TAP-in bụ akara ọrụ Synopsys, Inc. SystemC bụ ụghalaahịa nke Open SystemC Initiative ma ejiri ya n'okpuru ikike. ARM na AMBA bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke ARM Limited. Saber bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke SabreMark Limited Partnership ma ejiri ya n'okpuru ikike. Ngwaahịa niile ma ọ bụ aha ụlọ ọrụ nwere ike ịbụ ụghalaahịa nke ndị nwe ha.
E bipụtara ya na USA October 2014

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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

ọdịnaya

Isi nke 1: Okwu Mmalite
Synopsys FPGA na Prototyping Ngwaahịa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ngwa 16 FPGA Mmejuputa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synopsys Atụmatụ Ngwá Ọrụ FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Oke akwụkwọ ahụ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ntọala akwụkwọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Ndị na-ege ntị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Na-amalite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Malite ngwa ngwa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Inweta Enyemaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ihe nlebanya onye ọrụ gafereview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Isi nke 2: FPGA Synthesis Eserese Na-aga
Usoro nhazi usoro mgbagwoju anya. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Isi nke 3: Ịkwadebe ntinye
Ịtọlite isi iyi HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ịmepụta isi iyi HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Iji Editọ Enyemaka Ọdịnihu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Na-enyocha isi iyi HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Edezi isi iyi HDL Files na Onye Nhazi Ederede arụnyere . . . . . . . . . . . . . . . . . . . . 35 Ịtọ ntọala Mmasị Ohere edezi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Iji ihe ndezi ederede mpụga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Iji ndọtị ọba akwụkwọ maka Verilog Library Files . . . . . . . . . . . . . . . . . . . . . . . 42
Iji Isi mmalite Asụsụ agwakọta Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Iji Mgbakwunye Mgbakọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Oke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Iji Structural Verilog Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Oke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-arụ ọrụ na Constraint Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Mgbe a ga-eji mmachi Files n'elu Source Code. . . . . . . . . . . . . . . . . . . . . . . . 53 Iji edezi ederede maka mmachi Files (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Ntuziaka Syntax maka mmachi Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Nyochaa mmachi Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic
Ịtọlite Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Ịmepụta oru ngo File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Imepe oru ngo dị adị File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Ime mgbanwe na oru ngo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Ntọala oru ngo View Gosipụta Mmasị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Na-emelite Verilog gụnyere ụzọ na oru ngo ochie Files . . . . . . . . . . . . . . . . . . . . 65
Ijikwa Project File Ọchịchị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Ịmepụta nchekwa nchekwa omenala. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Na-emegharị nchekwa nchekwa ọrụ omenala. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Na-emegharị omenala Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Ịtọlite mmejuputa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Na-arụ ọrụ na ọtụtụ mmejuputa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Ịtọpụta Synthesis Logic Nhọrọ Mmejuputa . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ịtọ ngwaọrụ Nhọrọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Ịtọlite nhọrọ kachasị mma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Na-akọwapụta ugboro na mmachi zuru ụwa ọnụ Files . . . . . . . . . . . . . . . . . . . . . . 80 Na-akọwapụta nhọrọ nsonaazụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Na-akọwapụta mmepụta akụkọ oge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Ịtọ ntọala Verilog na VHDL Nhọrọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Na-akọwapụta àgwà na ntuziaka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Na-akọwapụta njirimara na ntuziaka na VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Na-akọwapụta njirimara na ntuziaka na Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . 92 Na-akọwapụta njirimara iji SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . 93 Na-akọwapụta njirimara na mmachi File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Na-achọ Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ịmata ihe Files ka ịchọọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Nzacha nke Files ka ịchọọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Na-amalite ọchụchọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 nsonaazụ ọchụchọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LO
Ịdebe akwụkwọ Files na Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Dekọọ ọrụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Un-Archive a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Detuo ihe oru ngo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Isi nke 5: Na-akọwa ihe mgbochi
Iji SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ịmepụta ihe mgbochi na SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Ịmepụta ihe mgbochi na FDC Template Command. . . . . . . . . . . . . . . . 116
Na-akọwapụta mmachi SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Ịbanye na dezie ihe mgbochi oke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Ịtọ elekere na mmachi ụzọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Na-akọwa mmachi ntinye na mmepụta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Na-akọwapụta Ụdị Pad I/O Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Iji TCL View nke SCOPE GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Ntuziaka maka ntinye na ndezi mmachi. . . . . . . . . . . . . . . . . . . . . . . . 127
Na-akọwapụta ewepu oge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Na-akọwapụta site na/gaa/site na isi ihe maka ewepu oge. . . . . . . . . . . . . . . . . 130 Na-akọwa ụzọ ọtụtụ okirikiri. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Na-akọwa Ụzọ Ụgha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Ịchọta ihe na Tcl chọta na gbasaa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Na-akọwapụta ụkpụrụ ọchụchọ maka ịchọta Tcl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Nnụcha Tcl Chọta nsonaazụ na -filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Iji Tcl Chọta Iwu iji kọwaa mkpokọta. . . . . . . . . . . . . . . . . . . . . 138 Iji Tcl gbasaa Iwu iji kọwaa mkpokọta. . . . . . . . . . . . . . . . . . 140 Na-elele Tcl chọta na gbasaa nsonaazụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Iji Tcl chọta na gbasaa na Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Iji mkpokọta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Tụnyere usoro maka ịkọwa mkpokọta. . . . . . . . . . . . . . . . . . . . . . . 144 Ịmepụta na iji mkpokọta SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Mepụta mkpokọta site na iji iwu Tcl. . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Viewing na iji iwu Tcl jikwaa mkpokọta. . . . . . . . . . . . . . . 150
Na-atụgharị SDC ka FDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Iji SCOPE Editor (Legacy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Ịbanye ma na-edezi ihe mgbochi SCOPE (Ihe nketa) . . . . . . . . . . . . . . . . . . . . . 157 Na-akọwapụta mmachi oge oge SCOPE (Ihe nketa) . . . . . . . . . . . . . . . . . . . . . . . 159 Ịbanye mmachi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Ịtọ elekere na mmachi ụzọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 na-akọwa elekere. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Na-akọwa mmachi ntinye na mmepụta (ihe nketa) . . . . . . . . . . . . . . . . . . . . . . . 169 Na-akọwa ụzọ ụgha (Ihe nketa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 6: Mmekọrịta na nyocha nsonaazụ ya
Ịmepụta atụmatụ gị. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Njikọ mgbagha na-agba ọsọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Iji nyocha ọhụụ maka njikwa ọrụ. . . . . . . . . . . . . . . . . . . . . . 174
Na-enyocha ndekọ File Nsonaazụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Viewna-arụ ọrụ na Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Ịnweta akụkọ akọwapụtara ngwa ngwa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Ịnweta rịzọlt tere aka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Nyochaa nsonaazụ Iji Ndekọ File Akụkọ . . . . . . . . . . . . . . . . . . . . . . . . . 189 Iji windo nche. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Nyochaa ojiji akụrụngwa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Ijikwa ozi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Nyochaa nsonaazụ na ozi ahụ Viewihe . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Ozi nzacha na ozi ahụ Viewihe . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Ozi nzacha site na ahịrị iwu. . . . . . . . . . . . . . . . . . . . . . . . . . 197 na-eji ederede Tcl na-enyocha ozi akpaaka. . . . . . . . . . . . . . . . . . . . . . . . 198 Ndekọ File Njikwa ozi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ijikwa ịdọ aka ná ntị. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Iji Gaa n'ihu na Njehie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Iji Gaa n'ihu na mperi maka nchịkọta okwu mkpokọta. . . . . . . . . . . . . . . . . . . 203
Isi nke 7: Nyochaa na HDL Analyst na FSM Viewer
Na-arụ ọrụ na Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Ịdịiche n'etiti HDL Analyst Views . . . . . . . . . . . . . . . . . . . . . . . . 209 Na-emeghe Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 ViewNgwongwo ihe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Ịhọrọ ihe na RTL/Technology Views . . . . . . . . . . . . . . . . . . . . . . . 215 Na-arụ ọrụ na Multisheet Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Na-aga n'etiti Viewdị na mpio atụmatụ . . . . . . . . . . . . . . . . . . . . . . . 218 Ịtọ ntọala View Mmasị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Ijikwa Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Ịchọgharị nhazi nhazi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Nchọgharị imewe na-eme njem na ihe nchọgharị hierarchy. . . . . . . . . . . . . . . . 222 Na-enyocha ọkwa ọkwa ihe site na ịkwanye/ịkpọpụta . . . . . . . . . . . . . . . . . . . . . . . 223 Na-enyocha usoro ihe omume nke ihe ngosi . . . . . . . . . . . . . . . . . . . 228
Ịchọta Ihe . . . . . . . . . . . . .LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Nchọgharị ka ịchọta ihe na HDL Analyst Views . . . . . . . . . . . . . . . . . . . . . . . 230 Iji Chọta maka Ọchụchọ Ọchịchọ na Amachibidoro . . . . . . . . . . . . . . . . . . . . 232 Iji Wildcards na Chọta Iwu. . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-ejikọta Chọta na nzacha iji mezie ọchụchọ. . . . . . . . . . . . . . . . . . . . . . 240 Iji Chọta ka Chọọ Netlist mmepụta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Ntugharị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing n'ime RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 243 Crossprobing sitere na RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 244 Nlegharị anya site na windo nchịkọta akụkọ ederede. . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Na-agafe na windo Tcl Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Ntugharị si na FSM Viewihe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Iji Ngwá Ọrụ Analyst HDL nyochaa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 ViewNhazi nhazi na ọnọdụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Nzacha nhazi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Mgbasa Pin na Net Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Na-agbasawanye na Viewnjikọ njikọ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Nhazi nhazi nke na-adaba adaba. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 ibelata ojiji ebe nchekwa ka ị na-enyocha atụmatụ. . . . . . . . . . . . . . . . . . . 267
Iji FSM Viewihe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Isi nke 8: Nyochaa Oge
Na-enyocha oge na Schematic Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 ViewOzi oge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Na-akọwapụta ozi oge n'ime atụmatụ Views . . . . . . . . . . . . . . . . . . 275 Na-enyocha Osisi elekere na RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 ViewỤzọ Dị Mkpa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Ijikwa Slack Na-adịghị mma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Iji STA na-emepụta akụkọ oge omenala. . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Iji ihe mgbochi imewe nyocha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ihe ngosi 284 maka iji ihe mgbochi imewe nyocha. . . . . . . . . . . . . . . . . . . . . . 285 Ịmepụta ADC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Iji aha ihe nke ọma na adc File . . . . . . . . . . . . . . . . . . . . . . . . . 290
Iji Mmachi akpaaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Nsonaazụ nke mmachi akpaaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Isi nke 9: Inweta ihe dị elu
Na-akọwa Igbe ojii maka Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 igbe ojii ozugbo na I/Os na Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . 298 igbe ojii ozugbo na I/Os na VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 300 na-agbakwụnye ihe mgbochi oge nke igbe ojii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Na-agbakwụnye àgwà igbe ojii ndị ọzọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta igwe steeti maka Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Na-akọwa igwe steeti na Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Na-akọwa igwe steeti na VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Na-akọwapụta FSM nwere njirimara na ntuziaka. . . . . . . . . . . . . . . . . . . . . . . . 309
Na-akọwapụta FSM dị mma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Ntinye RAM akpaaka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Gbochie RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 RAM àgwà. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Inferring Block Ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Na-amalite RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 na-ebido RAM na Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 na-ebido RAM na VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Isi nke 10: Na-akọwapụta nkwalite ọkwa-ichepụta
Ndụmọdụ maka nkwalite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ndụmọdụ kachasị mma 330. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Na-ebuli elu maka Mpaghara. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Na-ebuli elu maka oge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Ịla ezumike nká . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Ịchịkwa oge ezumike. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 ezumike nka Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 mkpesa ezumike nka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Olee otú ezumike nka si arụ ọrụ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Na-echekwa ihe ka emebere ya nke ọma. . . . . . . . . . . . . . . . . . . . . . . . . . 342 Iji syn_keep maka Nchekwa ma ọ bụ mmegharị . . . . . . . . . . . . . . . . . . . . . . . 343 Ịchịkwa ọkwa dị elu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Ichekwa usoro ọchịchị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Na-ebuli Fanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Ịtọba oke fanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Ịchịkwa nchikota na mmegharị . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Ịkekọrịta akụrụngwa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Ịtinye I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Igwe igwe steeti na-ebuli elu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Na-ekpebi mgbe a ga-ebuli igwe steeti. . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Na-agba ọsọ FSM Compiler LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Na-agba ọsọ FSM Explorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Ịtinye nyocha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta nyocha na koodu isi mmalite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Na-agbakwunye njirimara nyocha na mmekọrịta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Isi nke 11: Na-arụ ọrụ na mkpokọta mkpokọta
Isi ihe nchịkọta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Advantages of Compile Point Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Isi ihe nchịkọta akwụkwọ ntuziaka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Isi ihe mkpokọta akwụgoro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ụdị ntụpọ 369 chịkọtara. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Isi ihe nchịkọta mkpokọta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Mkpokọta ihe mgbochi Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Interface Logic Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Interface oge maka mkpokọta mkpokọta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Nchịkọta Ihe Nchịkọta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Mmụba Mgbakwunye Mgbakọ Nchịkọta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 n'ihu-nkọwa nke ihe mgbochi oge mkpokọta . . . . . . . . . . . . . . . . 384
Ihe nchịkọta nchịkọta Synthesizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Akwụkwọ ntuziaka chịkọta ọnụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Ịmepụta mmachi ọkwa dị elu File maka ihe nchịkọta . . . . . . . . . . . . . . . . 388 Na-akọwapụta ihe nchịkọta akwụkwọ ntuziaka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Ịtọ mmachi n'ọkwa chịkọta . . . . . . . . . . . . . . . . . . . . . . . . 391 Na-enyocha Nsonaazụ Nchịkọta Nchịkọta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Iji ihe chịkọta ọnụ na atụmatụ ndị ọzọ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Na-ejikọta ihe nchịkọta na ọtụtụ nhazi. . . . . . . . . . . . . . . . . . . . . . . 396
Na-emeghari na-abawanye. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Na-emegharị ihe nchịkọta ọnụ na-abawanye. . . . . . . . . . . . . . . . . . . . . . . . . 397
Isi nke 12: Na-arụ ọrụ na ntinye IP
Iji SYNCore na-emepụta IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Na-akọwapụta FIFO na SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Na-akọwapụta RAM na SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Na-akọwapụta Byte-Enyere RAM na SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . 416 Na-akọwapụta ROM na SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Na-akọwapụta Adder/Mmepụta nwere SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Na-akọwapụta Counters nwere SYNCore. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Synopsys FPGA IP Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 karịrịview nke Synopsys FPGA IP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Izo ya ezo na ntupu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
Na-arụ ọrụ na IP ezoro ezo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-ezochi adreesị IP gị. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Na-ezobe IP na encryptP1735.pl Script. . . . . . . . . . . . . . . . . . . . . . . . . 448 Iji ederede zoro ezo IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Na-akọwapụta usoro mmepụta edemede. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Na-akwado ngwugwu IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Iji Hyper Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Iji Hyper Source maka Prototyping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Iji Hyper Source maka atụmatụ IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 eriri eriri site na nhazi ọkwa nke IP. . . . . . . . . . . . . . . 461
Isi nke 13: Usoro kachasị mma maka nrụpụta
Iji Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Ọnọdụ ogbe na-agba ọsọ na oru ngo File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 na-agba ọsọ mode na Tcl Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Ikikere kwụ n'ahịrị. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Na-arụ ọrụ na Tcl Scripts na iwu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Iji Tcl Iwu na Scripts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Ịmepụta edemede ọrụ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Ntọala ọnụọgụgụ nke ọrụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Ịmepụta Tcl Synthesis Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Iji Tcl mgbanwe iji nwalee ugboro elekere dị iche iche. . . . . . . . . . . . . . . . . . 476 Iji Tcl mgbanwe iji nwalee ọtụtụ teknụzụ ebumnuche. . . . . . . . . . . . . . . . . 478 Na-eji edemede eme ihe n'okpuru. . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Eji synhooks.tcl na-eme njem na-akpaghị aka. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Isi nke 14: Iji Multiprocessing
Enwere otutu ihe eji eme ihe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Ịtọ ntọala kacha arụ ọrụ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Iji ikike. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Isi nke 15: Na-ebuli maka atụmatụ Microsemi
Na-ebuli atụmatụ Microsemi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Iji igbe ojii Microsemi akọwapụtagoro mbụ. . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Iji Smartgen Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Na-arụ ọrụ na Radhard Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Na-akọwapụta syn_radhardlevel na koodu isi mmalite. . . . . . . . . . . . . . . . . . . . . . . 490 LO
Isi nke 16: Na-arụ ọrụ na mmepụta synthesis
Nyefee ozi na ngwa P&R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta ebe Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Na-akọwapụta ebe maka ọdụ ụgbọ mmiri Microsemi. . . . . . . . . . . . . . . . . . . . . . . . . 495 Na-akọwapụta nnukwu na ntinye aha aha. . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Na-emepụta mmepụta akọwapụtara nke onye na-ere ahịa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 na-echepụta mmepụta nye onye na-ere gị. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Ịhazi usoro Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Isi nke 17: Na-arụ ọrụ Post-Synthesis na-agba ọsọ
Na-agba ọsọ P&R na-akpaghị aka mgbe Synthesis gachara. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Na-arụ ọrụ na ngwaọrụ njirimara . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 na-amalite site na Synplify Pro Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Ijikwa nsogbu na mwepụta Identify . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Iji Ngwa njirimara . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Iji chịkọta ihe na ngwa njirimara. . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Na-eji ngwa VCS eme ihe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

ISI NKE 1
Okwu mmalite
Okwu mmeghe a na ngwanrọ Synplify Pro® na-akọwa ihe ndị a:
· Synopsys FPGA na Prototyping Products, na ibe 16 · Oke akwụkwọ, na ibe 21 · Mmalite, na ibe 22 · Onye ọrụ Interface Over.view, na ibe 24

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 1: Okwu Mmalite

Synopsys FPGA na Ngwaahịa Prototyping

Synopsys FPGA na Ngwaahịa Prototyping
Ọgụgụ na-egosi Synopsys FPGA na Prototyping ezinụlọ nke ngwaahịa.

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Synopsys FPGA na Ngwaahịa Prototyping

Isi nke 1: Okwu Mmalite

Ngwa mmejuputa FPGA
Ngwaahịa Synplify Pro na Synplify Premier bụ ngwaọrụ njikọ RTL emebere maka FPGAs (ụdị ọnụ ụzọ ámá mmemme) na CPLDs (ngwaọrụ mgbagwoju anya nwere ike ime).

Synplify Pro Synthesis Software
Ngwanrọ njikọ Synplify Pro FPGA bụ ọkọlọtọ ụlọ ọrụ de facto maka imepụta atụmatụ FPGA dị elu yana ọnụ ahịa dị oke ọnụ. Ya pụrụ iche
Algọridim na-ewepụta omume Synthesis Technology® (BEST), rụọ ọrụ
nkwalite ọkwa dị elu tupu ejikọta koodu RTL n'ime ezi uche FPGA. Ụzọ a na-enye ohere maka nkwalite dị elu n'ofe FPGA, oge ọsọ ọsọ, na ike ijikwa atụmatụ buru ibu. Software Synplify Pro na-akwado VHDL kachasị ọhụrụ na asụsụ Verilog gụnyere SystemVerilog na VHDL 2008. Ngwá ọrụ bụ teknụzụ na-adabere na ya na-enye ohere ịmegharị ngwa ngwa n'etiti ngwaọrụ FPGA na ndị na-ere ahịa site na otu ọrụ nhazi.

Synplify Premier Synthesis Software
Ọrụ Synplify Premier bụ ihe nrụpụta nke ngwa Synplify Pro, na-enye mmejuputa FPGA kachasị na gburugburu ebe nbipu. Ọ gụnyere ngwa na teknụzụ zuru oke maka ndị na-emepụta FPGA dị elu, ma na-ejekwa ozi dị ka injin njikọ maka ndị na-emepụta ASIC na-ezubere otu ụdị dabere na FPGA.
Ngwaahịa Synplify Premier na-enye ma ndị na-emepụta FPGA na ndị na-emepụta ASIC na-elekwasị anya n'otu FPGA na usoro kachasị mma nke mmejuputa nhazi na nbipu. N'akụkụ mmebe imewe, ọ gụnyere ọrụ maka mmechi oge, nkwenye mgbagha, ojiji IP, ndakọrịta ASIC, yana mmejuputa DSP, yana njikọta siri ike na ngwa ndị na-ere azụ FPGA. N'akụkụ mgbagha, ọ na-enye maka nkwenye n'ime sistemụ nke FPGA nke na-eme ka usoro nbipu dị ngwa ngwa, ma gụnyekwara usoro ngwa ngwa na agbakwunyere maka ịchọta nsogbu imewe na-adịghị ahụkebe.

Synopsys Njirimara Ngwa Ngwa FPGA
Tebụl a na-amata ọdịiche dị n'etiti isi ọrụ dị na Synplify Pro, Synplify, Synplify Premier, na Synplify Premier na ngwaahịa atụmatụ atụmatụ.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 1: Okwu Mmalite

Synopsys FPGA na Ngwaahịa Prototyping

Synplify Synplify Pro

Arụmọrụ

Synthesis Na-ewepụta Omume

Technology® (BESTTM)

Isi/IP nke ndị na-ere ere

Nkwado (ụfọdụ teknụzụ)

FSM Compiler

FSM Explorer

Ntugharị elekere gated

Debanye aha Pipelining

Debanye aha ezumike nka

Ntinye mmachi SCOPE®

Atụmatụ ntụkwasị obi dị elu

Ebe-na ụzọ agbakwunyere

Nyocha

HDL Analyst®

Nhọrọ

Nyocha oge

Ntụtu aka ruo n'isi

FSM Viewer

Nlegharị anya

Ihe Okike Nchọpụta

Identify® Instrumentor

Chọpụta Debugger

Nyocha ike (SAIF)

Nhazi anụ ahụ

Atụmatụ imewe File

Ọrụ ezi uche na mpaghara

Mekọrịta Premier
x
x
mmnweewe
xx
xxxxx

Synplify Premier DP
x
x
mmnweewe
xx
xxxxx
xx

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Synopsys FPGA na Ngwaahịa Prototyping

Isi nke 1: Okwu Mmalite

Ntụle mpaghara na ike mpaghara Pin ọrụ mmapụta anụ ahụ Synthesis Physical Analyst Synopsys DesignWare® Foundation Library Runtime Hierarchical Design emelitere njikarịcha ngwa ngwa Synthesis Multiprocessing Compile on Error Team Design Mixed Language Design Compile Points Hierarchical Design True Batch Mode (naanị ikike ịnya ụgbọ mmiri GUI) P&R Back-annotation of P&R Data Formal Verification

Synplify Synplify Pro

xxxx

–

Chọpụta njikọta

Oke

Mekọrịta Premier
xxx
xxxx
xxxx
x
x Usoro njikọ mgbagha x

Synplify Premier DP
x
xxxx
xxxx
xxxx
x
xx Logic njikọ mode
x

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 1: Okwu Mmalite

Synopsys FPGA na Ngwaahịa Prototyping

Nkọwa azụ nke P&R Data Design Environment Text Editor View Lelee windo ozi mpio Tcl Window Ọtụtụ mmejuputa onye na-ere teknụzụ Nkwado Ngosipụta atụmatụ oge ọjirija chịkọta ihe ngbanwe mgbanwe elekere gated na mperi.

Synplify Synplify Pro

Mekọrịta Premier
xxxxx ahọpụtara
xxxx

Synplify Premier DP
x
xxxxx ahọpụtara
xxxx

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Oke akwụkwọ ahụ

Isi nke 1: Okwu Mmalite

Oke akwụkwọ ahụ
Ndị na-esonụ kọwara obosara akwụkwọ a na ndị e bu n'obi na-ege ntị.

Ntọala akwụkwọ
Ntuziaka onye ọrụ bụ akụkụ nke nhazi akwụkwọ nke gụnyere akwụkwọ ntuziaka na nkuzi. Ezubere ya maka iji ya na akwụkwọ ndị ọzọ dị na nhazi ahụ. Ọ na-elekwasị anya n'ịkọwa otu esi eji sọftụwia FPGA Synopsys iji rụzuo ọrụ ndị a na-ahụkarị. Nke a pụtara ihe ndị a:
· Ntuziaka onye ọrụ na-akọwa naanị nhọrọ achọrọ iji rụọ ọrụ ndị a na-ahụkarị
kọwara na ntuziaka. Ọ naghị akọwa iwu na nhọrọ ọ bụla dị. Maka nkọwa zuru oke nke nhọrọ iwu yana syntax niile, rụtụ aka na Interface Overview isi na akwụkwọ ntuziaka Synopsys FPGA Synthesis Reference.
· Ntuziaka onye ọrụ nwere ozi dabere na ọrụ. Maka mmebi nke
otú e si hazie ozi, lee Inweta Enyemaka, na ibe 22.

Ndị na-ege ntị
Ngwa ngwanrọ Synplify Pro bụ maka onye nrụpụta sistemu FPGA. A na-eche na ị maara ihe ndị a:
· Nhazi nhazi · RTL · FPGA · Verilog/VHDL

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 1: Okwu Mmalite

Na-amalite

Na-amalite
Akụkụ a na-egosi gị otu esi amalite na sọftụwia njikọ Synopsys FPGA. Ọ na-akọwa isiokwu ndị a, mana ọ naghị edochi ozi dị na ntuziaka nwụnye gbasara inye ikike na nwụnye:
· Malite ngwa ngwa, na ibe 22 · Inweta enyemaka, na ibe 22

Ịmalite ngwa ngwa
1. Ọ bụrụ na imebeghị nke a, wụnye Synopsys FPGA synthesis software dịka ntuziaka nrụnye siri dị.
2. Malite software.
Ọ bụrụ na ị na-arụ ọrụ n'elu ikpo okwu Windows, họrọ
Mmemme-> Synopsys-> ụdị ngwaahịa sitere na bọtịnụ Malite.
Ọ bụrụ na ị na-arụ ọrụ n'elu ikpo okwu UNIX, pịnye nke kwesịrị ekwesị
iwu n'ahịrị iwu:
synplify_pro
· Iwu na-amalite njikọ ngwá ọrụ, na-emepe Project window. Ọ bụrụ
ị na-agba ọsọ software na mbụ, mpio na-egosiputa gara aga oru ngo. Maka ozi ndị ọzọ gbasara interface ahụ, lee Onye ọrụ Interface Overview isi nke akwụkwọ ntuziaka.

Inweta Enyemaka
Tupu ịkpọọ nkwado Synopsys, lelee ozi edere ede. Ị nwere ike nweta ozi ahụ n'ịntanetị site na menu enyemaka, ma ọ bụ rụtụ aka na ụdị PDF. Tebụl na-esonụ na-egosi gị otu esi ahazi ozi ahụ.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-amalite
Maka enyemaka na… Iji atụmatụ ngwanrọ Otu esi…
Ozi mgbaba
Ozi mperi Ịnye ikike Àmà na ntụziaka atụmatụ Synthesis Njirimara asụsụ na syntax Tcl syntax Tcl njikọ iwu mmelite ngwaahịa.

Isi nke 1: Okwu Mmalite
Rụtụ aka na… Synopsys FPGA Synthesis ntuziaka onye ọrụ Synopsys FPGA Synthesis ntuziaka onye ọrụ, ndetu ngwa na nkwado ahụ. web saịtị Synopsys FPGA Synthesis ntuziaka onye ọrụ, ndetu ngwa na nkwado web Enyemaka saịtị n'ịntanetị (họrọ Enyemaka->ozi njehie) Synopsys SolvNet Websaịtị Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Online enyemaka (họrọ Enyemaka->Tcl Enyemaka) Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference ManualWeb iwu menu)

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 1: Okwu Mmalite

Ihe nlebanya onye ọrụ gafereview

Ihe nlebanya onye ọrụ gafereview
Onye ọrụ interface (UI) nwere windo bụ isi, nke a na-akpọ Project view, na windo pụrụ iche ma ọ bụ views maka ọrụ dị iche iche. Maka nkọwa gbasara njirimara nke ọ bụla, lee Isi nke 2, Interface User karịrịview nke akwụkwọ ntuziaka Synopsys FPGA Synthesis Reference.

Synplify Pro Interface

Ogwe bọtịnụ

Toolbars Project view

Ọnọdụ

Nsonaazụ mmejuputa view

Taabụ iji nweta views

Tcl Script/Ozi Ohere LO

Lelee windo

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

ISI NKE 2
FPGA Synthesis imewe na-aga
Isiakwụkwọ a na-akọwa Flow Nrụpụta Ihe Logic Synthesis, na ibe 26.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 2: FPGA Synthesis Eserese Na-aga

Usoro nhazi usoro mgbagha

Ngwa Synopsys FPGA na-emepụta mgbagha site na ibu ụzọ chịkọta isi iyi RTL n'ime usoro mgbagha na-adabere na teknụzụ, wee na-ebuli ma na-esepụta echiche ahụ na akụrụngwa ndị akọwapụtara teknụzụ. Mgbe njikọ mgbagha gasịrị, ngwá ọrụ ahụ na-ewepụta netlist akọwapụtara nke onye na-ere ahịa na mmachi. file nke ị nwere ike iji dị ka ntinye na ngwaọrụ ebe-na ụzọ (P&R).
Ọnụọgụ na-esonụ na-egosi usoro na ngwa ọrụ ndị e ji eme njikọ uche na ụfọdụ n'ime isi ntinye na ntinye. Ị nwere ike iji ngwanrọ Synplify Pro maka usoro a. Nyocha oge mmekọrịta bụ nhọrọ. Ọ bụ ezie na ntinye ahụ na-egosi njedebe onye na-ere ahịa files dị ka ntinye aka ozugbo na ngwa P&R, ị ga-agbakwunye ndị a files na njikọ njikọ maka oge igbe ojii.

Ngwa FPGA Synopsys

RTL

Mkpokọta RTL

FDC

Njikọ uche

Ngụkọta netlist arụkọtara ọnụ na-egbochi mmachi ndị na-ere ahịa
Ngwaọrụ na-ere ere
Ebe & Ụzọ

Usoro njikọ mgbagha

N'ihi na a imewe eruba na nzọụkwụ-site-nzọụkwụ ntuziaka dabeere kpọmkwem imewe

data, budata nkuzi si na websaịtị. Usoro ndị a na-achịkọta

usoro maka synthesizing imewe, nke na-egosikwa na

ọnụ ọgụgụ na-esote.

1. Mepụta oru ngo.

2. Tinye isi iyi files na oru ngo.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Usoro nhazi usoro mgbagha

Isi nke 2: FPGA Synthesis Eserese Na-aga

3. Tọọ àgwà na ihe mgbochi maka imewe.
4. Tọọ nhọrọ maka mmejuputa atumatu na igbe okwu mmejuputa iwu.
5. Pịa ọsọ na-agba ọsọ mgbagha njikọ.
6. Nyochaa nsonaazụ ya, jiri ngwaọrụ dị ka log file, HDL Analyst schematic views, windo ozi na windo nche.
Mgbe ịmechara nhazi ahụ, ị nwere ike iji mmepụta files iji ngwaọrụ ndị na-ere ahịa na-agba ọsọ ebe-na ụzọ wee mejuputa FPGA.
Ọnụ ọgụgụ na-esonụ na-edepụta usoro ndị bụ isi na mgbaba:

Mepụta Project
Tinye Isi Iyi Files
Tọọ mmachi
Tọọ Nhọrọ
Gbaa ngwa ngwa
Nyochaa Nsonaazụ Ọnweghị ebumnuche enwetara?
Ee Ebe na Ụzọ

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 2: FPGA Synthesis Eserese Na-aga

Usoro nhazi usoro mgbagha

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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

ISI NKE 3
Na-akwado ntinye
Mgbe ị synthesize a imewe, ị kwesịrị ịtọ abụọ ụdị fileihe: HDL files na-akọwa gị imewe, na oru ngo files iji jikwaa imewe. Isiakwụkwọ a na-akọwa usoro iji guzobe ndị a files na oru ngo. Ọ na-agụnye ihe ndị a:
· Ịtọlite isi iyi HDL Files, na ibe 30 · Iji Mixed Language Source Files, na ibe 44 · Iji Mgbakwunye Compiler, na ibe 49 · Iji Structural Verilog Flow, na ibe 51 · Ịrụ ọrụ na mgbochi Files, na ibe 53

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

Ịtọlite isi iyi HDL Files
Akụkụ a na-akọwa otu esi edozi isi mmalite gị files; oru ngo file A kọwapụtara ntọlite n'ime Project Setting Up Files, na ibe 58. Isi mmalite files nwere ike ịbụ na Verilog ma ọ bụ VHDL. Maka ozi gbasara nhazi nke files maka njikọ, rụtụ aka na akwụkwọ ntuziaka. Akụkụ a na-atụle isiokwu ndị a:
· Ịmepụta isi iyi HDL Files, na ibe 30 · Iji Context Help Editor, na ibe 32 · Lelee isi iyi HDL Files, na ibe 34 · Na-edezi isi iyi HDL Files na Wuru-in Text Editor, na ibe 35 · Iji ihe Mpụga Ederede Editor, na ibe 41 · Ịtọ Mmasị Ohere edezi, na ibe 39 · Iji Library Extensions for Verilog Library Files, na ibe 42

Ịmepụta isi iyi HDL Files
Akụkụ a na-akọwa otu esi eji ndezi ederede arụnyere arụpụtara iji mepụta isi mmalite files, ma ọ dịghị abanye n'ime nkọwa nke ihe ndị files nwere. Maka nkọwa nke ihe ị nwere ike na enweghị ike ịgụnye, yana ozi akọwapụtara nke onye na-ere ahịa, lee akwụkwọ ntuziaka. Ọ bụrụ na ị nwere isi iyi files, ị nwere ike iji editọ ederede lelee syntax ma ọ bụ dezie ya file (lee ịlele Isi mmalite HDL Files, na ibe 34 na edezi isi iyi HDL Files with Wuru na-ederede Ederede, na ibe 35).
Ị nwere ike iji Verilog ma ọ bụ VHDL maka isi mmalite gị files. Nke files nwere v (Verilog) ma ọ bụ vhd (VHDL) file ndọtị, n'otu n'otu. Ị nwere ike iji Verilog na VHDL files na otu imewe. Maka ozi gbasara iji ngwakọta nke ntinye Verilog na VHDL files, lee Iji Isi Iyi Asụsụ agwakọta Files, na ibe 44.
1. Iji mepụta isi iyi ọhụrụ file ma pịa HDL file akara ngosi ( ) ma ọ bụ mee ihe ndị a:
Họrọ File-> Ọhụrụ ma ọ bụ pịa Ctrl-n.
N'ime igbe mkparịta ụka ọhụrụ, họrọ ụdị isi mmalite file ị chọrọ ịmepụta,
Verilog ma ọ bụ VHDL. NotLeOthat ị nwere ike iji Editọ Enyemaka Ọdịnihu maka atụmatụ Verilog nke nwere ihe nrụpụta SystemVerilog na isi mmalite.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

file. Maka ozi ọzọ, lee Iji Context Help Editor, na ibe 32.
Ọ bụrụ na ị na-eji usoro Verilog 2001 ma ọ bụ SystemVerilog, jide n'aka na ị ga-eme ka nhọrọ Verilog 2001 ma ọ bụ System Verilog tupu ịmee njikọ (Project->Nhọrọ mmejuputa->Verilog tab). Verilog ndabara file usoro maka ọrụ ọhụrụ bụ SystemVerilog.

Pịnye aha na ọnọdụ maka file wee pịa OK. Ndezi efu
mpio meghere na nọmba ahịrị n'aka ekpe.
2. Pịnye ozi isi mmalite na windo, ma ọ bụ bee na mado ya. Lee Isi mmalite HDL edezi Files with Wuru-in Text Editor, na ibe 35 maka ozi ndị ọzọ na-arụ ọrụ na mpio edezi.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

Maka nsonaazụ njikọ kacha mma, lelee akwụkwọ ntuziaka ma hụ na ị na-eji ihe nrụpụta dị na njirimara na ntuziaka ndị akọwapụtara nke ọma.
3. Chekwaa file site na-ahọpụta File->Chekwa ma ọ bụ akara ngosi Chekwa ( ).
Ozugbo ị mepụtara isi iyi file, ị nwere ike ịlele na ị nwere syntax ziri ezi, dị ka akọwara na ịlele HDL Source Files, na ibe 34.

Iji Context Help Editor
Mgbe ị mepụtara ma ọ bụ mepee atụmatụ Verilog file, jiri bọtịnụ Enyemaka Context gosipụtara na ala nke windo iji nyere gị aka koodu na Verilog/SystemVerilog rụrụ na isi mmalite. file ma ọ bụ iwu mgbochi Tcl n'ime Tcl gị file.
Iji jiri Editọ Enyemaka Ọdịnihu:
1. Pịa bọtịnụ Enyemaka Context iji gosipụta editọ ederede a.

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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

2. Mgbe ị na-ahọrọ ihe owuwu dị n'akụkụ aka ekpe nke windo ahụ, a na-egosipụta nkọwa enyemaka ntanetị maka ihe owuwu ahụ. Ọ bụrụ na arụrụ ọrụ ahọpụtara enyerela ọrụ a aka, a ga-egosipụta isiokwu enyemaka n'ịntanetị n'elu mpio ahụ wee gosipụta koodu ọnụọgụ ma ọ bụ ndebiri iwu maka ihe owuwu ahụ na ala.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

3. Agbanyekwa bọtịnụ Tinye Template. Mgbe ị pịrị bọtịnụ Fanye Template, koodu ma ọ bụ iwu egosiri na mpio ndebiri ga-etinye n'ime gị file na ebe nke cursor. Nke a na-enye gị ohere itinye koodu ma ọ bụ iwu ngwa ngwa ma gbanwee ya maka imewe nke ị ga-arụkọ.
4. Ọ bụrụ na ịchọrọ idetuo naanị akụkụ nke ndebiri, họrọ koodu ma ọ bụ iwu ịchọrọ itinye wee pịa Detuo. Ị nwere ike mgbe ahụ mado ya n'ime gị file.

Lelee isi iyi HDL Files

Akụrụngwa na-enyocha isi iyi HDL gị na-akpaghị aka files mgbe ọ na-achịkọta ha, mana ọ bụrụ na ịchọrọ ịlele koodu isi mmalite gị tupu njikọ, jiri usoro a. Enwere ụdị nlele abụọ ị na-eme na ngwa ngwa njikọ: syntax na njikọ.

1. Họrọ isi iyi files ị chọrọ ịlele.
Ka ịlele isi mmalite niile files na oru ngo, ewepụla ihe niile files n'ime
ndepụta oru ngo, ma hụ na ọ nweghị nke files na-emeghe na windo na-arụ ọrụ. Ọ bụrụ na ị nwere isi mmalite na-arụ ọrụ file, Akụrụngwa na-enyocha naanị ndị nọ n'ọrụ file.
Ka ịlele otu file, mepee file ya na File-> Mepee ma ọ bụ pịa ugboro abụọ
file na windo Project. Ọ bụrụ na ị nwere ihe karịrị otu file mepee ma chọọ ịlele naanị otu n'ime ha, tinye cursor gị na nke kwesịrị ekwesị file windo iji jide n'aka na ọ bụ windo na-arụ ọrụ.

2. Ka ịlele syntax, họrọ Run->Syntax Check ma ọ bụ pịa Shift+F7.

Akụrụngwa ahụ na-achọpụta njehie syntax dị ka mkpụrụokwu na akara edemede na-ezighi ezi ma na-akọkwa njehie ọ bụla na ndekọ dị iche. file (syntax.log). Ọ bụrụ na achọpụtaghị mperi, a na-akọ nlele syntax na-aga nke ọma na ala nke a file.

3. Iji mee nlele njikọ, họrọ Run->Synthesis Check ma ọ bụ pịa Shift+F8.

Akụrụngwa ahụ na-achọpụta njehie metụtara ngwaike dị ka koodu na-ezighi ezi

tụgharịa ma kọọ njehie ọ bụla na ndekọ dị iche file (syntax.log). Ọ bụrụ n'ebe ahụ

enweghị njehie, a na-akọ nyocha syntax na-aga nke ọma na ala nke a

file.

4. Mkpuview njehie ahụ site na imepe syntax.log file mgbe kpaliri wee jiri Chọta ịchọta ozi mperi (chọọ @E). Pịa ugboro abụọ na ya

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

Koodu njehie nke mkpụrụedemede 5 ma ọ bụ pịa ederede ozi wee pịa F1 iji gosipụta enyemaka ozi njehie ịntanetị.
5. Chọta akụkụ nke koodu kpatara njehie ahụ site na ịpị ugboro abụọ na ederede ozi na syntax.log. file. Window Editor Text na-emepe ebe kwesịrị ekwesị file ma gosi koodu nke kpatara njehie ahụ.
6. Tinyegharịa nzọụkwụ 4 na 5 ruo mgbe emeziri mmejọ syntax na njikọ niile.
Enwere ike ịhazi ozi dịka njehie, ịdọ aka ná ntị, ma ọ bụ ndetu. Review ozi niile ma dozie njehie ọ bụla. Ịdọ aka ná ntị adịchaghị njọ karịa mmejọ, mana ị ga-agụrịrị wee ghọta ha ọbụlagodi na ị kwadoghị ha niile. Ihe ndetu na-enye ihe ọmụma na ọ dịghị mkpa ka edozi ya.

Isi mmalite HDL edezi Fileya na Onye Nhazi Ederede arụnyere arụnyere
Ihe ndezi ederede arụnyere na-eme ka ọ dị mfe ịmepụta koodu isi iyi HDL gị, view ya, ma ọ bụ dezie ya mgbe ịchọrọ idozi njehie. Ọ bụrụ na ịchọrọ iji editọ ederede mpụga, lee Iji ihe ndezi ederede mpụga, na ibe 41.
1. Mee otu n'ime ihe ndị a iji mepee isi iyi file maka viewing ma ọ bụ dezie:
Ka imepee nke mbụ na-akpaghị aka file N'ime ndepụta nwere mperi, pịa F5.
Ka imepee otu file, Pịa ugboro abụọ file na Project window ma ọ bụ
jiri File-> Mepee (Ctrl-o) wee kọwaa isi mmalite file.
Window Ederede Ederede ga-emepe wee gosipụta isi mmalite file. Agụnyere ahịrị ọnụ. Keywords dị na-acha anụnụ anụnụ, na nkọwa na akwụkwọ ndụ akwụkwọ ndụ. Ụkpụrụ eriri dị na uhie. Ọ bụrụ na ịchọrọ ịgbanwe agba ndị a, hụ Mmasị Mmasị Window na-edezi, na ibe 39.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

2. Iji dezie a file, pịnye ozugbo na windo.
Tebụl a na-achịkọta ọrụ ndezi niile ị nwere ike iji. Ị nwekwara ike iji ụzọ mkpirisi ahụigodo kama iji iwu.

Iji…

Mee…

Bee, detuo, na mado; Họrọ iwu site na mmapụta (jituo megharịa, ma ọ bụ megharịa ihe omume bọtịnụ òké aka nri) ma ọ bụ dezie menu.

Gaa na ahịrị akọwapụtara

Pịa Ctrl-g ma ọ bụ họrọ Dezie->Gaa, pịnye nọmba ahịrị, wee pịa OK.

Chọta ederede

Pịa Ctrl-f ma ọ bụ họrọ Dezie ->Chọta. Pịnye ederede ịchọrọ ịchọta, wee pịa OK.

Dochie ederede

Pịa Ctrl-h ma ọ bụ họrọ Dezie->Dochie. Pịnye ederede ịchọrọ ịchọta, yana ederede ịchọrọ iji dochie ya. Pịa OK.

Mezue otu isiokwu

Pịnye mkpụrụedemede zuru oke iji chọpụta isiokwu pụrụ iche, wee pịa Esc.

Tinye ederede n'aka nri Họrọ ngọngọ, wee pịa Tab. Tinye ederede n'aka ekpe LSOHọrọ ngọngọ, wee pịa Shift-Tab.

Gbanwee na nke ukwu Họrọ ederede, wee họrọ Dezie->Elu elu ->Okwu ukwu ma ọ bụ pịa Ctrl-Shift-u.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

Iji… Gbanwee n'obere obere Tinye okwu mgbochi
Dezie ogidi

Mee…
Họrọ ederede, wee họrọ Dezie->Elu -> Obere obere ma ọ bụ pịa Ctrl-u.
Tinye cursor na mmalite nke ederede nkọwa, wee họrọ Dezie->Elu elu-> Koodu okwu ma ọ bụ pịa Alt-c.
Pịa Alt, ma jiri bọtịnụ òké aka ekpe họrọ kọlụm. N'ụfọdụ nyiwe, ị ga-eji igodo nke edobere ọrụ Alt, dị ka igodo Meta ma ọ bụ diamond.

3. Iji bee na mado akụkụ nke akwụkwọ PDF, họrọ akara ngosi T-ederede Họrọ akara, mee ka ederede ị chọrọ ma detuo ma mado ya n'ime gị. file. Akara ngosi Họrọ ederede na-enye gị ohere ịhọrọ akụkụ nke akwụkwọ ahụ.
4. Iji mepụta ma rụọ ọrụ na ibe edokọbara n'ime gị file, lee tebụl na-esonụ.
Ibe edokọbara bụ ụzọ dabara adaba iji mee ogologo oge files ma ọ bụ ịwụ elu gaa n'isi na koodu ị na-ezo aka na ya mgbe mgbe. Ị nwere ike iji akara ngosi dị na ogwe ngwaọrụ Dezie maka ọrụ ndị a. Ọ bụrụ na ịnweghị ike ịhụ ogwe ngwaọrụ Dezie n'akụkụ aka nri nke mpio gị, megharịa ụfọdụ ogwe ngwaọrụ ndị ọzọ.

Iji… Fanye ibe edokọbara
Hichapụ ibe edokọbara
Hichapụ ibe edokọbara niile

Mee…
Pịa ebe ọ bụla n'ahịrị nke ịchọrọ itinye ibe edokọbara. Họrọ Dezie->Tụgharịa ibe edokọbara, pịa Ctrl-F2, ma ọ bụ họrọ akara ngosi nke mbụ na ogwe ngwaọrụ Dezie. Emepụtara nọmba ahịrị iji gosi na enwere ibe edokọbara na mbido ahịrị ahụ.
Pịa ebe ọ bụla n'ahịrị nwere ibe edokọbara. Họrọ Dezie->Tụgharịa ibe edokọbara, pịa Ctrl-F2, ma ọ bụ họrọ akara ngosi nke mbụ na ogwe ngwaọrụ Dezie. Agakwaghị egosi nọmba ahịrị ka ihichapụ ibe edokọbara ahụ.
Họrọ Dezie->Hichapụ ibe edokọbara niile, pịa Ctrl-Shift-F2, ma ọ bụ họrọ akara ikpeazụ n'ime ogwe ngwaọrụ Dezie. A naghị akọwapụta ọnụọgụ ahịrị ahịrị ka ehichapụchara ibe edokọbara.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

Iji…
Ịnyagharịa a file iji ibe edokọbara

Mee…
Jiri iwu ibe edokọbara na-esote (F2) na ibe edokọbara gara aga (Shift-F2) sitere na menu Dezie ma ọ bụ akara ngosi kwekọrọ na ogwe ngwaọrụ Dezie ka ị gaa na ibe edokọbara ịchọrọ.

5. Iji dozie njehie ma ọ bụ regharịaview ịdọ aka ná ntị na koodu isi mmalite, mee ihe ndị a:
Mepee HDL file na njehie ma ọ bụ ịdọ aka ná ntị site na ịpị ugboro abụọ file
na ndepụta oru ngo.
Pịa F5 ka ịga na njehie mbụ, ịdọ aka ná ntị, ma ọ bụ ndetu na file. Na
ala nke mpio edezi, ị na-ahụ ozi ederede.
Ka ịga na njehie, ịdọ aka ná ntị, ma ọ bụ ndetu na-esote, họrọ Gbaa->Mmehie/Ịdọ aka ná ntị ọzọ
ma ọ bụ pịa F5. Ọ bụrụ na enweghị ozi ọzọ na file, ị na-ahụ ozi "Ọ dịghị More Njehie / ịdọ aka ná ntị / Notes" na ala nke edezi window. Họrọ Gbaa-> Njehie/Ịdọ aka ná ntị ọzọ ma ọ bụ pịa F5 ka ịga na njehie, ịdọ aka ná ntị, ma ọ bụ dee ihe na-esote. file.
Ka ịnyagharịa na njehie gara aga, ịdọ aka ná ntị, ma ọ bụ ndetu, họrọ
Gbaa-> Njehie/ ịdọ aka ná ntị gara aga ma ọ bụ pịa Shift-F5.
6. Iji weta enyemaka ozi njehie maka nkọwa zuru ezu nke njehie, ịdọ aka ná ntị, ma ọ bụ ndetu:
Mepee ndekọ usoro ederede file (pịa View Log) ma pịa ugboro abụọ
koodu njehie nke mkpụrụedemede 5 ma ọ bụ pịa ederede ozi wee pịa F1.
Mepee ndekọ HTML file wee pịa koodu njehie nke mkpụrụedemede ise.
Na windo Tcl, pịa taabụ Ozi wee pịa mkpụrụedemede 5
koodu njehie na kọlụm ID.
7. Iji gafee nyocha site na windo koodu isi gaa na nke ọzọ views, mepee view wee họrọ mpempe koodu. Hụ Crossprobing si na windo Editor Text, na ibe 246 maka nkọwa.
8. Mgbe ị doziri njehie niile, họrọ File->Chekwa ma ọ bụ pịa akara ngosi Chekwa ka ịchekwaa file.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

Ịtọ ntọala Mmasị Window edezi
Ị nwere ike hazie mkpụrụedemede na agba ejiri na windo edezi ederede.
1. Họrọ Nhọrọ->Nhọrọ ndezi na ma Synopsys Editor ma ọ bụ Mpụga Editor. Maka ozi ọzọ gbasara onye ndezi mpụga, lee Iji ihe ndezi ederede mpụga, na ibe 41.
2. Mgbe ahụ dabere na ụdị nke file imeghe, ị nwere ike ịtọ ndabere, agba agba syntax, na mmasị font iji jiri onye ndezi ederede.

Mara: Mgbe ahụ, mmasị ndezi ederede ị debere maka nke a file ga-emetụta mmadụ niile files nke a file ụdị.

Enwere ike iji windo edezi ederede ka ịtọọ mmasị maka ọrụ files, isi mmalite files (Verilog/VHDL), ndekọ files, tcl files, mmachi files, ma ọ bụ ndabara ọzọ files site na igbe okwu Nhọrọ Editor.
3. Ị nwere ike ịtọ agba syntax maka ụfọdụ nhọrọ syntax nkịtị, dị ka isiokwu, eriri, na nkọwa. Maka example na log file, ịdọ aka ná ntị na njehie nwere ike ịbụ agba agba maka njirimara dị mfe.
Pịa na ogige ihu ma ọ bụ ndabere maka ihe kwekọrọ na mpaghara Syntax Coloring iji gosipụta palette agba.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

Ị nwere ike ịhọrọ agba ndị bụ isi ma ọ bụ kọwaa agba agba ma tinye ha na palette agba omenala gị. Ka ịhọrọ agba ịchọrọ pịa OK.
4. Ka ịtọọ font na nha mkpụrụedemede maka onye ndezi ederede, jiri menu ndọda.
5. Lelee Debe Taabụ iji mee ka ntọala tab nwee ike, wee tọọ spacing taabụ site na iji akụ elu ma ọ bụ ala maka nha Tab.

LO 6. Pịa OK n'ụdị nhọrọ nchịkọta akụkọ.
© 2014 Synopsys, Inc. 40

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

Iji Editọ Ederede Mpụga
Ị nwere ike iji editọ ederede dị na mpụga dị ka vi ma ọ bụ emacs kama nchịkọta ederede arụnyere n'ime ya. Mee ihe ndị a iji mee ka onye ndezi ederede dị na mpụga nwee ike. Maka ozi gbasara iji editọ ederede arụnyere, hụ Na-edezi isi iyi HDL Files na Onye Ederede Ederede Wuru, na ibe 35.
1. Họrọ Nhọrọ->Nhọrọ Editor wee gbanye nhọrọ Editor Mpụga.
2. Họrọ nchịkọta akụkọ mpụga, na-eji usoro dabara adaba na sistemụ arụmọrụ gị.
Ọ bụrụ na ị na-arụ ọrụ na ikpo okwu Windows, pịa bọtịnụ…(Chọgharịa).
wee họrọ ndezi ederede mpụga nke enwere ike ime ya.
Site na UNIX ma ọ bụ Linux maka onye na-edezi ederede na-emepụta nke ya
mpio, pịa bọtịnụ Chọgharịa wee họrọ ndezi ederede mpụga nke enwere ike ime ya.
Site na ikpo okwu UNIX maka onye na-edezi ederede na-emepụtaghị nke ya
windo, anaghị eji … Chọgharịa bọtịnụ. Kama pịnye xterm-e editor. Ọnụ ọgụgụ na-esonụ na-egosi VI kpọmkwem dị ka onye ndezi mpụga.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Ịtọlite isi iyi HDL Files

Site na ikpo okwu Linux, maka onye na-edezi ederede na-emepụtaghị nke ya
windo, anaghị eji … Chọgharịa bọtịnụ. Kama, pịnye gnome-terminal -x editọ. Iji emacs maka example, pịnye gnome-terminal -x emacs.
Eji emacs na vi ndị ndezi ederede nwalee ngwanro a.
3. Pịa OK.

Iji ndọtị ọba akwụkwọ maka Verilog Library Files
Enwere ike itinye mgbakwunye ọba akwụkwọ na ọbá akwụkwọ Verilog files gụnyere gị imewe maka oru ngo. Mgbe ị na-enye ụzọ ọchụchọ na akwụkwọ ndekọ aha nwere ọba akwụkwọ Verilog files, ị nwere ike ịkọwapụta ndọtị ọbá akwụkwọ ọhụrụ a yana Verilog na SystemVerilog (.v na .sv) file ndọtị.
Iji mee nke a:
1. Họrọ taabụ Verilog nke ogwe nhọrọ mmejuputa iwu.
2. Họrọ ebe akwụkwọ ndekọ aha maka ọbá akwụkwọ Verilog files ka etinyere na nhazi gị maka ọrụ ahụ.
3. Ezipụta ndọtị Library.
Enwere ike ịkọwa ndọtị ọbá akwụkwọ ọ bụla, dị ka .av, .bv, .cv, .xxx, .va, .vas (mgbakwunye ọba akwụkwọ dị iche na oghere).
Ọnụ ọgụgụ na-esonụ na-egosi gị ebe ị ga-abanye n'ọbá akwụkwọ na igbe okwu.

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite isi iyi HDL Files

Isi nke 3: Ịkwadebe ntinye

Tcl dabara maka example bụ iwu a:
set_option -libext .av .bv .cv .dv .ev
Maka nkọwa, lee libext, na ibe 57 na Ntuziaka Iwu.
4. Mgbe ị chịkọtara nhazi ahụ, ị nwere ike nyochaa na log file na ụlọ akwụkwọ files na ndị a extensions e loaded na-agụ. Maka exampLe:
@N: Na-agba ọsọ Verilog Compiler na SystemVerilog mode @I::"C:dirtop.v" @N: CG1180 :"C:dirtop.v":8:0:8:3|Na-ebunye file C:dirlib1sub1.av sitere na akwụkwọ ndekọ aha ọbá akwụkwọ akọwapụtara C:dirlib1 @I::"C:dirlib1sub1.av" @N: CG1180 :"C:dirtop.v":10:0:10:3|Na-ebunye file C:dirlib2sub2.bv sitere na akwụkwọ ndekọ aha ụlọ akwụkwọ akọwapụtara C:dirlib2 @I::"C:dirlib2sub2.bv" @N: CG1180 :"C:dirtop.v":12:0:12:3|Na-ebunye file

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Iji Isi mmalite Asụsụ agwakọta Files

C:dirlib3sub3.cv sitere na akwụkwọ ndekọ aha ọbá akwụkwọ akọwapụtara C:dirlib3 @I::”C:dirlib3sub3.cv” @N: CG1180 :”C:dirtop.v”:14:0:14:3|Na-ebunye file C:dirlib4sub4.dv sitere na akwụkwọ ndekọ aha ụlọ akwụkwọ akọwapụtara C:dirlib4 @I::"C:dirlib4sub4.dv" @N: CG1180 :"C:dirtop.v":16:0:16:3|Na-ebunye file C:dirlib5sub5.ev sitere na akwụkwọ ndekọ aha ọbá akwụkwọ akọwapụtara C:dirlib5 @I::”C:dirlib5sub5.ev” Verilog syntax nlele gara nke ọma!

Iji Isi mmalite Asụsụ agwakọta Files
Site na ngwanrọ Synplify Pro, ị nwere ike iji ngwakọta nke ntinye VHDL na Verilog files na ọrụ gị. Maka examples nke VHDL na Verilog files, lee akwụkwọ ntuziaka.
1. Cheta na Verilog anaghị akwado ọdụ ụgbọ mmiri VHDL na-akwadoghị ma guzobe nhazi asụsụ agwakọtara. fileya mere.
2. Ọ bụrụ na ịchọrọ ịhazi Verilog na VHDL files na nchekwa dị iche iche, họrọ Nhọrọ->Project View Nhọrọ na gbanye na View Ihe oru ngo Files na nhọrọ nchekwa.
Mgbe ị gbakwunye ya files na oru ngo, Verilog na VHDL files nọ na folda dị iche iche na Project view.
3. Mgbe ịmepee oru ngo ma ọ bụ mepụta nke ọhụrụ, tinye Verilog na VHDL files dị ka ndị a:
Họrọ Project-> Tinye isi iyi File iwu ma ọ bụ pịa Tinye File bọtịnụ. Na ụdị, setịpụ Files nke Ụdị ka HDL Files (*.vhd, *.vhdl, *.v). Họrọ Verilog na VHDL files ị chọrọ ma tinye ha na nke gị
oru ngo. Pịa OK. Maka nkọwa gbasara ịgbakwunye files na oru ngo, lee Ime Mgbanwe na Project, na ibe 62.
LO

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Iji Isi mmalite Asụsụ agwakọta Files

Isi nke 3: Ịkwadebe ntinye

Nke files ị gbakwunyere na-egosipụta na Project view. Nke a na ọnụ ọgụgụ na-egosi na files ahaziri na iche iche nchekwa.
4. Mgbe ị na-edozi nhọrọ ngwaọrụ (bọtịnụ nhọrọ mmejuputa), kọwaa modul elu-larịị. Maka ozi ndị ọzọ gbasara ịtọ nhọrọ ngwaọrụ, hụ Nhọrọ mmejuputa ihe nrụnye mgbagha, na ibe 75.
Ọ bụrụ na modul dị elu bụ Verilog, pịa taabụ Verilog wee pịnye ya
aha nke elu-larịị modul.
Ọ bụrụ na modul elu-larịị bụ VHDL, pịa taabụ VHDL wee pịnye aha
nke ụlọ ọrụ kachasị elu. Ọ bụrụ na modul elu-larịị adịghị n'ọbá akwụkwọ ọrụ ndabara, ị ga-edepụta ụlọ akwụkwọ ebe onye nchịkọta nwere ike ịhụ modul ahụ. Maka ozi gbasara otu esi eme nke a, lee VHDL Panel, na ibe 200.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Iji Isi mmalite Asụsụ agwakọta Files

Ị ga-ezipụta nke ọma modul ọkwa dị elu, n'ihi na ọ bụ mmalite nke mapper na-ewepụta netlist jikọtara ọnụ.
5. Họrọ taabụ nsonaazụ mmejuputa n'otu ụdị wee họrọ otu mmepụta HDL maka mmepụta files emepụtara site na ngwanrọ. Maka ozi ndị ọzọ gbasara ịtọ nhọrọ ngwaọrụ, hụ Nhọrọ mmejuputa ihe nrụnye mgbagha, na ibe 75.
Maka netlist mmepụta Verilog, họrọ Dee Verilog Netlist. Maka netlist mmepụta VHDL, họrọ Dee VHDL Netlist. Tọọ ngwaọrụ ọ bụla ọzọ nhọrọ wee pịa OK.
Ị nwere ike ugbu a synthesize gị imewe. Akụrụngwa na-agụ n'ụdị agwakọtara nke isi mmalite files wee mepụta otu srs file nke a na-eji synthesis.
6. Ọ bụrụ na ị na-enwe nsogbu, lee Nchọpụta nsogbu atụmatụ agwakọta asụsụ, na ibe 47 maka ozi ndị ọzọ na ndụmọdụ.
LO

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Iji Isi mmalite Asụsụ agwakọta Files

Isi nke 3: Ịkwadebe ntinye

Ịchọpụta nsogbu atụmatụ agwakọta asụsụ
Akụkụ a na-enye ndụmọdụ maka ijikwa ọnọdụ ndị nwere ike iwepụta ụdị asụsụ agwakọtara.

VHDL File Nye iwu
Maka naanị atụmatụ VHDL ma ọ bụ ihe agwakọtara agwakọta ebe akọwapụtaghị ọkwa dị elu, ngwa njikọ FPGA na-ahazigharị VHDL na-akpaghị aka. files nke mere na a na-achịkọta ngwugwu VHDL n'usoro ziri ezi.
Agbanyeghị, ọ bụrụ na ị nwere nhazi asụsụ agwakọtara ebe ị kọwapụtara ọkwa dị elu, ị ga-akọwarịrị VHDL. file ịtụ maka ngwá ọrụ. Naanị ị ga-eme nke a otu ugboro, site na ịhọrọ Run->Hazie VHDL files iwu. Ọ bụrụ na ịmeghị nke a, ị ga-enweta ozi njehie.

akara ngosi zuru ụwa ọnụ VHDL
Ugbu a, ị nweghị ike ịnweta akara ngosi VHDL zuru ụwa ọnụ n'ụdị asụsụ agwakọtara, n'ihi na ngwa ọrụ na-emejuputa akara ngosi ndị a naanị na atụmatụ VHDL.

Na-agafe VHDL Boolean Generics na Verilog Parameters
Ngwá ọrụ ahụ na-enye igbe ojii maka akụrụngwa VHDL nwere ụdị Boolean, ma ọ bụrụ na etinyere akụrụngwa ahụ ozugbo na nhazi Verilog. Nke a bụ n'ihi na Verilog anaghị amata ụdị data Boolean, yabụ na uru Boolean ga-egosipụtarịrị nke ọma. Ọ bụrụ na uru VHDL Boolean jeneriki bụ TRUE na Verilog nkịtị na-anọchi anya 1, Verilog compiler na-akọwa nke a dị ka igbe ojii.
Iji zere iwebata igbe ojii, Verilog nkịtị maka VHDL Boolean generic set to TRUE ga-abụrịrị 1'b1, ọ bụghị 1. N'otu aka ahụ, ọ bụrụ na VHDL Boolean jeneriki bụ FALSE, Verilog nke kwekọrọ na ya ga-abụrịrị 1'b0, ọ bụghị 0. Nke a bụ ex.ample na-egosi otu esi anọchi anya Boolean generics ka ha wee gafee oke VHDL-Verilog nke ọma, na-enweghị itinye igbe ojii.

Nkwupụta ụlọ ọrụ VHDL

Ngwa ngwa Verilog

Ụlọ ọrụ abc bụ Generic (
Nọmba_Bits Nkesa_Bit );

: integer: boolean

:= 0; := Ụgha;

abc # ( .Number_Bits (16), .Kewaa_Bit (1'b0)
)

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Iji Isi mmalite Asụsụ agwakọta Files

Na-agafe VHDL Generics na-enweghị itinye igbe ojii
N'ọnọdụ ebe paramita akụrụngwa Verilog, (maka example [0:0] RSR = 1'b0) adabaghị n' nha VHDL akụrụngwa jeneriki (RSR: integer: = 0), ngwaọrụ ahụ na-enye igbe ojii.
Ị nwere ike ịrụ ọrụ na nke a site na iwepu akara obosara ụgbọ ala nke [0:0] na Verilog files. Mara na ị ga-ejirịrị ụdị integer VHDL n'ihi na ụdị ndị ọzọ anaghị ekwe ka ejikọta akụkụ Verilog kwesịrị ekwesị.

LO
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Iji Mgbakwunye Compiler

Isi nke 3: Ịkwadebe ntinye

Iji Mgbakwunye Compiler
Jiri mmụba Compiler na-abawanye iji belata nke ọma oge ịgbakọ mkpokọta maka nnukwu atụmatụ. Akụrụngwa na-achịkọta naanị mkpa files mgbe e mere mgbanwe imewe wee jiri nchekwa data nchịkọta ihe. Onye nchịkọta ihe na-emegharị SRS file naanị maka modul emetụtara na modul nne na nna ozugbo.
Iji mee usoro a, mee ihe ndị a:
1. Tinye Verilog ma ọ bụ VHDL files maka imewe.
2. Kwado nhọrọ nchịkọta mmụba sitere na taabụ Verilog ma ọ bụ VHDL nke panel Nhọrọ mmejuputa.
Otu SRS file emepụtara maka modul imewe ọ bụla na ndekọ ndekọ synwork.

3. Gbaa onye nchịkọta ihe maka oge mbụ.
4. Ọ bụrụ na e mere mgbanwe nhazi, megharịa ihe nchịkọta.
Onye nchịkọta akụkọ na-enyocha nchekwa data wee chọpụta ma SRS files bụ ihe ọhụrụ, mgbe ahụ naanị modul ndị gbanwere na modul nne na nna ozugbo ka emegharịrị. Nke a nwere ike inye aka melite oge ojiri gaa maka imewe.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Iji Mgbakwunye Compiler

Oke
Ihe nchịkọta agbakwunyere anaghị akwado:
· Nhazi files gụnyere na ma ọ bụ Verilog ma ọ bụ VHDL eruba · Ngwakọta HDL na-asọpụta · Nhazi nwere ntugharị modul cross (XMR)

LO
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Iji Structural Verilog Flow

Isi nke 3: Ịkwadebe ntinye

Iji Structural Verilog Flow
Ngwa njikọ na-anabata Verilog nhazi files dị ka ntinye maka ọrụ imewe gị. Ihe nhazi nke Verilog na-eme nyocha semantic syntax site na iji parser dị arọ ya iji kwalite oge ọsọ. Onye nchịkọta a anaghị arụ ọrụ mmịpụta ngwaike dị mgbagwoju anya ma ọ bụ ọrụ njikarịcha RTL, yabụ, ngwanro ahụ na-agbakọ ngwa ngwa nke Verilog nhazi. files. Akụrụngwa nwere ike ịgụ Verilog arụpụtara ndị a files, ọ bụrụ na ha nwere:
· Instantiations nke technology primitives
· Nkwupụta ekenye dị mfe
· Àgwà ndị akọwapụtara na Verilog 2001 na usoro ochie
Ihe nrụpụta niile, ma ewezuga njirimara ga-akọwarịrị n'ụdị Verilog 95
Ka ijiri ntinye Verilog nhazi files:
1. Ị ga-ezipụta Verilog nhazi files itinye n'ime imewe gị. Iji mee nke a, tinye ya file iji otu n'ime usoro ndị a:
Project->Tinye Isi mmalite File ma ọ bụ Tinye File bọtịnụ na Project view Tcl iwu: add_file -structver fileAha
Ọsọ a nwere ike ịnwe naanị Verilog nhazi files ma ọ bụ agwakọta HDL files (Verilog/VHDL/EDF/SRS) yana ndebanye aha Verilog files. Agbanyeghị, ụdị Verilog/VHDL/EDF/SRS anaghị akwado n'ime modul Verilog arụrụ arụ.
2. The bughi Verilog files na-agbakwunyere na Structural Verilog nchekwa na Project view. Ị nwekwara ike ịgbakwunye files na ndekọ a, mgbe ị na-eme ihe ndị a:
Họrọ Verilog nhazi file. Pịa aka nri wee họrọ File Nhọrọ. Họrọ Structural Verilog site na File Pịnye menu ndọda.
3. Gbaa njikọ.
Ngwa njikọ na-ewepụta vm ma ọ bụ edf netlist file dabere na teknụzụ akọwapụtara. Usoro a yiri nke ndabara njikọ eruba.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Iji Structural Verilog Flow

Oke
Mmachi nke nrụnye Verilog anaghị akwado ihe ndị a:
Ihe atụ RTL maka onye ọ bụla ọzọ file Ụdị · Njikwa oru ngo (HPM) na-aga · Ọrụ mgbagwoju anya · Ụdị na mgba ọkụ ndị akọwapụtara kpọmkwem.

LO
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Na-arụ ọrụ na Constraint Files

Isi nke 3: Ịkwadebe ntinye

Na-arụ ọrụ na Constraint Files
Mmachi files bụ ederede files nke SCOPE interface na-emepụta na-akpaghị aka (lee Specifying SCOPE Constraints, na ibe 119), ma ọ bụ nke ị jiri aka gị mepụta ederede ederede. Ha nwere iwu Tcl ma ọ bụ njiri mara nke na-egbochi njikọ ahụ. N'aka nke ọzọ, ịnwere ike ịtọ ihe mgbochi na koodu isi mmalite, mana nke a abụghị usoro kachasị amasị.
Nkebi a nwere ozi gbasara
Mgbe a ga-eji mmachi Files n'elu koodu isi mmalite, na ibe 53
· Iji edezi ederede maka mgbochi Files (Legacy), na ibe 54
Ntuziaka Syntax Tcl maka mmachi Files, na ibe 55
· Nyochaa mmachi Files, na ibe 56
Maka nkọwa gbasara akụkọ a, lee mkpesa nleba anya mgbochi, na
ibe 270.nke akwụkwọ ntuziaka, na ibe 56

Mgbe iji mmachi Files n'elu Source Code
Ị nwere ike ịgbakwunye ihe mgbochi na mmachi files (nke SCOPE interface mepụtara ma ọ bụ tinye na ndezi ederede) ma ọ bụ na koodu isi mmalite. N'ozuzu, ọ ka mma iji mmachi files, n'ihi na ịgaghị achịkọta maka mmachi ka ọ rụọ ọrụ. Ọ na-emekwa ka koodu isi mmalite gị nwee ike ibugharị. Lee Iji SCOPE Editor, na ibe 112 maka ozi ndị ọzọ.
Agbanyeghị, ọ bụrụ na ị nwere mgbochi oge igbe ojii dị ka syn_tco, syn_tpd, na syn_tsu, ị ga-etinyerịrị ha dị ka ntuziaka na koodu isi mmalite. N'adịghị ka njirimara, ntụziaka nwere ike ịgbakwunye naanị na koodu isi mmalite, ọ bụghị iji gbochie files. Hụ Ịkọwapụta àgwà na ntụzịaka, na ibe 90 maka ozi ndị ọzọ gbasara ịgbakwunye ntụziaka na koodu isi mmalite.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 3: Ịkwadebe ntinye

Na-arụ ọrụ na Constraint Files

Iji edezi ederede maka mmachi Files (Legacy)
Ị nwere ike iji nchịkọta akụkọ Legacy SCOPE maka mmachi SDC files kere tupu ewepụtara ụdị G-2012.09. Agbanyeghị, a na-atụ aro ka ị tụgharịa asụsụ SDC gị files na FDC files iji mee ka ụdị nchịkọta akụkọ SCOPE kachasị ọhụrụ wee jiri njikwa mmachi oge emelitere na ngwa ọrụ.
Ọ bụrụ n’ịhọrọ iji editọ SCOPE nke ketara, ngalaba a na-egosi gị otu esi eji aka mepụta mmachi Tcl. file. Akụrụngwa na-emepụta nke a na-akpaghị aka file ọ bụrụ na ị na-eji nchịkọta akụkọ SCOPE nke nketa iji tinye ihe mgbochi. Ihe mgbochi Tcl file naanị nwere mmachi oge izugbe. Ekwesịrị itinye mmachi igbe ojii na koodu isi mmalite. Maka ozi agbakwunyere, hụ Mgbe ị ga-eji mmachi Files n'elu koodu isi mmalite, na ibe 53.
1. Mepee a file maka edezi.
Gbaa mbọ hụ na ị mechiri windo SCOPE, ma ọ bụ na ị nwere ike
degharịa mmachi ndị gara aga.
Iji mepụta ọhụrụ file, họrọ File-> Ọhụrụ, wee họrọ mmachi File
(SCOPE) nhọrọ. Pịnye aha maka aha file wee pịa OK.
Iji dezie ihe dị file, họrọ File-> Mepee, tọọ ya Files nke Ụdị nzacha ka
Mmachi Files (sdc) wee mepee ya file ị chọrọ.
2. Soro ntuziaka syntax na Tcl Syntax Guidelines for Constraint Files, na ibe 55.
3. Tinye ihe mgbochi oge ịchọrọ. Maka syntax, lee akwụkwọ ntuziaka. Ọ bụrụ na ị nwere mmachi oge igbe ojii, ị ga-etinyerịrị ha na koodu isi mmalite.
4. Ị nwekwara ike ịgbakwunye àgwà ndị na-ere ahịa na mmachi file na-eji define_attribute. Hụ nkọwapụta njirimara na mmachi File, na peeji nke 97 maka ozi ndị ọzọ.
5. Chekwaa file.
6. Tinye ihe file na oru ngo dị ka akọwara na Ime mgbanwe na Project, na ibe 62, na-agba ọsọ synthesis.

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Na-arụ ọrụ na Constraint Files

Isi nke 3: Ịkwadebe ntinye

Ntuziaka Syntax Tcl maka mmachi Files
Akụkụ a na-ekpuchi ntuziaka izugbe maka iji Tcl maka mmachi files:
· Tcl na-enwe mmetụta.
Maka ịkpọ ihe aha: Aha ihe ga-adakọrịrị na aha dị na koodu HDL. Tinye ihe atụ na aha ọdụ ụgbọ mmiri n'ime curly nkwado { . Ejila oghere n'aha. Jiri ntụpọ (.) kewapụta aha nhazi. Na modul Verilog, jiri syntax ndị a dịka ọmụmaatụ, ọdụ ụgbọ mmiri, na
aha net:
v:cell [prefix:] aha ihe
Ebe cell bụ aha nke ihe eji emepụta ihe, prefix bụ prefix iji mata ihe ndị nwere otu aha, iheAha bụ ihe atụ ụzọ nwere ntụpọ (.) separator. Prefix nwere ike ịbụ nke ọ bụla n'ime ihe ndị a:

Prefix (Nke dị ala) i: p: b: n:

Aha ihe atụ aha ọdụ ụgbọ mmiri (ọdụ ụgbọ mmiri dum) Mpekere nke aha netwọk ọdụ ụgbọ mmiri

Na modul VHDL, jiri syntax ndị a dịka ọmụmaatụ, ọdụ ụgbọ mmiri, na ụgbụ
aha na modul VHDL:
v: cell [.view] [prefix:]Aha ihe
Ebe v: na-akọwapụta ya dị ka a view ihe, lib bụ aha ụlọ akwụkwọ ahụ, cell bụ aha ụlọ ọrụ mmepụta ihe, view bụ aha maka architecture, prefix bụ prefix iji mata ihe nwere otu aha, na objectName bụ ụzọ ihe atụ nwere ntụpọ (.) nkesa. View dị naanị mkpa ma ọ bụrụ na e nwere ihe karịrị otu architecture maka imewe. Lee tebụl dị n'elu maka prefixes nke ihe.

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Isi nke 3: Ịkwadebe ntinye

Na-arụ ọrụ na Constraint Files

· Kaadị ọhịa ndị dabara na aha bụ * (akara mmuke dakọtara ọnụ ọgụgụ ọ bụla
agwa) na ? (akara ajụjụ dabara otu agwa). Mkpụrụedemede ndị a adabaghị na ntụpọ ejiri dị ka ndị na-ekewa ndị isi. Maka exampLe, eriri na-esote na-achọpụta ihe niile nke steeti statereg na modul statemod:
i:statemod.statereg[*]

Nyochaa mmachi Files
Ị nwere ike ịlele syntax na ozi ndị ọzọ dị mkpa na mmachi gị files na-eji iwu Constraint Check. Iji wepụta mkpesa mmachi, mee ihe ndị a:
1. Mepụta ihe mgbochi file ma tinye ya na oru ngo gi.
2. Họrọ Gbaa->Nleba mmachi.
Iwu a na-ewepụta akụkọ na-enyocha syntax na ntinye nke mmachi oge na mmachi njikọ FPGA. files maka oru ngo gi. Edere akụkọ a na projectName_cck.rpt file ma depụta ozi ndị a:
Mgbochi ndị anaghị etinye n'ọrụ Mgbochi ndị bara uru yana ọdabara maka imewe Mgbasawanye Wildcard na mmachi Mmachi na ihe na-adịghị adị.
Maka nkọwapụta na akụkọ a, lee mkpesa mkpesa mgbochi, na ibe 270.nke akwụkwọ ntuziaka

LO
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ISI NKE 4
Ịtọlite Project Synthesis Logic
Mgbe ị na-eji ngwaọrụ njikọ Synopsys FPGA rụpụta ihe, ị ga-ewepụtarịrị ọrụ maka imewe gị. Nke a na-akọwa usoro maka ịtọpụta oru ngo maka njikọ mgbagha:
· Ntọala ọrụ Files, na ibe 58 · Ijikwa Project File Usoro nhazi, na ibe 66 · Ịtọlite mmejuputa iwu, na ibe 72 · Ịmepụta Nhọrọ Mmezu Logic Synthesis, na ibe 75 · Ịkpọpụta àgwà na ntuziaka, na ibe 90 · Ịchọta Files, na ibe 98 · Ịdebe akwụkwọ Files na Projects, na ibe 101

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite Project Files

Ịtọlite Project Files
Akụkụ a na-akọwa ihe ndabere nke otu esi edozi na jikwaa ọrụ file maka imewe gị, gụnyere ozi ndị a:
· Ịmepụta Project File, na ibe 58 · Imepe ihe dị adị File, na ibe 61 · Ime mgbanwe na oru ngo, na ibe 62 · Setting Project View Ngosipụta Mmasị, na ibe 63 · Imelite Verilog gụnyere ụzọ n'ime oru ngo ochie Files, na ibe 65
Maka otu example na mwube oru ngo file, rụtụ aka na nkuzi maka ngwá ọrụ ị na-eji.

Ịmepụta Project File
Ị ga-edozi ọrụ file maka oru ngo ọ bụla. Otu oru ngo nwere data achọrọ maka otu imewe: ndepụta nke isi mmalite files, nsonazụ nke njikọ ahụ file, na ntọala nhọrọ ngwaọrụ gị. Usoro na-esonụ na-egosi gị otu esi edozi ọrụ file iji otu iwu.
1. Malite site na ịhọrọ otu n'ime ihe ndị a: File-> wuo oru ngo, File-> Mepee Project, ma ọ bụ akara ngosi P. Pịa New Project.
Window Project na-egosi ọrụ ọhụrụ. Pịa Tinye File bọtịnụ, pịa F4, ma ọ bụ họrọ Project->Tinye isi iyi File iwu. Ihe mgbakwunye Files to Project dialog igbe ga-emepe.
2. Tinye isi iyi files na oru ngo.
Gbaa mbọ hụ na Lee n'ọhịa dị n'elu ụdị ahụ na-atụ aka nri
ndekọ. Nke files ka edepụtara n'ime igbe. Ọ bụrụ na ị naghị ahụ files, lelee na Files nke ụdị ubi ka atọrọ ka ọ gosipụta nke ziri ezi file ụdị. Ọ bụrụ na ị nwere ntinye agwakọtara files, soro usoro akọwara n'iji Isi Iyi Asụsụ agwakọta Files, na ibe 44.

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Ịtọlite Project Files

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ka ịgbakwunye ihe niile files na ndekọ ozugbo, pịa bọtịnụ Tinye All na
akụkụ aka nri nke ụdị ahụ. Ịgbakwunye files n'otu n'otu, pịa na file na ndepụta wee pịa bọtịnụ Tinye, ma ọ bụ pịa ugboro abụọ file aha.
Ị nwere ike ịgbakwunye niile files na ndekọ wee wepụ ndị ị na-adịghị mkpa na Wepụ bọtịnụ.
Ọ bụrụ na ị na-agbakwunye VHDL files, họrọ ọba akwụkwọ kwesịrị ekwesị site na menu mmapụta VHDL Library. A na-etinye ọbá akwụkwọ ị họọrọ na VHDL niile files mgbe ị pịrị OK na igbe okwu.
Window oru ngo gị na-egosiputa oru ohuru file. Ọ bụrụ na ị pịa akara gbakwunyere n'akụkụ ọrụ ahụ wee gbasaa ya, ị ga-ahụ ihe ndị a:
Otu nchekwa (nchekwa abụọ maka nhazi asụsụ agwakọtara) nwere isi mmalite files.
Ọ bụrụ na gị files adịghị na folda n'okpuru akwụkwọ ndekọ aha, ị nwere ike ịtọ mmasị a site na ịhọrọ Nhọrọ->Project View Nhọrọ na ịlele View oru ngo files na igbe nchekwa. Nke a na-ekewa otu ụdị file site na onye ozo na Project view site n'itinye ha na nchekwa dị iche iche.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite Project Files

Mmejuputa a na-akpọ rev_1 na ndabara. Mmejuputa ya bụ
Ndozigharị nke imewe gị n'ime ọnọdụ nke ngwanro njikọ, ma edochiela sọftụwia na usoro njikwa koodu mpụga mpụga. Ọtụtụ mmejuputa iwu na-ahapụ gị ka ị gbanwee ngwaọrụ na nhọrọ njikọ iji nyochaa nhọrọ nhazi. Ị nwere ike ịme ọtụtụ mmejuputa na Synplify Pro. Onye ọ bụla mmejuputa iwu nwere njikọ nke ya na nhọrọ ngwaọrụ yana ọrụ metụtara ya files.

3. Tinye ọba akwụkwọ ọ bụla ị chọrọ, na-eji usoro akọwara na nzọụkwụ gara aga ka ịgbakwunye Verilog ma ọ bụ VHDL ọba akwụkwọ. file.
Maka ọba akwụkwọ ndị na-ere ahịa, tinye ọbá akwụkwọ kwesịrị ekwesị file ka
oru ngo. Rịba ama na maka ụfọdụ ezinụlọ, a na-ebunye ụlọ akwụkwọ ndị ahụ na-akpaghị aka ma ọ dịghị mkpa ka ị tinye ha n'ụzọ doro anya na ọrụ ahụ. file.
Ka ịgbakwunye ọba akwụkwọ ngwugwu VHDL nke ndị ọzọ, tinye .vhd kwesịrị ekwesị file na imewe, dị ka akọwara na nzọụkwụ 2. Right pịa file na Project view ma họrọ File Nhọrọ, ma ọ bụ họrọ Project-> Tọọ ọba akwụkwọ VHDL. Ezipụta aha ọba akwụkwọ dabara na simulators. Maka example, MYLIB. Jide n'aka na ọbá akwụkwọ ngwugwu a dị n'ihu nhazi toplevel na ndepụta nke files na Project view.
Maka ozi gbasara ịtọ Verilog na VHDL file nhọrọ, hụ Setting Verilog na VHDL Nhọrọ, na ibe 84. Ị nwekwara ike ịtọ ndị a file nhọrọ emechaa, tupu ịgba ọsọ njikọ.
Maka ozi ndị ọzọ akọwapụtara nke onye na-ere ihe gbasara iji ọba akwụkwọ macro na-ere ahịa na bLoOxes ojii, lee Optimizing for Microsemi Designs, na ibe 487.
Maka akụrụngwa teknụzụ jeneriki, ị nwere ike itinye ya
Ọbá akwụkwọ Verilog dabere na teknụzụ wetara ya na ngwanro ahụ

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Ịtọlite Project Files

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

(install_dir/lib/generic_technology/gtech.v) na imewe gị, ma ọ bụ tinye ọba akwụkwọ akụrụngwa nke gị. Ejila ha abụọ ọnụ n'ihi na enwere ike inwe esemokwu.
4. Lelee file ịtụ na Project view. File usoro dị mkpa karịsịa maka VHDL files.
Maka VHDL files, ị nwere ike ịtụ ya ozugbo files site na
na-ahọpụta Run->Hazie VHDL Files. N'aka nke ọzọ, jiri aka mee ihe ahụ files na Project view. ngwugwu files ga-abụ nke mbụ na ndepụta n'ihi na a na-achịkọta ha tupu ejiri ha. Ọ bụrụ na ị nwere blocks imewe gbasaa ọtụtụ files, gbaa mbọ hụ na ị nwere ihe ndị a file iwu: nke file nwere ụlọ ọrụ ga-abụ nke mbụ, na-esote ụkpụrụ ụlọ file, na n'ikpeazụ nke file na nhazi.
Na Project view, lelee na nke ikpeazụ file na Project view bụ nke
elu-larịị isi iyi file. N'aka nke ọzọ, ị nwere ike ịkọwapụta ọkwa dị elu file mgbe ịtọọ nhọrọ ngwaọrụ.
5. Họrọ File-> Chekwa, pịnye aha maka ọrụ ahụ, wee pịa Chekwa. Window Project na-egosipụta mgbanwe gị.
6. Imechi oru ngo file, họrọ bọtịnụ Mechie Project ma ọ bụ File->Mechie Project.

Imepe ihe omume dị adị File
Enwere ụzọ abụọ iji mepee ọrụ file: Open Project na jeneriki File ->Mepee iwu.
1. Ọ bụrụ na ọrụ ị chọrọ imeghe bụ nke ị rụrụ na nso nso a, ị nwere ike họrọ ya ozugbo: File->Arụmọrụ nso nso a-> aha oru ngo.
2. Jiri otu n'ime ụzọ ndị a iji mepee ọrụ ọ bụla file:

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite Project Files

Mepee Iwu Project

File->Mepee Iwu

Họrọ File->Mepee Project, pịa bọtịnụ Mepee Project n'akụkụ aka ekpe nke windo Project, ma ọ bụ pịa akara ngosi P.
Iji mepee ọrụ na-adịbeghị anya, pịa ya ugboro abụọ site na listi ọrụ na-adịbeghị anya.
Ma ọ bụghị ya, pịa bọtịnụ Existing Project ka imepe igbe okwu mepere emepe wee họrọ ọrụ ahụ.

Họrọ File-> Mepee.
Ezipụta ndekọ ziri ezi na Lee In: ubi.
Tọọ File nke Ụdị ka Project Filenke (*.prj). Igbe ahụ depụtara ọrụ ahụ files.
Pịa ugboro abụọ na ọrụ ịchọrọ imeghe.

Ọrụ ahụ na-emepe na windo Project.

Ime mgbanwe na oru ngo
Na-emekarị, ị na-agbakwunye, ihichapụ, ma ọ bụ dochie files.
1. Ka ịgbakwunye isi iyi ma ọ bụ mgbochi files na oru ngo, họrọ Tinye Files bọtịnụ ma ọ bụ Project-> Tinye isi iyi File imeghe Họrọ Files ka Tinye na igbe mkparịta ụka Project. Hụ Ịmepụta Project File, na ibe 58 maka nkọwa.
2. Ihichapụ a file site na oru ngo, pịa nke file na mpio oru ngo, ma pịa igodo Hichapụ.
3. Iji dochie a file na oru ngo,
Họrọ nke file ị chọrọ ịgbanwe na Project window.
Pịa Change File bọtịnụ, ma ọ bụ họrọ Project->Change File.
Na Isi Iyi File igbe okwu na-emepe, tọọ Look In na ndekọ aha
ebe ọhụrụ file dị. Nke ọhụrụ file ga-abụ nke otu ụdị ka file ị chọrọ dochie.
Ọ bụrụ na ịhụghị nke gị file edepụtara, họrọ ụdị nke file ị chọrọ si
nke Files nke Ụdị ubi.
Pịa ya ugboro abụọ file. Nke ọhụrụ file dochie nke ochie na oru ngo
ndepụta. LO
4. Iji kọwaa otú oru ngo files na-echekwara na oru ngo, pịa aka nri na a file na Project view ma họrọ File Nhọrọ. Tọọ Chekwa File nhọrọ ka ma ọ bụ ikwu na Project ma ọ bụ zuru okè ụzọ.

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Ịtọlite Project Files

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

5. Iji lelee oge stamp na a file, Pịa aka nri na a file na Project view ma họrọ File Nhọrọ. Lelee oge nke ahụ file emezigharịrị ikpeazụ. Pịa OK.

Ntọala Project View Gosipụta Mmasị
Ị nwere ike hazie nhazi na ngosipụta nke oru ngo files. 1. Họrọ Nhọrọ->Arụmọrụ View Nhọrọ. Ihe oru ngo a View Ụdị nhọrọ ga-emepe.

2. Iji hazie ụdị ntinye dị iche iche files na nchekwa dị iche iche, lelee View Ihe oru ngo Files na folda.
Ịlele nhọrọ a na-emepụta nchekwa dị iche iche na Project view maka mmachi files na isi iyi files.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite Project Files

3. Njikwa file gosi na ihe ndị a:
Gosipụta ihe niile na-akpaghị aka files, site na ịlele Show Project Library. Ọ bụrụ
Nke a na-adịghị achịkwa, Project view anaghị egosipụta files ruo mgbe ị pịrị akara gbakwunyere wee gbasaa files na folda.
Lelee otu igbe dị na Project File Aha Ngosipụta ngalaba nke
ụdị iji chọpụta otú fileaha na-egosipụta. Ị nwere ike igosipụta naanị ya fileaha, ụzọ ikwu, ma ọ bụ ụzọ zuru oke.
4. Iji view oru ngo files na folda ahaziri ahazi, lelee View Ihe oru ngo Files na nchekwa nchekwa. Maka ozi ọzọ, lee Ịmepụta nchekwa nchekwa, na ibe 66. Ụdị nchekwa na-egosipụta naanị ma ọ bụrụ na enwere ọtụtụ ụdị na folda omenala.

nchekwa nchekwa omenala
© 2014 Synopsys, Inc. 64

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọlite Project Files

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

5. Imepe ihe karịrị otu mmejuputa n'otu Project view, lelee Kwe ka emepee otutu oru ngo.
Ọrụ 1

Ọrụ 2

6. Jikwaa mmepụta file gosi na ihe ndị a:
Lelee ihe ngosi niile Files n'ime igbe ndekọ aha nsonaazụ iji gosipụta mmepụta niile
files eme mgbe njikọ.
Gbanwee mmepụta file nhazi site na ịpị na otu n'ime nkụnye eji isi mee
na nsonaazụ mmejuputa view. Ị nwere ike ikpokọta files n'ụdị ma ọ bụ hazie ha dịka ụbọchị emezigharịrị ikpeazụ ha si dị.
7. Iji view file ozi, họrọ nke file na Project view, Pịa aka nri, wee họrọ File Nhọrọ. Maka example, ị nwere ike ịlele ụbọchị a file emeziri.
Na-emelite Verilog Gụnyere Ụzọ n'ime Ọrụ Ochie Files
Ọ bụrụ na ị nwere oru ngo file emebere ya na ngwa ngwa ochie (tupu 8.1), Verilog gụnyere ụzọ na nke a file bụ ndị metụtara ndekọ ndekọ ma ọ bụ isi iyi file ya na `gụnye nkwupụta. Na mwepụta mgbe 8.1 gasịrị, ọrụ ahụ file `gụnye ụzọ bụ ihe metụtara ọrụ a file naanị. GUI na mwepụta ndị na-adịbeghị anya anaghị ebulite prj nke ochie na-akpaghị aka files irube isi n'iwu ọhụrụ. Iji kwalite ma jiri ọrụ ochie file, mee otu n'ime ihe ndị a:
· Jiri aka dezie prj file na editọ ederede ma tinye ihe ndị a na
ahịrị tupu set_option ọ bụla -include_path:
set_option -project_relative_gụnyere 1
· Malite ọhụrụ oru ngo na a ọhụrụ version nke software na ihichapụ
ochie oru ngo. Nke a ga-eme prj ọhụrụ file rube isi n'iwu ọhụrụ ebe gụnyere ndị metụtara prj file.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ijikwa Project File Ọchịchị

Ijikwa Project File Ọchịchị
Akụkụ ndị a na-akọwa otu ị nwere ike ịmepụta na jikwaa folda ahaziri na files na Project view:
· Ịmepụta nchekwa nchekwa omenala · Ijikwa nchekwa nchekwa ọrụ omenala · Na-emegharị omenala Files

Ịmepụta nchekwa nchekwa omenala
Ị nwere ike ịmepụta nchekwa ezi uche ma hazie ya files na nhazi ọkwa dị iche iche n'ime Project gị view. Enwere ike ịkọwapụta folda ndị a na aha ma ọ bụ ọkwa ọ bụla. Maka examplee, ị nwere ike dakọtara na sistemụ arụmọrụ gị file Ọdịdị ma ọ bụ HDL Logic hierarchy. A na-eji agba anụnụ anụnụ mara nchekwa nchekwa omenala.

Enwere ụzọ dị iche iche iji mepụta folda omenala wee tinye files ha na oru ngo. Jiri otu n'ime ụzọ ndị a:

1. Pịa aka nri na oru ngo file ma ọ bụ nchekwa omenala ọzọ wee họrọ Tinye nchekwa site na menu mmapụta. Mee nke ọ bụla n'ime ihe ndị a file arụ ọrụ:

Pịa aka nri na ngosipụta ya

na nke ahụ

fyioleuoCrOafnileesitahnedr

họrọ họrọ

Tinye na nchekwa. Obere menu bụ nchekwa ma ọ bụ mepụta

ọhụrụ nchekwa.

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Ijikwa Project File Ọchịchị

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Rịba ama na ị nwere ike ịkpọ folda aha n'amaghị ama, mana ejila agwa (/) n'ihi na nke a bụ akara nkewa nke ọkwa.
Iji nyegharịa folda aha, pịa aka nri na folda ahụ wee họrọ Kpọgharia aha site na
menu mmapụta. Igbe kpọgharia aha nchekwa na-egosi; ezipụta aha ọhụrụ.
2. Jiri Tinye Files na igbe mkparịta ụka Project ka ịgbakwunye ọdịnaya niile nke ọkwa nchekwa, wee debe ya na nhọrọ files n'ime folda omenala dabara na ọkwa nchekwa OS nke edepụtara na ngosipụta igbe okwu.

Iji mee nke a, họrọ Tinye File bọtịnụ na Project view.
Họrọ nchekwa ọ bụla achọrọ dị ka dsp site na igbe okwu, wee
pịa bọtịnụ Tinye. Nke a na-enye ohere niile files site na dsp hierarchy banye na folda omenala nke i mebere.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ijikwa Project File Ọchịchị

Ka idowe ya na-akpaghị aka files n'ime folda omenala kwekọrọ
na OS nchekwa hierarchy, lelee nhọrọ a na-akpọ Tinye Files gaa na nchekwa nchekwa omenala na igbe mkparịta ụka.
Site na ndabara, aha folda omenala bụ otu aha dị ka nchekwa ahụ
nwere files ma ọ bụ nchekwa a ga-agbakwunye na ọrụ ahụ. Agbanyeghị, ị nwere ike gbanwee ka esi akpọ folda aha, site na ịpị bọtịnụ Nhọrọ nchekwa. E gosipụtara igbe okwu na-esonụ.

Iji:
Naanị folda nwere files maka aha nchekwa, pịa Jiri OS
Aha nchekwa.
Aha ụzọ na nchekwa ahọpụtara iji chọpụta ọkwa nke
egosipụtara ọkwa maka ụzọ nchekwa omenala.

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Ijikwa Project File Ọchịchị

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

3. Ị nwere ike ịdọrọ na dobe files na nchekwa sitere na ngwa os Explorer n'ime Project view. Njirimara a dị na desktọpụ Windows na Linux na-agba KDE.
Mgbe ị dọrọ na dobe a file, a na-agbakwunye ya ozugbo na ọrụ ahụ.
Ọ bụrụ na enweghị ọrụ mepere emepe, ngwanro na-emepụta ọrụ.
Mgbe ị dọrọ na dobe a file n'elu folda, a ga-etinye ya na nke ahụ
nchekwa. Na mbụ, Tinye Files to Project dialog igbe gosipụtara na-arịọ gị ka ị kwado ya files ka agbakwunyere na oru ngo. Ị nwere ike pịa OK iji nabata ya files. Ọ bụrụ na ịchọrọ ime mgbanwe, ị nwere ike pịa bọtịnụ Wepu All wee kọwaa nzacha ọhụrụ ma ọ bụ nhọrọ.

Mara: Iji gosi nchekwa nchekwa omenala na Project view, họrọ Nhọrọ->Project View Nhọrọ nhọrọ, wee gbanye/ gbanyụọ igbe nlele maka View Ihe oru ngo Files na nchekwa nchekwa omenala na igbe mkparịta ụka.

Na-emegharị nchekwa nchekwa ọrụ omenala
Usoro na-esonụ na-akọwa otú ị nwere ike wepụ files site na nchekwa, hichapụ folda, wee gbanwee usoro nchekwa nchekwa.
1. Iji wepu a file site na folda omenala, ma ọ bụ:
Dọrọ na dobe ya na nchekwa ọzọ ma ọ bụ n'ime ọrụ ahụ. Mee ka ọ pụta ìhè file, Pịa aka nri wee họrọ Wepu na nchekwa na
menu mmapụta.
Ejila igodo Hichapụ (DEL), n'ihi na nke a na-ewepu file site na oru ngo.
2. Iji hichapụ folda omenala, gosi ya wee pịa aka nri wee họrọ Hichapụ site na menu mmapụta ma ọ bụ pịa igodo DEL. Mgbe ị na-ehichapụ folda, mee otu n'ime nhọrọ ndị a:
Pịa Ee ka ihichapụ folda na files dị na nchekwa si
oru ngo.
Pịa Mba ka ihichapụ naanị folda ahụ.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ijikwa Project File Ọchịchị

3. Ịgbanwe nhazi nke folda omenala:
Dọrọ na dobe nchekwa ahụ n'ime folda ọzọ ka ọ bụrụ obere-
nchekwa ma ọ bụ n'elu oru ngo ka ibuga ya na elu-ọkwa.
Ka iwepu ọkwa ọkwa dị elu nke folda omenala, dọrọ na dobe
sub-ọkwa nke achọrọ n'elu oru ngo. Wee hichapụ ndekọ mgbọrọgwụ efu maka nchekwa ahụ.
Maka example, ọ bụrụ na ndekọ ndekọ aha omenala dị adị bụ:
/ Ọpụamples/Verilog/RTL
Ka e were ya na ịchọrọ naanị ndị isi RTL otu ọkwa, wee dọkpụrụ ma dobe RTL n'elu oru ngo a. Mgbe nke ahụ gasịrị, ị nwere ike ihichapụ / Examples/Verilog ndekọ.

Na-emegharị omenala Files
Na mgbakwunye, ịnwere ike ịme ụdị omenala ndị a file arụ ọrụ:
1. Ka ịkwụsịtụ ngosi nke files na Ụdị nchekwa, pịa aka nri na Project view wee họrọ Project View Nhọrọ ma ọ bụ họrọ Nhọrọ->Arụmọrụ View Nhọrọ. Gbanyụọ nhọrọ View Ihe oru ngo Files na Ụdị nchekwa na igbe mkparịta ụka.
2. Igosipụta files n'usoro mkpụrụedemede kama ịhazi usoro ọrụ, lelee Ụdị Files bọtịnụ na Project view ogwe njikwa. Pịa igodo ala dị n'akụkụ aka ekpe nke panel iji gbanye ma gbanyụọ njikwa njikwa.

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Ijikwa Project File Ọchịchị

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ogwe njikwa gbanwee
3. Ịgbanwe usoro nke files na oru ngo:
Gbaa mbọ hụ na ị gbanyụọ nchekwa nchekwa na nhazi files. Dọrọ na dobe a file ruo n'ọnọdụ a chọrọ na ndepụta nke files.
4. Ịgbanwe file pịnye, dọrọ ma dobe ya na folda ụdị ọhụrụ. Akụrụngwa ga-agwa gị maka nkwenye.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite mmejuputa iwu

Ịtọlite mmejuputa iwu
Mmejuputa atumatu bu mbipute nke oru ngo, ejiri otu ihe mgbochi na ntọala ndi ozo mejuputa. Ihe oru ngo nwere ike inwe otutu mmejuputa iwu, nke obula nwere ntọala nke ya.

Na-arụ ọrụ na Multiple mmejuputa
Ngwá ọrụ Synplify Pro na-enye gị ohere ịmepụta ọtụtụ mmejuputa otu imewe wee tulee nsonaazụ. Nke a na-enye gị ohere ịnwale ntọala dị iche iche maka otu imewe. Mmejuputa atumatu bu ntughari nke imewe gi n'ime onodu nke ngwanro njikọ, ma edochila ngwa na usoro njikwa koodu isi mmalite.
1. Pịa bọtịnụ Tinye mmejuputa ma ọ bụ họrọ Project->New Mmejuputa ma tọọ nhọrọ ngwaọrụ ọhụrụ (Ngwaọrụ taabụ), nhọrọ ọhụrụ (Nhọrọ taabụ), ma ọ bụ ihe mgbochi ọhụrụ. file (Mgbochi tab).
Akụrụngwa na-emepụta mmejuputa ọzọ na ọrụ ahụ view. Mmejuputa ohuru a nwere otu aha dika nke bu nke gara aga, ma jiri onu ogugu di iche. Ọnụọgụ na-esonụ na-egosi mmejuputa abụọ, rev1 na rev2, yana mmejuputa iwu ugbu a (na-arụ ọrụ).

Mmejuputa ohuru a na-eji otu koodu isi mmalite files, mana nhọrọ ngwaọrụ dị iche iche na mgbochi. Ọ na-eṅomi ụfọdụ files site na mmejuputa atumatu gara aga: tlg log file, srs RTL netlist file, na design_fsm.sdc file nke FSM Explorer mepụtara. Akụrụngwa na-edobe akụkọ ihe mere eme nke njikọ na-agba ọsọ.

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Ịtọlite mmejuputa iwu

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

2. Gbaa njikọ ọzọ na ntọala ọhụrụ.
Iji mee naanị mmejuputa iwu ugbu a, pịa Gbaa ọsọ.
Iji mee mmemme niile na oru ngo, họrọ Gbaa->Gbaa ihe niile
Mmejuputa.
Ị nwere ike iji ọtụtụ mmejuputa iji nwalee akụkụ dị iche ma ọ bụ jiri oge dị iche mee nnwale. Hụ Nhọrọ mmejuputa usoro mgbagha mgbagha, na ibe 75 maka ozi gbasara nhọrọ ntọala.
Ihe oru ngo a view na-egosi mmejuputa iwu niile na mmejuputa a na-arụsi ọrụ ike gosipụtara na mmepụta kwekọrọ files emepụtara maka mmejuputa a na-arụ ọrụ egosiri na nsonaazụ mmejuputa view n'aka nri; na-agbanwe mmejuputa a na-arụ ọrụ na-agbanwe mmepụta file ngosi. Window Watch na-enyocha mmejuputa a na-arụ ọrụ. Ọ bụrụ na ị hazie windo a ka ọ na-ekiri mmejuputa iwu niile, a na-emelite mmejuputa ọhụrụ na-akpaghị aka na mpio ahụ.
3. Tụlee nsonaazụ ya.
Jiri mpio nche tụnyere njirisi ahọpụtara. Gbaa mbọ hụ na ịtọọ
mmejuputa iwu nke ịchọrọ iji tụnyere iwu Configure Watch. Lee Iji Ihe Nleta Lee, na peeji nke 190 maka nkọwa zuru ezu.

Iji tụnyere nkọwa, tulee ndekọ ahụ file nsonaazụ.
4. Iji nyegharịa mmejuputa aha, pịa bọtịnụ òké aka nri na aha mmejuputa na ọrụ ahụ view, họrọ Gbanwee mmejuputa aha site na menu mmapụta, ma pịnye aha ọhụrụ.
Rịba ama na UI dị ugbu a na-edegharị mmejuputa iwu; ewepụtara tupu 9.0 chekwaa mmejuputa a ga-akpọgharị aha.
5. Iji detuo mmejuputa iwu, pịa bọtịnụ òké aka nri na aha mmejuputa na ọrụ ahụ view, họrọ Detuo mmejuputa iwu site na menu mmapụta, ma pịnye aha ọhụrụ maka oyiri ahụ.

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Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ịtọlite mmejuputa iwu

6. Ka ihichapụ mmejuputa iwu, pịa bọtịnụ òké aka nri na aha mmejuputa na ọrụ ahụ view, wee họrọ Wepu mmejuputa iwu site na menu mmapụta.

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Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic
Ịtọlite Usoro Mmejuputa Nhọrọ
Ị nwere ike ịtọ nhọrọ zuru ụwa ọnụ maka mmejuputa njikọ gị, ụfọdụ n'ime ha nwere teknụzụ. Akụkụ a na-akọwa otu esi edobe nhọrọ zuru ụwa ọnụ dị ka ngwaọrụ, njikarịcha, na file nhọrọ na iwu Nhọrọ mmejuputa. Maka ozi gbasara ịtọọ mmachi maka mmejuputa atumatu, lee Specifying SCOPE Constraints, na ibe 119. Maka ozi gbasara iji njiri mara ma ọ bụ ntuziaka onye ọ bụla gafere ntọala ụwa, lee Specifying Attributes and Directives, na ibe 90.
Akụkụ a na-atụle isiokwu ndị a:
· Ịtọ ntọala ngwaọrụ, na ibe 75 · Ịtọlite nhọrọ nkwalite, na ibe 78 · Ịkọwapụta ugboro ugboro na mmachi zuru ụwa ọnụ. Files, na ibe 80 · Ịkpọpụta nhọrọ nsonaazụ, na ibe 82 · Ịkpọpụta mmepụta akụkọ oge, na ibe 84 · Ịtọpụta nhọrọ Verilog na VHDL, na ibe 84
Ịtọ ntọala ngwaọrụ
Nhọrọ ngwaọrụ bụ akụkụ nke nhọrọ zuru ụwa ọnụ ị nwere ike ịtọ maka nhazi njikọ. Ha gụnyere nhọrọ akụkụ (teknụzụ, akụkụ na ọkwa ọsọ) na nhọrọ mmejuputa (ntinye I/O na fanouts). Nhọrọ na mmejuputa nhọrọ ndị a nwere ike ịdị iche site na teknụzụ gaa na teknụzụ, yabụ lelee isiakwụkwọ ndị na-ere ahịa nke akwụkwọ ntuziaka maka ozi gbasara nhọrọ ndị na-ere gị.
1. Mepee ụdị nhọrọ mmejuputa site na ịpị bọtịnụ nhọrọ mmejuputa ma ọ bụ họrọ Project->Nhọrọ mmejuputa, wee pịa taabụ ngwaọrụ n'elu ma ọ bụrụ na ahọrọbeghị ya.
2. Họrọ teknụzụ, akụkụ, ngwugwu, na ọsọ. Nhọrọ dị iche iche, dabere na teknụzụ ị họọrọ.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
3. Tọọ nhọrọ nkewa ngwaọrụ. Nhọrọ dịgasị iche iche, dabere na teknụzụ ị họọrọ.
Ọ bụrụ na ịmaghị ihe nhọrọ pụtara, pịa nhọrọ ka ịhụ
nkọwa n'ime igbe dị n'okpuru. Maka nkọwa zuru ezu nke nhọrọ, pịa F1 ma ọ bụ rụtụ aka na isi nke ndị na-ere ahịa kwesịrị ekwesị na akwụkwọ ntuziaka.
Ka ịtọọ nhọrọ, pịnye uru ma ọ bụ lelee igbe ka ị mee ya.
Maka ozi ndị ọzọ gbasara ịtọ oke oke na ịla ezumike nka, lee Setting Fanout Limits, na ibe 348, na Retiming, na ibe 334, otu n'otu. Maka nkọwa gbasara nhọrọ ndị ọzọ akọwapụtara nke onye na-ere ihe, rụtụ aka na ngalaba ndị na-ere ahịa dabara adaba na ezinụlọ teknụzụ dị na akwụkwọ ntuziaka.

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Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

4. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK.
5. Pịa Run bọtịnụ ka synthesize imewe. Akụrụngwa ahụ na-achịkọta ma na-esepụta atụmatụ ya site na iji nhọrọ ndị ị debere.
6. Ka ịtọọ nhọrọ ngwaọrụ na edemede, jiri set_option Tcl iwu. Tebụlụ na-esote nwere ndepụta mkpụrụedemede nke nhọrọ ngwaọrụ dị na taabụ ngwaọrụ nke etinyere n'iwu Tcl kwekọrọ. N'ihi na nhọrọ ndị a bụ teknụzụ- na ezinụlọ, nhọrọ niile edepụtara na tebụl nwere ike ọ gaghị adị na teknụzụ ahọpụtara. Iwu niile na-amalite site na set_option, na-esote syntax dị na kọlụm dị ka egosiri. Lelee akwụkwọ ntuziaka maka ndepụta nhọrọ kachasị maka onye na-ere gị.
Tebụl na-esonụ na-egosi ọtụtụ nhọrọ ngwaọrụ.

Ngwongwo akọwara nhọrọ maka onye nyocha Gbanyụọ ntuziaka ntinye m/O

Iwu Tcl (set_option…) -run_prop_extract {1|0} -disable_io_insertion {1|0} -fanout_limit fanout_value

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa

Nhọrọ

Tcl Command (set_option…)

ngwugwu

- ngwugwu pkg_name

Akụkụ

- akụkụ_aha

Kpebie ndị ọkwọ ụgbọala agwakọtara

-edozi_onye ọkwọ ụgbọ ala {1|0}

Ọsọ

-speed_grade speed_grade

Nkà na ụzụ

- okwu teknụzụ

Melite oge nchịkọta oge data -update_models_cp {0|1}

Ọgbọ nchekwa data HDL Analyst -hdl_qload {1|0}

Ịtọlite nhọrọ kacha mma
Nhọrọ kachasị mma bụ akụkụ nke nhọrọ zuru ụwa ọnụ ị nwere ike ịtọ maka mmejuputa. Akụkụ a na-agwa gị otu esi edobe nhọrọ dị ka ugboro na nhọrọ njikarịcha zuru ụwa ọnụ dị ka nkesa akụrụngwa. Ị nwekwara ike ịtọ ụfọdụ nhọrọ ndị a na bọtịnụ kwesịrị ekwesị na UI.
1. Mepee ụdị nhọrọ mmejuputa site na ịpị bọtịnụ mmejuputa ma ọ bụ họrọ Project->Nhọrọ mmejuputa, wee pịa Nhọrọ taabụ n'elu.
2. Pịa njikarịcha nhọrọ ị chọrọ, ma na ụdị ma ọ bụ na Project view. Nhọrọ gị dịgasị iche, dabere na teknụzụ. Ọ bụrụ na nhọrọ adịghị maka nkà na ụzụ gị, ọ na-agba agba. Ịtọ ntọala n'otu ebe na-emelite ya ozugbo na nke ọzọ.

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Ihe oru ngo View

Nhọrọ mmejuputa nhọrọ->Nhọrọ

Maka nkọwa gbasara iji njikarịcha ndị a rụtụ aka na ngalaba ndị a:

FSM Compiler FSM Explorer
Ịkekọrịta ihe onwunwe ezumike nka

Igwe na-ebuli steeti, na ibe 354
Na-agba ọsọ FSM Explorer, na ibe 359 Rịba ama: Naanị akụkụ nke teknụzụ Microsemi na-akwado nhọrọ FSM Explorer. Jiri Project->Nhọrọ mmejuputa->Options panel iji chọpụta ma ọ bụrụ na akwadoro nhọrọ a maka ngwaọrụ ị depụtara na ngwaọrụ gị.
Ịkekọrịta akụrụngwa, na ibe 352
Ịla ezumike nká, na ibe 334

Nhọrọ iwu Tcl set_option dabara bụ ndị a:

Nhọrọ FSM Compiler FSM Explorer Ịkekọrịta ihe onwunwe ezumike nka

set_option Tcl Nhọrọ iwu -symbolic_fsm_compiler {1|0} -use_fsm_explorer {1|0} -resource_sharing {1|0} -weghachi {1|0}

3. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
4. Pịa Run bọtịnụ na-agba ọsọ njikọ.
Akụrụngwa na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.
Ọgbọ nchekwa data HDL Analyst
Site na ndabara, ngwanro ahụ na-agụ atụmatụ ahụ dum, na-arụpụta njikarịcha mgbagha na ịgbasa oge, wee dee mmepụta na otu netlist (srs). Ka atụmatụ na-ebuwanye ibu, oge iji na-agba ọsọ na ihichapụ imewe ahụ na-esiwanye ike.
Nhọrọ a na-enye ohere ka onye na-achịkọta ihe buru ụzọ kewaa nhazi ahụ n'ime ọtụtụ modul nke edere iji kewaa netlist files (srs). Iji mee nhọrọ a, họrọ igbe nlele HDL Analyst Database Generation na Nhọrọ taabụ nke igbe mmejuputa nhọrọ. Njirimara a na-eme ka ojiji ebe nchekwa dịkwuo mma maka nnukwu atụmatụ.
Enwere ike ịgbanye njirimara a site na windo Tcl Script site na iji set_option Tcl iwu:
set_option -hdl_qload 1
Ozugbo enyere HDL Analyst Database Generation nhọrọ, jiri nhọrọ ntinye ngwa ngwa na-abawanye na ngwa nyocha HDL iji gosipụta imewe ahụ site na iji otu netlist (srs) ma ọ bụ ọtụtụ netlists RTL module dị elu (srs). Ngwá ọrụ nwere ike were advantage nke atụmatụ a site n'ịkwalite naanị ndị isi ihe emetụtara. Maka exampYa mere, ihe nchọgharị ndị isi nwere ike gbasaa naanị ọkwa ọkwa dị ala ka achọrọ maka ibu ngwa ngwa. Nhọrọ nrịbawanye ngwa ngwa dị na ngalaba izugbe nke igbe mkparịta ụka Nhọrọ Analyst HDL. Lee Panel General, na ibe 304.

Na-akọwapụta ugboro ugboro na mmachi zuru ụwa ọnụ Files

Usoro a na-agwa gị otu esi edobe ugboro zuru ụwa ọnụ ma kọwaa ihe mgbochi files maka mmejuputa iwu.

1. Ka ịtọọ ugboro zuru ụwa ọnụ, mee otu n'ime ihe ndị a:

Pịnye ugboro zuru ụwa ọnụ na Project view.

Mepee ụdị nhọrọ mmejuputa site na ịpị mmejuputa

Nhọrọ bọtịnụ mmachi taabụ.

họrọ Nhọrọ

Project-> Mmejuputa

Nhọrọ,

pịa

nke

Iwu Tcl set_option dabara bụ -frequencyfrequencyValue.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic
Ị nwere ike iji mmachi mpaghara mebie ugboro zuru ụwa ọnụ, dị ka akọwara na Specifying SCOPE Constraints, na ibe 119. N'ime ngwa Synplify Pro, ị nwere ike ịmepụta ihe mgbochi elekere maka imewe gị kama ịtọọ ugboro zuru ụwa ọnụ. Hụ Iji mmachi akpaaka, na ibe 291 maka nkọwa.
Ọrụ Frequency Global na mgbochi View
Nhọrọ mmejuputa->Mgbochi

2. Ezipụta mmachi files maka mmejuputa iwu, mee otu n'ime ihe ndị a:
Họrọ Project->Nhọrọ mmejuputa->Mgbochi. Lelee mmachi
files ị chọrọ iji na oru ngo.
Site na nhọrọ mmejuputa-> mgbochi, ị nwekwara ike pịa ka
tinye mmachi file.
Na mmejuputa iwu nke ịchọrọ iji họrọ, pịa Tinye File n'ime
Ihe oru ngo view, ma gbakwunye mmachi files ị chọrọ.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
Iji mepụta mmachi files, lee Nkọwapụta Mgbochi SCOPE, na ibe 119.
3. Iji wepu mmachi filesite na mmejuputa iwu, mee otu n'ime ihe ndị a:
Họrọ Project->Nhọrọ mmejuputa->Mgbochi. Pịa gbanyụọ checkbox
n'akụkụ nke file aha.
Na Project view, Pịa aka nri mmachi file a ga-ewepụ na
họrọ Wepu na Project.
Nke a na-ewepụ mmachi file site na mmejuputa iwu, ma anaghị ehichapụ ya.
4. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK.
Mgbe ị na-ahazi nhazi ahụ, ngwanro ahụ na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.
Na-akọwapụta nhọrọ nsonaazụ
Nkebi a na-egosi gị otu esi akọwapụta njirisi maka mmepụta nke njikọ na-agba ọsọ.
1. Mepee ụdị nhọrọ mmejuputa site na ịpị bọtịnụ nhọrọ mmejuputa ma ọ bụ họrọ Project->Nhọrọ mmejuputa, wee pịa taabụ nsonaazụ mmejuputa n'elu.

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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

2. Ezipụta mmepụta files ị chọrọ n'ịwa.
Iji mepụta netlist mapụtara files, pịa Dee mapped Verilog Netlist ma ọ bụ Dee
Ederede VHDL Netlist.
Iji wepụta mmachi akọwapụtara nke onye na-ere ahịa file maka nkọwa n'ihu,
pịa Dee mmachi na-ere ahịa File. Hụ Maka nkọwa gbasara akụkọ a, lee mkpesa nleba anya mgbochi, na ibe 270.nke akwụkwọ ntuziaka, na ibe 56 maka ozi ndị ọzọ.
3. Tọọ ndekọ nke ịchọrọ ide nsonaazụ ya.
4. Tọọ usoro maka mmepụta file. Iwu Tcl dakọtara maka idebe bụ project -result_format format.
Ị nwekwara ike ịtọ àgwà iji jikwaa maapụ aha. Maka nkọwapụta, rụtụ aka na isi nke ndị na-ere ahịa kwesịrị ekwesị na akwụkwọ ntuziaka.
5. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK.
Mgbe ị na-ahazi nhazi ahụ, ngwanro ahụ na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
Na-akọwapụta mmepụta akụkọ oge
Ị nwere ike ikpebi ego ole a kọrọ na akụkọ oge site na ịtọ nhọrọ ndị a.
1. Ịhọrọ Project->Nhọrọ mmejuputa, wee pịa taabụ Report Time. 2. Tọọ ọnụ ọgụgụ nke ụzọ dị oke egwu ịchọrọ ka ngwanrọ na-akọ.

3. Ezipụta ọnụọgụ mmalite na njedebe nke ịchọrọ ịhụ ka akọwara na ngalaba ụzọ dị oke egwu.
4. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK. Mgbe ị na-ahazi nhazi ahụ, ngwanro ahụ na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.
Ịtọ ntọala Verilog na VHDL Nhọrọ
Mgbe ị melite Verilog na VHDL isi iyi fileN'ime oru ngo gị, ị nwekwara ike ịkọwa ụfọdụ nhọrọ nchịkọta.
Ịtọ ntọala Verilog File Nhọrọ
Ị tọọrọ Verilog file nhọrọ site na ịhọrọ ma Project->Nhọrọ mmejuputa-> Verilog, ma ọ bụ Nhọrọ->Hazie Verilog Compiler.

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Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

1. Ezipụta usoro Verilog iji mee ihe.
Iji tọọ ndị nchịkọta ihe n'ụwa niile maka ndị niile files na oru ngo, họrọ
Project->Nhọrọ mmejuputa-> Verilog. Ọ bụrụ na ị na-eji Verilog 2001 ma ọ bụ SystemVerilog, lelee akwụkwọ ntuziaka maka ihe ndị akwadoro.
Iji kọwapụta Verilog compiler na per file ndabere, họrọ nke file n'ime
Ihe oru ngo view. Pịa aka nri wee họrọ File Nhọrọ. Họrọ onye nchịkọta kwesịrị ekwesị. Verilog ndabara file usoro maka ọrụ ọhụrụ bụ SystemVerilog.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
2. Ezipụta modul elu-larịị ma ọ bụrụ na i mebeghị nke a na Project view.
3. Iji wepụ paramita na koodu isi mmalite, mee ihe ndị a:
Pịa Wepụ Parameters. Iji kagbuo ndabara, tinye uru ọhụrụ maka oke.
Akụrụngwa na-eji uru ọhụrụ ahụ naanị maka mmejuputa iwu ugbu a. Rịba ama na akwadoghị mmịpụta oke maka atụmatụ agwakọtara.

4. Pịnye na ntuziaka na Compiler Directives, na-eji oghere kewaa nkwupụta. Ị nwere ike pịnye ntuziaka ị ga-eji 'ifdef' ma kọwaa nkwupụta dị na koodu ahụ. Maka example, ABC=30 rụpụtara na ngwanrọ na-ede nkwupụta ndị a na ọrụ ahụ file:
set_option -hdl_define -set "ABC=30"
LO

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic
5. N'ime usoro usoro gụnyere, kọwaa ụzọ ọchụchọ maka gụnyere iwu maka Verilog. files ndị dị na ọrụ gị. Jiri bọtịnụ dị n'akụkụ aka nri elu nke igbe ahụ ka ịgbakwunye, ihichapụ, ma ọ bụ hazie ụzọ ndị ahụ.
6. Na Library Directories, ezipụta ụzọ na ndekọ nke nwere ọbá akwụkwọ files maka oru ngo gi. Jiri bọtịnụ dị n'akụkụ aka nri elu nke igbe ahụ ka ịgbakwunye, ihichapụ, ma ọ bụ hazie ụzọ ndị ahụ.
7. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK. Mgbe ị na-ahazi nhazi ahụ, ngwanro ahụ na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Oru Nrụpụta Logic Synthesis Setting Logic Synthesis Nhọrọ Mmejuputa
Ịtọlite VHDL File Nhọrọ
Ị tọọrọ VHDL file nhọrọ site na ịhọrọ ma Project->Nhọrọ mmejuputa->VHDL, ma ọ bụ Nhọrọ->Hazie VHDL Compiler.

Maka isi iyi VHDL, ị nwere ike ịkọwapụta nhọrọ ndị akọwara n'okpuru.
1. Ezipụta modul elu-larịị ma ọ bụrụ na i mebeghị nke a na Project view. Ọ bụrụ na modul elu-larịị adịghị n'ọbá akwụkwọ ọrụ ndabara, ị ga-edepụta ụlọ akwụkwọ ebe onye nchịkọta nwere ike ịhụ modul ahụ. Maka ozi gbasara otu esi eme nke a, lee VHDL Panel, na ibe 200.
Ịnwekwara ike iji nhọrọ a maka nhazi asụsụ agwakọtara ma ọ bụ mgbe ịchọrọ ịkọwapụta modul na-abụghị ezigbo ụlọ ọrụ dị elu maka ngosipụta HDL Analyst na LdOebugging na schematic. views. 2. Maka ngbanwe igwe steeti akọwapụtara onye ọrụ, mee ihe ndị a:
Ezipụta ụdị ngbanwe nke ịchọrọ iji.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Ịtọpụta Usoro Mmejuputa Nhọrọ nke Logic Synthesis Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic
Gbanyụọ ihe nchịkọta FSM.
Mgbe ị na-ahazi imewe ahụ, ngwanro ahụ na-eji ntuziaka nchịkọta nke ị debere ebe a iji tinye koodu igwe steeti ma ọ naghị arụ ọrụ mkpokọta FSM, nke ga-akagbu ntuziaka nchịkọta. N'aka nke ọzọ, ị nwere ike kọwapụta igwe steeti nwere njirimara syn_encoding, dị ka akọwara na Defining State Machines na VHDL, na ibe 308.
3. Iji wepụta generics na koodu isi mmalite, mee nke a:
Pịa Wepụ Generic Constant. Iji kagbuo ndabara, tinye uru ọhụrụ maka ọnụọgụgụ.
Akụrụngwa na-eji uru ọhụrụ maka mmejuputa ugbu a naanị. Rịba ama na ịnweghị ike wepụ mkpụrụ ndụ ihe nketa ma ọ bụrụ na ị nwere nhazi asụsụ agwakọtara.

4. Ka ịkwanye tristates gafee usoro/mgbochi oke, lelee na agbanyere Push Tristates. Maka nkọwa, hụ Nhọrọ Push Tristates, na ibe 212 n'ime akwụkwọ ntuziaka.
5. Kpebie nkọwa nke njikọ_na na nhazi_off ntuziaka:
Iji mee ka onye nchịkọta akụkọ kọwapụta synthes_on na synthesis_off ntuziaka
dị ka translate_on/translate_off, mee ka Synthesis Gbanyụọ/ Gbanyụọ dị ka nhọrọ ntụgharị asụsụ / gbanyụọ.
Ka ileghara synthesis_on na synthesis_off ntuziaka, gbaa mbọ hụ na
A naghị enyocha nhọrọ a. Hụ translate_off/translate_on, na ibe 226 n'akwụkwọ ntuziaka maka ozi ndị ọzọ.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Na-akọwapụta àgwà na ntuziaka

6. Tọọ nhọrọ mmejuputa iwu ndị ọzọ dị ka achọrọ (lee Nhọrọ mmezu nke usoro mgbagha, na ibe 75 maka ndepụta nhọrọ). Pịa OK.
Mgbe ị na-ahazi nhazi ahụ, ngwanro ahụ na-achịkọta ma na-esepụta atụmatụ ahụ site na iji nhọrọ ndị ị debere.

Na-akọwapụta àgwà na ntuziaka

Àgwà na ntuziaka bụ nkọwapụta nke ị na-ekenye iji chepụta ihe iji jikwaa otu esi enyocha, na-emeziwanye ya na maapụ gị.
Njirimara na-ejikwa njikarịcha maapụ yana ntuziaka njikwa njikarịcha mkpokọta. N'ihi ọdịiche a, ị ga-ezipụta ntuziaka na koodu isi mmalite. Tebụlụ a na-akọwa ụzọ ndị dị iji mepụta njirimara na nkọwa ntuziaka:

Mgbochi ndị editọ VHDL Verilog SCOPE File

Njirimara Ee Ee Ee Ee

Ntuziaka Ee Ee Mba Mba

Ọ ka mma ịkọwapụta njirimara na nchịkọta akụkọ SCOPE ma ọ bụ ihe mgbochi file, n'ihi na ị gaghị ebu ụzọ chịkọta atụmatụ ahụ. Maka ntụzịaka, ị ga-achịkọtarịrị imewe ha ka ọ rụọ ọrụ.
Ọ bụrụ na SCOPE / mgbochi file na koodu isi iyi HDL akọwapụtara maka imewe, ihe mgbochi nwere mkpa mgbe enwere esemokwu.
Maka nkọwa ndị ọzọ, rụtụ aka na ndị a:
Ịkpọpụta àgwà na ntụziaka na VHDL, na ibe 91 · Ịkọpụta àgwà na ntụziaka na Verilog, na ibe 92 File, na ibe 97

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta àgwà na ntuziaka

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Na-akọwapụta njirimara na ntuziaka na VHDL
Ị nwere ike iji ụzọ ndị ọzọ ịgbakwunye àgwà na ihe, dị ka e depụtara na Specifying àgwà na ntụziaka, na ibe 90. Otú ọ dị, ị nwere ike ezipụta ntụziaka naanị na koodu isi mmalite. Enwere ụzọ abụọ nke ịkọwapụta njirimara na ntuziaka na VHDL:
· Iji ngwungwu njirimara akọwapụtagoro
· Ikwuwapụta njirimara oge ọ bụla ejiri ya
Maka nkọwa nke syntax àgwà VHDL, lee VHDL Attribute and Directive Syntax, na ibe 561 n'ime akwụkwọ ntuziaka.

Iji ngwungwu àgwà VHDL akọwapụtagoro
Onye advantage iji ngwungwu akọwapụtagoro bụ ka ị zere ịkọwapụta njirimara na ntuziaka oge ọ bụla itinye ha na koodu isi mmalite. The mweputage bụ na koodu isi mmalite gị adịchaghị ebugharị. Ngwungwu njirimara dị na installDirectory/lib/vhd/synattr.vhd.
1. Iji jiri ngwungwu njirimara akọwapụtagoro nke gụnyere n'ọba akwụkwọ ngwanrọ, tinye ahịrị ndị a na syntax:
nchịkọta ụlọ akwụkwọ; jiri synplify.attributes.all;
2. Tinye àgwà ma ọ bụ ntụziaka ị chọrọ mgbe imewe unit nkwupụta.
nkwupụta ; attribute_name of objectName: objectType bụ uru;
Maka exampLe:
ihe dị mfe bụ ọdụ ụgbọ mmiri (q: pụọ bit_vector(7 ruo 0); d : na bit_vector (7 ruo 0); clk: na bit);
àgwà syn_noclockbuf nke clk: mgbaama bụ eziokwu;
Maka nkọwapụta nke mgbakọ syntax, lee VHDL Attribute and Directive Syntax, na ibe 561 na akwụkwọ ntuziaka.
3. Tinye isi iyi file na oru ngo.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Na-akọwapụta àgwà na ntuziaka

Na-ekwupụta njirimara na ntụzịaka VHDL
Ọ bụrụ na ijighị ngwungwu njirimara, ị ga-emerịrị kọwapụta njirimara oge ọ bụla itinyere ha na koodu isi mmalite.
1. Oge ọ bụla ị na-eji njirimara ma ọ bụ ntuziaka, kọwapụta ya ozugbo ka nkwupụta nkeji imewe jiri syntax ndị a:
design_unit_nkwuputa ; àgwà àgwàAha : dataỤdị ; àgwà àgwàAha iheAha : objectỤdị bụ uru ;
Maka exampLe:
ihe dị mfe bụ ọdụ ụgbọ mmiri (q: pụọ bit_vector(7 ruo 0); d : na bit_vector (7 ruo 0); clk: na bit);
àgwà syn_noclockbuf: boolean; àgwà syn_noclockbuf nke clk: mgbaàmà bụ eziokwu;
2. Tinye isi iyi file na oru ngo.

Na-akọwapụta njirimara na ntuziaka na Verilog
Ị nwere ike iji ụzọ ndị ọzọ ịgbakwunye àgwà na ihe, dị ka akọwara na Specifying àgwà na ntụziaka, na ibe 90. Otú ọ dị, ị nwere ike ezipụta ntụziaka naanị na koodu isi mmalite.
Verilog enweghị njirimara na ntụzịaka akọwapụtagoro nke ọma, yabụ ị ga-agbakwunye ha dịka nkwupụta. Njirimara ma ọ bụ aha ntuziaka na-ebute ụzọ site na nchịkọta isiokwu. Verilog files na-enwe mmetụta nke ikpe, ya mere a ga-akọwarịrị njirimara na ntụzịaka kpọmkwem dịka e gosipụtara na nkọwa syntax ha. Maka nkọwapụta syntax, lee Verilog Attribute and Directive Syntax, na ibe 363 n'ime akwụkwọ ntuziaka.
1. Ka ịgbakwunye àgwà ma ọ bụ ntụziaka na Verilog, jiri Verilog akara ma ọ bụ gbochie ikwu okwu (C-style) syntax ozugbo na-eso ihe imewe. Ihe mgbochi ga-eburịrị semicolon, ọ bụrụ na enwere otu.
LO

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta àgwà na ntuziaka

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Nkọwa okwu Verilog Block Syntax
/ * synthesis attributeAha = uru *//* ndekọ ndekọ aha = uru */

Nkọwa okwu Verilog Line Syntax
// synthesis attributeAha = uru // ndekọ ndekọ aha = uru

Maka nkọwapụta nke iwu syntax, lee Verilog Attribute and Directive Syntax, na ibe 363 na akwụkwọ ntuziaka. Ndị a bụ examples:
modul fifo (si, na) /* njikọ syn_hier = "ike" */;
2. Iji tinye ọtụtụ njirimara ma ọ bụ ntụziaka n'otu ihe ahụ, kewaa àgwà ndị ahụ na oghere ọcha, ma emeghachila isiokwu njikọ. Ejila rịkọm. Maka exampLe:
ọnọdụ ikpe /* njikọ zuru_case parallel_case */;
3. Ọ bụrụ na a na-akọwa ọtụtụ ndekọ site na iji otu Verilog reg nkwupụta ma tinye otu àgwà na ha, mgbe ahụ, ngwa ngwa ngwa na-emetụta aha ikpeazụ ekwuputara na nkwupụta reg. Maka exampLe:
reg [5:0] q, q_a, q_b, q_c, q_d /* njikọ syn_preserve=1 */;
A na-etinye àgwà syn_preserve naanị na q_d. Nke a bụ omume a na-atụ anya maka ngwaọrụ njikọ. Iji tinye njirimara a na ndebanye aha niile, ị ga-eji nkwupụta Verilog reg dị iche maka ndebanye aha ma tinye àgwà ahụ.

Ịkọwapụta njirimara iji SCOPE Editor
Window SCOPE na-enye interface dị mfe iji tinye àgwà ọ bụla. Ị nweghị ike iji ya maka ịgbakwunye ntụziaka, n'ihi na a ga-agbakwunye ha na isi mmalite files. (Lee Nkọwapụta Àgwà na Ntuziaka na VHDL, na ibe 91 ma ọ bụ Ịkpọpụta àgwà na ntụziaka na Verilog, na ibe 92). Usoro na-esonụ na-egosi otu esi etinye àgwà ozugbo na windo SCOPE.
1. Malite na nhazi agbakọtara wee mepee windo SCOPE. Ka ịgbakwunye njirimara na mmachi dị file, mepee windo SCOPE site na ịpị nke dị file na Project view. Ka ịgbakwunye njirimara na nke ọhụrụ file, pịa akara ngosi SCOPE wee pịa Initialize ka imepe windo SCOPE.
2. Pịa àgwà taabụ na ala nke SCOPE window.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Na-akọwapụta àgwà na ntuziaka

Ị nwere ike buru ụzọ họrọ ihe ahụ (nzọụkwụ 3) ma ọ bụ nke mbụ (nzọụkwụ 4).

3. Iji kọwaa ihe ahụ, mee otu n'ime ihe ndị a na kọlụm ihe. Ọ bụrụ na ị kọwapụtala njirimara a, kọlụm ihe ahụ na-edepụta naanị nhọrọ ihe bara uru maka njirimara ahụ.
Họrọ ụdị ihe dị na kọlụm Filter Object, wee họrọ otu
ihe sitere na ndepụta nhọrọ na kọlụm Ihe. Nke a bụ ụzọ kachasị mma iji hụ na ị na-akọwapụta ihe dabara adaba, yana syntax ziri ezi.

LO
Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Na-akọwapụta àgwà na ntuziaka

Isi nke 4: Ịtọlite arụmọrụ Synthesis Logic

Dọrọ ihe ị chọrọ iji tinye njirimara na ya
RTL ma ọ bụ teknụzụ views gaa na kọlụm ihe dị na windo SCOPE. Maka ụfọdụ njirimara, ịdọrọ na idobe nwere ike ọ gaghị ahọrọ ihe ziri ezi. Maka examplee, ọ bụrụ na ịchọrọ ịtọ syn_hier na modul ma ọ bụ ihe dị ka ọnụ ụzọ ámá, ị ga-edozi ya na view maka modul ahụ. Ihe a ga-enwe syntax: v:moduleAme na Verilog, ma ọ bụ v:library.moduleAha na VHDL, ebe ị nwere ike inwe ọtụtụ ọba akwụkwọ.
Pịnye aha ihe ahụ na kọlụm ihe. Ọ bụrụ na ị maghị
aha, jiri Chọta iwu ma ọ bụ kọlụm Filter Object. Gbaa mbọ hụ na pịnye prefix kwesịrị ekwesị maka ihe ahụ ebe achọrọ ya. Maka example, ịtọ àgwà na a view, ị ga-agbakwunye v: prefix na modul ma ọ bụ aha aha. Maka VHDL, ị nwere ike ịkọwapụta ọbaakwụkwọ yana aha modul.
4. Ọ bụrụ na ị kọwapụta ihe ahụ na mbụ, ị nwere ike ịkọwapụta àgwà ugbu a. Ndepụta a na-egosi naanị ezigbo njirimara maka ụdị ihe ị họọrọ. Ezipụta àgwà ahụ site na ijide bọtịnụ òké na kọlụm àgwà wee họrọ àgwà site na listi ahụ.

Ọ bụrụ na ibu ụzọ họrọ ihe ahụ, nhọrọ ndị dị na-ekpebi ihe ahọpụtara na teknụzụ ị na-eji. Ọ bụrụ na ị họrọ àgwà ahụ na mbụ, teknụzụ na-ekpebi nhọrọ ndị dịnụ.
Mgbe ịhọrọ otu njiri mara, windo SCOPE na-agwa gị ụdị uru ị ga-etinyerịrị maka njirimara ahụ wee nye nkọwa dị nkenke nke njirimara ahụ. Ọ bụrụ na ibu ụzọ họrọ njirimara ahụ, gbaa mbọ laghachi azụ wee kọwapụta ihe ahụ.
5. Mejupụta uru. Jide bọtịnụ òké dị na kọlụm Uru, wee họrọ na listi ahụ. Ị nwekwara ike pịnye uru.

Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi October 2014

Isi nke 4: Ịtọlite Logic Sy

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SYnOPSYS FPGA Synthesis Synplify Pro maka mbipụta Microsemi [pdf] Ntuziaka onye ọrụ
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SYnOPSYS FPGA Synthesis Synplify Pro maka ntuziaka onye ọrụ mbipụta Microsemi

Synthesis FPGA Synplify Pro maka mbipụta Microsemi

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Isi nke 1: Okwu Mmalite

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Isi nke 2: FPGA Synthesis Eserese Na-aga

Isi nke 3: Ịkwadebe ntinye

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