SYnOPSYS FPGA Synthesis Synplify Pro rau Microsemi Edition Tus Neeg Siv Qhia

Synopsys FPGA Synthesis - Synplify Pro rau Microsemi Edition
yog ib qho cuab yeej zoo rau kev siv FPGA nrog ntau yam
nta tsim los pab cov neeg siv hauv logic synthesis thiab tsim
ntws.

Cov lus qhia siv khoom

Tshooj 1: Kev Taw Qhia

Tshooj no muab ib qho ntxivview ntawm Synopsys FPGA thiab
Prototyping Products, FPGA Implementation Tools, thiab Synopsys FPGA
Cov cuab yeej nta.

Scope ntawm Cov Ntaub Ntawv

Cov ntaub ntawv teev muaj cov ntaub ntawv ntawm cov khoom nta
thiab yog npaj rau cov neeg siv txaus siab rau FPGA synthesis thiab tsim
ntws.

Pib pib

Txhawm rau pib siv lub software, tso nws ua raws li cov lus qhia
cov lus qhia thiab xa mus rau tus neeg siv phau ntawv qhia kev pab.

Tus neeg siv interface dhauview

Paub koj tus kheej nrog tus neeg siv interface kom ua tau zoo
taug kev los ntawm cov software nta.

Tshooj 2: FPGA Synthesis Design Flows

Tshooj lus no qhia txog Logic Synthesis Design Flow rau FPGA
synthesis.

Tshooj 3: Npaj cov tswv yim

Kawm paub siv Mixed Language Source Files thiab Incremental
Compiler rau kev npaj tswv yim zoo.

Nco tseg: Yuav tsum paub txog tej kev txwv uas cuam tshuam
Nrog kev siv Incremental Compiler.

FAQ

Q: Kuv puas tuaj yeem luam cov ntaub ntawv?

A: Yog lawm, daim ntawv tso cai daim ntawv cog lus tso cai luam theej rau sab hauv
tsuas yog siv nrog cov khoom tsim nyog.

Q: Kuv yuav pib lub software li cas?

A: Xa mus rau ntu "Pib Pib" hauv Tshooj 1 ntawm cov
Cov neeg siv phau ntawv qhia rau cov lus qhia ntxaws txog kev pib lub software.

Q: Dab tsi yog cov neeg siv khoom npaj rau phau ntawv qhia no?

A: Cov lus qhia siv yog tsom rau cov tib neeg nyiam FPGA
synthesis thiab tsim ntws.

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Synopsys FPGA Synthesis
Synplify Pro rau Microsemi Edition
Cov neeg siv phau ntawv qhia
Lub Kaum Hli 2014

Daim Ntawv Ceeb Toom Copyright thiab Cov Ntaub Ntawv Muaj Cai
Copyright © 2014 Synopsys, Inc. All rights reserved. Cov software thiab cov ntaub ntawv no muaj cov ntaub ntawv tsis pub lwm tus paub thiab cov tswv cuab uas yog cov cuab yeej ntawm Synopsys, Inc. Cov software thiab cov ntaub ntawv tau muab los ntawm daim ntawv tso cai daim ntawv cog lus thiab yuav siv tau lossis theej tsuas yog raws li cov lus cog tseg ntawm daim ntawv tso cai. Tsis muaj ib feem ntawm cov software thiab cov ntaub ntawv yuav raug luam tawm, xa tawm, lossis txhais, hauv ib daim ntawv lossis los ntawm ib qho twg, hluav taws xob, tshuab, phau ntawv, kho qhov muag, lossis lwm yam, yam tsis muaj kev tso cai ua ntej ntawm Synopsys, Inc., lossis raws li tau muab los ntawm daim ntawv cog lus daim ntawv tso cai.
Txoj Cai Copy Documentation
Daim ntawv tso cai pom zoo nrog Synopsys tso cai rau tus neeg muaj ntawv tso cai luam cov ntaub ntawv rau nws siv sab hauv nkaus xwb.
Txhua daim ntawv luam yuav suav nrog tag nrho cov cai lij choj, cov cim lag luam, cov cim kev pabcuam, thiab cov ntawv ceeb toom muaj cai, yog tias muaj. Cov ntawv tso cai yuav tsum muab cov lej sib txuas rau txhua daim ntawv luam. Cov ntawv luam no yuav tsum muaj cov lus dab neeg hauv qab no ntawm nplooj ntawv npog:
"Cov ntaub ntawv no tau muab luam tawm nrog kev tso cai los ntawm Synopsys, Inc., rau kev siv tshwj xeeb ntawm __________________________________________ thiab nws cov neeg ua haujlwm. Qhov no yog tus lej __________."
Destination Control Statement
Tag nrho cov ntaub ntawv muaj nyob rau hauv daim ntawv tshaj tawm no yog ua raws li txoj cai tswj kev xa tawm ntawm Tebchaws Meskas. Kev tshaj tawm rau cov pej xeem ntawm lwm lub teb chaws uas cuam tshuam rau Tebchaws Meskas txoj cai lij choj raug txwv. Nws yog tus nyeem ntawv lub luag haujlwm los txiav txim siab txog cov kev cai siv tau thiab ua raws li lawv.
LO

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tsis lees paub
SYNOPSYS, INC., thiab nws cov ntawv tso cai ua tsis muaj kev lav phib xaub ntawm txhua yam, nthuav tawm lossis hais txog, nrog rau cov ntaub ntawv no, suav nrog, tab sis tsis txwv rau, SAIB XYUAS KEV PAB CUAM NTAWM CHAW UA HAUJ LWM Lub Hom Phiaj.
Cov cim lag luam sau npe (®)
Synopsys, AEON, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certificate, CHIPit, CoMET, CODE V, Tsim Compiler, DesignWare, EMBED-IT!, Formality, Galaxy Custom Designer, Ntiaj Teb Synthesis, HAPS, HapsTrak, HDL Analyst, HSIM, MSPICE, LASTify, I. ModelTools, NanoSim, NOVeA, OpenVera, ORA, PathMill, Lub cev Compiler, PrimeTime, SCOPE, Simply Better Results, SiVL, SNUG, SolvNet, Sonic Focus, STAR Memory System, Syndicated, Synplicity, Synplicity logo, Synplify, Synplify Pro, Synplify Environment UMRBus, VCS, Vera, thiab YIELDirector yog cov cim lag luam ntawm Synopsys, Inc.
Cov cim lag luam (TM)
AFGen, Apollo, ARC, ASAP, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, CustomExplorer, CustomSim, DC Kws Tshaj Lij, DC Tus Kws Tsim Kho, DC Professionally DesignerHDL, DesignPower, DFTMAX, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HIMplus, i-Virtual Stepper, IICE, in-T-andem Jupiter-DP, JupiterXT, JupiterXT-ASIC, Kev ywj pheej, Libra-Passport, tsev qiv ntawv Compiler, Macro-PLUS, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, ORAengineering, Lub cev muaj zog Planet, Tus kws tshuaj ntsuam xyuas, Raphael, RippledMixer, Saturn, Scirocco, Scirocco-i, SiWare, Star-RCXT, Star-SimXT, StarRC, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCSi, VHDL Compiler, VMC, thiab Worksheet Buffer yog cov cim lag luam ntawm Synopsys,

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Service Marks (sm)
MAP-in, SVP Café, thiab TAP-in yog cov cim kev pabcuam ntawm Synopsys, Inc. SystemC yog lub cim lag luam ntawm Open SystemC Initiative thiab siv raws li daim ntawv tso cai. ARM thiab AMBA yog cov npe lag luam ntawm ARM Limited. Saber yog lub npe lag luam ntawm SabreMark Limited Partnership thiab siv raws li daim ntawv tso cai. Tag nrho lwm yam khoom lossis tuam txhab npe yuav yog cov cim lag luam ntawm lawv cov tswv.
Luam tawm hauv Tebchaws Meskas Lub Kaum Hli 2014

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Cov ntsiab lus

Tshooj 1: Kev Taw Qhia
Synopsys FPGA thiab Prototyping Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FPGA Cov cuab yeej siv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synopsys FPGA Tool Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Scope ntawm Cov Ntaub Ntawv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cov Ntaub Ntawv Teeb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cov neeg tuaj saib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pib pib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pib lub Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Tau txais kev pab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Tus neeg siv interface dhauview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tshooj 2: FPGA Synthesis Design Flows
Logic Synthesis Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Tshooj 3: Npaj cov tswv yim
Kev teeb tsa HDL Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Tsim HDL Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Siv Cov Ntsiab Lus Pab Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Txheeb xyuas HDL Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Kho HDL Source Files nrog Built-in Text Editor . . . . . . . . . . . . . . . . . . . . 35 Kev teeb tsa Editing Window Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Siv ib qho External Text Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Siv Library Extensions rau Verilog Library Files. . . . . . . . . . . . . . . . . . . . . . . 42
Siv cov lus sib xyaw Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Siv Incremental Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Kev txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Siv cov qauv Verilog Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Kev txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Ua haujlwm nrog kev txwv Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Thaum Yuav Siv Kev Txwv Files dhau Source Code. . . . . . . . . . . . . . . . . . . . . . . . 53 Siv Cov Ntawv Sau rau Kev Txwv Files (Legacy). . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Syntax Guidelines for Constraint Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Txheeb xyuas qhov txwv Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Tshooj 4: Kev teeb tsa Logic Synthesis Project
Kev teeb tsa qhov project Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Tsim ib qhov project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Qhib ib qhov project uas twb muaj lawm File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Kev hloov pauv rau qhov project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Kev teeb tsa qhov project View Zaub Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Kev Hloov Kho Verilog suav nrog Txoj Kev hauv Txoj Haujlwm Laus Files. . . . . . . . . . . . . . . . . . . . 65
Tswj Project File Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Tsim Custom Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Manipulating Custom Project Folders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Manipulating Custom Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Kev teeb tsa kev siv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ua haujlwm nrog ntau qhov kev siv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Teem Logic Synthesis Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Teem Cov Kev Xaiv Ntaus Ntaus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Kev Xaiv Qhov Zoo Tshaj Plaws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Kev Qhia Txog Ntiaj Teb Tshaj Lij thiab Kev Txwv Files. . . . . . . . . . . . . . . . . . . . . . 80 Qhia meej qhov kev xaiv tau. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Qhia Txog Lub Sijhawm Tshaj Tawm Tshaj Tawm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Teem Verilog thiab VHDL Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Kev Qhia Txog Cov Cai thiab Cov Lus Qhia hauv VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 91 Qhia Txog Cov Cai thiab Cov Lus Qhia hauv Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Qhia Txog Cov Cai Siv SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . 93 Qhia cov cwj pwm hauv cov kev txwv File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ib
Nrhiav Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Kev txheeb xyuas qhov Files mus Nrhiav. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Lim cov Files mus nrhiav. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Pib Tshawb Nrhiav. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Tshawb nrhiav . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LOJ
Kev khaws cia Files thiab Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Archive ib qhov project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Un-Archive a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Luam ib qhov Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Tshooj 5: Kev Qhia Txog Kev Txwv
Siv SCOPE Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Tsim kev txwv hauv SCOPE Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Tsim Kev Txwv Nrog FDC Template Command . . . . . . . . . . . . . . . . 116
Qhia txog SCOPE Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Nkag mus thiab hloov kho Scope txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Kev teeb tsa lub moos thiab txoj kev txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Txhais cov tswv yim thiab tso tawm qhov txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Qhia meej hom I/O Pad Hom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Siv TCL View ntawm SCOPE GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Cov Lus Qhia rau Kev Nkag Mus thiab Kho Cov Kev Txwv . . . . . . . . . . . . . . . . . . . . . . . . 127
Qhia Txog Lub Sijhawm Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Txhais Los Ntawm/Rau/Tshaj Cov Ntsiab Lus rau Timing Exceptions . . . . . . . . . . . . . . . . . 130 Txhais Txoj Kev Ntau Yam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Defining False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Nrhiav Cov Khoom nrog Tcl nrhiav thiab nthuav . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Qhia Txog Cov Qauv Tshawb Nrhiav rau Tcl nrhiav . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Refining Tcl Nrhiav tau nrog -filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Siv Tcl Nrhiav Cov Lus txib los txhais cov ntawv sau. . . . . . . . . . . . . . . . . . . . . 138 Siv Tcl nthuav cov lus txib kom txhais cov ntawv sau. . . . . . . . . . . . . . . . . . 140 Tshawb xyuas Tcl nrhiav thiab nthuav cov txiaj ntsig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Siv Tcl nrhiav thiab nthuav dav hauv Batch Hom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Siv Cov Sau. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Kev sib piv ntawm cov txheej txheem los txiav txim siab sau. . . . . . . . . . . . . . . . . . . . . . . 144 Tsim thiab siv SCOPE Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Tsim Kev Sau siv Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Viewing thiab Manipulating Collections nrog Tcl Commands . . . . . . . . . . . . . . . 150
Konvertiere SDC in FWB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Siv SCOPE Editor (Legacy). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Nkag mus thiab hloov kho SCOPE txwv (Legacy). . . . . . . . . . . . . . . . . . . . . 157 Qhia txog SCOPE Timing Constraints (Legacy). . . . . . . . . . . . . . . . . . . . . . . 159 Nkag mus rau Default Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Teem Lub Sij Hawm thiab Txoj Kev Txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Txhais Moos. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Txhais cov tswv yim thiab tso tawm cov kev txwv (Legacy). . . . . . . . . . . . . . . . . . . . . . . 169 Defining False Paths (Legacy). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 6: Synthesizing and Analyzing the results
Synthesizing Koj Tsim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Khiav Logic Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Siv Kev Tshawb Fawb Txog Kev Tswj Xyuas Haujlwm. . . . . . . . . . . . . . . . . . . . . . 174
Tshawb xyuas Log File Cov txiaj ntsig. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Viewing thiab ua hauj lwm nrog lub log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Nkag mus rau Cov Lus Qhia Tshwj Xeeb nrawm nrawm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Nkag mus tau qhov chaw nyob deb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Txheeb xyuas cov txiaj ntsig siv lub cav File Tshaj tawm. . . . . . . . . . . . . . . . . . . . . . . . . 189 Siv Lub Qhov rai Saib. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Kev Tshawb Fawb Kev Siv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Tswj cov lus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Txheeb xyuas cov txiaj ntsig hauv Cov Lus Viewyog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Lim cov lus hauv Cov Lus Viewyog . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Lim cov lus los ntawm kab hais kom ua. . . . . . . . . . . . . . . . . . . . . . . . . . 197 Automating Message Lim nrog Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . 198 Ib File Message Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Kev Ceeb Toom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Siv Txuas mus rau qhov yuam kev. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Siv Txuas ntxiv ntawm qhov yuam kev rau Compile Point Synthesis . . . . . . . . . . . . . . . . . . . 203
Tshooj 7: Kev soj ntsuam nrog HDL Analyst thiab FSM Viewer
Ua haujlwm hauv Schematic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Sib txawv ntawm HDL Analyst Views. . . . . . . . . . . . . . . . . . . . . . . . 209 Qhib lub Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Viewntawm Object Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Xaiv Cov Khoom hauv RTL/Technology Views. . . . . . . . . . . . . . . . . . . . . . . 215 Ua haujlwm nrog Multisheet Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Tsiv ntawm Views hauv Schematic Qhov rai. . . . . . . . . . . . . . . . . . . . . . . 218 Setting Schematic View Kev nyiam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Tswj Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Tshawb nrhiav Design Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Traversing Design Hierarchy nrog Hierarchy Browser . . . . . . . . . . . . . . . . 222 Kev Tshawb Nrhiav Cov Khoom Hierarchy los ntawm Pushing/Popping . . . . . . . . . . . . . . . . . . . . . . . 223 Kev Tshawb Fawb Txog Yam Khoom Hierarchy ntawm Transparent Instances . . . . . . . . . . . . . . . . . . . 228
Nrhiav Cov Khoom . . . . . . . . . . . . .LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Tshawb nrhiav Cov Khoom hauv HDL Analyst Views. . . . . . . . . . . . . . . . . . . . . . . 230 Siv Nrhiav rau hierarchical thiab txwv kev tshawb nrhiav. . . . . . . . . . . . . . . . . . . . 232 Siv Wildcards nrog Nrhiav Cov Lus txib . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Ua ke Nrhiav nrog Filtering los kho cov kev tshawb nrhiav. . . . . . . . . . . . . . . . . . . . . . 240 Siv Nrhiav los Tshawb Nrhiav Cov Ntawv Tshaj Tawm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Hla kev soj ntsuam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Hla kev soj ntsuam hauv ib qho RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 243 Kev Tshawb Fawb Txog Kev Tshawb Fawb los ntawm RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . . . 244 Crossprobing los ntawm Text Editor Qhov rai . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Crossprobing los ntawm Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Kev soj ntsuam los ntawm FSM Viewyog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Kev Ntsuam Xyuas Nrog HDL Analyst Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Viewhauv Design Hierarchy and Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Filtering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Expanding Pin thiab Net Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Kev nthuav dav thiab Viewhauv kev sib txuas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Flattening Schematic Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Txo kev siv lub cim xeeb thaum soj ntsuam cov qauv . . . . . . . . . . . . . . . . . . . 267
Kev siv FSM Viewyog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Tshooj 8: Kev Ntsuas Lub Sijhawm
Txheeb xyuas Sijhawm Sijhawm hauv Schematic Views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Viewhauv Cov Ntaub Ntawv Sijhawm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Annotating Timeing Information nyob rau hauv Schematic Views. . . . . . . . . . . . . . . . . . 275 Txheeb xyuas Cov Ntoo Tsob Ntoo Hauv RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Viewhauv Critical Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Kov Tsis Zoo Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Tsim Daim Ntawv Qhia Txog Lub Sijhawm Kev Cai nrog STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Siv cov kev ntsuas tsim kev txwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Scenarios rau Siv Kev Tshawb Fawb Tsim Kev Txwv . . . . . . . . . . . . . . . . . . . . . . 285 Tsim ADC File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Siv Object Names kom raug hauv adc File . . . . . . . . . . . . . . . . . . . . . . . . . 290 ib
Siv Auto Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Cov txiaj ntsig ntawm Auto Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 ib
Tshooj 9: Inferring High-Level Objects
Defining Black Boxes rau Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Boxes thiab I/Os hauv Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . 298 Instantiating Black Boxes thiab I/Os hauv VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 300 Ntxiv Black Box Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Ntxiv Lwm Yam Khoom Dub Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Txhais lub Xeev Machinery rau Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Txhais Lub Xeev Cov Tshuab hauv Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Txhais lub xeev cov tshuab hauv VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Qhia FSMs nrog Cov Cai thiab Cov Lus Qhia. . . . . . . . . . . . . . . . . . . . . . . . 309
Kev Qhia Txog Kev Nyab Xeeb FSMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Automatic RAM Inference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Thaiv RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 RAM yam ntxwv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Inferring Block RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Pib pib RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Initializing RAMs hauv Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Initializing RAMs hauv VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Tshooj 10: Kev Qhia Txog Kev Tsim Kho-Level Optimizations
Lub tswv yim rau Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 General Optimization Tips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Optimizing rau Cheeb Tsam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Optimizing rau Sijhawm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Retimeing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Tswj Retiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Retiming Exampua le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Retimeing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Yuav Ua Li Cas Retimeing Ua Haujlwm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Khaws cov khoom los ntawm kev ua kom zoo nyob deb. . . . . . . . . . . . . . . . . . . . . . . . . . 342 Siv syn_keep rau Preservation lossis Replication . . . . . . . . . . . . . . . . . . . . . . . 343 Tswj Hierarchy Flattening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Preserving Hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Optimizing Fanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Teeb Fanout txwv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Tswj Kev Tsis Txaus Siab thiab Kev Tshaj Tawm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Kev sib faib cov peev txheej. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 ib
Inserting I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Optimizing Lub Xeev Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Txiav txim siab thaum twg los txhim kho lub xeev cov tshuab . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Khiav FSM Compiler LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Khiav FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 ib
Inserting Probes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 ib

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Txheeb xyuas cov kev sojntsuam hauv qhov Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Ntxiv Cov Ntsiab Lus Sib Tham Sib Tham. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Tshooj 11: Ua hauj lwm nrog cov ntsiab lus sau
Compile Point Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Advantages ntawm Compile Point Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Phau Ntawv Sau Cov Ntsiab Lus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Nested Compile Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Compile Point Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Compile Point Synthesis Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Compile Point Constraint Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Interface Logic Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Interface Sijhawm rau Sau Cov Ntsiab Lus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Compile Point Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Incremental Compile Point Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Forward-annotation ntawm Compile Point Timing Constraints . . . . . . . . . . . . . . . . 384 ib
Synthesizing Compile Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 Phau Ntawv Qhia Cov Ntsiab Lus Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Tsim ib qho kev txwv saum toj kawg nkaus File rau Compile Points. . . . . . . . . . . . . . . . 388 Txhais Lus Txhais Phau Ntawv Sau Cov Ntsiab Lus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Kev teeb tsa kev txwv nyob rau theem Compile Point . . . . . . . . . . . . . . . . . . . . . . . . 391 Txheeb xyuas Compile Point Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ib 393
Siv Compile Points nrog rau lwm yam nta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Kev sib xyaw ua ke cov ntsiab lus nrog Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . ib 396
Resynthesizing Incrementally. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Resynthesizing Compile Points Incrementally . . . . . . . . . . . . . . . . . . . . . . . . . ib 397
Tshooj 12: Ua haujlwm nrog IP nkag
Tsim IP nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Qhia FIFOs nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Qhia RAMs nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 Qhia Txog Byte-Enable RAMs nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . 416 Qhia ROMs nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Specification Adder/Subtractors nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Specification Counters nrog SYNCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 ib
Synopsys FPGA IP Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Nwsview ntawm Synopsys FPGA IP Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 Encryption thiab Decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 ib
Ua haujlwm nrog Encrypted IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 ib

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Encrypting Koj tus IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Encrypting IP nrog tus encryptP1735.pl tsab ntawv . . . . . . . . . . . . . . . . . . . . . . . . . 448 Encrypting IP nrog cov ntawv encryptIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Qhia meej txog Txoj Cai Tso Tawm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Npaj IP Pob. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 ib
Siv Hyper Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Siv Hyper Source rau Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Siv Hyper Source rau IP Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Threading Signals Los ntawm Tsim Hierarchy ntawm IP. . . . . . . . . . . . . . . 461 ib
Tshooj 13: Txhim kho cov txheej txheem rau kev tsim khoom
Siv Batch Hom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Khiav Batch hom ntawm ib qhov project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Khiav Batch Hom nrog Tcl Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Queing Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 ib
Ua haujlwm nrog Tcl Scripts thiab Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Siv Tcl Commands thiab Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Tsim Cov Ntawv Sau Ua Haujlwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Teem caij Cov Hauj Lwm Uas Sib Tham. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Tsim Tcl Synthesis Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Siv Tcl Variables los sim sib txawv moos zaus . . . . . . . . . . . . . . . . . . 476 Siv Tcl Variables sim ob peb lub hom phiaj yees. . . . . . . . . . . . . . . . . 478 Khiav hauv qab-up Synthesis nrog ib tsab ntawv. . . . . . . . . . . . . . . . . . . . . . . . . . . 479 ib
Automating Flows nrog synhooks.tcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 ib
Tshooj 14: Siv Multiprocessing
Multiprocessing Nrog Compile Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Kev teeb tsa cov hauj lwm sib luag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Daim ntawv tso cai siv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 ib
Tshooj 15: Ua kom zoo rau Microsemi Designs
Optimizing Microsemi Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Siv Predefined Microsemi Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Siv Smartgen Macros. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Ua haujlwm nrog Radhard Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Qhia meej syn_radhardlevel hauv qhov Code. . . . . . . . . . . . . . . . . . . . . . . 490 LOJ
Tshooj 16: Ua hauj lwm nrog Synthesis Output
Kev xa cov ntaub ntawv mus rau P&R cov cuab yeej. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 ib

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Qhia Pin Qhov Chaw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Qhia qhov chaw rau Microsemi Bus Ports . . . . . . . . . . . . . . . . . . . . . . . . . 495 Qhia meej Macro thiab Sau Npe Tso Npe. . . . . . . . . . . . . . . . . . . . . . . . . . . 495 ib
Generating Vendor-Specific Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Targeting Output rau koj tus neeg muag khoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Customizing Netlist Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 ib
Tshooj 17: Kev Ua Haujlwm Tom Qab Kev Sib Txuas
Khiav P&R Automatically tom qab Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Ua haujlwm nrog Identify Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Launching los ntawm Synplify Pro Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 Kev daws teeb meem nrog Launching Qhia . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Siv Cov Cuab Yeej Qhia Tawm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Siv Cov Ntsiab Lus Sib Sau nrog Cov Cai Qhia . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Simulating nrog VCS Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1
Taw qhia
Qhov kev taw qhia no rau Synplify Pro® software piav qhia cov hauv qab no:
· Synopsys FPGA thiab Prototyping Products, nyob rau nplooj 16 · Scope of the Document, on page 21 · Pib dua, nyob rau nplooj 22 · User Interface Overview,,paj 24

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1: Kev Taw Qhia

Synopsys FPGA thiab Prototyping Khoom

Synopsys FPGA thiab Prototyping Khoom
Cov duab hauv qab no qhia txog Synopsys FPGA thiab Prototyping tsev neeg ntawm cov khoom.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Synopsys FPGA thiab Prototyping Khoom

Tshooj 1: Kev Taw Qhia

FPGA Implementation Tools
Synplify Pro thiab Synplify Premier cov khoom yog RTL synthesis cov cuab yeej tshwj xeeb tsim rau FPGAs (field programmable gate arrays) thiab CPLDs (cov programmable logic nyuaj).

Synplify Pro Synthesis Software
Synplify Pro FPGA synthesis software yog tus txheej txheem kev lag luam de facto rau kev ua tau zoo, tus nqi tsim nyog FPGA. Nws qhov tshwj xeeb
Behavior Extracting Synthesis Technology® (BEST) algorithms, ua
high-level optimizations ua ntej synthesizing RTL code rau hauv FPGA logic tshwj xeeb. Txoj hauv kev no tso cai rau kev ua kom zoo tshaj plaws thoob plaws FPGA, lub sijhawm ua haujlwm nrawm, thiab muaj peev xwm los daws cov qauv tsim loj heev. Lub Synplify Pro software txhawb nqa qhov tseeb VHDL thiab Verilog lus tsim nrog rau SystemVerilog thiab VHDL 2008. Cov cuab yeej yog thev naus laus zis ywj pheej tso cai rau kev ceev thiab yooj yim retargeting ntawm FPGA cov khoom siv thiab cov neeg muag khoom los ntawm ib txoj haujlwm tsim.

Synplify Premier Synthesis Software
Synplify Premier functionality yog superset ntawm Synplify Pro cov cuab yeej, muab qhov kawg FPGA kev siv thiab debug ib puag ncig. Nws suav nrog cov txheej txheem dav dav ntawm cov cuab yeej thiab thev naus laus zis rau cov neeg tsim qauv FPGA siab heev, thiab tseem ua haujlwm ua lub cav sib xyaw rau ASIC prototypers tsom rau ib qho FPGA-raws li prototypes.
Cov khoom lag luam Synplify Premier muaj ob tus neeg tsim qauv FPGA thiab ASIC prototypers tsom rau ib leeg FPGAs nrog txoj kev siv tau zoo tshaj plaws ntawm kev tsim qauv thiab kev debug. Ntawm qhov kev tsim qauv tsim, nws suav nrog kev ua haujlwm rau lub sijhawm kaw, kev txheeb xyuas qhov tseeb, kev siv IP, ASIC kev sib raug zoo, thiab kev siv DSP, nrog rau kev sib koom ua ke nruj nrog FPGA tus neeg muag khoom rov qab cov cuab yeej. Ntawm qhov debug sab, nws muab rau hauv-system pov thawj ntawm FPGAs uas ua rau kom ceev cov txheej txheem debug, thiab tseem suav nrog txoj kev nrawm thiab nce ntxiv rau kev nrhiav cov teeb meem tsim tsis yooj yim.

Synopsys FPGA Tool Nta
Cov lus no txawv ntawm qhov kev ua haujlwm loj hauv Synplify Pro, Synplify, Synplify Premier, thiab Synplify Premier nrog cov khoom tsim Planner.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1: Kev Taw Qhia

Synopsys FPGA thiab Prototyping Khoom

Synplify Synplify Pro

Kev ua tau zoo

Cwj pwm Extracting Synthesis

Technology® (BESTTM)

Tus neeg muag khoom-Generated Core/IP

Kev them nyiaj yug (qee yam technologies)

FSM Compiler

FSM Explorer

Gated Clock Hloov

Sau npe Pipelining

Sau npe Retiming

SCOPE® Constraint nkag

Kev ntseeg siab nta

Integrated qhov chaw-thiab-txoj kev

Kev tsom xam

HDL Analyst®

Kev xaiv

Timing Analyzer

Point-to-point

FSM Viewer

Kev soj ntsuam

Probe Point Creation

Identify® Instrumentor

Txheeb xyuas Debugger

Kev txheeb xyuas lub zog (SAIF)

Kev Tsim Lub Cev

Tsim Kev Npaj File

Logic Assignment rau Regions

Synplify Premier
x
x
xxxxxxxxx
xx kev
xxxxxx ib

Synplify Premier DP
x
x
xxxxxxxxx
xx kev
xxxxxx ib
xx kev

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Synopsys FPGA thiab Prototyping Khoom

Tshooj 1: Kev Taw Qhia

Kev kwv yees thaj tsam thiab cheeb tsam Peev Pin Assignment Physical Optimizations Physical Synthesis Physical Analyst Synopsys DesignWare® Foundation Library Runtime Hierarchical Design Enhanced Optimization Fast Synthesis Multiprocessing Compile on Error Team Design Mixed Language Design Compile Points Hierarchical Design True Batch Mode (Floating Batch licences only) Rov qab-annotation ntawm P&R Cov Ntaub Ntawv Pov Thawj

Synplify Synplify Pro

xxxx

–

Txheeb xyuas kev sib koom ua ke

txwv

Synplify Premier
xxx ib
xxxxx
xxxx
x
x Logic synthesis hom x

Synplify Premier DP
x
xxxxx
xxxxx
xxxx
x
xx Logic synthesis hom
x

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1: Kev Taw Qhia

Synopsys FPGA thiab Prototyping Khoom

Rov qab-annotation ntawm P&R Cov Ntaub Ntawv Tsim Ib puag ncig Text Editor View Saib Qhov rai Message Window Tcl Qhov rai Ntau Qhov Kev Ua Haujlwm Kev Muag Khoom Technology Txhawb Prototyping Nta Runtime nta Sau Cov Ntsiab Lus Gated Clock Conversion Compile ntawm yuam kev

Synplify Synplify Pro

Synplify Premier
xxxxx Xaiv
xxxx

Synplify Premier DP
x
xxxxx Xaiv
xxxx

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Scope ntawm Cov Ntaub Ntawv

Tshooj 1: Kev Taw Qhia

Scope ntawm Cov Ntaub Ntawv
Cov hauv qab no piav qhia txog cov peev txheej ntawm cov ntaub ntawv no thiab cov neeg tuaj saib xav tau.

Cov Ntaub Ntawv Teeb
Cov neeg siv phau ntawv qhia no yog ib feem ntawm cov ntaub ntawv teeb tsa uas suav nrog phau ntawv qhia siv thiab cov lus qhia. Nws yog npaj rau siv nrog rau lwm cov ntaub ntawv nyob rau hauv lub teeb. Nws tsom ntsoov piav qhia yuav ua li cas siv Synopsys FPGA software kom ua tiav cov haujlwm raug. Qhov no qhia txog cov hauv qab no:
· Tus neeg siv phau ntawv qhia tsuas yog piav qhia txog cov kev xaiv uas xav tau los ua cov haujlwm ib txwm ua
piav nyob rau hauv phau ntawv qhia. Nws tsis piav txog txhua qhov kev hais kom ua thiab kev xaiv. Txhawm rau ua tiav cov lus piav qhia ntawm tag nrho cov kev xaiv hais kom ua thiab syntax, xa mus rau Tus Neeg Siv Khoom Siv Tshajview tshooj hauv Synopsys FPGA Synthesis Reference Manual.
· Cov neeg siv phau ntawv qhia muaj cov ntaub ntawv ua haujlwm. Rau kev sib cais ntawm
Cov ntaub ntawv raug teeb tsa li cas, saib Tau Txais Kev Pab, ntawm nplooj 22.

Cov neeg mloog
Cov cuab yeej Synplify Pro software yog tsom rau FPGA tus tsim tawm. Nco ntsoov tias koj muaj kev paub txog cov hauv qab no:
· Tsim synthesis · RTL · FPGAs · Verilog/VHDL

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1: Kev Taw Qhia

Pib pib

Pib pib
Tshooj lus no qhia koj yuav pib li cas nrog Synopsys FPGA synthesis software. Nws piav qhia cov ntsiab lus hauv qab no, tab sis tsis hloov pauv cov ntaub ntawv hauv cov lus qhia kev teeb tsa txog kev tso cai thiab kev teeb tsa:
· Pib lub Software, ntawm nplooj 22 · Tau Txais Kev Pab, nyob rau nplooj 22

Pib lub Software
1. Yog tias koj tsis tau ua li ntawd, nruab Synopsys FPGA synthesis software raws li cov lus qhia installation.
2. Pib lub software.
Yog tias koj tab tom ua haujlwm ntawm Windows platform, xaiv
Cov Kev Pabcuam-> Synopsys-> cov khoom lag luam los ntawm lub pob pib.
Yog tias koj tab tom ua haujlwm ntawm UNIX platform, ntaus qhov tsim nyog
hais kom ua ntawm kab hais kom ua:
synplify_pro
· Cov lus txib pib lub cuab yeej synthesis, thiab qhib qhov Project qhov rai. Yog
koj tau khiav cov software ua ntej, lub qhov rais qhia txog qhov project dhau los. Yog xav paub ntxiv txog lub interface, saib Tus Neeg Siv Khoom Siv Tshajview tshooj ntawm phau ntawv qhia siv.

Tau txais kev pab
Ua ntej koj hu rau Synopsys Support, saib los ntawm cov ntaub ntawv sau tseg. Koj tuaj yeem nkag mus rau cov ntaub ntawv hauv online los ntawm Pab Pawg, lossis xa mus rau PDF version. Cov lus hauv qab no qhia koj li cas cov ntaub ntawv raug teeb tsa.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Pib pib
Rau kev pab nrog… Siv software nta Yuav ua li cas…
Cov ntaub ntawv ntws
Cov lus yuam kev Daim ntawv tso cai Cov yam ntxwv thiab cov lus qhia Synthesis nta Lus thiab syntax Tcl syntax Tcl synthesis commands Cov khoom hloov tshiab

Tshooj 1: Kev Taw Qhia
Xa mus rau… Synopsys FPGA Synthesis User Guide Synopsys FPGA Synthesis User Guide, daim ntawv teev npe ntawm kev txhawb nqa web site Synopsys FPGA Synthesis User Guide, daim ntawv sau npe ntawm kev txhawb nqa web site kev pab online (xaiv Pab-> Cov lus yuam kev) Synopsys SolvNet Website Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Phau Ntawv Kev Pab Online (xaiv Pab-> Tcl Pab) Synopsys FPGA Synthesis Reference Manual Synopsys FPGA Synthesis Reference Manual (Web menu commands)

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 1: Kev Taw Qhia

Tus neeg siv interface dhauview

Tus neeg siv interface dhauview
Tus neeg siv interface (UI) muaj lub qhov rais loj, hu ua Project view, thiab tshwj xeeb qhov rais los yog views rau cov haujlwm sib txawv. Yog xav paub meej txog txhua yam ntawm cov yam ntxwv, saib Tshooj 2, Tus Neeg Siv Khoom Siv Tshajview ntawm Synopsys FPGA Synthesis Reference Manual.

Synplify Pro Interface

Khawm Vaj Huam Sib Luag

Toolbars Project view

xwm txheej

Cov txiaj ntsig ua tiav view

Tabs nkag mus views

Tcl Script/Messages Window LO

Saib Qhov rai

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 2
FPGA Synthesis Design Flows
Tshooj lus no piav qhia txog Logic Synthesis Design Flow, ntawm nplooj 26.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 2: FPGA Synthesis Design Flows

Logic Synthesis Design Flow

Synopsys FPGA cov cuab yeej sib txuas cov logic los ntawm thawj zaug sau RTL qhov chaw rau hauv cov txheej txheem thev naus laus zis-ywj siab, thiab tom qab ntawd ua kom zoo dua thiab ua tiav cov laj thawj rau kev siv thev naus laus zis tshwj xeeb. Tom qab logic synthesis, lub cuab yeej tsim ib tus neeg muag khoom tshwj xeeb netlist thiab txwv file uas koj tuaj yeem siv los ua cov khoom siv rau qhov chaw-thiab-txoj kev (P&R) cuab yeej.
Cov duab hauv qab no qhia cov theem thiab cov cuab yeej siv rau kev sib txuas lus logic thiab qee qhov kev tawm tswv yim loj thiab cov khoom tawm. Koj tuaj yeem siv Synplify Pro synthesis software rau qhov ntws no. Lub sijhawm sib tham sib tsom xam yog xaiv tau. Txawm hais tias qhov ntws qhia tau hais tias tus neeg muag khoom txwv files raws li kev nkag ncaj qha rau P&R cov cuab yeej, koj yuav tsum ntxiv cov no files mus rau qhov project synthesis rau lub sij hawm lub thawv dub.

Synopsys FPGA Tool

RTL

RTL Muab tso ua ke

FDC

Logic Synthesis

Synthesized netlist Synthesis constraints Vendor constraints
Cov cuab yeej muag khoom
Qhov chaw & Txoj Kev

Logic Synthesis txheej txheem

Rau ib tug tsim txaus nrog cov lus qhia step-by-step raws li kev tsim tshwj xeeb

cov ntaub ntawv, download tau lub tutorial los ntawm lub webqhov chaw. Cov kauj ruam hauv qab no xaus

cov txheej txheem rau synthesizing tus tsim, uas kuj yog illustrated nyob rau hauv lub

daim duab raws li nram no.

1. Tsim ib qhov project.

2. Ntxiv qhov chaw files rau qhov project.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Logic Synthesis Design Flow

Tshooj 2: FPGA Synthesis Design Flows

3. Teem cov cwj pwm thiab kev txwv rau kev tsim.
4. Teem cov kev xaiv rau kev siv nyob rau hauv Implementation Options dialog box.
5. Nyem Khiav kom khiav logic synthesis.
6. Txheeb xyuas cov txiaj ntsig, siv cov cuab yeej zoo li lub cav file, HDL Analyst schematic views, Message window thiab Watch Window.
Tom qab koj tau ua tiav qhov tsim, koj tuaj yeem siv cov zis tawm files khiav qhov chaw-thiab-txoj kev nrog tus neeg muag khoom thiab siv FPGA.
Daim duab hauv qab no teev cov kauj ruam tseem ceeb hauv kev ntws:

Tsim qhov project
Ntxiv Qhov Chaw Files
Teeb Cov Kev Txwv
Teeb Cov Kev Xaiv
Khiav lub Software
Tshawb xyuas cov txiaj ntsig tsis muaj lub hom phiaj?
Yog Qhov Chaw thiab Txoj Kev

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 2: FPGA Synthesis Design Flows

Logic Synthesis Design Flow

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3
Npaj cov tswv yim
Thaum koj muab cov qauv tsim, koj yuav tsum teeb tsa ob hom files: HDL files uas piav txog koj tus qauv tsim, thiab qhov project files tswj tus tsim. Tshooj no piav qhia txog cov txheej txheem los teeb tsa cov no files thiab qhov project. Nws npog cov hauv qab no:
· Teeb tsa HDL qhov chaw Files, ntawm nplooj ntawv 30 · Siv Cov Lus Sib Tw Files, ntawm nplooj ntawv 44 · Siv Cov Kev Sib Txuas Ntxiv, ntawm nplooj ntawv 49 · Siv cov qauv Verilog Flow, ntawm nplooj 51 · Ua haujlwm nrog kev txwv Files, paj 53

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

Kev teeb tsa HDL Source Files
Tshooj lus no piav qhia yuav ua li cas teeb tsa koj qhov chaw files; qhov project file kev teeb tsa tau piav qhia nyob rau hauv Setting Up Project Files, ntawm nplooj ntawv 58. Source files tuaj yeem nyob hauv Verilog lossis VHDL. Yog xav paub ntxiv txog kev teeb tsa lub files rau synthesis, xa mus rau Phau Ntawv Qhia Siv. Tshooj lus no tham txog cov ncauj lus hauv qab no:
· Tsim HDL Source Files, nyob rau nplooj 30 · Siv Cov Ntsiab Lus Pab Kho Mob, nyob rau nplooj 32 · Tshawb xyuas HDL Source Files, ntawm nplooj ntawv 34 · Kho HDL Source Files nrog Cov Ntawv Sau Ua Ke, ntawm nplooj ntawv 35 · Siv Cov Ntawv Sau Sab Nraud, ntawm nplooj ntawv 41 · Kev teeb tsa Editing Qhov rai nyiam, nyob rau nplooj 39 · Siv Cov Tsev Qiv Ntawv Ntxiv rau Verilog Library Files, paj 42

Tsim HDL Source Files
Tshooj lus no piav qhia yuav ua li cas siv cov ntawv nyeem built-in los tsim qhov chaw files, tab sis tsis mus rau hauv cov ntsiab lus ntawm dab tsi lub files muaj. Yog xav paub meej txog yam koj tuaj yeem ua tau thiab tsis tuaj yeem suav nrog, nrog rau cov ntaub ntawv tshwj xeeb ntawm tus neeg muag khoom, saib phau ntawv qhia siv. Yog tias koj twb muaj qhov chaw files, koj tuaj yeem siv cov ntawv nyeem los tshawb xyuas cov syntax lossis hloov kho file (saib Txheeb Xyuas HDL Source Files, ntawm nplooj ntawv 34 thiab Hloov Kho HDL Source Files nrog Built-in Text Editor, ntawm nplooj 35).
Koj tuaj yeem siv Verilog lossis VHDL rau koj qhov chaw files. Cov files muaj v (Verilog) lossis vhd (VHDL) file extensions, feem. Koj tuaj yeem siv Verilog thiab VHDL files nyob rau hauv tib tus qauv. Yog xav paub ntxiv txog kev siv kev sib xyaw ntawm Verilog thiab VHDL cov tswv yim files, saib Siv Mixed Language Source Files,nqe 44.
1. Tsim ib qhov chaw tshiab file los yog nyem rau HDL file icon ( ) lossis ua cov hauv qab no:
Xaiv File-> Tshiab lossis nias Ctrl-n.
Hauv New dialog box, xaiv hom ntawm qhov chaw file koj xav tsim,
Verilog los yog VHDL. NotLeOthat koj tuaj yeem siv Context Help Editor rau Verilog tsim uas muaj SystemVerilog tsim hauv qhov chaw

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

file. Yog xav paub ntxiv, saib Siv Cov Ntsiab Lus Pab Kho Mob, nyob rau nplooj 32.
Yog tias koj siv Verilog 2001 hom ntawv lossis SystemVerilog, nco ntsoov ua kom lub Verilog 2001 lossis System Verilog xaiv ua ntej koj khiav synthesis (Project-> Implementation Options-> Verilog tab). Lub default Verilog file hom ntawv rau cov haujlwm tshiab yog SystemVerilog.

Ntaus lub npe thiab qhov chaw rau lub file thiab nyem OK. Ib tug dawb huv editing
lub qhov rais qhib nrog kab zauv ntawm sab laug.
2. Ntaus cov ntaub ntawv hauv lub qhov rais, lossis txiav thiab muab tso rau nws. Saib Editing HDL Source Files nrog Built-in Text Editor, nyob rau nplooj ntawv 35 kom paub ntau ntxiv txog kev ua haujlwm hauv Editing qhov rai.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

Txhawm rau kom tau txais txiaj ntsig zoo tshaj plaws, txheeb xyuas Phau Ntawv Qhia Txog Kev Siv thiab xyuas kom meej tias koj siv cov khoom tsim muaj thiab cov neeg muag khoom tshwj xeeb thiab cov lus qhia zoo.
3. Txuag cov file los ntawm kev xaiv File-> Txuag lossis txuag lub cim ( ).
Thaum koj tau tsim ib qhov chaw file, koj tuaj yeem tshawb xyuas tias koj muaj qhov zoo sib xws, raws li tau piav qhia hauv Kev Tshawb Fawb HDL Source Files,nqe 34.

Siv Cov Ntsiab Lus Pab Editor
Thaum koj tsim lossis qhib Verilog tsim file, siv cov ntsiab lus pab khawm tso tawm nyob rau hauv qab ntawm lub qhov rais los pab koj code nrog Verilog / SystemVerilog tsim hauv qhov chaw file los yog Tcl txwv commands rau hauv koj Tcl file.
Txhawm rau siv Context Help Editor:
1. Nyem rau ntawm Cov Ntsiab Lus Pab khawm kom pom cov ntawv nyeem no.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

2. Thaum koj xaiv ib lub tsev nyob rau sab laug-sab ntawm lub qhov rais, cov lus piav qhia kev pab hauv internet rau kev tsim yog tso tawm kom pom. Yog tias qhov kev tsim kho uas tau xaiv muaj qhov ua haujlwm no tau qhib, cov ncauj lus pab hauv online tau tshwm sim nyob rau sab saum toj ntawm lub qhov rais thiab cov lej lej lossis cov qauv hais kom ua rau qhov kev tsim kho yog tshwm rau hauv qab.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

3. Ntxig Template khawm kuj qhib. Thaum koj nias lub khawm Insert Template, cov cai lossis cov lus txib qhia hauv lub qhov rais template tau muab tso rau hauv koj file ntawm qhov chaw ntawm tus cursor. Qhov no tso cai rau koj yooj yim ntxig cov cai lossis cov lus txib thiab hloov kho nws rau tus qauv tsim uas koj yuav ua ke.
4. Yog hais tias koj xav luam ib feem ntawm lub template, xaiv cov cai los yog cov lus txib uas koj xav mus ntxig rau thiab nias Luam. Tom qab ntawd koj tuaj yeem paste nws rau hauv koj tus kheej file.

Tshawb xyuas HDL Source Files

Lub software cia li kuaj koj HDL qhov chaw files thaum nws compiles lawv, tab sis yog hais tias koj xav mus xyuas koj qhov chaws code ua ntej synthesis, siv cov txheej txheem hauv qab no. Muaj ob hom kev txheeb xyuas koj ua hauv software synthesis: syntax thiab synthesis.

1. Xaiv qhov chaw files koj xav mus kuaj.
Mus xyuas txhua qhov chaw files nyob rau hauv ib qhov project, deselect tag nrho files hauv
daim ntawv teev npe, thiab xyuas kom meej tias tsis muaj qhov files qhib nyob rau hauv lub qhov rais active. Yog hais tias koj muaj ib tug active qhov chaw file, lub software tsuas xyuas cov active file.
Mus xyuas ib leeg file, qhib file nrog File-> Qhib los yog ob npaug nias rau
file hauv qhov project qhov rais. Yog tias koj muaj ntau tshaj ib file qhib thiab xav tshawb xyuas tsuas yog ib qho ntawm lawv, muab koj tus cursor tso rau hauv qhov tsim nyog file qhov rais kom paub tseeb tias nws yog lub qhov rais active.

2. Txheeb xyuas cov syntax, xaiv Run-> Syntax Check lossis nias ua haujlwm + F7.

Lub software kuaj pom cov syntax yuam kev xws li cov ntsiab lus tsis raug thiab cov cim cim thiab qhia txog qhov yuam kev hauv ib lub cav cais file (syntax.log). Yog tias tsis pom qhov yuam kev, qhov kev kuaj xyuas syntax ua tiav tau tshaj tawm hauv qab ntawm qhov no file.

3. Txhawm rau khiav ib qho kev txheeb xyuas, xaiv Khiav-> Synthesis Check lossis nias ua haujlwm + F8.

Lub software kuaj xyuas cov teeb meem cuam tshuam txog hardware xws li tsis raug cai

flip-flops thiab tshaj tawm cov kev ua yuam kev hauv ib lub cav cais file (syntax.log). Yog muaj

tsis muaj qhov yuam kev, qhov kev tshawb xyuas syntax ua tiav tau tshaj tawm hauv qab ntawm qhov no

file.

4.Re Ibview qhov yuam kev los ntawm qhib lub syntax.log file thaum raug ceeb toom thiab siv Nrhiav kom pom cov lus yuam kev (nrhiav rau @E). Ob-nias ntawm qhov

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

5-tus cwj pwm yuam kev los yog nyem rau ntawm cov ntawv xov xwm thiab thawb F1 kom pom cov lus yuam kev hauv online.
5. Nrhiav ib feem ntawm cov cai ua lub luag haujlwm rau qhov yuam kev los ntawm ob-nias ntawm cov ntawv xov xwm hauv syntax.log file. Lub qhov rais Text Editor qhib qhov tsim nyog file thiab qhia txog cov cai uas ua rau muaj qhov yuam kev.
6. Rov ua cov kauj ruam 4 thiab 5 kom txog thaum tag nrho cov syntax thiab synthesis yuam kev raug kho.
Cov lus tuaj yeem muab faib ua qhov yuam kev, ceeb toom, lossis sau ntawv. Review tag nrho cov lus thiab daws tej yam tsis raug. Cov lus ceeb toom tsis tshua hnyav dua li qhov ua yuam kev, tab sis koj yuav tsum nyeem thiab nkag siab lawv txawm tias koj tsis daws tag nrho lawv. Cov ntawv sau yog qhia thiab tsis tas yuav daws.

Hloov kho HDL Source Files nrog Built-in Text Editor
Cov ntawv nyeem built-in ua rau nws yooj yim los tsim koj HDL qhov chaws, view nws, lossis kho nws thaum koj xav tau kho qhov yuam kev. Yog tias koj xav siv cov ntawv sau sab nraud, saib Siv Cov Ntawv Sau Sab Nraud, ntawm nplooj ntawv 41.
1. Ua ib qho hauv qab no kom qhib qhov chaw file rau viewlos yog kho:
Txhawm rau qhib thawj zaug file hauv daim ntawv uas tsis raug, nias F5.
Txhawm rau qhib qhov tshwj xeeb file, ob-nias lub file hauv qhov Project qhov rais los yog
siv File-> Qhib (Ctrl-o) thiab qhia qhov chaw file.
Lub qhov rais Text Editor qhib thiab qhia qhov chaw file. Cov kab yog suav. Cov lus tseem ceeb yog xiav, thiab cov lus hauv ntsuab. Cov hlua tseem ceeb yog xim liab. Yog tias koj xav hloov cov xim no, saib Kev Hloov Kho Qhov rai nyiam, ntawm nplooj ntawv 39.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

2. Kho kom raug a file, ntaus ntawv ncaj qha rau ntawm qhov rais.
Cov lus no qhia txog cov kev hloov kho uas koj siv tau. Koj tuaj yeem siv cov keyboard shortcuts tsis yog cov lus txib.

Rau…

Ua…

Txiav, luam, thiab muab tshuaj; Xaiv qhov hais kom ua los ntawm cov popup (tuav cia undo, los yog redo ib qho kev txiav txim ntawm txoj cai nas khawm) los yog Kho cov ntawv qhia zaub mov.

Mus rau ib txoj kab tshwj xeeb

Nias Ctrl-g lossis xaiv Kho kom raug-> Mus Rau, ntaus tus lej kab, thiab nyem OK.

Nrhiav cov ntawv

Nias Ctrl-f lossis xaiv Kho kom raug -> Nrhiav. Ntaus cov ntawv koj xav nrhiav, thiab nyem OK.

Hloov cov ntawv nyeem

Nias Ctrl-h lossis xaiv Kho-> Hloov. Ntaus cov ntawv koj xav nrhiav, thiab cov ntawv koj xav hloov nrog. Nyem OK.

Ua kom tiav ib lo lus tseem ceeb

Ntaus cov cim txaus los txheeb xyuas lo lus tseem ceeb, thiab nias Esc.

Indent ntawv rau sab xis Xaiv qhov thaiv, thiab nias Tab. Indent ntawv rau sab laug LSOelect lub thaiv, thiab nias Shift-Tab.

Hloov mus rau cov ntaub ntawv loj Xaiv cov ntawv nyeem, thiab tom qab ntawd xaiv Kho kom raug -> Advanced -> Uppercase lossis nias Ctrl-Shift-u.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

Rau… Hloov mus rau cov ntaub ntawv qis Ntxiv thaiv cov lus pom
Kho cov kab

Ua…
Xaiv cov ntawv nyeem, thiab xaiv Edit->Advanced -> Lowercase los yog nias Ctrl-u.
Muab tus cursor rau thaum pib ntawm cov ntawv nyeem, thiab xaiv Edit-> Advanced-> Comment Code lossis nias Alt-c.
Nias Alt, thiab siv tus nas laug khawm los xaiv kab. Ntawm qee lub platform, koj yuav tsum siv tus yuam sij uas Alt ua haujlwm tau teeb tsa, zoo li Meta lossis pob zeb diamond key.

3. Txhawm rau txiav thiab muab tshuaj txhuam ib ntu ntawm cov ntaub ntawv PDF, xaiv T-shaped Text Select icon, taw qhia cov ntawv koj xav tau thiab luam thiab muab tso rau hauv koj cov ntawv. file. Lub Text Select icon cia koj xaiv ib feem ntawm daim ntawv.
4. Tsim thiab ua haujlwm nrog bookmarks hauv koj file, saib cov lus hauv qab no.
Bookmarks yog ib txoj hauv kev yooj yim rau kev mus ntev files los yog dhia mus rau cov ntsiab lus hauv cov cai uas koj xa mus rau ntau zaus. Koj tuaj yeem siv cov cim hauv Kho kom raug toolbar rau cov haujlwm no. Yog tias koj tsis tuaj yeem pom Kho kom raug toolbar nyob rau sab xis ntawm koj lub qhov rais, hloov pauv qee qhov ntawm lwm qhov toolbars.

Rau… Ntxig ib phau ntawv
Rho tawm ib bookmark
Tshem tag nrho cov bookmarks

Ua…
Nyem qhov twg hauv kab koj xav bookmark. Xaiv Edit-> Toggle Bookmarks, nias Ctrl-F2, lossis xaiv thawj lub cim hauv Kho kom raug toolbar. Tus lej xov tooj raug qhia kom pom tias muaj ib qho bookmark ntawm qhov pib ntawm kab ntawd.
Nyem qhov twg hauv kab nrog lub bookmark. Xaiv Edit-> Toggle Bookmarks, nias Ctrl-F2, lossis xaiv thawj lub cim hauv Kho kom raug toolbar. Tus lej xov tooj yuav tsis tseem ceeb tom qab lub bookmark raug tshem tawm.
Xaiv Edit-> Rho tawm tag nrho cov Bookmarks, nias Ctrl-Shift-F2, lossis xaiv lub cim kawg hauv Kho kom raug toolbar. Cov kab zauv yuav tsis raug qhia ntxiv lawm tom qab cov bookmarks raug tshem tawm.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

Rau…
Mus rau a file siv bookmarks

Ua…
Siv Cov Ntawv Ceeb Toom Tom ntej (F2) thiab Yav dhau los Bookmark (Shift-F2) cov lus txib los ntawm Kho kom raug cov ntawv qhia zaub mov lossis cov cim sib thooj los ntawm Kho kom raug toolbar mus rau qhov bookmark koj xav tau.

5. Kho qhov yuam kev lossis rovview ceeb toom hauv qhov chaws, ua cov hauv qab no:
Qhib HDL file nrog rau qhov yuam kev los yog ceeb toom los ntawm ob-nias lub file
nyob rau hauv daim ntawv teev cov project.
Nias F5 mus rau thawj qhov yuam kev, ceeb toom, lossis ceeb toom hauv file. Nyob ntawm
hauv qab ntawm lub qhov rais Editing, koj pom cov ntawv nyeem.
Txhawm rau mus rau qhov yuam kev tom ntej, ceeb toom, lossis ceeb toom, xaiv Khiav-> Tom ntej yuam kev / Ceeb toom
los yog nias F5. Yog tsis muaj lus ntxiv nyob rau hauv file, koj pom cov lus "Tsis muaj yuam kev / ceeb toom / Sau ntawv" nyob rau hauv qab ntawm lub qhov rais Editing. Xaiv Run-> Tom ntej no yuam kev / ceeb toom los yog nias F5 mus rau qhov yuam kev, ceeb toom, los yog ceeb toom nyob rau hauv lub tom ntej no file.
Txhawm rau rov qab mus rau qhov yuam kev dhau los, ceeb toom, lossis ceeb toom, xaiv
Khiav-> Qhov yuam kev dhau los / ceeb toom lossis nias Shift-F5.
6. Txhawm rau nqa cov lus yuam kev pab rau cov lus piav qhia tag nrho ntawm qhov yuam kev, ceeb toom, lossis ceeb toom:
Qhib cov ntawv sau hom ntawv file (nias View Log) thiab ob npaug nias rau
5-tus cim yuam kev code lossis nyem rau ntawm cov ntawv sau thiab nias F1.
Qhib HTML log file thiab nyem rau ntawm 5-tus cim yuam kev code.
Hauv Tcl lub qhov rais, nyem qhov Messages tab thiab nyem rau ntawm 5-tus cim
yuam kev code hauv kab ID.
7. Rau crossprobe los ntawm lub qhov rais code qhov rais mus rau lwm yam views, qhib view thiab xaiv daim code. Saib Crossprobing los ntawm Text Editor Window, ntawm nplooj 246 kom paub meej.
8. Thaum koj tau kho tag nrho cov yuam kev, xaiv File-> Txuag lossis nyem lub cim Txuag kom txuag tau file.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa Editing Qhov rai Preferences
Koj tuaj yeem hloov kho cov fonts thiab xim siv hauv Text Editing qhov rai.
1. Xaiv Options->Editor Options thiab Synopsys Editor lossis Sab Nraud Editor. Yog xav paub ntxiv txog tus editor sab nraud, saib Siv Cov Ntawv Sau Sab Nraud, ntawm nplooj ntawv 41.
2. Ces nyob ntawm seb hom file koj qhib, koj tuaj yeem teeb tsa keeb kwm yav dhau, xim xim syntax, thiab font nyiam siv nrog cov ntawv nyeem.

Nco tseg: Tom qab ntawd, cov ntawv nyeem kev nyiam koj tau teem rau qhov no file yuav siv tau rau txhua tus files ntawm qhov no file hom.

Lub qhov rais Text Editing tuaj yeem siv los teeb tsa nyiam rau qhov project files, source files (Verilog/VHDL), log files, txl files, kev txwv files, los yog lwm yam default files los ntawm Editor Options dialog box.
3. Koj tuaj yeem teeb cov xim syntax rau qee qhov kev xaiv syntax, xws li cov ntsiab lus, cov hlua, thiab cov lus pom. Rau example v log file, ceeb toom thiab yuam kev tuaj yeem ua xim-coded kom paub yooj yim.
Nyem rau hauv Foreground lossis Background teb rau cov khoom sib xws hauv Syntax Coloring teb los tso saib cov xim palette.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

Koj tuaj yeem xaiv cov xim yooj yim lossis txhais cov xim kev cai thiab ntxiv rau koj cov xim palette. Txhawm rau xaiv koj cov xim xav tau nyem OK.
4. Txhawm rau teeb tsa font thiab font loj rau cov ntawv nyeem, siv cov ntawv rub-down.
5. Kos Khaws Tabs kom qhib tab tab, tom qab ntawd teeb lub tab sib nrug siv lub xub nce lossis nqis rau Tab Loj.

LO 6. Nyem OK ntawm daim ntawv Editor Options.
© 2014 Synopsys, Inc. 40

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

Siv tus External Text Editor
Koj tuaj yeem siv cov ntawv sau sab nraud xws li vi lossis emacs es tsis txhob siv cov ntawv sau ua ke. Ua cov hauv qab no txhawm rau pab kom muaj cov ntawv nyeem sab nraud. Yog xav paub ntxiv txog kev siv cov ntawv sau ua ke, saib Hloov Kho HDL Source Files nrog Built-in Text Editor, ntawm nplooj 35.
1. Xaiv Options->Editor Options thiab qhib qhov External Editor xaiv.
2. Xaiv tus editor sab nraud, siv cov txheej txheem tsim nyog rau koj lub operating system.
Yog tias koj tab tom ua haujlwm ntawm lub Windows platform, nyem lub pob ... (Xaiv) khawm
thiab xaiv cov ntawv nyeem sab nraud executable.
Los ntawm UNIX lossis Linux platform rau cov ntawv nyeem uas tsim nws tus kheej
lub qhov rais, nyem lub … Xauj khawm thiab xaiv cov ntawv nyeem sab nraud executable.
Los ntawm UNIX platform rau cov ntawv nyeem uas tsis tsim nws tus kheej
lub qhov rais, tsis txhob siv lub ... Saib khawm. Hloov chaw ntaus xterm -e editor. Cov duab hauv qab no qhia VI tau teev tseg raws li tus kws kho sab nraud.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Kev teeb tsa HDL Source Files

Los ntawm Linux platform, rau cov ntawv nyeem uas tsis tsim nws tus kheej
lub qhov rais, tsis txhob siv lub ... Saib khawm. Hloov chaw, ntaus gnome-terminal -x editor. Txhawm rau siv emacs rau example, ntaus gnome-terminal -x emacs.
Cov software tau raug sim nrog cov emacs thiab vi cov ntawv nyeem.
3. Nyem OK.

Siv Library Extensions rau Verilog Library Files
Cov tsev qiv ntawv txuas ntxiv tuaj yeem ntxiv rau Verilog tsev qiv ntawv files suav nrog koj tus qauv tsim rau qhov project. Thaum koj muab cov kev tshawb nrhiav rau cov npe uas muaj cov tsev qiv ntawv Verilog files, koj tuaj yeem hais qhia cov tsev qiv ntawv tshiab txuas ntxiv nrog rau Verilog thiab SystemVerilog (.v thiab .sv) file txuas ntxiv.
Ua li no:
1. Xaiv lub Verilog tab ntawm Implementation Options panel.
2. Qhia qhov chaw ntawm Lub Tsev Qiv Ntawv Phau Ntawv Qhia rau lub tsev qiv ntawv Verilog files yuav tsum suav nrog hauv koj tus qauv tsim rau qhov project.
3. Qhia cov tsev qiv ntawv Extensions.
Txhua lub tsev qiv ntawv txuas ntxiv tuaj yeem raug teev tseg, xws li .av, .bv, .cv, .xxx, .va, .vas ( cais tsev qiv ntawv txuas ntxiv nrog qhov chaw).
Cov duab hauv qab no qhia koj qhov twg nkag mus rau lub tsev qiv ntawv txuas ntxiv ntawm lub dialog box.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa HDL Source Files

Tshooj 3: Npaj cov tswv yim

Tcl sib npaug rau qhov example yog cov lus txib nram qab no:
set_option -libext .av .bv .cv .dv .ev
Yog xav paub ntxiv, saib libext, ntawm nplooj ntawv 57 nyob rau hauv Cov Lus Qhia Siv.
4. Tom qab koj sau cov qauv tsim, koj tuaj yeem tshawb xyuas hauv lub cav file tias lub tsev qiv ntawv files nrog cov extensions no tau loaded thiab nyeem. Rau example:
@N: Khiav Verilog Compiler hauv SystemVerilog hom @I::"C:dirtop.v" @N: CG1180 :"C:dirtop.v":8:0:8:3|Loading file C:dirlib1sub1.av los ntawm cov tsev qiv ntawv teev npe C:dirlib1 @I::"C:dirlib1sub1.av" @N: CG1180 :"C:dirtop.v":10:0:10:3|Loading file C:dirlib2sub2.bv los ntawm cov tsev qiv ntawv teev npe C:dirlib2 @I::"C:dirlib2sub2.bv" @N: CG1180 :"C:dirtop.v":12:0:12:3|Loading file

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Siv cov lus sib xyaw Files

C:dirlib3sub3.cv los ntawm cov chaw qiv ntawv teev npe C:dirlib3 @I::"C:dirlib3sub3.cv" @N: CG1180 :"C:dirtop.v":14:0:14:3|Loading file C:dirlib4sub4.dv los ntawm cov tsev qiv ntawv teev npe C:dirlib4 @I::"C:dirlib4sub4.dv" @N: CG1180 :"C:dirtop.v":16:0:16:3|Loading file C:dirlib5sub5.ev los ntawm cov tsev qiv ntawv teev npe C:dirlib5 @I::"C:dirlib5sub5.ev" Verilog syntax check ua tiav!

Siv cov lus sib xyaw Files
Nrog rau Synplify Pro software, koj tuaj yeem siv qhov sib xyaw ntawm VHDL thiab Verilog cov tswv yim files hauv koj qhov project. Rau examples ntawm VHDL thiab Verilog files, saib phau ntawv qhia siv.
1. Nco ntsoov tias Verilog tsis txhawb VHDL cov chaw nres nkoj uas tsis muaj kev txwv thiab teeb tsa cov lus sib xyaw files raws.
2. Yog tias koj xav npaj cov Verilog thiab VHDL files nyob rau hauv ntau folders, xaiv Options->Project View Options thiab toggle ntawm lub View Qhov project Files hauv Folders xaiv.
Thaum koj ntxiv cov files rau qhov project, Verilog thiab VHDL files yog nyob rau hauv nyias folders nyob rau hauv qhov Project view.
3. Thaum koj qhib ib qhov project lossis tsim ib qho tshiab, ntxiv Verilog thiab VHDL files raws li nram no:
Xaiv qhov Project-> Ntxiv Source File hais kom ua los yog nyem qhov Add File khawm. Ntawm daim ntawv, teem Files ntawm Hom rau HDL Files (*.vhd, *.vhdl, *.v). Xaiv cov Verilog thiab VHDL files koj xav tau thiab ntxiv lawv rau koj
qhov project. Nyem OK. Yog xav paub ntxiv txog kev ntxiv files mus rau ib qhov project, saib Kev Hloov Kho rau ib qhov project, nyob rau nplooj 62.
LO

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Siv cov lus sib xyaw Files

Tshooj 3: Npaj cov tswv yim

Cov files koj ntxiv yog tso tawm nyob rau hauv qhov Project view. Daim duab no qhia tau hais tias files teem nyob rau hauv nyias folders.
4. Thaum koj teeb tsa cov kev xaiv ntaus ntawv (Ib qho kev xaiv xaiv khawm), qhia cov qib sab saum toj. Yog xav paub ntxiv txog kev teeb tsa cov cuab yeej xaiv, saib Teem Logic Synthesis Implementation Options, ntawm nplooj 75.
Yog hais tias lub sab saum toj-theem module yog Verilog, nyem lub Verilog tab thiab ntaus lub
lub npe ntawm lub sab saum toj module.
Yog hais tias lub sab saum toj module yog VHDL, nyem lub VHDL tab thiab ntaus lub npe
ntawm qhov chaw saum toj kawg nkaus. Yog hais tias lub sab saum toj module tsis nyob rau hauv lub neej ntawd lub tsev qiv ntawv ua hauj lwm, koj yuav tsum qhia kom meej lub tsev qiv ntawv uas lub compiler yuav nrhiav tau lub module. Yog xav paub ntxiv txog yuav ua li cas, saib VHDL Vaj Huam Sib Luag, ntawm nplooj 200.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Siv cov lus sib xyaw Files

Koj yuav tsum tau qhia meej meej rau theem sab saum toj module, vim tias nws yog qhov pib ntawm qhov uas tus mapper tsim ib qho kev sib koom ua ke netlist.
5. Xaiv qhov Kev Ua Tau Zoo tab ntawm tib daim ntawv thiab xaiv ib qho kev tso zis HDL rau cov zis files generated los ntawm software. Yog xav paub ntxiv txog kev teeb tsa cov cuab yeej xaiv, saib Teem Logic Synthesis Implementation Options, ntawm nplooj 75.
Rau Verilog tso zis netlist, xaiv Sau Verilog Netlist. Rau VHDL tso zis netlist, xaiv Sau VHDL Netlist. Teem lwm yam kev xaiv ntaus ntawv thiab nyem OK.
Tam sim no koj tuaj yeem tsim koj tus qauv tsim. Lub software nyeem nyob rau hauv cov ntaub ntawv sib xyaw ntawm qhov chaw files thiab generates ib srs file uas yog siv rau synthesis.
6. Yog tias koj ntsib teeb meem, mus saib Troubleshooting Mixed Language Designs, nyob rau nplooj 47 yog xav paub ntxiv thiab cov lus qhia.
LO

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Siv cov lus sib xyaw Files

Tshooj 3: Npaj cov tswv yim

Troubleshooting Mixed Language Designs
Tshooj lus no muab cov lus qhia txog kev tuav cov xwm txheej tshwj xeeb uas tuaj yeem tsim cov lus sib xyaw.

VHDL File Kev txiav txim
Rau VHDL-tsuas yog cov qauv tsim lossis cov qauv sib xyaw uas cov qib siab tshaj plaws tsis tau teev tseg, FPGA cov cuab yeej sib txuas tau txiav txim siab rov teeb tsa VHDL files kom cov pob VHDL tau muab tso ua ke kom raug.
Txawm li cas los xij, yog tias koj muaj kev sib xyaw hom lus uas koj tau teev saum toj kawg nkaus, koj yuav tsum qhia VHDL file xaj rau lub cuab yeej. Koj tsuas yog yuav tsum ua qhov no ib zaug, los ntawm kev xaiv Run-> Teem VHDL files lus. Yog tias koj tsis ua qhov no, koj tau txais cov lus yuam kev.

VHDL Ntiaj Teb Cov Teeb Meem
Tam sim no, koj tsis tuaj yeem muaj VHDL ntiaj teb cov teeb liab hauv cov qauv lus sib xyaw, vim tias lub cuab yeej tsuas yog siv cov teeb liab no hauv VHDL nkaus xwb.

Dhau VHDL Boolean Generics rau Verilog Parameters
Cov cuab yeej infers lub thawv dub rau VHDL tivthaiv nrog Boolean generics, yog hais tias cov khoom yog instantiated nyob rau hauv ib tug Verilog tsim. Qhov no yog vim Verilog tsis paub hom ntaub ntawv Boolean, yog li tus nqi Boolean yuav tsum raug sawv cev kom raug. Yog tias tus nqi ntawm VHDL Boolean generic yog TRUE thiab Verilog literal yog sawv cev los ntawm 1, Verilog compiler txhais qhov no yog lub thawv dub.
Txhawm rau kom tsis txhob cuam tshuam lub thawv dub, Verilog literal rau VHDL Boolean generic teem rau TRUE yuav tsum yog 1'b1, tsis yog 1. Ib yam li ntawd, yog tias VHDL Boolean generic yog FALSE, qhov sib txuas Verilog literal yuav tsum yog 1'b0, tsis yog 0. Cov nram qab no ex.ample qhia yuav ua li cas los sawv cev rau Boolean generics kom lawv ua raws li VHDL-Verilog ciam teb, tsis muaj inferring lub thawv dub.

VHDL Qhov Chaw Tshaj Tawm

Verilog Instantiation

Entity abc yog Generic (
Number_Bits Faib_Bit );

: integer: boolean

:=0; := Tsis tseeb;

abc #( .Number_Bits (16), .Divide_Bit (1'b0)
)

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Siv cov lus sib xyaw Files

Hla VHDL Generics yam tsis muaj kev cuam tshuam lub thawv dub
Nyob rau hauv rooj plaub uas Verilog tivthaiv parameter, (example [0:0] RSR = 1'b0) tsis phim qhov loj ntawm qhov sib thooj VHDL tivthaiv generic (RSR : integer := 0), cov cuab yeej infers lub thawv dub.
Koj tuaj yeem ua haujlwm ib ncig ntawm qhov no los ntawm kev tshem cov npav dav dav ntawm [0: 0] hauv Verilog files. Nco ntsoov tias koj yuav tsum siv VHDL generic ntawm hom integer vim tias lwm hom tsis tso cai rau kev khi zoo ntawm Verilog tivthaiv.

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Siv Incremental Compiler

Tshooj 3: Npaj cov tswv yim

Siv Incremental Compiler
Siv Incremental Compiler flow kom txo qis compiler runtime rau cov qauv loj. Lub software recompiles tsuas yog cuam tshuam files thaum tsim kev hloov pauv tsim thiab rov siv cov ntaub ntawv compiler. Lub compiler regenerates SRS file tsuas yog rau qhov cuam tshuam module thiab tam sim niam txiv module.
Txhawm rau khiav qhov dej no, ua cov hauv qab no:
1. Ntxiv Verilog lossis VHDL files rau kev tsim.
2. Pab kom Incremental Compile xaiv los ntawm Verilog lossis VHDL tab ntawm Kev Xaiv Kev Xaiv vaj huam sib luag.
Ib SRS file yog tsim rau txhua tus qauv tsim nyob rau hauv synwork directory.

3. Khiav lub compiler thawj zaug.
4. Yog tias muaj kev hloov pauv tsim, rov ua dua lub compiler.
Lub compiler txheeb xyuas cov ntaub ntawv thiab txiav txim siab seb SRS files yog hloov tshiab, ces tsuas yog modules uas tau hloov thiab tam sim no niam txiv modules yog regenerated. Qhov no tuaj yeem pab txhim kho lub sijhawm ua haujlwm rau kev tsim.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Siv Incremental Compiler

Kev txwv
Incremental compiler tsis txhawb:
· Configuration files suav nrog Verilog lossis VHDL ntws · Mixed HDL ntws · Cov qauv tsim nrog cross module referencing (XMR)

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Siv tus qauv Verilog Flow

Tshooj 3: Npaj cov tswv yim

Siv tus qauv Verilog Flow
Cov cuab yeej synthesis lees txais cov qauv Verilog files raws li cov tswv yim rau koj qhov project tsim. Tus txheej txheem Verilog compiler ua syntax semantic checks siv nws lub teeb parser los txhim kho runtime. Cov compiler no tsis ua cov khoom siv kho vajtse nyuaj lossis RTL optimization ua haujlwm, yog li ntawd, cov software khiav ceev ceev ntawm cov qauv Verilog. files. Lub software tuaj yeem nyeem cov qauv tsim Verilog files, yog tias lawv muaj:
· Instantitions ntawm technology primitives
· Yooj yim muab nqe lus
· Cov cwj pwm tau teev tseg hauv Verilog 2001 thiab cov qauv qub
· Tag nrho cov tsim, tshwj tsis yog cov cwj pwm yuav tsum tau teev nyob rau hauv Verilog 95 hom
Siv cov qauv Verilog input files:
1. Koj yuav tsum qhia kom meej tus qauv Verilog files suav nrog hauv koj tus qauv tsim. Ua li no, ntxiv cov file rau qhov project siv ib qho ntawm cov hauv qab no:
Project-> Ntxiv Source File los yog Add File khawm hauv qhov Project view Tcl command: add_file -structver fileLub npe
Qhov kev ntws no tuaj yeem muaj cov qauv Verilog nkaus xwb files los yog sib xyaw HDL files (Verilog/VHDL/EDF/SRS) nrog rau cov qauv Verilog netlist files. Txawm li cas los xij, Verilog / VHDL / EDF / SRS piv txwv tsis tau txais kev txhawb nqa hauv cov qauv Verilog module.
2. Tus qauv Verilog files tau ntxiv rau Structural Verilog nplaub tshev hauv qhov Project view. Koj tuaj yeem ntxiv files rau phau ntawv no, thaum koj ua cov hauv qab no:
Xaiv tus qauv Verilog file. Right-click thiab xaiv File Kev xaiv. Xaiv Cov Qauv Verilog los ntawm File Ntaus cov ntawv qhia zaub mov nco-down.
3. Khiav synthesis.
Cov cuab yeej synthesis generates vm lossis edf netlist file nyob ntawm cov tshuab tau teev tseg. Cov txheej txheem no zoo ib yam li cov txheej txheem synthesis ntws.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Siv tus qauv Verilog Flow

Kev txwv
Kev txwv ntawm cov qauv Verilog ntws tsis txhawb cov hauv qab no:
· RTL piv txwv rau lwm yam file hom · Hierarchical project management (HPM) flows · Complex assignments · Compiler-specific modes and switches

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Ua haujlwm nrog kev txwv Files

Tshooj 3: Npaj cov tswv yim

Ua haujlwm nrog kev txwv Files
Kev txwv files yog text files uas tau txais kev tsim los ntawm SCOPE interface (saib Specifying SCOPE Constraints, ntawm nplooj ntawv 119), lossis uas koj tsim manually nrog cov ntawv nyeem. Lawv muaj Tcl cov lus txib lossis cov cwj pwm uas txwv kev sib txuas ua haujlwm. Xwb, koj tuaj yeem teeb tsa cov kev txwv hauv qhov chaws, tab sis qhov no tsis yog txoj kev nyiam.
Tshooj lus no muaj cov ntaub ntawv hais txog
· Thaum Yuav Siv Kev Txwv Files dhau Source Code, ntawm nplooj 53
· Siv cov ntawv nyeem rau kev txwv Files (Legacy), ntawm nplooj 54
· Tcl Syntax Guidelines for Constraint Files, paj 55
· Txheeb xyuas qhov txwv Files, paj 56
· Yog xav paub meej txog tsab ntawv ceeb toom no, saib Daim Ntawv Ceeb Toom Kev Ntsuam Xyuas Kev Txwv, ntawm
nplooj 270. ntawm Phau Ntawv Qhia Txog Kev Siv, nyob rau nplooj 56

Thaum Yuav Siv Kev Txwv Files dhau Source Code
Koj tuaj yeem ntxiv cov kev txwv hauv kev txwv files (tsim los ntawm SCOPE interface lossis nkag rau hauv cov ntawv nyeem) lossis hauv qhov chaws. Feem ntau, nws yog qhov zoo dua los siv kev txwv files, vim tias koj tsis tas yuav rov ua dua rau cov kev txwv kom siv tau. Nws kuj ua rau koj qhov chaws tuaj yeem yooj yim dua. Saib Siv SCOPE Editor, ntawm nplooj 112 kom paub ntau ntxiv.
Txawm li cas los xij, yog tias koj muaj lub thawv dub lub sijhawm txwv xws li syn_tco, syn_tpd, thiab syn_tsu, koj yuav tsum sau lawv raws li cov lus qhia hauv qhov chaws. Tsis zoo li cov cwj pwm, cov lus qhia tsuas yog ntxiv rau hauv qhov chaws, tsis txwv files. Saib Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia, ntawm nplooj 90 kom paub ntau ntxiv txog kev ntxiv cov lus qhia rau qhov chaws.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Ua haujlwm nrog kev txwv Files

Siv tus Text Editor rau kev txwv Files (Legacy)
Koj tuaj yeem siv Legacy SCOPE editor rau SDC txwv files tsim ua ntej tso tawm version G-2012.09. Txawm li cas los xij, nws raug nquahu kom koj txhais koj tus SDC files rau FDC files kom pab tau qhov tseeb version ntawm SCOPE editor thiab siv lub sijhawm txhim kho kev txwv tuav hauv lub cuab yeej.
Yog tias koj xaiv siv cov cuab yeej cuab tam SCOPE, ntu no qhia koj yuav ua li cas los tsim ib qho kev txwv Tcl file. Lub software yeej tsim qhov no file yog tias koj siv qhov qub SCOPE editor los nkag rau cov kev txwv. Tcl kev txwv file tsuas muaj kev txwv lub sij hawm. Cov kev txwv lub thawv dub yuav tsum tau nkag rau hauv qhov chaws. Yog xav paub ntxiv, saib Thaum Yuav Siv Kev Txwv Files dhau Source Code, ntawm nplooj 53.
1. Qhib a file rau kho.
Nco ntsoov tias koj tau kaw lub qhov rais SCOPE, lossis koj tuaj yeem ua tau
overwrite cov kev txwv yav dhau los.
Tsim ib tug tshiab file, xaiv File-> Tshiab, thiab xaiv qhov txwv File
(SCOPE) kev xaiv. Sau lub npe rau lub file thiab nias OK.
Kho qhov uas twb muaj lawm file, xaiv File-> Qhib, teeb tsa Files ntawm hom lim rau
Kev txwv Files (sdc) thiab qhib lub file koj xav.
2. Ua raws li cov txheej txheem syntax hauv Tcl Syntax Guidelines for Constraint Files,nqe 55.
3. Nkag mus rau lub sijhawm txwv koj xav tau. Rau cov syntax, saib Phau Ntawv Qhia Kev Siv. Yog tias koj muaj lub sijhawm teem sijhawm ntawm lub thawv dub, koj yuav tsum sau lawv hauv qhov chaws.
4. Koj tuaj yeem ntxiv cov yam ntxwv tshwj xeeb ntawm tus neeg muag khoom hauv qhov txwv file siv define_attribute. Saib Specifying Attributes in the Constraints File, nyob rau nplooj 97 yog xav paub ntxiv.
5. Txuag cov file.
6. Ntxiv cov file mus rau qhov project raws li tau piav qhia hauv Kev Hloov Kho rau Ib Qhov Kev Pabcuam, nyob rau nplooj 62, thiab khiav synthesis.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Ua haujlwm nrog kev txwv Files

Tshooj 3: Npaj cov tswv yim

Tcl Syntax Guidelines for Constraint Files
Tshooj lus no suav nrog cov lus qhia dav dav rau kev siv Tcl rau kev txwv files:
· Tcl yog case-sensitive.
· Rau npe cov khoom: Lub npe khoom yuav tsum phim lub npe hauv HDL code. Muab piv txwv thiab cov npe chaw nres nkoj hauv curly braces { }. Tsis txhob siv qhov chaw hauv cov npe. Siv lub dot (.) cais cov npe hierarchical. Hauv Verilog modules, siv cov syntax hauv qab no piv txwv li, chaw nres nkoj, thiab
net npe:
v:cell [prefix:]objectName
Qhov twg ntawm tes yog lub npe ntawm qhov tsim qauv, prefix yog ib qho ua ntej los txheeb xyuas cov khoom nrog tib lub npe, objectName yog ib qho piv txwv txoj hauv kev nrog dot (.) cais. Lub prefix tuaj yeem yog ib qho ntawm cov hauv qab no:

Prefix (Lab-case) i: p: b: n:

Object Instance npe Chaw nres nkoj npe (tag nrho qhov chaw nres nkoj) Me ntsis hlais ntawm qhov chaw nres nkoj Net npe

Hauv VHDL modules, siv cov syntax hauv qab no piv txwv li, chaw nres nkoj, thiab net
Cov npe hauv VHDL modules:
v: cev [.view] [prefix:]objectName
Qhov twg v: qhia tias nws yog a view object, lib yog lub npe ntawm lub tsev qiv ntawv, cell yog lub npe ntawm tus tsim qauv, view yog ib lub npe rau lub architecture, prefix yog ib tug prefix los txheeb xyuas cov khoom nrog tib lub npe, thiab objectName yog ib qho piv txwv txoj kev nrog lub dot (.) separator. View tsuas yog xav tau yog tias muaj ntau tshaj ib qho architecture rau kev tsim. Saib cov lus saum toj no rau cov khoom ua ntej.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 3: Npaj cov tswv yim

Ua haujlwm nrog kev txwv Files

· Lub npe piv cov tsiaj qus yog * (asterisk phim ib tus lej ntawm
cov cim) thiab? (cov lus nug cim phim ib tus cim). Cov cim no tsis phim cov dots siv los ua hierarchy separators. Rau example, cov hlua hauv qab no qhia tag nrho cov khoom ntawm statereg piv txwv hauv statemod module:
i:statemod.statereg[*]

Tshawb xyuas qhov txwv Files
Koj tuaj yeem tshawb xyuas syntax thiab lwm yam ntaub ntawv tseem ceeb ntawm koj qhov kev txwv files siv Constraint Check hais kom ua. Txhawm rau tsim ib daim ntawv ceeb toom txwv, ua cov hauv qab no:
1. Tsim kom muaj kev txwv file thiab ntxiv rau koj qhov project.
2. Xaiv Run-> Constraint Check.
Cov lus txib no tsim cov ntawv tshaj tawm uas kuaj xyuas cov syntax thiab siv tau ntawm lub sijhawm txwv nyob rau hauv FPGA synthesis txwv files rau koj qhov project. Daim ntawv tshaj tawm tau sau rau qhov projectName_cck.rpt file thiab sau cov ntaub ntawv hauv qab no:
Cov kev txwv uas tsis siv Cov Kev txwv uas siv tau thiab siv tau rau tus tsim Wildcard nthuav dav ntawm cov kev txwv Kev txwv ntawm cov khoom uas tsis muaj nyob
Yog xav paub meej txog tsab ntawv ceeb toom no, mus saib Daim Ntawv Qhia Txog Kev Txiav Txim Siab, ntawm nplooj ntawv 270.of Phau Ntawv Qhia Txog Kev Siv

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4
Kev teeb tsa Logic Synthesis Project
Thaum koj tsim cov qauv tsim nrog Synopsys FPGA cov cuab yeej sib txuas, koj yuav tsum teeb tsa ib qhov project rau koj tus tsim. Cov hauv qab no piav qhia txog cov txheej txheem rau kev teeb tsa ib qhov project rau logic synthesis:
· Teeb tsa qhov project Files, ntawm nplooj ntawv 58 · Tswj Project File Hierarchy, nyob rau nplooj 66 · Kev teeb tsa kev siv, nyob rau nplooj 72 · Teem caij Logic Synthesis Implementation Options, nyob rau nplooj 75 · Qhia cov cwj pwm thiab cov lus qhia, nyob rau nplooj 90 · Nrhiav Files, ntawm nplooj ntawv 98 · Archiving Files thiab Projects, ntawm nplooj 101

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa qhov project Files

Kev teeb tsa qhov project Files
Tshooj lus no piav qhia txog cov hauv paus ntawm kev teeb tsa thiab tswj qhov project file rau koj tus qauv tsim, suav nrog cov ntaub ntawv hauv qab no:
· Tsim ib qhov project File, nyob rau nplooj 58 · Qhib ib qhov project uas twb muaj lawm File, nyob rau nplooj 61 · Ua Kev Hloov Rau Ib Qhov Kev Ua Haujlwm, nyob rau nplooj 62 · Teeb Qhov Project View Zaub Preferences, nyob rau nplooj 63 · Hloov kho Verilog suav nrog Txoj Kev hauv Cov Haujlwm Loj Files, paj 65
Rau ib qho example ntawm kev teeb tsa ib qhov project file, xa mus rau cov lus qhia rau lub cuab yeej koj siv.

Tsim ib qhov project File
Koj yuav tsum teeb tsa ib qhov project file rau txhua qhov project. Ib qhov project muaj cov ntaub ntawv xav tau rau ib qho kev tsim tshwj xeeb: cov npe ntawm qhov chaw files, cov ntsiab lus synthesis file, thiab koj ntaus ntawv xaiv chaw. Cov txheej txheem hauv qab no qhia koj yuav ua li cas teeb tsa ib qhov project file siv tus kheej cov lus txib.
1. Pib los ntawm xaiv ib qho ntawm cov hauv qab no: File-> Tsim Project, File-> Qhib Project, lossis P icon. Nyem Tshiab Project.
Qhov Project qhov rai qhia qhov project tshiab. Nyem qhov Ntxiv File khawm, nias F4, lossis xaiv qhov Project-> Ntxiv Qhov Chaw File lus txib. Qhov Add Files rau Project dialog box qhib.
2. Ntxiv qhov chaw files rau qhov project.
Nco ntsoov saib hauv daim teb nyob rau sab saum toj ntawm daim ntawv taw qhia rau sab xis
phau ntawv. Cov files tau teev nyob rau hauv lub thawv. Yog koj tsis pom cov files, check tias Files ntawm Hom teb yog teem los tso saib qhov tseeb file hom. Yog hais tias koj muaj mix input files, ua raws li cov txheej txheem tau piav qhia hauv Kev Siv Cov Lus Sib Txuas Files,nqe 44.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa qhov project Files

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Ntxiv tag nrho cov files nyob rau hauv phau ntawv qhia ib zaug, nyem qhov Add All khawm rau
sab xis ntawm daim ntawv. Ntxiv files tus kheej, nyem rau ntawm file nyob rau hauv daim ntawv thiab ces nias lub Add khawm, los yog ob-nias lub file npe.
Koj tuaj yeem ntxiv tag nrho cov files nyob rau hauv phau ntawv qhia thiab ces tshem tawm cov uas koj tsis xav tau nrog lub Remove khawm.
Yog tias koj ntxiv VHDL files, xaiv lub tsev qiv ntawv tsim nyog los ntawm VHDL Library popup ntawv qhia zaub mov. Lub tsev qiv ntawv koj xaiv yog siv rau txhua VHDL files thaum koj nias OK nyob rau hauv lub dialog box.
Koj qhov project qhov rais qhia txog qhov project tshiab file. Yog tias koj nyem rau ntawm lub cim ntxiv ib sab ntawm qhov project thiab nthuav nws, koj pom cov hauv qab no:
Ib daim nplaub tshev (ob folders rau cov lus sib xyaw tsim) nrog rau qhov chaw files.
Yog koj files tsis nyob hauv ib daim nplaub tshev nyob rau hauv qhov project directory, koj tuaj yeem teeb qhov kev nyiam no los ntawm kev xaiv Options-> Project View Options thiab xyuas cov View qhov project files hauv folders box. Qhov no cais ib hom file los ntawm lwm qhov hauv qhov Project view los ntawm muab lawv nyob rau hauv nyias folders.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa qhov project Files

Qhov kev siv, npe rev_1 los ntawm lub neej ntawd. Kev siv yog
kev hloov kho ntawm koj tus qauv tsim nyob rau hauv cov ntsiab lus ntawm cov synthesis software, thiab tsis txhob hloov lwm qhov code tswj software thiab cov txheej txheem. Ntau qhov kev siv tso cai rau koj hloov kho cov cuab yeej thiab kev sib txuas los tshawb nrhiav cov kev xaiv tsim. Koj tuaj yeem muaj ntau qhov kev siv hauv Synplify Pro. Txhua qhov kev siv nws muaj nws tus kheej synthesis thiab kev xaiv khoom siv thiab nws tus kheej txoj haujlwm ntsig txog files.

3. Ntxiv cov tsev qiv ntawv uas koj xav tau, siv cov txheej txheem tau piav qhia hauv cov kauj ruam dhau los ntxiv rau Verilog lossis VHDL lub tsev qiv ntawv file.
Rau cov khw muag khoom tshwj xeeb, ntxiv cov tsev qiv ntawv tsim nyog file mus rau
qhov project. Nco ntsoov tias rau qee cov tsev neeg, cov tsev qiv ntawv tau thauj khoom cia thiab koj tsis tas yuav ntxiv lawv rau qhov project. file.
Ntxiv rau lub tsev qiv ntawv VHDL thib peb, ntxiv qhov tsim nyog .vhd file mus rau tus tsim, raws li tau piav nyob rau hauv kauj ruam 2. Txoj nyem rau file hauv qhov Project view thiab xaiv File Kev xaiv, lossis xaiv qhov Project-> Teem VHDL tsev qiv ntawv. Qhia lub npe tsev qiv ntawv uas sib haum nrog cov simulators. Rau example, MYLIB. Nco ntsoov tias lub tsev qiv ntawv pob no yog ua ntej tus qauv tsim saum toj kawg nkaus hauv daim ntawv teev npe files hauv Project view.
Yog xav paub ntxiv txog kev teeb tsa Verilog thiab VHDL file cov kev xaiv, saib Setting Verilog thiab VHDL Options, nyob rau nplooj 84. Koj tuaj yeem teeb tsa cov no file xaiv tom qab, ua ntej khiav synthesis.
Yog xav paub ntxiv txog tus neeg muag khoom tshwj xeeb txog kev siv cov chaw muag khoom macro tsev qiv ntawv thiab bLoOxes dub, saib Optimizing for Microsemi Designs, ntawm nplooj 487.
Rau cov khoom siv thev naus laus zis, koj tuaj yeem ntxiv cov
technology-kev ywj pheej Verilog tsev qiv ntawv muab nrog software

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa qhov project Files

Tshooj 4: Kev teeb tsa Logic Synthesis Project

(install_dir/lib/generic_ thev naus laus zis/gtech.v) rau koj tus qauv tsim, lossis ntxiv koj lub tsev qiv ntawv generic tivthaiv. Tsis txhob siv ob qho tib si ua ke vim muaj kev tsis sib haum xeeb.
4. Tshawb xyuas file xaj hauv qhov Project view. File kev txiav txim yog qhov tseem ceeb tshwj xeeb rau VHDL files.
Rau VHDL files, koj tuaj yeem txiav txim qhov files by
xaiv Run-> Teem VHDL Files. Xwb, manually txav lub files hauv Project view. Pob files yuav tsum ua ntej ntawm daim ntawv vim tias lawv tau muab tso ua ke ua ntej lawv siv. Yog tias koj muaj kev tsim blocks kis tau ntau dua files, xyuas kom koj muaj cov hauv qab no file order: ua file muaj qhov chaw yuav tsum yog thawj zaug, tom qab ntawd los ntawm architecture file, thiab thaum kawg lub file nrog rau configuration.
Hauv qhov project view, xyuas tias kawg file hauv qhov Project view yog cov
qhov chaw saum toj kawg nkaus file. Xwb, koj tuaj yeem teev cov qib saum toj kawg nkaus file thaum koj teeb tsa cov kev xaiv ntaus ntawv.
5. Xaiv File-> Txuag, ntaus lub npe rau qhov project, thiab nyem Txuag. Qhov Project qhov rai qhia txog koj cov kev hloov pauv.
6. Kaw ib qhov project file, xaiv Kaw Project khawm lossis File-> Kaw qhov project.

Qhib qhov project uas twb muaj lawm File
Muaj ob txoj hauv kev qhib qhov project file: Open Project and the generic File -> Qhib hais kom ua.
1. Yog tias qhov project koj xav qhib yog ib qho uas koj tau ua haujlwm tsis ntev los no, koj tuaj yeem xaiv nws ncaj qha: File-> Cov Haujlwm Tsis ntev los no-> projectName.
2. Siv ib qho ntawm cov hauv qab no los qhib ib qhov project file:

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Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa qhov project Files

Qhib Project Command

File-> Qhib Command

Xaiv File-> Qhib Project, nyem rau ntawm pob Qhib Project nyob rau sab laug ntawm lub qhov rais Project, los yog nyem rau P icon.
Txhawm rau qhib qhov project tsis ntev los no, nyem ob npaug rau nws los ntawm cov npe ntawm cov haujlwm tsis ntev los no.
Txwv tsis pub, nyem lub pob Qhov project uas twb muaj lawm los qhib lub thawv qhib thiab xaiv qhov project.

Xaiv File-> Qhib.
Qhia kom meej cov npe raug nyob rau hauv Saib Hauv: teb.
Teeb File ntawm Type to Project Files (*.prj). Lub thawv teev qhov project files.
Ob-nias ntawm qhov project koj xav qhib.

Qhov project qhib nyob rau hauv lub qhov rais Project.

Ua Kev Hloov Rau Ib Qhov Haujlwm
Feem ntau, koj ntxiv, rho tawm, lossis hloov files.
1. Ntxiv qhov los yog txwv files rau ib qhov project, xaiv qhov Ntxiv Files khawm lossis Project-> Ntxiv Source File qhib qhov Xaiv Files Ntxiv rau qhov Project dialog box. Saib Tsim Ib Qhov Project File, nyob rau nplooj 58 kom paub meej.
2. Txhawm rau rho tawm a file los ntawm ib qhov project, nyem qhov file nyob rau hauv qhov project qhov rais, thiab nias lub Delete key.
3. Hloov a file hauv ib qhov project,
Xaiv tus file koj xav hloov nyob rau hauv qhov Project qhov rais.
Nyem qhov Hloov File khawm, lossis xaiv Project-> Hloov File.
Hauv Qhov Chaw File dialog box uas qhib, teem Saib rau hauv phau ntawv qhia
qhov nov file yog nyob. Qhov tshiab file yuav tsum yog tib yam li cov file koj xav hloov.
Yog koj tsis pom koj file teev, xaiv hom file koj xav tau los ntawm
tus Files ntawm hom teb.
Double-click lub file. Qhov tshiab file hloov qhov qub hauv qhov project
lis. LO
4. Qhia kom meej li cas qhov project files tau txais kev cawmdim hauv qhov project, txoj nyem rau ntawm a file hauv qhov Project view thiab xaiv File Kev xaiv. Teem lub Txuag File kev xaiv rau tus txheeb ze rau qhov Project lossis Absolute Path.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa qhov project Files

Tshooj 4: Kev teeb tsa Logic Synthesis Project

5. Txheeb xyuas lub sijhawm stamp ntawm a file, right click rau a file hauv qhov Project view thiab xaiv File Kev xaiv. Tshawb xyuas lub sijhawm uas cov file tau hloov kho kawg. Nyem OK.

Kev teeb tsa qhov project View Zaub Preferences
Koj tuaj yeem kho lub koom haum thiab tso saib ntawm qhov project files. 1. Xaiv Options->Project View Kev xaiv. Txoj Haujlwm View Options form qhib.

2. Los npaj ntau hom kev tawm tswv yim files nyob rau hauv cais folders, kos View Qhov project Files hauv Folders.
Txheeb xyuas qhov kev xaiv no tsim cov folders cais hauv qhov Project view rau kev txwv files thiab qhov chaw files.

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Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa qhov project Files

3. Tswj file tso saib nrog cov hauv qab no:
Automatically tso saib tag nrho cov files, los ntawm kev txheeb xyuas Show Project Library. Yog
qhov no yog unchecked, qhov Project view tsis tso saib files kom txog thaum koj nyem rau ntawm lub cim ntxiv thiab nthuav cov files nyob rau hauv ib daim ntawv tais ceev tseg.
Kos ib lub thawv hauv qhov Project File Lub npe Display section ntawm lub
daim ntawv los txiav txim seb yuav ua li cas filecov npe raug tso tawm. Koj tuaj yeem tso saib xwb filelub npe, txoj kev txheeb ze, los yog txoj kev tseeb.
4. To view qhov project files nyob rau hauv customized custom folders, kos View Qhov project Files hauv Custom Folders. Yog xav paub ntxiv, saib Creating Custom Folders, ntawm nplooj ntawv 66. Hom folders tsuas yog tso tawm yog tias muaj ntau hom hauv ib daim ntawv teev npe kev cai.

Custom Folders
© 2014 Synopsys, Inc. 64

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Kev teeb tsa qhov project Files

Tshooj 4: Kev teeb tsa Logic Synthesis Project

5. Txhawm rau qhib ntau dua ib qho kev siv hauv tib qhov Project view, kos tso cai rau ntau qhov project qhib.
Qhov project 1

Qhov project 2

6. Tswj cov zis file tso saib nrog cov hauv qab no:
Kos qhov Qhia tag nrho Files hauv Results Directory box los tso saib tag nrho cov zis
files generated tom qab synthesis.
Hloov cov zis file koom haum los ntawm txhaj rau hauv ib qho ntawm cov kab ntawv header
nyob rau hauv qhov kev ua tau zoo view. Koj tuaj yeem pab pawg files los ntawm hom lossis txheeb lawv raws li hnub uas lawv tau hloov kho zaum kawg.
7. To view file cov ntaub ntawv, xaiv cov file hauv qhov Project view, right-click, thiab xaiv File Kev xaiv. Rau example, koj tuaj yeem tshawb xyuas hnub a file raug hloov kho.
Hloov kho Verilog suav nrog Txoj Kev hauv Txoj Haujlwm Laus Files
Yog tias koj muaj qhov project file tsim nrog ib tug laus version ntawm lub software (ua ntej mus rau 8.1), lub Verilog muaj xws li paths nyob rau hauv no file yog txheeb ze rau cov txiaj ntsig directory lossis qhov chaw file nrog cov 'xws li nqe lus. Hauv kev tso tawm tom qab 8.1, qhov project file ' suav nrog txoj hauv kev yog txheeb ze rau qhov project file nkaus xwb. Lub GUI hauv qhov kev tshaj tawm tsis ntev los no tsis tuaj yeem hloov kho cov laus prj files kom ua raws li cov cai tshiab. Txhim kho thiab siv qhov qub project file, ua ib qho hauv qab no:
· Manually kho lub prj file hauv ib phau ntawv editor thiab ntxiv cov hauv qab no rau ntawm
kab ua ntej txhua set_option -include_path:
set_option -project_relative_includes 1
· Pib ib qhov project tshiab nrog ib tug tshiab version ntawm lub software thiab tshem tawm cov
qub project. Qhov no yuav ua rau lub prj tshiab file ua raws txoj cai tshiab uas suav nrog yog txheeb ze rau prj file.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Tswj Project File Hierarchy

Tswj Project File Hierarchy
Cov ntu hauv qab no piav qhia seb koj tuaj yeem tsim thiab tswj cov folders customized thiab files hauv Project view:
· Tsim Custom Folders · Manipulating Custom Project Folders · Manipulating Custom Files

Tsim Custom Folders
Koj tuaj yeem tsim cov ntawv tais ceev tseg thiab kho kom haum files hauv ntau pawg hierarchy hauv koj qhov Project view. Cov folders no tuaj yeem teev nrog txhua lub npe lossis qib hierarchy. Rau example, koj tuaj yeem sib phim koj lub operating system file qauv lossis HDL logic hierarchy. Kev cai folders yog txawv los ntawm lawv cov xim xiav.

Muaj ntau txoj hauv kev los tsim cov folders kev cai thiab tom qab ntawd ntxiv files rau lawv hauv ib qhov project. Siv ib qho ntawm cov hauv qab no:

1. Right-click rau ib qhov project file los yog lwm qhov kev cai nplaub tshev thiab xaiv Ntxiv Folder los ntawm cov ntawv qhia zaub mov popup. Tom qab ntawd ua ib qho ntawm cov hauv qab no file kev ua haujlwm:

Right-click displays li ntawd

pe ib

fyioleuoLcrOafnileeesitahnedr

xaiv xaiv

Muab tso rau hauv Folder. Ib daim ntawv qhia zaub mov uas twb muaj lawm lossis tsim

tshiab folder.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tswj Project File Hierarchy

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Nco ntsoov tias koj tuaj yeem sau npe rau daim nplaub tshev, txawm li cas los xij tsis txhob siv tus cwj pwm (/) vim qhov no yog lub cim hierarchy cais.
Txhawm rau hloov npe lub nplaub tshev, nyem rau ntawm lub nplaub tshev thiab xaiv Rename los ntawm
cov ntawv qhia zaub mov popup. Lub Rename Folder dialog box tshwm; qhia lub npe tshiab.
2. Siv qhov Ntxiv Files mus rau qhov project dialog box ntxiv tag nrho cov ntsiab lus ntawm ib daim nplaub tshev hierarchy, thiab xaiv qhov chaw files rau hauv kev cai folders coj mus rau OS nplaub tshev hierarchies teev nyob rau hauv lub dialog box zaub.

Txhawm rau ua qhov no, xaiv qhov Ntxiv File khawm hauv qhov Project view.
Xaiv ib qho kev thov folders xws li dsp los ntawm lub dialog box, ces
nias lub Add khawm. Qhov no tso tag nrho cov files los ntawm dsp hierarchy rau hauv cov ntawv tais ceev tseg koj nyuam qhuav tsim.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Tswj Project File Hierarchy

Yuav cia li tso lub files rau hauv kev cai folders coj mus rau
lub OS nplaub tshev hierarchy, kos cov kev xaiv hu ua Ntxiv Files rau Custom Folders ntawm lub dialog box.
Los ntawm lub neej ntawd, lub npe nplaub tshev kev cai yog tib lub npe raws li daim nplaub tshev
muaj files lossis nplaub tshev ntxiv rau qhov project. Txawm li cas los xij, koj tuaj yeem hloov kho cov folders npe li cas, los ntawm txhaj rau ntawm Folders Option khawm. Lub dialog box hauv qab no tau tshwm sim.

Siv:
Tsuas yog cov ntawv tais ceev tseg uas muaj files rau lub npe nplaub tshev, nyem rau Siv OS
Folder Name.
Txoj kev lub npe mus rau lub nplaub tshev xaiv los txiav txim siab qib ntawm
hierarchy reflected rau txoj kev cai nplaub tshev.

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Tswj Project File Hierarchy

Tshooj 4: Kev teeb tsa Logic Synthesis Project

3. Koj tuaj yeem luag thiab poob files thiab folders los ntawm OS Explorer daim ntawv thov rau hauv qhov Project view. Cov yam ntxwv no muaj nyob rau ntawm Windows thiab Linux desktops khiav KDE.
Thaum koj luag thiab poob ib file, nws yog tam sim ntawd ntxiv rau qhov project.
Yog tias tsis muaj qhov project qhib, software tsim ib qhov project.
Thaum koj luag thiab poob ib file tshaj ib daim nplaub tshev, nws yuav muab tso rau hauv qhov ntawd
nplaub tshev. Thaum xub thawj, qhov Add Files rau Project dialog box yog tso tawm kom koj paub meej tias qhov files yuav ntxiv rau qhov project. Koj tuaj yeem nyem OK kom lees txais files. Yog tias koj xav hloov pauv, koj tuaj yeem nyem lub pob Tshem Tawm Tag Nrho thiab qhia cov lim tshiab lossis kev xaiv.

Nco tseg: Los tso saib cov folders kev cai hauv qhov Project view, xaiv qhov Options-> Project View Xaiv cov ntawv qhia zaub mov, tom qab ntawd qhib / kaw lub thawv rau View Qhov project Files hauv Custom Folders ntawm lub dialog box.

Manipulating Custom Project Folders
Cov txheej txheem hauv qab no piav qhia koj yuav tshem tawm li cas files los ntawm folders, rho tawm folders, thiab hloov lub folder hierarchy.
1. Tshem tawm a file los ntawm ib daim ntawv teev kev cai, xws li:
Luag thiab xa nws mus rau lwm lub nplaub tshev lossis mus rau qhov project. Highlight cov file, right-click thiab xaiv Tshem tawm ntawm Folder los ntawm cov
popup zaub mov.
Tsis txhob siv tus yuam sij rho tawm (DEL), vim qhov no tshem tawm file los ntawm qhov project.
2. Txhawm rau rho tawm ib daim nplaub tshev kev cai, taw qhia nws ces right-click thiab xaiv Rho tawm los ntawm cov ntawv qhia zaub mov popup lossis nias tus yuam sij DEL. Thaum koj rho tawm ib daim nplaub tshev, ua ib qho kev xaiv hauv qab no:
Nyem Yes mus rho tawm cov nplaub tshev thiab cov files muaj nyob rau hauv daim nplaub tshev los ntawm
qhov project.
Nyem Tsis yog tsuas yog rho tawm cov ntawv tais ceev tseg.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Tswj Project File Hierarchy

3. Hloov cov hierarchy ntawm cov ntaub ntawv kev cai:
Luag thiab tso lub nplaub tshev hauv lwm lub nplaub tshev kom nws yog sub-
folder los yog tshaj qhov project kom txav nws mus rau theem saum toj kawg nkaus.
Txhawm rau tshem tawm cov txheej txheem saum toj kawg nkaus ntawm cov ntaub ntawv kev cai, luag thiab poob
qhov xav tau sub-theem ntawm hierarchy tshaj qhov project. Tom qab ntawd rho tawm qhov khoob hauv paus directory rau daim nplaub tshev.
Rau example, yog hais tias tus uas twb muaj lawm kev cai folder directory yog:
/Ex ibamples/Verilog/RTL
Piv txwv tias koj xav tau ib-theem RTL hierarchy nkaus xwb, ces luag thiab tso RTL hla qhov project. Tom qab ntawd, koj tuaj yeem rho tawm / Examples/Verilog directory.

Manipulating Custom Files
Tsis tas li ntawd, koj tuaj yeem ua raws li cov kev cai hauv qab no file kev ua haujlwm:
1. Txhawm rau suppress cov zaub ntawm files nyob rau hauv Hom folders, right-click nyob rau hauv qhov Project view thiab xaiv Project View Options los yog xaiv Options-> Project View Kev xaiv. Disable qhov kev xaiv View Qhov project Files hauv Hom Folders ntawm lub dialog box.
2. Los tso saib files nyob rau hauv alphabetical order es tsis txhob ntawm qhov project order, kos lub Sort Files khawm hauv qhov Project view tswj vaj huam sib luag. Nyem lub xub xub hauv qab-sab laug ces kaum ntawm lub vaj huam sib luag kom toggle lub tswj vaj huam sib luag rau thiab tawm.

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tswj Project File Hierarchy

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Tswj Vaj Huam Sib Luag Toggle
3. Hloov qhov kev txiav txim ntawm files nyob rau hauv qhov project:
Nco ntsoov lov tes taw kev cai folders thiab sorting files. Luag thiab poob a file mus rau txoj haujlwm xav tau hauv daim ntawv teev npe files.
4. Hloov cov file ntaus ntawv, luag thiab xa nws mus rau lub hom ntawv tshiab. Lub software yuav qhia koj rau kev txheeb xyuas.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa kev siv

Kev teeb tsa kev siv
Ib qho kev siv yog ib qho qauv ntawm ib qhov project, siv nrog ib qho kev txwv tshwj xeeb thiab lwm qhov chaw. Ib qhov project tuaj yeem muaj ntau yam kev siv, txhua tus nrog nws tus kheej qhov chaw.

Ua haujlwm nrog ntau yam kev siv
Cov cuab yeej Synplify Pro cia koj tsim ntau qhov kev siv ntawm tib tus qauv thiab tom qab ntawd sib piv cov txiaj ntsig. Qhov no cia koj sim nrog ntau qhov chaw rau tib tus qauv. Kev nqis tes ua yog kev hloov kho ntawm koj tus qauv tsim nyob rau hauv cov ntsiab lus ntawm cov synthesis software, thiab tsis hloov lwm qhov code tswj software thiab cov txheej txheem.
1. Nyem lub khawm Ntxiv Ntxiv los yog xaiv qhov Project-> Kev Siv Tshiab thiab teeb tsa cov kev xaiv tshiab (Device tab), cov kev xaiv tshiab (Kev xaiv tab), lossis qhov txwv tshiab file (Cov kev txwv tab).
Lub software tsim lwm qhov kev siv hauv qhov project view. Qhov kev siv tshiab muaj lub npe tib yam li yav dhau los, tab sis nrog tus lej sib txawv. Cov duab hauv qab no qhia txog ob qhov kev siv, rev1 thiab rev2, nrog rau qhov kev siv tam sim no (active) tseem ceeb.

Qhov kev siv tshiab no siv tib qhov chaws files, tab sis txawv cov kev xaiv thiab kev txwv. Nws luam ib co files los ntawm kev siv yav dhau los: lub log tlg file, tus srs RTL netlist file, thiab design_fsm.sdc file tsim los ntawm FSM Explorer. Lub software khaws cov keeb kwm rov ua dua ntawm cov synthesis khiav.

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev teeb tsa kev siv

Tshooj 4: Kev teeb tsa Logic Synthesis Project

2. Khiav synthesis dua nrog cov chaw tshiab.
Txhawm rau khiav qhov kev siv tam sim no nkaus xwb, nyem Run.
Txhawm rau khiav txhua qhov kev siv hauv ib qhov project, xaiv Run-> Khiav Tag Nrho
Kev nqis tes ua.
Koj tuaj yeem siv ntau qhov kev siv los sim ib feem sib txawv lossis sim nrog ntau zaus. Saib Teem Cov Kev Sib Txuas Kev Sib Txuas Ntxiv, ntawm nplooj ntawv 75 kom paub meej txog kev teeb tsa kev xaiv.
Txoj Haujlwm view qhia tag nrho cov kev siv nrog cov kev ua haujlwm tseem ceeb uas tau hais tseg thiab cov txiaj ntsig sib xws files generated rau lub active kev siv tso tawm nyob rau hauv lub Implementation Results view ntawm sab xis; hloov cov active siv hloov cov zis file tso saib. Lub Watch qhov rais saib xyuas qhov kev ua haujlwm nquag. Yog tias koj teeb tsa lub qhov rais no los saib txhua qhov kev siv, qhov kev siv tshiab tau hloov kho tshiab hauv lub qhov rais.
3. Sib piv cov txiaj ntsig.
Siv lub Watch qhov rais los sib piv cov qauv xaiv. Nco ntsoov teem
cov kev siv koj xav muab piv nrog Configure Watch hais kom ua. Saib Siv Lub Qhov rai Saib, ntawm nplooj 190 kom paub meej.

Sib piv cov ntsiab lus, sib piv cov cav file tshwm sim.
4. Txhawm rau hloov npe qhov kev siv, nyem rau ntawm tus nas khawm sab xis ntawm lub npe siv hauv qhov project view, xaiv Hloov Siv Lub Npe los ntawm cov ntawv qhia zaub mov popup, thiab ntaus lub npe tshiab.
Nco ntsoov tias tam sim no UI overwrites qhov kev siv; tso tawm ua ntej 9.0 khaws cia qhov kev siv los hloov npe.
5. Txhawm rau luam ib qho kev siv, nyem rau ntawm tus nas khawm sab xis ntawm lub npe siv hauv qhov project view, xaiv Copy Implementation los ntawm cov ntawv qhia zaub mov popup, thiab ntaus lub npe tshiab rau daim ntawv theej.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev teeb tsa kev siv

6. Txhawm rau rho tawm qhov kev siv, nyem rau ntawm tus nas khawm sab xis ntawm lub npe siv hauv qhov project view, thiab xaiv Remove Implementation from the popup menu.

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project
Teem Logic Synthesis Implementation Options
Koj tuaj yeem teeb tsa cov kev xaiv thoob ntiaj teb rau koj qhov kev siv synthesis, qee qhov ntawm lawv cov cuab yeej tshwj xeeb. Tshooj lus no piav qhia yuav ua li cas los teeb tsa cov kev xaiv thoob ntiaj teb xws li ntaus ntawv, kev ua kom zoo, thiab file cov kev xaiv nrog rau kev siv cov kev xaiv hais kom ua. Rau cov ntaub ntawv hais txog kev teeb tsa kev txwv rau kev siv, saib Specifying SCOPE Constraints, nyob rau nplooj 119. Yog xav paub txog kev overriding ntiaj teb no chaw nrog ib tug cwj pwm los yog cov lus qhia, saib Specifying Attributes and Directives, nyob rau nplooj 90.
Tshooj lus no tham txog cov ncauj lus hauv qab no:
· Teem Cov Kev Xaiv Ntaus Ntaus, nyob rau nplooj 75 · Kev Xaiv Qhov Zoo Tshaj Plaws, nyob rau nplooj 78 · Qhia Txog Ntiaj Teb Tshaj Lij Tshaj Lij thiab Kev Txwv Files, ntawm nplooj 80 · Qhia Txog Cov Kev Xaiv Tau Zoo, nyob rau nplooj 82 · Qhia Txog Lub Sijhawm Tshaj Tawm Tshaj Tawm, nyob rau nplooj 84 · Teem Verilog thiab VHDL Options, ntawm nplooj 84
Kev teeb tsa ntaus ntawv xaiv
Cov kev xaiv ntaus ntawv yog ib feem ntawm cov kev xaiv thoob ntiaj teb uas koj tuaj yeem teem caij rau kev sib sau ua ke. Lawv suav nrog kev xaiv ib feem (thev naus laus zis, qib thiab qib ceev) thiab kev xaiv ua haujlwm (I / O ntxig thiab fanouts). Cov kev xaiv thiab kev siv ntawm cov kev xaiv no tuaj yeem sib txawv los ntawm kev siv tshuab mus rau thev naus laus zis, yog li xyuas cov neeg muag khoom tshooj ntawm Phau Ntawv Qhia rau cov ntaub ntawv hais txog koj tus neeg muag khoom xaiv.
1. Qhib Daim Ntawv Xaiv Qhov Kev Xaiv los ntawm nias lub pob Xaiv Qhov Kev Xaiv los yog xaiv qhov Project-> Cov Kev Xaiv Ua Haujlwm, thiab nyem lub Ntaus tab nyob rau sab saum toj yog tias nws tsis tau xaiv lawm.
2. Xaiv cov tshuab, ib feem, pob, thiab ceev. Muaj cov kev xaiv sib txawv, nyob ntawm seb lub tshuab koj xaiv.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
3. Teem lub ntaus ntawv xaiv xaiv. Cov kev xaiv sib txawv, nyob ntawm seb lub tshuab koj xaiv.
Yog tias koj tsis paub meej tias qhov kev xaiv txhais tau li cas, nyem rau ntawm qhov kev xaiv pom
ib qho kev piav qhia hauv lub thawv hauv qab no. Rau cov lus piav qhia tag nrho ntawm cov kev xaiv, nyem F1 lossis xa mus rau tshooj neeg muag khoom tsim nyog hauv Phau Ntawv Qhia.
Txhawm rau teeb tsa ib qho kev xaiv, ntaus tus nqi lossis kos lub thawv kom nws qhib.
Yog xav paub ntxiv txog kev teeb tsa fanout txwv thiab ncua sijhawm, saib Setting Fanout Limits, ntawm nplooj 348, thiab Retiming, ntawm nplooj 334, raws li. Yog xav paub meej txog lwm cov kev xaiv tshwj xeeb ntawm tus neeg muag khoom, xa mus rau tshooj neeg muag khoom tsim nyog thiab tsev neeg thev naus laus zis hauv Phau Ntawv Qhia.

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Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project

4. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK.
5. Nias lub khawm Khiav los ua ke cov qauv tsim. Lub software compiles thiab maps tus tsim siv cov kev xaiv uas koj teem.
6. Txhawm rau teeb tsa kev xaiv khoom siv nrog tsab ntawv, siv cov lus txib set_option Tcl. Cov lus hauv qab no muaj cov npe ntawm cov tsiaj ntawv ntawm cov kev xaiv ntaus ntawv ntawm lub cuab yeej tab mapped rau qhov sib npaug Tcl cov lus txib. Vim tias cov kev xaiv yog thev naus laus zis- thiab tsev neeg, tag nrho cov kev xaiv tau teev tseg hauv cov lus yuav tsis muaj nyob rau hauv cov cuab yeej xaiv. Tag nrho cov lus txib pib nrog set_option, ua raws li cov syntax hauv kem raws li qhia. Tshawb xyuas Phau Ntawv Qhia Txog Kev Qhia rau cov npe uas muaj ntau tshaj plaws ntawm cov kev xaiv rau koj tus neeg muag khoom.
Cov lus hauv qab no qhia tau hais tias feem ntau ntawm cov khoom siv xaiv.

Option Annotated Properties for Analyst Disable I/O Insertion Fanout Guide

Tcl Command (set_option…) -run_prop_extract {1|0} -disable_io_insertion {1|0} -fanout_limit fanout_value

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options

Kev xaiv

Tcl Command (set_option…)

Pob

- pob pkg_name

Ib feem

- part_name

daws cov tsav tsheb sib xyaw

-resolve_multiple_driver {1|0}

Ceev

-speed_qib speed_grade

Technology

-Technology lo lus tseem ceeb

Hloov kho Compile Point Timing Data -update_models_cp {0|1}

HDL Analyst Database Generation -hdl_qload {1|0}

Teem Cov Kev Xaiv Optimization
Optimization xaiv yog ib feem ntawm cov kev xaiv thoob ntiaj teb uas koj tuaj yeem teem caij rau kev siv. Tshooj lus no qhia koj yuav ua li cas los teeb tsa cov kev xaiv xws li zaus thiab thoob ntiaj teb kev ua kom zoo tshaj plaws xws li kev sib faib cov peev txheej. Koj tuaj yeem teeb tsa qee qhov kev xaiv no nrog cov khawm tsim nyog ntawm UI.
1. Qhib daim ntawv Xaiv Qhov Kev Xaiv los ntawm nias lub pob Xaiv Qhov Kev Xaiv los yog xaiv qhov Project-> Cov Kev Xaiv Ua Haujlwm, thiab nyem rau ntawm Cov Xaiv tab nyob rau sab saum toj.
2. Nyem qhov kev xaiv optimization koj xav tau, xws li nyob rau hauv daim ntawv los yog nyob rau hauv qhov project view. Koj cov kev xaiv sib txawv, nyob ntawm seb lub tshuab. Yog tias qhov kev xaiv tsis muaj rau koj cov thev naus laus zis, nws yog greyed. Teem qhov kev xaiv nyob rau hauv ib qho chaw cia li hloov kho nws nyob rau hauv lwm yam.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project

Qhov project View

Optimization Options Implementation Options-> Options

Yog xav paub ntxiv txog kev siv cov optimizations no mus saib cov ntu hauv qab no:

FSM Compiler FSM Explorer
Kev Sib Tham Sib Tham Sib Tham

Optimizing State Machines, ntawm nplooj 354
Khiav lub FSM Explorer, nyob rau nplooj 359 Ceebtoom: Tsuas yog ib feem ntawm Microsemi technologies txhawb FSM Explorer kev xaiv. Siv qhov Project-> Implementation Options-> Options panel los txiav txim seb qhov kev xaiv no puas txaus siab rau lub cuab yeej koj tau teev tseg hauv koj lub cuab yeej.
Kev Sib Koom Kev Pabcuam, ntawm nplooj 352
Retiming, ntawm nplooj 334

Qhov sib npaug Tcl set_option hais kom ua cov kev xaiv muaj raws li hauv qab no:

Option FSM Compiler FSM Explorer Resource Sib Koom Retiming

set_option Tcl Command Option -symbolic_fsm_compiler {1|0} -use_fsm_explorer {1|0} -resource_sharing {1|0} -retiming {1|0}

3. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
4. Nyem lub khawm Khiav kom khiav synthesis.
Lub software compiles thiab maps tus tsim siv cov kev xaiv uas koj teem.
HDL Analyst Database Generation
Los ntawm lub neej ntawd, lub software nyeem tag nrho cov qauv tsim, ua qhov kev ua kom zoo tshaj plaws thiab lub sijhawm nthuav tawm, thiab sau cov ntawv tso tawm mus rau ib qho netlist (srs). Raws li cov qauv tsim tau loj dua, lub sijhawm los khiav thiab debug tus tsim yuav nyuaj dua.
Cov kev xaiv no tso cai rau lub compiler ua ntej muab faib cov qauv tsim rau hauv ntau lub modules uas tau sau los cais netlist files (srs). Txhawm rau pab kom qhov kev xaiv no, xaiv HDL Analyst Database Generation checkbox ntawm Cov Kev Xaiv tab ntawm Kev Xaiv Cov Kev Xaiv dialog box. Cov yam ntxwv no txhim kho kev nco siv tau zoo rau cov qauv tsim loj.
Cov yam ntxwv no tseem tuaj yeem qhib los ntawm Tcl Script window siv cov lus txib nram qab no set_option Tcl:
set_option -hdl_qload 1
Thaum HDL Analyst Database Generation xaiv tau qhib, siv qhov kev xaiv nce nrawm nrawm hauv HDL Analyst cov cuab yeej los tso saib cov qauv siv ib leeg netlist (srs) lossis ntau theem RTL module netlists (srs). Cov cuab yeej tuaj yeem siv advantage ntawm no feature los ntawm dynamically loading tsuas yog cuam tshuam tsim hierarchy. Rau example, qhov browser hierarchy tuaj yeem nthuav dav tsuas yog qib qis qis raws li xav tau rau kev thauj khoom ceev. Qhov kev xaiv nce nrawm nrawm yog nyob rau ntawm General vaj huam sib luag ntawm HDL Analyst Options dialog box. Saib General Panel, ntawm nplooj 304.

Kev Qhia Txog Lub Ntiaj Teb Ntau zaus thiab kev txwv Files

Cov txheej txheem no qhia koj yuav ua li cas los teeb tsa lub ntiaj teb zaus thiab qhia qhov txwv files rau kev siv.

1. Txhawm rau teeb tsa lub ntiaj teb zaus, ua ib qho hauv qab no:

Ntaus lub ntiaj teb zaus hauv qhov project view.

Qhib Daim Ntawv Xaiv Qhov Kev Xaiv los ntawm nyem qhov Kev Siv

Options khawm Constraints tab.

kev xaiv

Qhov project-> Implementation

Kev xaiv,

thiab

nias

tus

Qhov sib npaug Tcl set_option hais kom ua yog -frequency frequencyValue.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project
Koj tuaj yeem hla lub ntiaj teb zaus nrog cov kev txwv hauv zos, raws li tau piav qhia hauv Specifying SCOPE Constraints, ntawm nplooj ntawv 119. Hauv Synplify Pro cov cuab yeej, koj tuaj yeem tsim cov sijhawm txwv rau koj tus qauv es tsis txhob teeb tsa lub ntiaj teb zaus. Saib Siv Auto Constraints, ntawm nplooj 291 kom paub meej.
Ntiaj teb no Frequency thiab Constraints Project View
Kev xaiv ua-> txwv

2. Qhia qhov txwv files rau kev siv, ua ib qho hauv qab no:
Xaiv qhov Project-> Implementation Options-> Constraints. Tshawb xyuas qhov txwv
files koj xav siv nyob rau hauv qhov project.
Los ntawm Cov Kev Xaiv Ua Haujlwm-> Kev txwv tsis pub muaj vaj huam sib luag, koj tuaj yeem nyem rau
ntxiv ib qho kev txwv file.
Nrog rau kev siv koj xav siv xaiv, nyem Ntxiv File hauv
Qhov project view, thiab ntxiv qhov txwv files koj xav tau.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
Tsim kom muaj kev txwv files, saib Specifying SCOPE Constraints, ntawm nplooj 119.
3. Tshem tawm qhov txwv files los ntawm kev siv, ua ib qho hauv qab no:
Xaiv qhov Project-> Implementation Options-> Constraints. Nyem tawm lub checkbox
tom ntej no file npe.
Hauv qhov project view, right-click qhov txwv file raug tshem tawm thiab
xaiv Remove from Project.
Qhov no tshem tawm qhov txwv file los ntawm kev siv, tab sis tsis rho tawm nws.
4. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK.
Thaum koj tsim cov qauv tsim, lub software suav nrog thiab kos cov qauv tsim siv cov kev xaiv uas koj tau teeb tsa.
Qhia meej txog cov kev xaiv tshwm sim
Tshooj lus no qhia koj yuav ua li cas qhia cov txheej txheem rau cov zis ntawm kev sib txuas ua haujlwm.
1. Qhib daim ntawv Xaiv Qhov Kev Xaiv los ntawm nias lub pob Xaiv Qhov Kev Xaiv los yog xaiv qhov Project-> Cov Kev Xaiv Ua Haujlwm, thiab nyem rau ntawm qhov Kev Ua Tau Zoo tab nyob rau sab saum toj.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project

2. Qhia qhov tso zis files koj xav tsim.
Txhawm rau tsim mapped netlist files, nyem Sau Mapped Verilog Netlist lossis Sau
Mapped VHDL Netlist.
Txhawm rau tsim kom muaj kev txwv tus neeg muag khoom tshwj xeeb file rau pem hauv ntej annotation,
nyem Sau Tus Neeg Muag Khoom Txwv File. Saib Kom Paub meej ntawm tsab ntawv ceeb toom no, saib Daim Ntawv Ceeb Toom Kev Ntsuas, nyob ntawm nplooj ntawv 270.of Phau Ntawv Qhia Txog Kev Siv, nyob rau nplooj 56 yog xav paub ntxiv.
3. Teem cov npe uas koj xav sau cov txiaj ntsig.
4. Teem hom ntawv rau cov zis file. Qhov sib npaug Tcl hais kom ua rau scripting yog qhov project -result_format hom.
Tej zaum koj kuj yuav xav teem cov cwj pwm los tswj lub npe-mapping. Yog xav paub meej, saib rau tshooj neeg muag khoom tsim nyog hauv Phau Ntawv Qhia Txog Kev Siv.
5. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK.
Thaum koj tsim cov qauv tsim, lub software suav nrog thiab kos cov qauv tsim siv cov kev xaiv uas koj tau teeb tsa.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
Qhia Txog Lub Sijhawm Tshaj Tawm Tshaj Tawm
Koj tuaj yeem txiav txim siab ntau npaum li cas tau tshaj tawm hauv lub sijhawm qhia los ntawm kev teeb tsa cov kev xaiv hauv qab no.
1. Xaiv Txoj Haujlwm-> Kev Xaiv Ua Haujlwm, thiab nyem rau lub sijhawm qhia tab. 2. Teem tus naj npawb ntawm txoj kev tseem ceeb uas koj xav kom lub software qhia.

3. Qhia tus naj npawb ntawm cov ntsiab lus pib thiab qhov kawg uas koj xav pom qhia hauv cov kab lus tseem ceeb.
4. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK. Thaum koj tsim cov qauv tsim, lub software suav nrog thiab kos cov qauv tsim siv cov kev xaiv uas koj tau teeb tsa.
Teem Verilog thiab VHDL Options
Thaum koj teeb tsa Verilog thiab VHDL qhov chaw files hauv koj qhov project, koj tuaj yeem qhia qee yam kev xaiv compiler.
Kev teeb tsa Verilog File Kev xaiv
Koj teem Verilog file kev xaiv los ntawm kev xaiv qhov Project-> Implementation Options-> Verilog, lossis Options-> Configure Verilog Compiler.

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Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project

1. Qhia meej hom Verilog siv.
Txhawm rau teeb tsa lub compiler thoob ntiaj teb rau txhua tus files hauv qhov project, xaiv
Project-> Implementation Options-> Verilog. Yog tias koj tab tom siv Verilog 2001 lossis SystemVerilog, tshawb xyuas phau ntawv qhia txog kev txhawb nqa.
Txhawm rau qhia Verilog compiler ntawm ib file hauv paus, xaiv lub file hauv
Qhov project view. Right-click thiab xaiv File Kev xaiv. Xaiv lub compiler tsim nyog. Lub default Verilog file hom ntawv rau cov haujlwm tshiab yog SystemVerilog.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
2. Qhia meej rau theem sab saum toj module yog tias koj tsis tau ua qhov no hauv Txoj Haujlwm view.
3. Txhawm rau rho tawm tsis tau los ntawm qhov chaws, ua cov hauv qab no:
Nyem Extract Parameters. Txhawm rau override lub neej ntawd, nkag mus rau tus nqi tshiab rau qhov ntsuas.
Lub software siv tus nqi tshiab rau kev siv tam sim no nkaus xwb. Nco ntsoov tias kev rho tawm parameter tsis txaus siab rau kev tsim qauv sib xyaw.

4. Ntaus cov lus qhia hauv Compiler Directives, siv qhov chaw los cais cov nqe lus. Koj tuaj yeem ntaus hauv cov lus qhia uas koj ib txwm nkag nrog 'ifdef thiab 'txhais nqe lus hauv cov cai. Rau example, ABC = 30 tshwm sim hauv software sau cov nqe lus hauv qab no rau qhov project file:
set_option -hdl_define -set “ABC=30”
LO

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project
5. Nyob rau hauv Include Path Order, qhia cov kev tshawb nrhiav rau cov lus txib rau Verilog files uas nyob hauv koj qhov project. Siv cov nyees khawm nyob rau sab xis saum toj ntawm lub npov ntxiv, rho tawm, lossis rov ua cov txheej txheem.
6. Nyob rau hauv Phau Ntawv Teev Npe, qhia txoj hauv kev mus rau cov npe uas muaj cov tsev qiv ntawv files rau koj qhov project. Siv cov nyees khawm nyob rau sab xis saum toj ntawm lub npov ntxiv, rho tawm, lossis rov ua cov txheej txheem.
7. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK. Thaum koj tsim cov qauv tsim, lub software suav nrog thiab kos cov qauv tsim siv cov kev xaiv uas koj tau teeb tsa.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project Teeb Logic Synthesis Implementation Options
Kev teeb tsa VHDL File Kev xaiv
Koj teev VHDL file cov kev xaiv los ntawm kev xaiv qhov Project-> Implementation Options-> VHDL, lossis Options-> Configure VHDL Compiler.

Rau VHDL qhov chaw, koj tuaj yeem teev cov kev xaiv tau piav qhia hauv qab no.
1. Qhia meej rau theem sab saum toj module yog tias koj tsis tau ua qhov no hauv Txoj Haujlwm view. Yog hais tias lub sab saum toj module tsis nyob rau hauv lub neej ntawd lub tsev qiv ntawv ua hauj lwm, koj yuav tsum qhia kom meej lub tsev qiv ntawv uas lub compiler yuav nrhiav tau lub module. Yog xav paub ntxiv txog yuav ua li cas, saib VHDL Vaj Huam Sib Luag, ntawm nplooj 200.
Koj tseem tuaj yeem siv qhov kev xaiv no rau kev tsim cov lus sib xyaw lossis thaum koj xav qhia ib qho module uas tsis yog qhov tseeb saum toj kawg nkaus rau HDL Analyst displaying thiab LdOebugging hauv schematic views. 2. Rau cov neeg siv lub xeev lub tshuab encoding, ua cov hauv qab no:
Qhia meej hom encoding koj xav siv.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Teem Logic Synthesis Implementation Options Tshooj 4: Teem Lub Logic Synthesis Project
Disable FSM compiler.
Thaum koj tsim cov qauv tsim, software siv cov lus qhia compiler koj tau teeb tsa ntawm no los encode lub xeev cov cav tov thiab tsis khiav FSM compiler, uas yuav override cov lus qhia compiler. Xwb, koj tuaj yeem txhais lub xeev cov cav tov nrog syn_encoding tus cwj pwm, raws li tau piav qhia hauv Defining State Machines hauv VHDL, ntawm nplooj 308.
3. Txhawm rau rho tawm generics los ntawm qhov chaws, ua qhov no:
Nyem Extract Generic Constants. Txhawm rau override lub neej ntawd, nkag mus rau tus nqi tshiab rau ib qho generic.
Lub software siv tus nqi tshiab rau kev siv tam sim no nkaus xwb. Nco ntsoov tias koj tsis tuaj yeem rho tawm cov generics yog tias koj muaj hom lus sib xyaw.

4. Txhawm rau thawb tristates hla cov txheej txheem / thaiv ciam teb, xyuas tias Push Tristates tau qhib. Yog xav paub meej, saib Push Tristates Option, ntawm nplooj 212 hauv Phau Ntawv Qhia Txog Kev Siv.
5. Txiav txim siab kev txhais lus ntawm synthesis_on thiab synthesis_off cov lus qhia:
Ua kom lub compiler txhais synthesis_on thiab synthesis_off directives
zoo li translate_on/translate_off, pab kom Synthesis On/Off Implemented as Translate On/Off option.
Txhawm rau tsis quav ntsej cov synthesis_on thiab synthesis_off cov lus qhia, xyuas kom meej tias
qhov kev xaiv no tsis raug kuaj xyuas. Saib translate_off/translate_on, nyob rau nplooj 226 hauv Phau Ntawv Qhia Txog Kev Qhia kom paub ntau ntxiv.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

6. Teem lwm cov kev xaiv rau kev siv raws li xav tau (saib Setting Logic Synthesis Implementation Options, nyob rau nplooj 75 rau ib daim ntawv teev cov kev xaiv). Nyem OK.
Thaum koj tsim cov qauv tsim, lub software suav nrog thiab kos cov qauv tsim siv cov kev xaiv uas koj tau teeb tsa.

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Cov cwj pwm thiab cov lus qhia yog cov lus qhia tshwj xeeb uas koj muab rau cov khoom tsim los tswj txoj kev koj tsim tau txheeb xyuas, ua kom zoo dua qub, thiab ua tiav.
Cov cwj pwm tswj kev ua kom zoo tshaj plaws thiab cov lus qhia tswj kev ua kom zoo tshaj plaws compiler. Vim qhov sib txawv no, koj yuav tsum qhia cov lus qhia hauv qhov chaws. Cov lus no piav qhia txog txoj hauv kev uas muaj los tsim tus cwj pwm thiab cov lus qhia tshwj xeeb:

VHDL Verilog SCOPE Editor txwv File

Tus cwj pwm Yes Xus muaj Yes Xus

Cov Lus Qhia Yog Yog Tsis Yog Tsis Yog

Nws yog qhov zoo dua los qhia cov cwj pwm hauv SCOPE editor lossis cov kev txwv file, vim hais tias koj tsis tas yuav recompile tus tsim ua ntej. Rau cov lus qhia, koj yuav tsum sau cov qauv tsim kom lawv siv tau.
Yog SCOPE/constraints file thiab HDL qhov chaws tau teev tseg rau kev tsim, cov kev txwv muaj qhov tseem ceeb thaum muaj kev tsis sib haum xeeb.
Yog xav paub ntxiv, mus saib hauv qab no:
· Specifying Attributes and Direectives in VHDL, on page 91 · Specifying Attributes and Directives in Verilog, on page 92 · Specifying Attributes UsLiOng the SCOPE Editor, nyob rau nplooj 93 · Specifying Attributes in the Constraints File,,paj 97

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Qhia cov cwj pwm thiab cov lus qhia hauv VHDL
Koj tuaj yeem siv lwm txoj hauv kev los ntxiv cov cwj pwm rau cov khoom, raws li teev nyob rau hauv Specifying Attributes and Directives, nyob rau nplooj 90. Txawm li cas los xij, koj tuaj yeem hais qhia cov lus qhia hauv qhov chaws xwb. Muaj ob txoj hauv kev los txhais cov cwj pwm thiab cov lus qhia hauv VHDL:
· Siv cov pob khoom uas tau teev ua ntej
· Tshaj tawm tus cwj pwm txhua zaus nws siv
Yog xav paub meej ntawm VHDL attribute syntax, saib VHDL Attribute thiab Directive Syntax, nyob rau nplooj 561 hauv Phau Ntawv Qhia.

Siv cov Predefined VHDL Attributes Pob
Lub advantage rau kev siv cov pob khoom ua ntej yog tias koj tsis txhob rov txhais cov yam ntxwv thiab cov lus qhia txhua zaus koj suav nrog lawv hauv qhov chaws. Lub disadvantage yog tias koj lub hauv paus code yog tsawg portable. Cov pob khoom muaj nyob hauv installDirectory/lib/vhd/synattr.vhd.
1. Txhawm rau siv cov pob khoom uas tau hais tseg ua ntej suav nrog hauv lub tsev qiv ntawv software, ntxiv cov kab no rau cov lus sib dhos:
tsev qiv ntawv synplify; siv synplify.attributes.all;
2. Ntxiv tus cwj pwm lossis cov lus qhia uas koj xav tau tom qab kev tshaj tawm ntawm chav tsim.
cov lus tshaj tawm; attribute attribute_name ntawm objectName : objectType yog tus nqi ;
Rau example:
entity simpledff yog chaw nres nkoj (q: tawm bit_vector(7 downto 0); d : hauv bit_vector(7 downto 0); clk : hauv ntsis);
attribute syn_noclockbuf ntawm clk : teeb liab muaj tseeb;
Yog xav paub meej txog cov lus cog tseg, saib VHDL Attribute thiab Directive Syntax, nyob rau nplooj 561 hauv Phau Ntawv Qhia.
3. Ntxiv qhov chaw file mus rau qhov project.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Tshaj tawm VHDL Cov Cai thiab Cov Lus Qhia
Yog tias koj tsis siv lub pob khoom, koj yuav tsum rov hais dua cov cwj pwm txhua zaus koj suav nrog lawv hauv qhov chaws.
1. Txhua zaus koj siv tus cwj pwm lossis cov lus qhia, txhais nws tam sim ntawd tom qab kev tshaj tawm ntawm chav tsim qauv siv cov syntax hauv qab no:
design_unit_declaration ; attribute attributeName: dataType; attribute attributeName of objectName : objectType is value ;
Rau example:
entity simpledff yog chaw nres nkoj (q: tawm bit_vector(7 downto 0); d : hauv bit_vector(7 downto 0); clk : hauv ntsis);
attribute syn_noclockbuf : boolean; attribute syn_noclockbuf ntawm clk :signal muaj tseeb;
2. Ntxiv qhov chaw file mus rau qhov project.

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia hauv Verilog
Koj tuaj yeem siv lwm txoj hauv kev los ntxiv cov yam ntxwv rau cov khoom, raws li tau piav qhia hauv Specifying Attributes and Directives, nyob rau nplooj 90. Txawm li cas los xij, koj tuaj yeem hais qhia cov lus qhia hauv qhov chaws xwb.
Verilog tsis muaj predefined synthesis cwj pwm thiab cov lus qhia, yog li koj yuav tsum ntxiv lawv raws li cov lus pom. Tus cwj pwm los yog lub npe qhia yog ua ntej los ntawm cov ntsiab lus synthesis. Verilog files yog cov ntaub ntawv rhiab heev, yog li cov cwj pwm thiab cov lus qhia yuav tsum tau teev raws nraim li tau hais hauv lawv cov lus piav qhia. Rau cov ntsiab lus syntax, saib Verilog Attribute thiab Directive Syntax, nyob rau nplooj 363 hauv Phau Ntawv Qhia.
1. Txhawm rau ntxiv tus cwj pwm lossis cov lus qhia hauv Verilog, siv Verilog kab lossis thaiv kev tawm tswv yim (C-style) syntax ncaj qha tom qab tus qauv tsim. Thaiv cov lus yuav tsum ua ntej lub semicolon, yog tias muaj ib qho.
LO

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Verilog Block Comment Syntax
/* synthesis attributeName = tus nqi */ /* synthesis directoryName = tus nqi */

Verilog Line Comment Syntax
// synthesis attributeName = tus nqi // synthesis directoryName = tus nqi

Yog xav paub meej txog cov kev cai syntax, saib Verilog Attribute thiab Directive Syntax, ntawm nplooj 363 hauv Phau Ntawv Qhia. Cov hauv qab no yog examples:
module fifo(tawm, hauv) /* synthesis syn_hier = "hard" */;
2. Txhawm rau txuas ntau tus cwj pwm lossis cov lus qhia rau tib yam khoom, cais cov cwj pwm nrog qhov chaw dawb, tab sis tsis txhob rov ua cov ntsiab lus synthesis. Tsis txhob siv commas. Rau example:
case state /* synthesis full_case parallel_case */;
3. Yog tias ntau qhov kev sau npe raug txhais siv ib nqe lus Verilog reg thiab tus cwj pwm raug siv rau lawv, ces cov software synthesis tsuas yog siv qhov kawg tshaj tawm rau npe hauv daim ntawv reg. Rau example:
reg [5:0] q, q_a, q_b, q_c, q_d /* synthesis syn_preserve=1 */;
Lub syn_preserve tus cwj pwm tsuas yog siv rau q_d. Qhov no yog tus cwj pwm xav tau rau cov cuab yeej sib txuas. Txhawm rau siv tus cwj pwm no rau txhua qhov kev sau npe, koj yuav tsum siv daim ntawv Verilog reg cais rau txhua tus neeg sau npe thiab siv tus cwj pwm.

Kev Qhia Tus Cwj Pwm Siv SCOPE Editor
Lub qhov rais SCOPE muab qhov yooj yim-rau-siv interface ntxiv rau txhua tus cwj pwm. Koj tsis tuaj yeem siv nws los ntxiv cov lus qhia, vim lawv yuav tsum tau ntxiv rau hauv qhov chaw files. (Saib Specifying Attributes and Direectives in VHDL, nyob rau nplooj 91 los yog Specifying Attributes and Directives in Verilog, ntawm nplooj 92). Cov txheej txheem hauv qab no qhia yuav ua li cas ntxiv tus cwj pwm ncaj qha hauv SCOPE qhov rai.
1. Pib nrog tus qauv tsim thiab qhib lub qhov rais SCOPE. Ntxiv cov cwj pwm rau qhov kev txwv uas twb muaj lawm file, qhib lub qhov rais SCOPE los ntawm txhaj rau qhov uas twb muaj lawm file hauv qhov Project view. Txhawm rau ntxiv cov cwj pwm rau ib qho tshiab file, nyem qhov SCOPE icon thiab nyem Initialize qhib lub qhov rais SCOPE.
2. Nyem rau lub tab tab nyob hauv qab ntawm SCOPE qhov rai.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Koj tuaj yeem xaiv qhov khoom ua ntej (qib 3) lossis tus cwj pwm ua ntej (qib 4).

3. Txhawm rau qhia qhov khoom, ua ib qho ntawm cov hauv qab no hauv kab ke Object. Yog tias koj twb tau teev tus cwj pwm, Cov khoom kab ntawv tsuas yog siv tau cov khoom xaiv rau tus cwj pwm ntawd.
Xaiv hom khoom nyob rau hauv Object Filter kem, thiab tom qab ntawd xaiv ib qho
khoom los ntawm cov npe ntawm cov kev xaiv hauv kab Object. Qhov no yog txoj hauv kev zoo tshaj plaws los xyuas kom meej tias koj tab tom teev ib yam khoom uas tsim nyog, nrog rau qhov tseeb syntax.

LO
Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Kev Qhia Txog Tus Cwj Pwm thiab Cov Lus Qhia

Tshooj 4: Kev teeb tsa Logic Synthesis Project

Luag cov khoom uas koj xav kom txuas tus cwj pwm los ntawm qhov
RTL lossis Technology views mus rau Object kem hauv SCOPE qhov rai. Rau qee tus cwj pwm, luag thiab tso tseg yuav tsis xaiv qhov khoom zoo. Rau example, yog tias koj xav teeb tsa syn_hier ntawm ib qho module lossis qhov chaw zoo li lub rooj vag, koj yuav tsum teeb tsa rau ntawm view rau qhov module. Cov khoom yuav muaj cov ntsiab lus no: v:moduleName hauv Verilog, lossis v:library.moduleName hauv VHDL, qhov twg koj tuaj yeem muaj ntau lub tsev qiv ntawv.
Ntaus lub npe ntawm cov khoom nyob rau hauv kab Object. Yog koj tsis paub
lub npe, siv cov lus txib Nrhiav lossis Cov Khoom Lim Kab. Nco ntsoov ntaus ntawv ua ntej tsim nyog rau cov khoom uas nws xav tau. Rau example, teem ib tug attribute rau a view, koj yuav tsum ntxiv v: ua ntej rau lub module lossis lub npe. Rau VHDL, tej zaum koj yuav tau qhia lub tsev qiv ntawv nrog rau lub npe module.
4. Yog tias koj teev cov khoom ua ntej, tam sim no koj tuaj yeem teev tus cwj pwm. Daim ntawv qhia tsuas yog cov cwj pwm siv tau rau hom khoom koj xaiv. Qhia kom meej tus cwj pwm los ntawm kev tuav tus nas khawm hauv kab Attribute thiab xaiv tus cwj pwm los ntawm cov npe.

Yog tias koj xaiv cov khoom ua ntej, cov kev xaiv muaj yog txiav txim siab los ntawm cov khoom xaiv thiab cov cuab yeej koj siv. Yog tias koj xaiv tus cwj pwm ua ntej, cov kev xaiv muaj yog txiav txim siab los ntawm kev siv tshuab.
Thaum koj xaiv tus cwj pwm, lub qhov rais SCOPE qhia koj txog yam muaj nuj nqis uas koj yuav tsum nkag rau tus cwj pwm ntawd thiab muab cov lus piav qhia luv luv ntawm tus cwj pwm. Yog tias koj xaiv tus cwj pwm ua ntej, nco ntsoov rov qab mus thiab qhia qhov khoom.
5. Sau tus nqi. Tuav tus nas khawm hauv kab nqes, thiab xaiv los ntawm cov npe. Koj tseem tuaj yeem ntaus tus nqi.

Synplify Pro rau Microsemi Edition Cov Neeg Siv Qhia Lub Kaum Hli 2014

Tshooj 4: Kev teeb tsa Logic Sy

Cov ntaub ntawv / Cov ntaub ntawv

SYnOPSYS FPGA Synthesis Synplify Pro rau Microsemi Edition [ua pdf] Cov neeg siv phau ntawv qhia
FPGA Synthesis Synplify Pro rau Microsemi Edition, Synthesis Synplify Pro rau Microsemi Edition, Synplify Pro rau Microsemi Edition, Pro rau Microsemi Edition, Microsemi Edition, Tsab

Cov ntaub ntawv

Cov neeg siv phau ntawv

SYnOPSYS FPGA Synthesis Synplify Pro rau Microsemi Edition Tus Neeg Siv Qhia

FPGA Synthesis Synplify Pro rau Microsemi Edition

Specifications

Cov ntaub ntawv khoom

Cov lus qhia siv khoom

Tshooj 1: Kev Taw Qhia

Scope ntawm Cov Ntaub Ntawv

Pib pib

Tus neeg siv interface dhauview

Tshooj 2: FPGA Synthesis Design Flows

Tshooj 3: Npaj cov tswv yim

FAQ

Q: Kuv puas tuaj yeem luam cov ntaub ntawv?

Q: Kuv yuav pib lub software li cas?

Q: Dab tsi yog cov neeg siv khoom npaj rau phau ntawv qhia no?

Cov ntaub ntawv / Cov ntaub ntawv

Cov ntaub ntawv

Cia ib saib

Ncua tseg teb