AN 795 Pedoman Palaksanaan pikeun 10G
Subsistem Ethernet Ngagunakeun Low Latency 10G MAC
Guide pamaké
AN 795 Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Nganggo Low Latency 10G MAC
AN 795: Nerapkeun Pedoman pikeun 10G Ethernet Subsistem Nganggo Low Latency 10G MAC Intel FPGA® IP dina Intel ® Arria® 10 Alat
Nerapkeun Pedoman pikeun 10G Ethernet Subsistem Nganggo Low Latency 10G MAC Intel ® FPGA IP dina Intel ® Arria® 10 Alat
Pedoman palaksanaan nunjukkeun anjeun kumaha ngagunakeun Intel Low Latency 10G Media Access Controller (MAC) sareng PHY IPs.
angka 1. Intel® Arria® 10 Low Latency Ethernet 10G Sistim MAC
meja 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Desain
Tabel ieu daptar sadaya Intel ® Arria® 10 desain pikeun Low Latency Ethernet 10G MAC Intel FPGA IP.
| Desain Example | Varian MAC | PHY | Kit ngembangkeun |
| 10GBase-R Ethernet | 10G | PHY pituin | Intel Arria 10 GX Transceiver SI |
| 10GBase-R ngadaptar Mode Ethernet |
10G | PHY pituin | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G / 10G Ethernet | 1G/10G | 1G / 10GbE sareng 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet jeung 1588 | 1G/10G | 1G / 10GbE sareng 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet | 10M / 100M / 1G / 10G | 1G / 10GbE sareng 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet jeung 1588 |
10M / 100M / 1G / 10G | 1G / 10GbE sareng 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet jeung 1588 | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G / 10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Intel Corporation. Sadaya hak disimpen. Intel, logo Intel, sareng merek Intel sanés mangrupikeun mérek dagang Intel Corporation atanapi anak perusahaanna. Intel ngajamin kinerja produk FPGA sareng semikonduktorna kana spésifikasi ayeuna saluyu sareng garansi standar Intel, tapi ngagaduhan hak pikeun ngarobih naon waé produk sareng jasa iraha waé tanpa aya bewara. Intel henteu nanggung tanggung jawab atanapi tanggung jawab anu timbul tina aplikasi atanapi pamakean inpormasi, produk, atanapi jasa anu dijelaskeun di dieu iwal ti dinyatakeun sapuk sacara tinulis ku Intel. Konsumén Intel disarankan pikeun ménta versi panganyarna tina spésifikasi alat sateuacan ngandelkeun inpormasi anu diterbitkeun sareng sateuacan nempatkeun pesenan produk atanapi jasa.
*Ngaran sareng merek sanésna tiasa diklaim salaku hak milik batur.
1. Nerapkeun Pedoman pikeun 10G Ethernet Subsistem Ngagunakeun Low Latency 10G MAC Intel® FPGA IP dina Intel® Arria® 10 Alat
683347 | 2020.10.28
Catetan:
Anjeun tiasa ngakses sadaya desain didaptarkeun ngaliwatan Low Latency Ethernet 10G MAC Intel® FPGA IP editor parameter dina software Intel Quartus Prime, iwal desain rujukan XAUI Ethernet. Anjeun tiasa kéngingkeun desain rujukan XAUI Ethernet ti Design Store.
Intel nawiskeun MAC sareng PHY IP anu misah pikeun subsistem Ethernet 10M ka 1G Multi-rate pikeun mastikeun palaksanaan anu fleksibel. Anjeun tiasa instantiate Low Latency Ethernet 10G MAC Intel FPGA IP sareng 1G / 2.5G / 5G / 10G Multi-rate Ethernet PHY, Intel Arria 10 1G / 10GbE sareng 10GBASE-KR PHY, atanapi XAUI PHY sareng Intel Arria 10 Transceiver Native PHY ka cater sarat desain béda.
Émbaran patali
- Low Latency Ethernet 10G MAC Intel FPGA IP Guide pamaké
Nyadiakeun inpo wincik ngeunaan instantiating na parameterizing MAC IP. - Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Desain Example Guide pamaké
Nyadiakeun inpo wincik tentang instantiating na parameterizing desain MAC examples. - Intel Arria 10 Transceiver PHY Pituduh pamaké
Nyadiakeun inpo wincik ngeunaan instantiating na parameterizing IP PHY. - Low Latency Ethernet 10G MAC Debug Daptar pariksa
- AN 699: Ngagunakeun Altera Ethernet Design Toolkit
Toolkit ieu mantuan Anjeun pikeun ngonpigurasikeun tur ngajalankeun desain rujukan Ethernet ogé debug sagala masalah nu patali Ethernet. - Analisis Tangkal Sesar pikeun Low Latency 10G MAC Data Korupsi Masalah
- Arria 10 Low Latency Ethernet 10G MAC na XAUI PHY Desain Rujukan
Nyayogikeun files pikeun desain rujukan.
1.1. Low Latency Ethernet 10G MAC sareng Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Anjeun tiasa ngonpigurasikeun Intel Arria 10 Transceiver Asalna PHY Intel FPGA IP pikeun nerapkeun 10GBASE-R PHY kalawan Ethernet lapisan fisik husus ngajalankeun pa laju data 10.3125 Gbps sakumaha didefinisikeun dina Klausa 49 spésifikasi IEEE 802.3-2008.
Konfigurasi ieu nyadiakeun XGMII mun Low Latency Ethernet 10G MAC Intel FPGA IP na implements a single-kanal 10.3 Gbps PHY nyadiakeun sambungan langsung ka SFP + modul optik ngagunakeun spésifikasi listrik SFI.
Intel nawiskeun dua desain subsistem Ethernet 10GBASE-R examples jeung anjeun bisa ngahasilkeun desain ieu dinamis ngagunakeun Low Latency Ethernet 10G MAC Intel FPGA IP redaktur parameter. Desain ngadukung simulasi fungsional sareng uji hardware dina kit pangembangan Intel anu ditunjuk.
Angka 2. Skéma Clocking sareng Reset pikeun Low Latency Ethernet 10G MAC sareng Intel Arria 10 Transceiver Native PHY di 10GBASE-R Design Example
Gambar 3. Skéma Clocking sareng Reset pikeun Low Latency Ethernet 10G MAC sareng Intel Arria 10 Transceiver Native PHY di 10GBASE-R Design Example kalawan ngadaptar Modeu Diaktipkeun
Émbaran patali
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Desain Example Guide pamaké
Nyadiakeun inpo wincik tentang instantiating na parameterizing desain MAC examples.
1.2. Low Latency Ethernet 10G MAC na XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP nyayogikeun XGMII ka Low Latency Ethernet 10G MAC Intel FPGA IP sareng ngalaksanakeun opat jalur masing-masing dina 3.125 Gbps dina antarmuka PMD.
XAUI PHY nyaéta palaksanaan lapisan fisik husus tina link 10 Gigabit Ethernet didefinisikeun dina spésifikasi IEEE 802.3ae-2008.
Anjeun tiasa kéngingkeun desain rujukan pikeun subsistem 10GbE anu dilaksanakeun nganggo Low Latency Ethernet 10G MAC sareng XAUI PHY Intel FPGA IPs ti Design Store. Desain ngadukung simulasi fungsional sareng uji hardware dina kit pangembangan Intel anu ditunjuk.
Gambar 4. Skéma Clocking sareng Reset pikeun Desain Rujukan Ethernet Latency Low 10G MAC sareng XAUI PHY 
Émbaran patali
- Arria 10 Low Latency Ethernet 10G MAC na XAUI PHY Desain Rujukan
Nyayogikeun files pikeun desain rujukan. - AN 794: Arria 10 Low Latency Ethernet 10G MAC sareng Desain Rujukan XAUI PHY
1.3. Low Latency Ethernet 10G MAC sareng 1G/10GbE sareng 10GBASEKR PHY Intel Arria 10 FPGA IPs
1G / 10GbE na 10GBASE-KR PHY Intel Arria 10 FPGA IP nyadiakeun MII, GMII na XGMII mun Low Latency Ethernet 10G MAC Intel FPGA IP.
1G / 10GbE na 10GBASE-KR PHY Intel Arria 10 FPGA IP ngalaksanakeun singlechannel 10Mbps / 100Mbps / 1Gbps / 10Gbps serial PHY. Desain nyadiakeun sambungan langsung ka 1G / 10GbE dual speed SFP + modul pluggable, 10M-10GbE 10GBASE-T jeung 10M / 100M / 1G / 10GbE 1000BASE-T tambaga PHY éksternal alat, atawa panganteur chip-to-chip. IP cores ieu ngarojong reconfigurable 10Mbps / 100Mbps / 1Gbps / 10Gbps ongkos data.
Intel nawiskeun dual-speed 1G / 10GbE sareng multi-speed 10Mb / 100Mb / 1Gb / 10GbE desain examples sareng anjeun tiasa ngahasilkeun desain ieu sacara dinamis nganggo Low Latency
Ethernet 10G MAC Intel FPGA IP editor parameter. Desain ngadukung simulasi fungsional sareng uji hardware dina kit pamekaran Intel anu ditunjuk.
Palaksanaan subsistem Ethernet multi-speed ngagunakeun 1G / 10GbE atanapi 10GBASE-KR PHY Intel Arria 10 FPGA desain IP merlukeun konstrain SDC manual pikeun jam PHY IP internal sarta penanganan pameuntasan domain jam. Tingal kana altera_eth_top.sdc file dina rarancang example uninga langkung seueur ngeunaan create_generated_clock diperlukeun, set_clock_groups na set_false_path SDC konstrain.
Angka 5. Skéma Clocking sareng Reset pikeun Low Latency Ethernet 10G MAC sareng Intel Arria 10 1G / 10GbE sareng 10GBASE-KR Desain Example (Modeu 1G/10GbE)
Angka 6. Skéma Clocking sareng Reset pikeun Low Latency Ethernet 10G MAC sareng Intel Arria 10 1G / 10GbE sareng 10GBASE-KR Desain Example (10Mb/100Mb/1Gb/10GbE Mode)
Émbaran patali
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Desain Example Guide pamaké
Nyadiakeun inpo wincik tentang instantiating na parameterizing desain MAC examples.
1.4. Low Latency Ethernet 10G MAC sareng 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Intel FPGA IP pikeun Intel Arria 10 alat nyadiakeun GMII na XGMII ka Low Latency Ethernet 10G MAC Intel FPGA IP.
1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Intel FPGA IP pikeun Intel Arria 10 alat implements a single-kanal 1G / 2.5G / 5G / 10Gbps serial PHY. Desain nyadiakeun sambungan langsung ka 1G / 2.5GbE dual speed SFP + modul pluggable, MGBASE-T na NBASE-T tambaga alat PHY éksternal, atawa panganteur chip-to-chip. IP ieu ngarojong reconfigurable 1G / 2.5G / 5G / 10Gbps ongkos data.
Intel nawiskeun dual-speed 1G / 2.5GbE, multi-speed 1G / 2.5G / 10GbE MGBASE-T, sareng multispeed 1G / 2.5G / 5G / 10GbE MGBASE-T design examples jeung anjeun bisa ngahasilkeun desain ieu dinamis ngagunakeun Low Latency Ethernet 10G MAC Intel FPGA IP redaktur parameter. Desain ngadukung simulasi fungsional sareng uji hardware dina kit pamekaran Intel anu ditunjuk.
Angka 7. Skéma Clocking sareng Reset pikeun Ethernet Latency Low 10G MAC sareng 1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Desain Example (Modeu 1G/2.5G)
Pikeun multi-speed 1G / 2.5GbE sareng 1G / 2.5G / 10GbE MBASE-T palaksanaan subsistem Ethernet nganggo 1G / 2.5G / 5G / 10G Multi-rate Ethernet PHY Intel FPGA IP, Intel nyarankeun anjeun nyalin modul konfigurasi ulang transceiver (alt_mge_rcfg_a10. sv) disadiakeun kalawan desain example. modul ieu reconfigures speed channel transceiver ti 1G ka 2.5G, atawa ka 10G, sarta sabalikna.
Palaksanaan subsistem Ethernet 1G/2.5GbE multi-speed sareng 1G/2.5G/10GbE MBASE-T Ethernet ogé merlukeun konstrain SDC manual pikeun jam IP PHY internal.
jeung jam domain pameuntasan penanganan. Tingal kana altera_eth_top.sdc file dina rarancang example uninga langkung seueur ngeunaan create_generated_clock diperlukeun, set_clock_groups na set_false_path SDC konstrain.
Angka 8. Skéma Clocking sareng Reset pikeun Ethernet Latency Low 10G MAC sareng 1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Desain Example (Modeu MBASE-T 1G/2.5G/10GbE) 
Angka 9. Skéma Clocking sareng Reset pikeun Low Latency Ethernet 10G MAC sareng 1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Desain Example (Modeu NBASE-T 1G/2.5G/5G/10GbE)
Émbaran patali
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Desain Example Guide pamaké Nyadiakeun inpo wincik tentang instantiating na parameterizing desain MAC examples.
1.5. Riwayat Révisi Dokumén pikeun AN 795: Palaksanaan Pedoman pikeun Subsistem Ethernet 10G Nganggo Laténsi Lemah 10G MAC Intel FPGA IP dina Alat Intel Arria 10
| Vérsi Dokumén | Parobahan |
| 2020.10.28 | • Rebranded salaku Intel. • Diganti ngaran dokumen salaku AN 795: Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Ngagunakeun Low Latency 10G MAC Intel FPGA IP dina Intel Arria 10 Alat. |
| titimangsa | Vérsi | Parobahan |
| Pébruari-17 | 2017.02.01 | Pelepasan awal. |
AN 795: Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Ngagunakeun Low
Latency 10G MAC Intel ® FPGA IP dina Intel® Arria® 10 Alat
Vérsi online
Kirim Eupan Balik
ID: 683347
Vérsi: 2020.10.28
Dokumén / Sumberdaya
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intel AN 795 Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Nganggo Low Latency 10G MAC [pdf] Pituduh pamaké AN 795 Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Ngagunakeun Low Latency 10G MAC, AN 795, Palaksanaan Pedoman pikeun 10G Ethernet Subsistem Ngagunakeun Low Latency 10G MAC, Ethernet Subsistem Ngagunakeun Low Latency 10G MAC, Low Latency 10G MAC |
