AN 795 Pedoman Implementasi kanggo 10G
Subsistem Ethernet Nggunakake Low Latency 10G MAC
Pandhuan pangguna
AN 795 Pedoman Implementasi kanggo Subsistem Ethernet 10G Nggunakake MAC 10G Latensi Rendah
AN 795: Implementasi Pedoman kanggo 10G Ethernet Subsistem Nggunakake Low Latency 10G MAC Intel FPGA® IP ing Intel ® Arria® 10 Piranti
Implementasi Pedoman kanggo Subsistem Ethernet 10G Nggunakake Latency Rendah 10G MAC Intel ® FPGA IP ing Piranti Intel ® Arria® 10
Pedoman implementasine nuduhake sampeyan carane nggunakake Intel's Low Latency 10G Media Access Controller (MAC) lan IP PHY.
Gambar 1. Intel® Arria® 10 Low Latency Ethernet 10G Sistem MAC
Tabel 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
Tabel iki nampilake kabeh desain Intel ® Arria® 10 kanggo Low Latency Ethernet 10G MAC Intel FPGA IP.
| Desain Example | Varian MAC | PHY | Kit Pangembangan |
| 10 GBase-R Ethernet | 10G | PHY asli | Intel Arria 10 GX Transceiver SI |
| Mode Register 10GBase-R Ethernet |
10G | PHY asli | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G/10G Ethernet | 1G/10G | 1G/10GbE lan 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet karo 1588 | 1G/10G | 1G/10GbE lan 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet | 10M / 100M / 1G / 10G | 1G/10GbE lan 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet karo 1588 |
10M / 100M / 1G / 10G | 1G/10GbE lan 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet karo 1588 | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G / 10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Intel Corporation. Kabeh hak dilindhungi undhang-undhang. Intel, logo Intel, lan merek Intel liyane minangka merek dagang saka Intel Corporation utawa anak perusahaan. Intel njamin kinerja produk FPGA lan semikonduktor kanggo specifications saiki miturut babar pisan standar Intel, nanging nduweni hak kanggo owah-owahan ing sembarang produk lan layanan ing sembarang wektu tanpa kabar. Intel ora tanggung jawab utawa tanggung jawab sing muncul saka aplikasi utawa panggunaan informasi, produk, utawa layanan sing diterangake ing kene kajaba sing disepakati kanthi tinulis dening Intel. Pelanggan Intel disaranake njupuk versi paling anyar saka spesifikasi piranti sadurunge ngandelake informasi sing diterbitake lan sadurunge nggawe pesenan kanggo produk utawa layanan.
* Jeneng lan merek liyane bisa diklaim minangka properti wong liya.
1. Implementasi Pedoman kanggo 10G Ethernet Subsistem Nggunakake Low Latency 10G MAC Intel® FPGA IP ing Intel® Arria® 10 Piranti
683347 | 2020.10.28
Cathetan:
Sampeyan bisa ngakses kabeh desain sing kadhaptar liwat Low Latency Ethernet 10G MAC Intel® FPGA IP editor parameter ing piranti lunak Intel Quartus Prime, kajaba desain referensi XAUI Ethernet. Sampeyan bisa entuk desain referensi XAUI Ethernet saka Design Store.
Intel nawakake IP MAC lan PHY sing kapisah kanggo subsistem Ethernet 10M nganti 1G Multi-rate kanggo mesthekake implementasine fleksibel. Sampeyan bisa instantiate Low Latency Ethernet 10G MAC Intel FPGA IP karo 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE lan 10GBASE-KR PHY, utawa XAUI PHY lan Intel Arria 10 Transceiver Native PHY kanggo ngebaki syarat desain beda.
Informasi sing gegandhengan
- Low Latency Ethernet 10G MAC Intel FPGA IP User Guide
Nyedhiyakake informasi rinci babagan instantiating lan parameterizing IP MAC. - Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example Pandhuan pangguna
Nyedhiyani informasi rinci babagan instantiating lan parameterizing desain MAC examples. - Intel Arria 10 Transceiver PHY User Guide
Nyedhiyakake informasi rinci babagan instantiating lan parameterisasi IP PHY. - Low Latency Ethernet 10G MAC Debug Checklist
- AN 699: Nggunakake Altera Ethernet Design Toolkit
Toolkit iki mbantu sampeyan ngatur lan mbukak desain referensi Ethernet uga debug masalah sing ana gandhengane karo Ethernet. - Analisis Fault Tree kanggo Masalah Korupsi Data 10G MAC Latency Low
- Arria 10 Low Latency Ethernet 10G MAC lan Desain Referensi XAUI PHY
Nyedhiyakake files kanggo desain referensi.
1.1. Low Latency Ethernet 10G MAC lan Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Sampeyan bisa ngatur Intel Arria 10 Transceiver Native PHY Intel FPGA IP kanggo ngleksanakake 10GBASE-R PHY karo Ethernet lapisan fisik tartamtu mlaku ing 10.3125 Gbps data rate minangka ditetepake ing Klausa 49 saka IEEE 802.3-2008 specifications.
Konfigurasi iki menehi XGMII kanggo Low Latency Ethernet 10G MAC Intel FPGA IP lan ngleksanakake siji-saluran 10.3 Gbps PHY nyediakake sambungan langsung menyang SFP + modul optik nggunakake specification electrical SFI.
Intel nawakake loro 10GBASE-R Ethernet subsistem desain examples lan sampeyan bisa generate desain iki mbosenke nggunakake Low Latency Ethernet 10G MAC Intel FPGA IP editor parameter. Desain kasebut ndhukung simulasi fungsional lan pengujian hardware ing kit pangembangan Intel sing ditunjuk.
Gambar 2. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan Intel Arria 10 Transceiver Native PHY ing 10GBASE-R Design Example
Gambar 3. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan Intel Arria 10 Transceiver Native PHY ing 10GBASE-R Design Example karo Register Mode Diaktifake
Informasi sing gegandhengan
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example Pandhuan pangguna
Nyedhiyani informasi rinci babagan instantiating lan parameterizing desain MAC examples.
1.2. Low Latency Ethernet 10G MAC lan XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP nyedhiyakake XGMII kanggo Low Latency Ethernet 10G MAC Intel FPGA IP lan ngetrapake papat jalur saben ing 3.125 Gbps ing antarmuka PMD.
XAUI PHY minangka implementasine lapisan fisik tartamtu saka link 10 Gigabit Ethernet sing ditetepake ing spesifikasi IEEE 802.3ae-2008.
Sampeyan bisa entuk desain referensi kanggo subsistem 10GbE sing diimplementasikake nggunakake Low Latency Ethernet 10G MAC lan XAUI PHY Intel FPGA IP saka Design Store. Desain kasebut ndhukung simulasi fungsional lan pengujian hardware ing kit pangembangan Intel sing ditunjuk.
Gambar 4. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan XAUI PHY Desain Referensi 
Informasi sing gegandhengan
- Arria 10 Low Latency Ethernet 10G MAC lan Desain Referensi XAUI PHY
Nyedhiyakake files kanggo desain referensi. - AN 794: Arria 10 Low Latency Ethernet 10G MAC lan Desain Referensi XAUI PHY
1.3. Low Latency Ethernet 10G MAC lan 1G/10GbE lan 10GBASEKR PHY Intel Arria 10 IP FPGA
1G / 10GbE lan 10GBASE-KR PHY Intel Arria 10 FPGA IP nyedhiyakake MII, GMII lan XGMII menyang Low Latency Ethernet 10G MAC Intel FPGA IP.
1G / 10GbE lan 10GBASE-KR PHY Intel Arria 10 FPGA IP ngleksanakake singlechannel 10Mbps / 100Mbps / 1Gbps / 10Gbps serial PHY. Desain kasebut nyedhiyakake sambungan langsung menyang modul pluggable 1G / 10GbE dual speed SFP +, 10M-10GbE 10GBASE-T lan 10M / 100M / 1G / 10GbE 1000BASE-T piranti PHY eksternal tembaga, utawa antarmuka chip-to-chip. Inti IP iki ndhukung tingkat data 10Mbps/100Mbps/1Gbps/10Gbps sing bisa dikonfigurasi ulang.
Intel nawakake dual-kacepetan 1G/10GbE lan multi-kacepetan 10Mb/100Mb/1Gb/10GbE desain examples lan sampeyan bisa ngasilake desain kasebut kanthi dinamis nggunakake Low Latency
Ethernet 10G MAC Intel FPGA IP editor parameter. Desain kasebut ndhukung simulasi fungsional lan pengujian hardware ing kit pangembangan Intel sing ditunjuk.
Implementasi subsistem Ethernet multi-kacepetan nggunakake 1G / 10GbE utawa 10GBASE-KR PHY Intel Arria 10 FPGA IP desain mbutuhake manual SDC alangan kanggo internal PHY jam IP lan jam domain nyebrang penanganan. Waca altera_eth_top.sdc file ing desain example ngerti liyane babagan create_generated_clock dibutuhake, set_clock_groups lan set_false_path SDC alangan.
Gambar 5. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan Intel Arria 10 1G/10GbE lan 10GBASE-KR Design Example (Mode 1G/10GbE)
Gambar 6. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan Intel Arria 10 1G/10GbE lan 10GBASE-KR Design Example (Mode 10Mb/100Mb/1Gb/10GbE)
Informasi sing gegandhengan
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example Pandhuan pangguna
Nyedhiyani informasi rinci babagan instantiating lan parameterizing desain MAC examples.
1.4. Low Latency Ethernet 10G MAC lan 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Intel FPGA IP kanggo piranti Intel Arria 10 nyedhiyakake GMII lan XGMII menyang Low Latency Ethernet 10G MAC Intel FPGA IP.
1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Intel FPGA IP kanggo piranti Intel Arria 10 ngleksanakake saluran siji 1G / 2.5G / 5G / 10Gbps serial PHY. Desain kasebut nyedhiyakake sambungan langsung menyang modul pluggable 1G / 2.5GbE dual speed SFP +, piranti PHY eksternal tembaga MGBASE-T lan NBASE-T, utawa antarmuka chip-to-chip. IP iki ndhukung tingkat data 1G/2.5G/5G/10Gbps sing bisa dikonfigurasi ulang.
Intel nawakake dual-kacepetan 1G/2.5GbE, multi-kacepetan 1G/2.5G/10GbE MGBASE-T, lan multi-kacepetan 1G/2.5G/5G/10GbE MGBASE-T desain examples lan sampeyan bisa generate desain iki mbosenke nggunakake Low Latency Ethernet 10G MAC Intel FPGA IP editor parameter. Desain kasebut ndhukung simulasi fungsional lan pengujian hardware ing kit pangembangan Intel sing ditunjuk.
Gambar 7. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (Mode 1G/2.5G)
Kanggo multi-kacepetan 1G / 2.5GbE lan 1G / 2.5G / 10GbE MBASE-T implementasi subsistem Ethernet nggunakake 1G / 2.5G / 5G / 10G Multi-rate Ethernet PHY Intel FPGA IP, Intel nyaranake sampeyan nyalin modul konfigurasi ulang transceiver (alt_mge_rcfg_a10. sv) diwenehake karo desain example. Modul iki reconfigures kacepetan saluran transceiver saka 1G kanggo 2.5G, utawa kanggo 10G, lan kosok balene.
Implementasi subsistem Ethernet 1G/2.5GbE multi-kacepetan lan 1G/2.5G/10GbE MBASE-T Ethernet uga mbutuhake watesan SDC manual kanggo jam IP PHY internal.
lan penanganan lintas domain jam. Waca altera_eth_top.sdc file ing desain example ngerti liyane babagan create_generated_clock dibutuhake, set_clock_groups lan set_false_path SDC alangan.
Gambar 8. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (Mode MBASE-T 1G/2.5G/10GbE) 
Gambar 9. Skema Clocking lan Reset kanggo Low Latency Ethernet 10G MAC lan 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (Mode NBASE-T 1G/2.5G/5G/10GbE)
Informasi sing gegandhengan
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Nyedhiyani informasi rinci babagan instantiating lan parameterizing desain MAC examples.
1.5. Riwayat Revisi Dokumen kanggo AN 795: Implementasi Pedoman kanggo Subsistem Ethernet 10G Nggunakake Low Latency 10G MAC Intel FPGA IP ing Piranti Intel Arria 10
| Versi Dokumen | Owah-owahan |
| 2020.10.28 | • Rebranded minangka Intel. • Ganti jeneng document minangka AN 795: Implementing Guidelines kanggo 10G Ethernet Subsistem Nggunakake Low Latency 10G MAC Intel FPGA IP ing Intel Arria 10 Piranti. |
| Tanggal | Versi | Owah-owahan |
| Februari-17 | 2017.02.01 | Rilis wiwitan. |
AN 795: Implementasi Pedoman kanggo 10G Ethernet Subsistem Nggunakake Low
Latency 10G MAC Intel ® FPGA IP ing Piranti Intel® Arria® 10
Versi Online
Kirimi Umpan Balik
Nomer Kode : 683347
Versi: 2020.10.28
Dokumen / Sumber Daya
 |
Pedoman Implementasi Intel AN 795 kanggo Subsistem Ethernet 10G Nggunakake MAC Latency Rendah 10G [pdf] Pandhuan pangguna AN 795 Pedoman Implementasi kanggo Subsistem Ethernet 10G Nggunakake MAC Latency Low 10G, AN 795, Pedoman Implementasi kanggo Subsistem Ethernet 10G Nggunakake MAC Latency Rendah 10G MAC, Subsistem Ethernet Nggunakake Low Latency 10G MAC, Low Latency 10G MAC |
