AN 795 Dokokin Aiwatar da 10G
Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC
Jagorar Mai Amfani
AN 795 Dokokin aiwatarwa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC
AN 795: Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC Intel FPGA® IP a cikin Intel ® Arria® 10 Na'urori
Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC Intel ® FPGA IP a cikin Intel ® Arria® 10 Na'urori
Jagororin aiwatarwa suna nuna muku yadda ake amfani da Intel's Low Latency 10G Media Access Controller (MAC) da PHY IPs.
Hoto 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC System
Tebur 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
Wannan tebur yana lissafin duk ƙirar Intel ® Arria® 10 don Low Latency Ethernet 10G MAC Intel FPGA IP.
| Zane Example | MAC Bambanci | PHY | Kit ɗin Ci gaba |
| 10GBase-R Ethernet | 10G | PHY ta asali | Intel Arria 10 GX Transceiver SI |
| Yanayin Rajista 10GBase-R Ethernet |
10G | PHY ta asali | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G/10G Ethernet | 1G/10G | 1G/10GbE da 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet tare da 1588 | 1G/10G | 1G/10GbE da 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet | 10M/100M/1G/10G | 1G/10GbE da 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet da 1588 |
10M/100M/1G/10G | 1G/10GbE da 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet tare da 1588 | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G/10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
1. Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC Intel® FPGA IP a cikin Intel® Arria® 10 na'urorin
683347 | 2020.10.28
Lura:
Kuna iya samun dama ga duk samfuran da aka jera ta hanyar Low Latency Ethernet 10G MAC Intel® FPGA IP editan siga a cikin Intel Quartus Prime software, ban da ƙirar ƙirar XAUI Ethernet. Kuna iya samun ƙirar tunani na XAUI Ethernet daga Shagon Zane.
Intel yana ba da keɓaɓɓen MAC da PHY IPs don 10M zuwa 1G Multi-rate Ethernet subsystems don tabbatar da aiwatar da sassauƙa. Kuna iya aiwatar da Low Latency Ethernet 10G MAC Intel FPGA IP tare da 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE da 10GBASE-KR PHY, ko XAUI PHY da Intel Arria 10 Transceiver caja na asali daban-daban bukatun PHY.
Bayanai masu alaƙa
- Ƙananan Latency Ethernet 10G MAC Intel FPGA IP Jagorar Mai Amfani
Yana ba da cikakkun bayanai game da saurin lokaci da daidaitawa da MAC IP. - Ƙananan Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani
Yana ba da cikakkun bayanai game da yin gaggawa da daidaitawa da ƙirar MACamples. - Intel Arria 10 Transceiver PHY Jagoran Mai Amfani
Yana ba da cikakken bayani game da saurin-sauri da daidaitawa da PHY IP. - Ƙananan Latency Ethernet 10G MAC Jerin Binciken Bugawa
- AN 699: Amfani da Altera Ethernet Design Toolkit
Wannan kayan aikin yana taimaka muku saitawa da gudanar da ƙira na nuni na Ethernet tare da cire duk wasu batutuwa masu alaƙa da Ethernet. - Fault Tree Analysis don Ƙananan Latency 10G MAC Batun Cin Hanci da Rashawa
- Arria 10 Low Latency Ethernet 10G MAC da XAUI PHY Reference Design
Yana bayar da files don ƙirar ƙira.
1.1. Ƙananan Latency Ethernet 10G MAC da Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Kuna iya saita Intel Arria 10 Transceiver Native PHY Intel FPGA IP don aiwatar da 10GBASE-R PHY tare da keɓaɓɓen Layer na zahiri na Ethernet yana gudana a ƙimar bayanan 10.3125 Gbps kamar yadda aka ayyana a cikin Sashe na 49 na ƙayyadaddun IEEE 802.3-2008.
Wannan saitin yana ba da XGMII zuwa Low Latency Ethernet 10G MAC Intel FPGA IP kuma yana aiwatar da tashoshi guda ɗaya na 10.3 Gbps PHY yana ba da haɗin kai tsaye zuwa na'urar gani ta SFP + ta amfani da ƙayyadaddun lantarki na SFI.
Intel yana ba da ƙirar tsarin tsarin 10GBASE-R Ethernet guda biyuampLes kuma za ku iya samar da waɗannan ƙira da ƙarfi ta amfani da Low Latency Ethernet 10G MAC Editan siga na IP na FPGA. Zane-zane na goyan bayan kwaikwaiyon aiki da gwajin kayan aiki akan na'urorin haɓakawa na Intel.
Hoto 2. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da Intel Arria 10 Transceiver Native PHY a cikin 10GBASE-R Design Exayalwaci
Hoto 3. Clocking da Sake saitin Tsari don Ƙananan Latency Ethernet 10G MAC da Intel Arria 10 Mai Canjawa Native PHY a cikin 10GBASE-R Design Exampda Register An Kunna Yanayin
Bayanai masu alaƙa
Ƙananan Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani
Yana ba da cikakkun bayanai game da yin gaggawa da daidaitawa da ƙirar MACamples.
1.2. Ƙananan Latency Ethernet 10G MAC da XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP yana ba da XGMII zuwa Low Latency Ethernet 10G MAC Intel FPGA IP kuma yana aiwatar da hanyoyi guda huɗu kowanne a 3.125 Gbps a wurin haɗin PMD.
XAUI PHY takamaiman aiwatar da Layer na jiki ne na hanyar haɗin Gigabit Ethernet 10 da aka ayyana a cikin ƙayyadaddun IEEE 802.3ae-2008.
Kuna iya samun ƙirar ƙira don tsarin 10GbE da aka aiwatar ta amfani da Low Latency Ethernet 10G MAC da XAUI PHY Intel FPGA IPs daga Shagon Zane. Ƙirar tana goyan bayan kwaikwaiyon aiki da gwajin kayan aiki akan ƙayyadaddun kayan haɓakawa na Intel.
Hoto 4. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da XAUI PHY Reference Design 
Bayanai masu alaƙa
- Arria 10 Low Latency Ethernet 10G MAC da XAUI PHY Reference Design
Yana bayar da files don ƙirar ƙira. - AN 794: Arria 10 Low Latency Ethernet 10G MAC da XAUI PHY Reference Design
1.3. Ƙananan Latency Ethernet 10G MAC da 1G/10GbE da 10GBASEKR PHY Intel Arria 10 FPGA IPs
1G/10GbE da 10GBASE-KR PHY Intel Arria 10 FPGA IP suna ba da MII, GMII da XGMII zuwa Ƙananan Latency Ethernet 10G MAC Intel FPGA IP.
1G/10GbE da 10GBASE-KR PHY Intel Arria 10 FPGA IP suna aiwatar da tashoshi guda 10Mbps/100Mbps/1Gbps/10Gbps serial PHY. Abubuwan ƙira suna ba da haɗin kai tsaye zuwa 1G / 10GbE dual speed SFP + pluggable modules, 10M-10GbE 10GBASE-T da 10M/100M/1G/10GbE 1000BASE-T jan karfe na waje PHY na'urorin, ko guntu-to-chip musaya. Waɗannan abubuwan haɗin IP suna goyan bayan sake daidaitawa 10Mbps/100Mbps/1Gbps/10Gbps ƙimar bayanai.
Intel yana ba da 1G/10GbE-dual-gudun da kuma 10Mb/100Mb/1Gb/10GbE mai saurin-sauri.amples kuma za ku iya samar da waɗannan ƙira da ƙarfi ta amfani da Low Latency
Ethernet 10G MAC Intel FPGA IP editan siga. Ƙirar tana goyan bayan kwaikwaiyon aiki da gwajin kayan aiki akan ƙayyadaddun kayan haɓakawa na Intel.
Aiwatar da tsarin tsarin Ethernet mai saurin gudu ta amfani da 1G/10GbE ko 10GBASE-KR PHY Intel Arria 10 FPGA IP ƙira yana buƙatar ƙuntatawa na SDC na hannu don agogon PHY IP na ciki da sarrafa yanki na agogo. Koma zuwa altera_eth_top.sdc file a cikin zane exampdon ƙarin sani game da ƙirƙira_generated_clock da ake buƙata, ƙungiyoyin_satin_clock_ da madaidaitan hanyar_false_hanyar SDC.
Hoto 5. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da Intel Arria 10 1G/10GbE da 10GBASE-KR Design Example (Yanayin 1G/10GbE)
Hoto 6. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da Intel Arria 10 1G/10GbE da 10GBASE-KR Design Example (10Mb/100Mb/1Gb/10GbE Yanayin)
Bayanai masu alaƙa
Ƙananan Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani
Yana ba da cikakkun bayanai game da yin gaggawa da daidaitawa da ƙirar MACamples.
1.4. Ƙananan Latency Ethernet 10G MAC da 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP don na'urorin Intel Arria 10 suna ba da GMII da XGMII zuwa Ƙananan Latency Ethernet 10G MAC Intel FPGA IP.
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP don na'urorin Intel Arria 10 suna aiwatar da serial PHY guda-1G/2.5G/5G/10Gbps. Ƙirar tana ba da haɗin kai tsaye zuwa 1G / 2.5GbE dual speed SFP + pluggable modules, MGBASE-T da NBASE-T jan karfe na waje PHY na'urorin, ko guntu-to-chip musaya. Waɗannan IPs suna tallafawa ƙimar bayanan 1G/2.5G/5G/10Gbps da za'a iya daidaita su.
Intel yana ba da 1G/2.5GbE mai dual-gudun, 1G/2.5G/10GbE MGBASE-T mai saurin gudu, da 1G/2.5G/5G/10GbE MGBASE-T zane ex.ampLes kuma za ku iya samar da waɗannan ƙira da ƙarfi ta amfani da Low Latency Ethernet 10G MAC Editan siga na IP na FPGA. Ƙirar tana goyan bayan kwaikwaiyon aiki da gwajin kayan aiki akan ƙayyadaddun kayan haɓakawa na Intel.
Hoto 7. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (Yanayin 1G/2.5G)
Don Multi-Speed 1G/2.5GbE da 1G/2.5G/10GbE MBASE-T Ethernet subsystem aiwatarwa ta amfani da 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP, Intel ya ba da shawarar ka kwafi transceiver reconfiguration module (alt_mge_rcfg_a10)ample. Wannan tsarin yana sake daidaita saurin tashar transceiver daga 1G zuwa 2.5G, ko zuwa 10G, kuma akasin haka.
Tsarin 1G/2.5GbE da yawa da 1G/2.5G/10GbE MBASE-T Ethernet subsystem aiwatarwa shima yana buƙatar ƙuntatawar SDC na hannu don agogon PHY IP na ciki
da agogon yanki na hayewa handling. Koma zuwa altera_eth_top.sdc file a cikin zane exampdon ƙarin sani game da ƙirƙira_generated_clock da ake buƙata, ƙungiyoyin_satin_clock_ da madaidaitan hanyar_false_hanyar SDC.
Hoto 8. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/10GbE MBASE-T Yanayin) 
Hoto 9. Tsarin rufewa da Sake saitin don Ƙananan Latency Ethernet 10G MAC da 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/5G/10GbE NBASE-T Yanayin)
Bayanai masu alaƙa
Ƙananan Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design ExampJagorar Mai Amfani Yana ba da cikakkun bayanai game da saurin lokaci da daidaita tsarin ƙirar MACamples.
1.5. Tarihin Bita na Takardu don AN 795: Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC Intel FPGA IP a cikin na'urorin Intel Arria 10
| Sigar Takardu | Canje-canje |
| 2020.10.28 | • Sake suna a matsayin Intel. • Sake sunan daftarin aiki a matsayin AN 795: Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC Intel FPGA IP a cikin na'urorin Intel Arria 10. |
| Kwanan wata | Sigar | Canje-canje |
| Fabrairu-17 | 2017.02.01 | Sakin farko. |
AN 795: Aiwatar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan
Latency 10G MAC Intel ® FPGA IP a cikin Intel® Arria® 10 Na'urori
Online Version
Aika da martani
Saukewa: 683347
Shafin: 2020.10.28
Takardu / Albarkatu
 |
intel AN 795 Dokokin aiwatarwa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC [pdf] Jagorar mai amfani AN 795 Gudanar da Sharuɗɗa don 10G Ethernet Subsystem Ta Amfani da Ƙananan Latency 10G MAC, AN 795, Gudanar da Sharuɗɗa don 10G Ethernet Subsystem Amfani da Ƙananan Latency 10G MAC |
