Ntuziaka mmejuputa iwu AN 795 maka 10G
Ethernet Subsystem Iji Low Latency 10G MAC
Ntuziaka onye ọrụ
Ntuziaka mmejuputa iwu AN 795 maka 10G Ethernet Subsystem Iji obere Latency 10G MAC
AN 795: Ntuziaka na-eme maka 10G Ethernet Subsystem Iji obere Latency 10G MAC Intel FPGA® IP na Intel ® Arria® 10 Ngwaọrụ
Na-eme ntuziaka maka 10G Ethernet Subsystem Iji obere Latency 10G MAC Intel ® FPGA IP na Intel ® Arria® 10 Ngwaọrụ
Ntuziaka mmejuputa iwu na-egosi gị otu esi eji Intel's Low Latency 10G Media Access Controller (MAC) na PHY IPs.
Ọgụgụ 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Sistemụ
Isiokwu 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
Tebụlụ a depụtara atụmatụ Intel® Arria® 10 niile maka Low Latency Ethernet 10G MAC Intel FPGA IP.
| Imepụta Example | MAC dị iche iche | PHY | Ngwa mmepe |
| 10GBase-R Ethernet | 10G | Ala nna PHY | Intel Arria 10 GX Transceiver SI |
| Ọnọdụ ndekọ 10GBase-R Ethernet |
10G | Ala nna PHY | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10G | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G/10G Ethernet | 1G/10G | 1G/10GbE na 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet nwere 1588 | 1G/10G | 1G/10GbE na 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet | 10M/100M/1G/10G | 1G/10GbE na 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Ethernet na 1588 |
10M/100M/1G/10G | 1G/10GbE na 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet | 1G/2.5G | 1G/2.5G/5G/10G Multi-ọnụego Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet nwere 1588 | 1G/2.5G | 1G/2.5G/5G/10G Multi-ọnụego Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G/10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-ọnụego Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-ọnụego Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke ụlọ ọrụ Intel ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
* Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
1. Na-eme ntuziaka maka 10G Ethernet Subsystem Iji Low Latency 10G MAC Intel® FPGA IP na Intel® Arria® 10 Ngwaọrụ
683347 | 2020.10.28
Mara:
Ị nwere ike ịnweta atụmatụ niile edepụtara site na onye na-edezi paramita IP Low Latency Ethernet 10G MAC Intel® FPGA na sọftụwia Intel Quartus Prime, belụsọ maka imepụta ntụaka XAUI Ethernet. Ị nwere ike nweta nhazi ntụaka XAUI Ethernet site na Ụlọ Ahịa Kere.
Intel na-enye MAC na PHY IP dị iche iche maka 10M ruo 1G Multi-rate Ethernet subsystems iji hụ na mmejuputa mgbanwe. Ị nwere ike ịmegharị Low Latency Ethernet 10G MAC Intel FPGA IP na 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE na 10GBASE-KR PHY, ma ọ bụ XAUI PHY na Intel Arria 10 Transceiver Native PHY ka ime ihe dị iche iche imewe chọrọ.
Ozi metụtara
- Obere Latency Ethernet 10G MAC ntuziaka onye ọrụ IP FPGA
Na-enye ozi zuru ezu gbasara ime ngwa ngwa na imezi MAC IP. - Obere Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example ntuziaka onye ọrụ
Na-enye ozi zuru ezu gbasara ịme ngwa ngwa na nhazi ihe nhazi MAC nke mbụamples. - Intel Arria 10 Transceiver PHY ntuziaka onye ọrụ
Na-enye ozi zuru ezu gbasara itinye ngwa ngwa na ịhazi PHY IP. - Obere Latency Ethernet 10G MAC Debug Checklist
- AN 699: Iji Altera Ethernet Design Toolkit
Ngwa ngwa a na-enyere gị aka ịhazi ma na-eme atụmatụ nrụtụ aka Ethernet yana ihichapụ ihe ọ bụla metụtara Ethernet. - Nyocha osisi mmejọ maka okwu nrụrụaka data 10G MAC dị ala
- Arria 10 Low Latency Ethernet 10G MAC na XAUI PHY Reference Design
Na-enye ihe files maka nkọwa nkọwa.
1.1. Obere Latency Ethernet 10G MAC na Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Ị nwere ike hazie Intel Arria 10 Transceiver Native PHY Intel FPGA IP iji mejuputa 10GBASE-R PHY na Ethernet kpọmkwem oyi akwa anụ ahụ na-agba ọsọ na 10.3125 Gbps data ọnụego dị ka akọwara na Clause 49 nke nkọwa IEEE 802.3-2008.
Nhazi a na-enye XGMII na Low Latency Ethernet 10G MAC Intel FPGA IP ma mejuputa otu ọwa 10.3 Gbps PHY na-enye njikọ kpọmkwem na modul ngwa anya SFP + site na iji nkọwa eletriki SFI.
Intel na-enye 10GBASE-R Ethernet subsystem design exampma ị nwere ike ịmepụta atụmatụ ndị a n'ike n'ike site na iji Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Nhazi ndị a na-akwado ịme anwansị arụ ọrụ na nnwale ngwaike na ngwa mmepe Intel ahapụtara.
Ọgụgụ 2. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC na Intel Arria 10 Transceiver Native PHY na 10GBASE-R Design Example
Ọgụgụ 3. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC na Intel Arria 10 Transceiver Native PHY na 10GBASE-R Design Ex.ample na Register Agbanyere ụkpụrụ
Ozi metụtara
Obere Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example ntuziaka onye ọrụ
Na-enye ozi zuru ezu gbasara ịme ngwa ngwa na nhazi ihe nhazi MAC nke mbụamples.
1.2. Obere Latency Ethernet 10G MAC na XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP na-enye XGMII ka Low Latency Ethernet 10G MAC Intel FPGA IP wee mejuputa ụzọ anọ ọ bụla na 3.125 Gbps na interface PMD.
XAUI PHY bụ mmejuputa oyi akwa anụ ahụ akọwapụtara nke njikọ 10 Gigabit Ethernet akọwapụtara na nkọwapụta IEEE 802.3ae-2008.
Ị nwere ike nweta nrụtụ aka maka 10GbE subsystem emejuputa atumatu site na iji Low Latency Ethernet 10G MAC na XAUI PHY Intel FPGA IPs si Ụlọ Ahịa Kere. Nhazi ahụ na-akwado ịme anwansị arụ ọrụ yana nnwale ngwaike na ngwa mmepe Intel ahapụtara.
Ọgụgụ 4. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na XAUI PHY Reference Design 
Ozi metụtara
- Arria 10 Low Latency Ethernet 10G MAC na XAUI PHY Reference Design
Na-enye ihe files maka nkọwa nkọwa. - AN 794: Arria 10 Low Latency Ethernet 10G MAC na XAUI PHY Reference Design
1.3. Obere Latency Ethernet 10G MAC na 1G/10GbE na 10GBASEKR PHY Intel Arria 10 FPGA IPs
1G/10GbE na 10GBASE-KR PHY Intel Arria 10 FPGA IP na-enye MII, GMII na XGMII na Low Latency Ethernet 10G MAC Intel FPGA IP.
1G/10GbE na 10GBASE-KR PHY Intel Arria 10 FPGA IP mejuputa otu ọwa 10Mbps/100Mbps/1Gbps/10Gbps serial PHY. Atụmatụ ndị ahụ na-enye njikọ kpọmkwem na 1G / 10GbE abụọ ọsọ SFP + pluggable modul, 10M-10GbE 10GBASE-T na 10M / 100M / 1G / 10GbE 1000BASE-T ọla kọpa mpụga PHY ngwaọrụ, ma ọ bụ mgbawa-to-chip interfaces. Ndị isi IP ndị a na-akwado ọnụego data 10Mbps/100Mbps/1Gbps/10Gbps nwere ike ịhazigharị.
Intel na-enye dual-speed 1G/10GbE na multi-speed 10Mb/100Mb/1Gb/10GbE imewe ex.amples na ị nwere ike ịmepụta atụmatụ ndị a n'ike n'ike site na iji Low Latency
Ethernet 10G MAC Intel FPGA IP parameter nchịkọta akụkọ. Nhazi ndị a na-akwado ịme anwansị arụ ọrụ yana nnwale ngwaike na ngwa mmepe Intel ahapụtara.
Mmejuputa ọtụtụ ọsọ Ethernet subsystem na-eji 1G/10GbE ma ọ bụ 10GBASE-KR PHY Intel Arria 10 FPGA IP imewe chọrọ mmachi SDC ntuziaka maka ime ime PHY IP clocks na njikwa ngafe ngalaba elekere. Rụtụ aka na altera_eth_top.sdc file na imewe exampka ịmatakwu banyere ihe achọrọ create_generated_clock, set_clock_groups na set_false_path SDC constraints.
Ọgụgụ 5. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na Intel Arria 10 1G/10GbE na 10GBASE-KR Design Ex.ample (Ụdị 1G/10GbE)
Ọgụgụ 6. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na Intel Arria 10 1G/10GbE na 10GBASE-KR Design Ex.ample (10Mb/100Mb/1Gb/10GbE Ọnọdụ)
Ozi metụtara
Obere Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example ntuziaka onye ọrụ
Na-enye ozi zuru ezu gbasara ịme ngwa ngwa na nhazi ihe nhazi MAC nke mbụamples.
1.4. Obere Latency Ethernet 10G MAC na 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP maka ngwaọrụ Intel Arria 10 na-enye GMII na XGMII na Low Latency Ethernet 10G MAC Intel FPGA IP.
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP maka ngwaọrụ Intel Arria 10 na-emejuputa otu ọwa 1G/2.5G/5G/10Gbps serial PHY. Nhazi ahụ na-enye njikọ kpọmkwem na 1G/2.5GbE abụọ ọsọ SFP + pluggable modul, MGBASE-T na NBASE-T ọla kọpa mpụga PHY ngwaọrụ, ma ọ bụ mgbawa-na-chip interfaces. IP ndị a na-akwado ọnụego data 1G/2.5G/5G/10Gbps nwere ike ịhazigharị.
Intel na-enye dual-speed 1G/2.5GbE, multi-speed 1G/2.5G/10GbE MGBASE-T, na multispeed 1G/2.5G/5G/10GbE MGBASE-T imewe exampma ị nwere ike ịmepụta atụmatụ ndị a n'ike n'ike site na iji Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Nhazi ndị a na-akwado ịme anwansị arụ ọrụ yana nnwale ngwaike na ngwa mmepe Intel ahapụtara.
Ọgụgụ 7. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Ex.ample (Ụdị 1G/2.5G)
Maka multi-speed 1G/2.5GbE na 1G/2.5G/10GbE MBASE-T Ethernet subsystem mmejuputa atumatu site na iji 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP, Intel na-atụ aro ka i detuo transceiver reconfiguration modul (alt_mge_rcfg_a10. sv) nyere na imewe example. Modul a na-ahazigharị ọsọ ọwa transceiver site na 1G ruo 2.5G, ma ọ bụ ruo 10G, yana ọzọ.
Multi-speed 1G/2.5GbE na 1G/2.5G/10GbE MBASE-T Ethernet subsystem mmejuputa iwu na-achọkwara mmachi SDC akwụkwọ ntuziaka maka ime ime PHY IP clocks.
na elekere ngalaba ngafe njikwa. Rụtụ aka na altera_eth_top.sdc file na imewe exampka ịmatakwu banyere ihe achọrọ create_generated_clock, set_clock_groups na set_false_path SDC constraints.
Ọgụgụ 8. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Ex.ample (1G/2.5G/10GbE MBASE-T Ọnọdụ) 
Ọgụgụ 9. Mkpuchi na Tọgharia atụmatụ maka Low Latency Ethernet 10G MAC na 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Ex.ample (1G/2.5G/5G/10GbE NBASE-T Ọnọdụ)
Ozi metụtara
Obere Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design ExampNtuziaka onye ọrụ na-enye ozi zuru ezu gbasara ịme ngwa ngwa na imezi ihe nhazi MACamples.
1.5. Akụkọ Ndozigharị akwụkwọ maka AN 795: Ntinye ntuziaka maka 10G Ethernet Subsystem Iji Low Latency 10G MAC Intel FPGA IP na Intel Arria 10 Ngwaọrụ
| Ụdị akwụkwọ | Mgbanwe |
| 2020.10.28 | • Agbanwegharịrị aha ya dị ka Intel. • A kpọgharịrị akwụkwọ ahụ ka ọ bụrụ AN 795: Ntuziaka mmejuputa maka 10G Ethernet Subsystem Iji Low Latency 10G MAC Intel FPGA IP na Intel Arria 10 Devices. |
| Ụbọchị | Ụdị | Mgbanwe |
| Febụwarị-17 | 2017.02.01 | Ntọhapụ mbụ. |
AN 795: Nrụ ọrụ ntuziaka maka 10G Ethernet Subsystem Iji obere
Latency 10G MAC Intel ® FPGA IP na Intel® Arria® 10 Ngwaọrụ
Version nke Ntanetị
Zipu nzaghachi
Nọmba ederede: 683347
Ụdị: 2020.10.28
Akwụkwọ / akụrụngwa
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intel AN 795 Ntuziaka mmejuputa maka 10G Ethernet Subsystem Iji Low Latency 10G MAC [pdf] Ntuziaka onye ọrụ AN 795 Ntuziaka na-emejuputa maka 10G Ethernet Subsystem Iji Low Latency 10G MAC, AN 795, Ntuziaka na-emejuputa maka 10G Ethernet Subsystem Iji Low Latency 10G MAC, Ethernet Subsystem Iji Low Latency 10G MAC, Low Latency 10G MAC |
