User Guide for intel models including: AN 795 Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC, AN 795, Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC, Ethernet Subsystem Using Low Latency 10G MAC, Low Latency 10G MAC
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel FPGA IP in Intel Arria 10 Devices
Describes the implementing guidelines on how to use Intel's Low Latency 10G Media Access Controller (MAC) and PHY IPs.
AN 795: Implementing Guidelines
for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
Online Version Send Feedback
AN-795
ID: 683347 Version: 2020.10.28
Contents
Contents
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices ....................................................... 3 1.1. Low Latency Ethernet 10G MAC and Intel Arria 10 Transceiver Native PHY Intel FPGA IPs........................................................................................................... 4 1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel FPGA IPs...................................... 6 1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASE-KR PHY Intel Arria 10 FPGA IPs........................................................................................................... 7 1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IPs.................................................................................................... 9 1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel FPGA IP in Intel Arria 10 Devices......... 12
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
2
Send Feedback
683347 | 2020.10.28 Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
Figure 1.
The implementing guidelines show you how to use Intel's Low Latency 10G Media Access Controller (MAC) and PHY IPs.
Intel® Arria® 10 Low Latency Ethernet 10G MAC System
FPGA
Client Module
Avalon-ST Interface
Low Latency Ethernet 10G MAC IP
XGMII/ GMII/MII
PHY IP
Serial External Interface PHY
Table 1.
Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
This table lists all the Intel® Arria® 10 designs for Low Latency Ethernet 10G MAC Intel FPGA IP.
Design Example
MAC Variant
PHY
Development Kit
10GBase-R Ethernet
10G
Native PHY
Intel Arria 10 GX Transceiver SI
10GBase-R Register Mode Ethernet
10G
Native PHY
Intel Arria 10 GX Transceiver SI
XAUI Ethernet
10G
XAUI PHY
Intel Arria 10 GX FPGA
1G/10G Ethernet
1G/10G
1G/10GbE and 10GBASE-KR Intel Arria 10 GX Transceiver
PHY
SI
1G/10G Ethernet with 1588
1G/10G
1G/10GbE and 10GBASE-KR Intel Arria 10 GX Transceiver
PHY
SI
10M/100M/1G/10G Ethernet
10M/100M/1G/10G
1G/10GbE and 10GBASE-KR Intel Arria 10 GX Transceiver
PHY
SI
10M/100M/1G/10G Ethernet with 1588
10M/100M/1G/10G
1G/10GbE and 10GBASE-KR Intel Arria 10 GX Transceiver
PHY
SI
1G/2.5G Ethernet
1G/2.5G
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Intel Arria 10 GX Transceiver SI
1G/2.5G Ethernet with 1588
1G/2.5G
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Intel Arria 10 GX Transceiver SI
1G/2.5G/10G Ethernet
1G/2.5G/10G
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Intel Arria 10 GX Transceiver SI
10G USXGMII Ethernet
1G/2.5G/5G/10G (USXGMII)
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Intel Arria 10 GX Transceiver SI
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.
ISO 9001:2015 Registered
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Note:
You can access all the listed designs through the Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor in the Intel Quartus® Prime software, except for the XAUI Ethernet reference design. You can get the XAUI Ethernet reference design from the Design Store.
Intel offers separate MAC and PHY IPs for the 10M to 1G Multi-rate Ethernet subsystems to ensure flexible implementation. You can instantiate the Low Latency Ethernet 10G MAC Intel FPGA IP with 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE and 10GBASE-KR PHY, or XAUI PHY and Intel Arria 10 Transceiver Native PHY to cater different design requirements.
Related Information
· Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Provides detailed information about instantiating and parameterizing the MAC IP.
· Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Provides detailed information about instantiating and parameterizing the MAC design examples.
· Intel Arria 10 Transceiver PHY User Guide Provides detailed information about instantiating and parameterizing the PHY IP.
· Low Latency Ethernet 10G MAC Debug Checklist
· AN 699: Using the Altera Ethernet Design Toolkit This toolkit helps you to configure and run Ethernet reference designs as well as debug any Ethernet related issues.
· Fault Tree Analysis for Low Latency 10G MAC Data Corruption Issue
· Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design Provides the files for the reference design.
1.1. Low Latency Ethernet 10G MAC and Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
You can configure the Intel Arria 10 Transceiver Native PHY Intel FPGA IP to implement the 10GBASE-R PHY with the Ethernet specific physical layer running at 10.3125 Gbps data rate as defined in Clause 49 of the IEEE 802.3-2008 specification.
This configuration provides an XGMII to Low Latency Ethernet 10G MAC Intel FPGA IP and implements a single-channel 10.3 Gbps PHY providing a direct connection to an SFP+ optical module using SFI electrical specification.
Intel offers two 10GBASE-R Ethernet subsystem design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kits.
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
4
Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 2.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel Arria 10 Transceiver Native PHY in 10GBASE-R Design Example
avalon_st 32-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
rx_rst_n
reconfig_clk
tx_rst_n csr_rst_n csr_clk (125 MHz) rx_156_25_clk
Low-Latency Ethernet 10G MAC
rx_coreclkin tx_coreclkin rx_cdr_refclk tx_serial_clk
Arria 10 Transceiver Native PHY (10GBASE-R)
tx_156_25_clk
rx_312_50_clk
tx_312_50_clk
reconfig_rst
ref_clk 322.265625 MHz
312.25 MHz IOPLL 156.25 MHz
ATX PLL 5156.25 MHz
Reset Signal Clock Signal Data Signal
Send Feedback
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
5
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 3.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel Arria 10 Transceiver Native PHY in 10GBASE-R Design Example with Register Mode Enabled
avalon_st 32-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
rx_rst_n
reconfig_clk
tx_rst_n csr_rst_n csr_clk (125 MHz) rx_xcvr_clk 322.265625 MHz
Low-Latency Ethernet 10G MAC
rx_coreclkin tx_coreclkin rx_cdr_refclk tx_serial_clk
Arria 10 Transceiver Native PHY (10GBASE-R Register Mode)
rx_clkout
tx_clkout
tx_xcvr_clk 322.265625 MHz
reconfig_rst
ref_clk 322.265625 MHz
ATX PLL 5156.25 MHz
Reset Signal Clock Signal Data Signal
Related Information
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Provides detailed information about instantiating and parameterizing the MAC design examples.
1.2. Low Latency Ethernet 10G MAC and XAUI PHY Intel FPGA IPs
The XAUI PHY Intel FPGA IP provides an XGMII to Low Latency Ethernet 10G MAC Intel FPGA IP and implements four lanes each at 3.125 Gbps at the PMD interface.
The XAUI PHY is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-2008 specification.
You can obtain the reference design for the 10GbE subsystem implemented using Low Latency Ethernet 10G MAC and XAUI PHY Intel FPGA IPs from Design Store. The design supports functional simulation and hardware testing on designated Intel development kit.
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
6
Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 4.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
avalon_st 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
avalon_mm_csr 32-bit Interface
phy_mgmt_clk
rx_rst_n
reconfig_clk
tx_rst_n csr_rst_n csr_clk (100 MHz)
Low-Latency Ethernet 10G MAC
xgmii_rx_clk
xgmii_tx_clk
XAUI
pll_ref_clk
PHY
rx_156_25_clk
tx_bonding_clocks
tx_156_25_clk
rx_312_50_clk
reconfig_rst
tx_312_50_clk
phy_mgmt_clk_reset
ref_clk 156.25 MHz
312.50 MHz fPLL 156.25 MHz
ATX PLL 1562.50 MHz
Reset Signal Clock Signal Data Signal
Related Information
· Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design Provides the files for the reference design.
· AN 794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1.3. Low Latency Ethernet 10G MAC and 1G/10GbE and 10GBASEKR PHY Intel Arria 10 FPGA IPs
The 1G/10GbE and 10GBASE-KR PHY Intel Arria 10 FPGA IP provide MII, GMII and XGMII to Low Latency Ethernet 10G MAC Intel FPGA IP.
The 1G/10GbE and 10GBASE-KR PHY Intel Arria 10 FPGA IP implement a singlechannel 10Mbps/100Mbps/1Gbps/10Gbps serial PHY. The designs provide a direct connection to 1G/10GbE dual speed SFP+ pluggable modules, 10M10GbE 10GBASE-T and 10M/100M/1G/10GbE 1000BASE-T copper external PHY devices, or chip-to-chip interfaces. These IP cores support reconfigurable 10Mbps/100Mbps/1Gbps/10Gbps data rates.
Send Feedback
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
7
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Intel offers dual-speed 1G/10GbE and multi-speed 10Mb/100Mb/1Gb/10GbE design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kit.
The multi-speed Ethernet subsystem implementation using 1G/10GbE or 10GBASE-KR PHY Intel Arria 10 FPGA IP design requires manual SDC constraints for the internal PHY IP clocks and clock domain crossing handling. Refer to the altera_eth_top.sdc file in the design example to know more about the required create_generated_clock, set_clock_groups and set_false_path SDC constraints.
Figure 5.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel Arria 10 1G/10GbE and 10GBASE-KR Design Example (1G/10GbE Mode)
avalon_st 64-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
speed_sel
rx_rst_n
tx_rst_n csr_rst_n csr_clk (125 MHz) gmii_rx_clk
Low-Latency Ethernet 10G MAC
mgmt_clk xgmii_rx_clk xgmii_tx_clk rx_cdr_ref_clk_10g
Arria 10 1G/10GbE and 10GBASE-KR PHY (1G/10G Mode)
gmii_tx_clk
tx_serial_clk_10g
rx_156_25_clk
rx_cdr_ref_clk_1g
tx_156_25_clk
tx_serial_clk_1g
rx_312_50_clk
mgmt_clk_reset
led_link
tx_312_50_clk
usr_seq_reset
tx_clkout
ref_clk 644.5/ 322.265625 MHz
312.50 MHz IOPLL 156.25 MHz
ATX PLL 5156.25 MHz
refclk 125 MHz
fPLL 625 MHz
Reset Signal Clock Signal Data Signal
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
8
Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 6.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel Arria 10 1G/10GbE and 10GBASE-KR Design Example (10Mb/100Mb/1Gb/ 10GbE Mode)
avalon_st 32-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
speed_sel
rx_rst_n
tx_rst_n csr_rst_n csr_clk (125 MHz) gmii_rx_clk
Low-Latency Ethernet 10G MAC
mgmt_clk xgmii_rx_clk xgmii_tx_clk rx_cdr_ref_clk_10g
Arria 10 1G/10GbE and 10GBASE-KR PHY (10M/100M/ 1G/10G Mode)
gmii_tx_clk
tx_serial_clk_10g
rx_156_25_clk
rx_cdr_ref_clk_1g
tx_156_25_clk
tx_serial_clk_1g
rx_312_50_clk
mgmt_clk_reset
mii_speed_set
tx_312_50_clk
usr_seq_reset
tx_clkout
ref_clk 644.5/ 322.265625 MHz
312.50 MHz IOPLL 156.25 MHz
ATX PLL 5156.25 MHz
refclk 125 MHz
fPLL 625 MHz
Reset Signal Clock Signal Data Signal
Related Information
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Provides detailed information about instantiating and parameterizing the MAC design examples.
1.4. Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
The 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP for Intel Arria 10 devices provides GMII and XGMII to the Low Latency Ethernet 10G MAC Intel FPGA IP.
Send Feedback
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
9
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 7.
The 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP for Intel Arria 10 devices implements a single-channel 1G/2.5G/5G/10Gbps serial PHY. The design provides a direct connection to 1G/2.5GbE dual speed SFP+ pluggable modules, MGBASE-T and NBASE-T copper external PHY devices, or chip-to-chip interfaces. These IPs support reconfigurable 1G/2.5G/5G/10Gbps data rates.
Intel offers dual-speed 1G/2.5GbE, multi-speed 1G/2.5G/10GbE MGBASE-T, and multispeed 1G/2.5G/5G/10GbE MGBASE-T design examples and you can generate these designs dynamically using the Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. The designs support functional simulation and hardware testing on designated Intel development kit.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G Mode)
avalon_st 32-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
speed_sel rx_rst_n
tx_rst_n csr_rst_n csr_clk (125 MHz)
Low-Latency Ethernet 10G MAC
csr_clk reconfig_clk rx_cdr_clk
1G/2.5G/5G/10G Multi-Rate Ethernet PHY
(1G/2.5G Mode)
gmii16n_rx_clk gmii16b_tx_clk
tx_serial_clk
rx_156_25_clk tx_156_25_clk
operating_speed
reconfig_reset
rx_clkout
reset
tx_clkout
IOPLL 156.25 MHz ATX PLL 1562.50 MHz
fPLL 625 MHz
Reset Signal Clock Signal Data Signal
For multi-speed 1G/2.5GbE and 1G/2.5G/10GbE MBASE-T Ethernet subsystem implementations using 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP, Intel recommends you copy the transceiver reconfiguration module
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
10
Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 8.
(alt_mge_rcfg_a10.sv) provided with the design example. This module reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.
The multi-speed 1G/2.5GbE and 1G/2.5G/10GbE MBASE-T Ethernet subsystem implementation also requires manual SDC constraints for the internal PHY IP clocks and clock domain crossing handling. Refer to the altera_eth_top.sdc file in the design example to know more about the required create_generated_clock, set_clock_groups and set_false_path SDC constraints.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/10GbE MBASE-T Mode)
avalon_st 64-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 72-bit Interface
avalon_mm_csr 32-bit Interface
speed_sel
xcvr_mode
rx_rst_n
tx_rst_n csr_rst_n csr_clk (125 MHz)
Low-Latency Ethernet 10G MAC
csr_clk reconfig_clk xgmii_rx_clk
1G/2.5G/5G/10G Multi-Rate Ethernet PHY
(MBASE-T Mode)
gmii_rx_clk
xgmii_tx_clk
gmii_tx_clk
tx_serial_clk
rx_156_25_clk
rx_cdr_refclk
tx_156_25_clk
operating_speed
rx_312_50_clk
reconfig_rst
rx_clkout
tx_312_50_clk
rst
tx_clkout
fPLL 625 MHz ATX PLL 1562.50 MHz
ref_clk 644.5/ 322.265625 MHz
ATX PLL 5156.25 MHz
312.50 MHz fPLL 156.25 MHz
Reset Signal Clock Signal Data Signal
Send Feedback
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
11
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Figure 9.
Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/5G/10GbE NBASE-T Mode)
avalon_st 64-bit Interface
avalon_mm_csr 32-bit Interface
XGMII 32-bit Interface
avalon_mm_csr 32-bit Interface
speed_sel
rx_rst_n
tx_rst_n csr_rst_n csr_clk (125 MHz)
Low-Latency Ethernet 10G MAC
csr_clk reconfig_clk xgmii_rx_clk
1G/2.5G/5G/10G Multi-Rate Ethernet PHY
(NBASE-T Mode)
xgmii_tx_clk
tx_serial_clk
rx_156_25_clk
rx_cdr_refclk
tx_156_25_clk
operating_speed
rx_312_50_clk
reconfig_rst
tx_312_50_clk
rst
ref_clk 644.5/ 322.265625 MHz
312.50 MHz fPLL 156.25 MHz
ATX PLL 5156.25 MHz
Reset Signal Clock Signal Data Signal
Related Information
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Provides detailed information about instantiating and parameterizing the MAC design examples.
1.5. Document Revision History for AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel FPGA IP in Intel Arria 10 Devices
Document Version
2020.10.28
Changes
· Rebranded as Intel. · Renamed the document as AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using
Low Latency 10G MAC Intel FPGA IP in Intel Arria 10 Devices.
Date February 2017
Version 2017.02.01
Initial release.
Changes
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
12
Send Feedback
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
683347 | 2020.10.28
Send Feedback
AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC Intel® FPGA IP in Intel® Arria® 10 Devices
13
mailto:FPGAtechdocfeedback@intel.com?subject=Feedback%20on%20AN%20795:%20Implementing%20Guidelines%20for%2010G%20Ethernet%20Subsystem%20Using%20Low%20Latency%2010G%20MAC%20Intel%20FPGA%20IP%20in%20Intel%20Arria%2010%20Devices%20(683347%202020.10.28)
FTA Low latency 10G MAC Data Corruption Issue - Intel Communities
1. Implementing Guidelines for 10G Ethernet Subsystem Using Low...