AN 795 Kugwiritsa Ntchito Malangizo a 10G
Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC
Wogwiritsa Ntchito
AN 795 Kugwiritsa Ntchito Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC
AN 795: Kukhazikitsa Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC Intel FPGA® IP mu Intel ® Arria® 10 Devices
Kukhazikitsa Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC Intel ® FPGA IP mu Intel ® Arria® 10 Devices
Malangizo ogwiritsira ntchito amakuwonetsani momwe mungagwiritsire ntchito Intel's Low Latency 10G Media Access Controller (MAC) ndi PHY IPs.
Chithunzi 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC System
Table 1. Intel® Arria® 10 Low Latency Ethernet 10G MAC Designs
Gome ili limatchula mapangidwe onse a Intel ® Arria® 10 a Low Latency Ethernet 10G MAC Intel FPGA IP.
| Design Example | Kusintha kwa MAC | PHY | Zida Zachitukuko |
| 10GBase-R Ethernet | 10g pa | Native PHY | Intel Arria 10 GX Transceiver SI |
| 10GBase-R Kulembetsa Mode Efaneti |
10g pa | Native PHY | Intel Arria 10 GX Transceiver SI |
| XAUI Efaneti | 10g pa | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G/10G Efaneti | 1G/10G | 1G/10GbE ndi 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/10G Ethernet yokhala ndi 1588 | 1G/10G | 1G/10GbE ndi 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Efaneti | 10M/100M/1G/10G | 1G/10GbE ndi 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M/100M/1G/10G Efaneti ndi 1588 |
10M/100M/1G/10G | 1G/10GbE ndi 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Efaneti | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G Ethernet yokhala ndi 1588 | 1G/2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G/2.5G/10G Efaneti | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Efaneti | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
1. Kugwiritsa Ntchito Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC Intel® FPGA IP mu Intel® Arria® 10 Devices
683347 | 2020.10.28
Zindikirani:
Mutha kupeza mapangidwe onse omwe adalembedwa kudzera pa Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor mu Intel Quartus Prime software, kupatulapo XAUI Ethernet reference design. Mutha kupeza mawonekedwe amtundu wa XAUI Ethernet kuchokera ku Design Store.
Intel imapereka ma IP osiyana a MAC ndi PHY a 10M mpaka 1G Multi-rate Ethernet subsystems kuti atsimikizire kukhazikitsidwa kosinthika. Mutha kulimbikitsa Low Latency Ethernet 10G MAC Intel FPGA IP ndi 1G/2.5G/5G/10G Multi-rate Ethernet PHY, Intel Arria 10 1G/10GbE ndi 10GBASE-KR PHY, kapena XAUI PHY ndi Intel Arria 10 Native PHYver kupita perekani zofunikira zosiyanasiyana zapangidwe.
Zambiri Zogwirizana
- Low Latency Ethernet 10G MAC Intel FPGA IP User Guide
Amapereka zambiri mwatsatanetsatane za instantiating ndi parameterizing MAC IP. - Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Exampndi User Guide
Imakupatsirani zambiri za instantiating ndi parameterizing MAC design examples. - Intel Arria 10 Transceiver PHY User Guide
Imakupatsirani zambiri za instantiating ndi parameterizing PHY IP. - Low Latency Ethernet 10G MAC Debug Checklist
- AN 699: Kugwiritsa Ntchito Altera Ethernet Design Toolkit
Chida ichi chimakuthandizani kukonza ndikuyendetsa mapangidwe a Ethernet komanso kukonza zolakwika zilizonse zokhudzana ndi Efaneti. - Fault Tree Analysis for Low Latency 10G MAC Data Corruption Issue
- Arria 10 Low Latency Ethernet 10G MAC ndi XAUI PHY Reference Design
Amapereka files kwa kamangidwe kalozera.
1.1. Low Latency Ethernet 10G MAC ndi Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Mutha kusintha Intel Arria 10 Transceiver Native PHY Intel FPGA IP kuti mugwiritse ntchito 10GBASE-R PHY yokhala ndi mawonekedwe amtundu wa Ethernet omwe akuyenda pamlingo wa data wa 10.3125 Gbps monga tafotokozera mu Ndime 49 ya mafotokozedwe a IEEE 802.3-2008.
Kukonzekera kumeneku kumapereka XGMII ku Low Latency Ethernet 10G MAC Intel FPGA IP ndipo imagwiritsa ntchito njira imodzi ya 10.3 Gbps PHY yopereka kulumikizana kwachindunji ku SFP + Optical module pogwiritsa ntchito SFI magetsi.
Intel imapereka mapangidwe awiri a 10GBASE-R Ethernet subsystem examples ndipo mutha kupanga mapangidwewa mwamphamvu pogwiritsa ntchito Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Mapangidwewa amathandizira kayeseleledwe kogwira ntchito komanso kuyesa kwa hardware pa zida zachitukuko za Intel.
Chithunzi 2. Kutseka ndi Kukonzanso Scheme kwa Low Latency Ethernet 10G MAC ndi Intel Arria 10 Transceiver Native PHY mu 10GBASE-R Design Example
Chithunzi 3. Kutseka ndi Kukonzanso Scheme kwa Low Latency Ethernet 10G MAC ndi Intel Arria 10 Transceiver Native PHY mu 10GBASE-R Design Exampndi Register Mode Wayatsidwa
Zambiri Zogwirizana
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Exampndi User Guide
Imakupatsirani zambiri za instantiating ndi parameterizing MAC design examples.
1.2. Low Latency Ethernet 10G MAC ndi XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP imapereka XGMII ku Low Latency Ethernet 10G MAC Intel FPGA IP ndipo imagwiritsa ntchito misewu inayi iliyonse pa 3.125 Gbps pa mawonekedwe a PMD.
XAUI PHY ndikukhazikitsa kwapadera kwa ulalo wa 10 Gigabit Ethernet wofotokozedwa mu IEEE 802.3ae-2008.
Mutha kupeza mawonekedwe amtundu wa 10GbE wokhazikitsidwa pogwiritsa ntchito Low Latency Ethernet 10G MAC ndi XAUI PHY Intel FPGA IPs kuchokera ku Design Store. Mapangidwewa amathandizira kayeseleledwe kogwira ntchito komanso kuyesa kwa hardware pa zida zachitukuko za Intel.
Chithunzi 4. Kutseka ndi Kukonzanso Scheme kwa Low Latency Ethernet 10G MAC ndi XAUI PHY Reference Design 
Zambiri Zogwirizana
- Arria 10 Low Latency Ethernet 10G MAC ndi XAUI PHY Reference Design
Amapereka files kwa kamangidwe kalozera. - AN 794: Arria 10 Low Latency Ethernet 10G MAC ndi XAUI PHY Reference Design
1.3. Low Latency Efaneti 10G MAC ndi 1G/10GbE ndi 10GBASEKR PHY Intel Arria 10 FPGA IPs
1G/10GbE ndi 10GBASE-KR PHY Intel Arria 10 FPGA IP imapereka MII, GMII ndi XGMII ku Low Latency Ethernet 10G MAC Intel FPGA IP.
1G/10GbE ndi 10GBASE-KR PHY Intel Arria 10 FPGA IP imagwiritsa ntchito njira imodzi ya 10Mbps/100Mbps/1Gbps/10Gbps PHY. Mapangidwewa amapereka kugwirizana kwachindunji kwa 1G/10GbE dual speed SFP+ pluggable modules, 10M–10GbE 10GBASE-T ndi 10M/100M/1G/10GbE 1000BASE-T zamkuwa zakunja za PHY zipangizo, kapena chip-to-chip interfaces. Ma IP cores awa amathandizira 10Mbps/100Mbps/1Gbps/10Gbps mitengo ya data.
Intel imapereka 1G/10GbE yapawiri-liwiro ndi ma multi-liwiro 10Mb/100Mb/1Gb/10GbEamples ndipo mutha kupanga mapangidwe awa mwamphamvu pogwiritsa ntchito Low Latency
Ethernet 10G MAC Intel FPGA IP parameter editor. Mapangidwewa amathandizira kayeseleledwe kogwira ntchito komanso kuyesa kwa Hardware pa zida zopangidwira za Intel.
Kukhazikitsa kwa ma multi-speed Ethernet subsystem pogwiritsa ntchito 1G/10GbE kapena 10GBASE-KR PHY Intel Arria 10 FPGA IP kumafuna zoletsa za SDC za mawotchi amkati a PHY IP ndi mawotchi odutsa mawotchi. Onani ku atera_eth_top.sdc file mu design exampndidziwe zambiri za zofunikira create_generated_clock, set_clock_groups ndi set_false_path SDC constraints.
Chithunzi 5. Kutseka ndi Kukonzanso Scheme kwa Low Latency Efaneti 10G MAC ndi Intel Arria 10 1G/10GbE ndi 10GBASE-KR Design Example (1G/10GbE Mode)
Chithunzi 6. Kutseka ndi Kukonzanso Scheme kwa Low Latency Efaneti 10G MAC ndi Intel Arria 10 1G/10GbE ndi 10GBASE-KR Design Example (10Mb/100Mb/1Gb/10GbE)
Zambiri Zogwirizana
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Exampndi User Guide
Imakupatsirani zambiri za instantiating ndi parameterizing MAC design examples.
1.4. Low Latency Efaneti 10G MAC ndi 1G/2.5G/5G/10G MultiRate Ethernet PHY Intel FPGA IPs
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP ya zida za Intel Arria 10 imapereka GMII ndi XGMII ku Low Latency Ethernet 10G MAC Intel FPGA IP.
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP ya zida za Intel Arria 10 imagwiritsa ntchito njira imodzi ya 1G/2.5G/5G/10Gbps PHY. Mapangidwewa amapereka kugwirizana kwachindunji kwa 1G / 2.5GbE awiri othamanga SFP + pluggable modules, MGBASE-T ndi NBASE-T zamkuwa zakunja za PHY zipangizo, kapena chip-to-chip interfaces. Ma IP awa amathandizira kusinthika kwa data 1G/2.5G/5G/10Gbps.
Intel imapereka 1G/2.5GbE yapawiri-speed, 1G/2.5G/10GbE MGBASE-T, ndi ma multispeed 1G/2.5G/5G/10GbE MGBASE-T examples ndipo mutha kupanga mapangidwewa mwamphamvu pogwiritsa ntchito Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Mapangidwewa amathandizira kayeseleledwe kogwira ntchito komanso kuyesa kwa hardware pa zida zachitukuko za Intel.
Chithunzi 7. Kutseka ndi Kukonzanso Scheme kwa Low Latency Efaneti 10G MAC ndi 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G Mode)
Kwa ma 1G/2.5GbE othamanga kwambiri ndi 1G/2.5G/10GbE MBASE-T Ethernet subsystem pogwiritsa ntchito 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP, Intel ikukulangizani kuti mukopere gawo lokonzanso transceiver (alt_mge_rcf. sv) zoperekedwa ndi kapangidwe kakaleample. Gawoli limakonzanso liwiro la njira ya transceiver kuchokera ku 1G kupita ku 2.5G, kapena kupita ku 10G, ndi mosemphanitsa.
Kukhazikitsa ma multi-speed 1G/2.5GbE ndi 1G/2.5G/10GbE MBASE-T Ethernet subsystem kumafunikanso zoletsa zapamanja za SDC za mawotchi amkati a PHY IP.
ndi wotchi ankalamulira kuwoloka akugwira. Onani ku atera_eth_top.sdc file mu design exampndidziwe zambiri za zofunikira create_generated_clock, set_clock_groups ndi set_false_path SDC constraints.
Chithunzi 8. Kutseka ndi Kukonzanso Scheme kwa Low Latency Efaneti 10G MAC ndi 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/10GbE MBASE-T Mode) 
Chithunzi 9. Kutseka ndi Kukonzanso Scheme kwa Low Latency Efaneti 10G MAC ndi 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/5G/10GbE NBASE-T Mode)
Zambiri Zogwirizana
Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example Upangiri Wogwiritsa Imapereka zambiri zatsatanetsatane komanso kuyika mawonekedwe a MAC examples.
1.5. Mbiri Yokonzanso Zolemba za AN 795: Kukhazikitsa Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC Intel FPGA IP mu Intel Arria 10 Devices
| Document Version | Zosintha |
| 2020.10.28 | • Adasinthidwanso kukhala Intel. • Anatchanso chikalatacho kukhala AN 795: Kutsatira Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Low Latency 10G MAC Intel FPGA IP mu Intel Arria 10 Devices. |
| Tsiku | Baibulo | Zosintha |
| February-17 | 2017.02.01 | Kutulutsidwa koyamba. |
AN 795: Kukhazikitsa Malangizo a 10G Ethernet Subsystem Pogwiritsa Ntchito Pang'ono
Latency 10G MAC Intel ® FPGA IP mu Intel® Arria® 10 Devices
Baibulo Lomasulira
Tumizani Ndemanga
ID: 683347
Mtundu: 2020.10.28
Zolemba / Zothandizira
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