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User GuideIntel Fronthaul Compression FPGA IP

Fronthaul Compression FPGA IP

Fronthaul Compression Intel® FPGA IP User Guide
Yakagadziridzwa Intel® Quartus® Prime
Dhizaini Suite: 21.4 IP
Shanduro: 1.0.1

Nezve Fronthaul Compression Intel® FPGA IP

Iyo Fronthaul Compression IP ine compression uye decompression yeU-ndege IQ data. Injini yekumanikidza inoverengera µ-mutemo kana block inoyangarara-point compression zvichibva pamushandisi data compression musoro (udCompHdr). Iyi IP inoshandisa Avalon yekushambadzira interface yeIQ data, masaini masaini, uye metadata uye sideband masaini, uye Avalon memory-mapped interface yekutonga uye mamiriro marejista (CSRs).
Iyo IP mepu yakadzvanya maIQ uye mushandisi data compression parameter (udCompParam) sekuenderana nechikamu chekubhadhara furemu fomati yakataurwa muO-RAN yakatarwa O-RAN Fronthaul Control, Mushandisi uye Synchronization Plane Version 3.0 Kubvumbi 2020 (O-RAN-WG4.CUS .0-v03.00). Avalon yekushambadzira sink uye source interface data hupamhi ndeye 128-bits yeiyo application interface uye 64 bits yekufambisa interface kutsigira yakanyanya compressoin reshiyo ye2: 1.
Related Information
O-RAN website
1.1. Fronthaul Compression Intel® FPGA IP Zvimiro

  • -mutemo uye block inoyangarara-point compression uye decompression
  • IQ yakafara 8-bit kusvika 16-bit
  • Yakatsiga uye ine simba kumisikidzwa yeU-ndege IQ fomati uye compression musoro
  • Multisections packet (kana O-RAN Inopindirana iripo)

1.2. Fronthaul Compression Intel® FPGA IP Chishandiso cheMhuri Tsigiro
Intel inopa anotevera dhizaini mazinga eIntel FPGA IP:

  • Rutsigiro rwepamberi-iyo IP inowanikwa kuti iedze uye iunganidze iyi mhuri yemudziyo. FPGA chirongwa file (.pof) tsigiro haiwanikwe yeQuartus Prime Pro Stratix 10 Edition Beta software uye sekuvharwa kweIP nguva hakugone kuvimbiswa. Modhi dzenguva dzinosanganisira yekutanga fungidziro yeinjiniya yekunonoka zvichienderana neruzivo rwekutanga post-rongedzo. Iwo mamodhi enguva anogona kushanduka sezvo silicon yekuyedza inovandudza kuwirirana pakati peiyo chaiyo silicon nemhando dzenguva. Iwe unogona kushandisa iyi IP musimboti wehurongwa hwekuvaka uye zviwanikwa zvekushandisa zvidzidzo, simulation, pinout, system latency assessments, basic time assessments (pipeline budgeting), uye I/O transfer strategy (data-nzira upamhi, kuputika kudzika, I/O zviyero tradeoffs. )
  • Yekutanga tsigiro-Intel inosimbisa iyo IP musimboti ine yekutanga nguva modhi yemhuri yemudziyo uyu. Iyo IP musimboti inosangana nezvose zvinoshanda zvinodiwa, asi inogona kunge ichiri kuongororwa nguva yemhuri yemudziyo. Iwe unogona kuishandisa mune zvigadzirwa zvekugadzira nekuchenjerera.
  • Rutsigiro rwekupedzisira-Intel inosimbisa iyo IP nemhando dzekupedzisira dzenguva yemhuri yemudziyo uyu. Iyo IP inosangana nezvose zvinoshanda uye nguva zvinodiwa zvemhuri yemudziyo. Iwe unogona kuishandisa mukugadzira zvigadzirwa.

Tafura 1. Fronthaul Compression IP Device Family Support

Mudziyo Mhuri Support
Intel® Agilex™ (E-tile) Preliminary
Intel Agilex (F-tile) Advance
Intel Arria® 10 Final
Intel Stratix® 10 (H-, uye E-tile zvishandiso chete) Final
Dzimwe mudziyo mhuri Hapana rutsigiro

Tafura 2. Mudziyo Unotsigirwa Speed ​​​​Grades

Mudziyo Mhuri FPGA Fabric Speed ​​​​Giredhi
Intel Agilex 3
Intel Arria 10 2
Intel Stratix 10 2

1.3. Kuburitsa Ruzivo rweFronthaul Compression Intel FPGA IP
Intel FPGA IP shanduro dzinoenderana neIntel Quartus® Prime Design Suite software shanduro kusvika v19.1. Kutanga muIntel Quartus Prime Design Suite software vhezheni 19.2, Intel FPGA IP ine chirongwa chitsva chekushandura.
Iyo Intel FPGA IP vhezheni (XYZ) nhamba inogona kuchinja neimwe Intel Quartus Prime software shanduro. Shanduko mu:

  • X inoratidza kudzokororwa kukuru kweIP. Kana iwe ukagadzirisa iyo Intel Quartus Prime software, iwe unofanirwa kuvandudza iyo IP.
  • Y inoratidza iyo IP inosanganisira zvinhu zvitsva. Gadzirisa IP yako kuti ubatanidze zvinhu zvitsva izvi.
  • Z inoratidza iyo IP inosanganisira shanduko diki. Gadzirisa IP yako kuti ubatanidze shanduko idzi.

Tafura 3. Fronthaul Compression IP Release Information

Item Tsanangudzo
Version 1.0.1
Zuva rekuburitswa Kukadzi 2022
Kodhi yekuraira IP-FH-COMP

1.4. Fronthaul Compression Performance uye Resource Usage
Zviwanikwa zveIP yakanangana neIntel Agilex mudziyo, Intel Arria 10 mudziyo, uye Intel Stratix 10 mudziyo.
Tafura 4. Fronthaul Compression Performance uye Resource Usage
Zvese zvinopinda ndezvekumanikidza uye decompression data nzira IP

Mudziyo IP ALMs Manyorerwo ane musoro M20K
  Primary Secondary
Intel Agilex Block-floating point 14,969 25,689 6,093 0
µ-mutemo 22,704 39,078 7,896 0
Block-inoyangarara nzvimbo uye µ-mutemo 23,739 41,447 8,722 0
Block-inoyangarara nzvimbo, µ-mutemo, uye yakawedzera IQ hupamhi 23,928 41,438 8,633 0
Intel Arria 10 Block-floating point 12,403 16,156 5,228 0
µ-mutemo 18,606 23,617 5,886 0
Block-inoyangarara nzvimbo uye µ-mutemo 19,538 24,650 6,140 0
Block-inoyangarara nzvimbo, µ-mutemo, uye yakawedzera IQ hupamhi 19,675 24,668 6,141 0
Intel Stratix 10 Block-floating point 16,852 30,548 7,265 0
µ-mutemo 24,528 44,325 8,080 0
Block-inoyangarara nzvimbo uye µ-mutemo 25,690 47,357 8,858 0
Block-inoyangarara nzvimbo, µ-mutemo, uye yakawedzera IQ hupamhi 25,897 47,289 8,559 0

Kutanga neFronthaul Compression Intel FPGA IP

Inotsanangura kuisa, parameterizing, simulating, uye kutanga iyo Fronthaul Compression IP.
2.1. Kuwana, Kuisa, uye Rezinesi iyo Fronthaul Compression IP
Iyo Fronthaul Compression IP ndeye yakawedzera Intel FPGA IP iyo isingabatanidzwe neIntel Quartus Prime kuburitswa.

  1. Gadzira Yangu Intel account kana iwe usina.
  2. Pinda mukati kuti uwane iyo Self-Service Licensing Center (SSLC).
  3. Tenga iyo Fronthaul Compression IP.
  4. Pa peji reSSLC, tinya Mhanyai IP. Iyo SSLC inopa yekuisa dialog bhokisi kutungamira kuisirwa kwako kweIP.
  5. Isa kunzvimbo imwechete seIntel Quartus Prime folda.

Tafura 5. Fronthaul Compression Installation Nzvimbo

Nzvimbo Software Platform
:\intelFPGA_pro\\quartus\ip \altera_cloud Intel Quartus Prime Pro Edition Windows *
:/intelFPGA_pro// quartus/ip/altera_cloud Intel Quartus Prime Pro Edition Linux *

Mufananidzo 1. Fronthaul Compression IP Installation Directory Structure Intel Quartus Prime installation directory

Intel Fronthaul Compression FPGA IP fig 7
Iyo Fronthaul Compression Intel FPGA IP ikozvino yaonekwa muIP Catalog.
Related Information

  • Intel FPGA website
  • Self-Service Licensing Center (SSLC)

2.2. Parameterizing iyo Fronthaul Compression IP
Kurumidza gadzirisa yako IP mutsauko muIP Parameter Mharidzo.

  1. Gadzira iyo Intel Quartus Prime Pro Edition chirongwa chekubatanidza yako IP musimboti.
    a. MuIntel Quartus Prime Pro Edition, tinya File Nyowani Project Wizard kugadzira itsva Intel Quartus Prime purojekiti, kana File Vhura Project kuvhura iripo Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo.
    b. Taura mhuri yemudziyo inosangana nekumhanyisa giredhi zvinodiwa zveIP.
    c. Dzvanya Finish.
  2. Mune IP Catalog, sarudza Fronthaul Compression Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
  3. Taura zita repamusoro-soro kune yako itsva tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
  4. Dzvanya OK. Iyo parameter editor inooneka.
    Intel Fronthaul Compression FPGA IP fig 6Mufananidzo 2. Fronthaul Compression IP Parameter Editor
  5. Rondedzera maparameter eiyo IP musiyano. Tarisa kuParameters kune ruzivo nezve chaiyo IP paramita.
  6. Dzvanya iyo Dhizaini Example tab uye tsanangura maparamita edhizaini yako example.
    Intel Fronthaul Compression FPGA IP fig 5Mufananidzo 3. Dhizaini Exampuye Parameter Editor
  7. Dzvanya Gadzira HDL. The Generation dialog box inoonekwa.
  8. Taura zvabuda file chizvarwa sarudzo, wobva wadzvanya Gadzira. Iyo IP musiyano files gadzira zvinoenderana nezvaunoda.
  9. Dzvanya Finish. Iyo parameter editor inowedzera yepamusoro-level .ip file kune purojekiti yazvino otomatiki. Kana ukakumbirwa kuti uwedzere nemaoko .ip file kupurojekiti, tinya Project Wedzera/Bvisa Files muProjekti yekuwedzera iyo file.
  10. Mushure mekugadzira uye nekumisikidza yako IP kusiyanisa, ita yakakodzera pini migove yekubatanidza madoko uye kuseta chero yakakodzera pa-chiitiko RTL paramita.

2.2.1. Fronthaul Compression IP Parameters
Tafura 6. Fronthaul Compression IP Parameters

Zita Hunhu Hunoshanda

Tsanangudzo

Data direction TX uye RX, TX chete, RX chete Sarudza TX yekumanikidza; RX ye decompression.
Compression nzira BFP, mu-Law, kana BFP uye mu-Law Sarudza block inoyangarara-nzvimbo, µ-mutemo, kana zvese.
Metadata yakafara 0 (Dzima Metadata Ports), 32, 64, 96, 128 (bit) Taura hupamhi hudiki hwebhazi remetadata (data isina kudzvanywa).
Gonesa IQ yakawedzera upamhi Kudzima kana kudzima Batidza IqWidth inotsigirwa ye8-bit kusvika 16-bit.
Dzima kune inotsigirwa IqWidth ye9, 12, 14 uye 16-bits.
O-RAN inoenderana Kudzima kana kudzima Batidza kuti uteedzere ORAN IP mepu yemetadata port uye taura metadata inoshanda chiratidzo chechikamu chega chega. Iyo IP inotsigira 128-bit wide metadata chete. Iyo IP inotsigira chikamu chimwe chete uye akawanda zvikamu pakiti. Metadata inoshanda pachikamu chega chega ine metadata inogoneka.
Dzima kuti IP ishandise metadata senge passthrough conduit masiginecha pasina chinodiwa chemepu (semuenzaniso: U-ndege numPrb inofungidzirwa 0). Iyo IP inotsigira metadata upamhi hwe0 (Disable Metadata Ports), 32, 64, 96, 128 bits. IP inotsigira chikamu chimwe chete pakiti. Metadata inoshanda kamwe chete pane metadata inogoneka yekusimbisa packet yega yega.

2.3. Yakagadzirwa IP File Chimiro
Iyo Intel Quartus Prime Pro Edition software inogadzira inotevera IP musimboti kubuda file chimiro.
Tafura 7. Yakagadzirwa IP Files

File Zita

Tsanangudzo

<yako_ip>.ip Iyo Platform Dhizaini system kana yepamusoro-level IP musiyano file.yako_ip> ndiro zita raunopa IP yako kusiyana.
<yako_ip>.cmp The VHDL Component Declaration (.cmp) file chinyorwa file iyo ine yemuno generic uye chiteshi tsananguro dzaunogona kushandisa muVHDL dhizaini files.
<yako_ip>.html Chirevo chine ruzivo rwekubatanidza, mepu yendangariro inoratidza kero yemuranda wega wega neruremekedzo kune yega tenzi kwayakabatanidzwa, uye parameter migove.
<yako_ip>_generation.rpt IP kana Platform Dhizaini yechizvarwa log file. Pfupiso yemameseji panguva yeIP chizvarwa.
<yako_ip>.qgsimc Inonyora masimulation paramita kutsigira kuwedzera patsva.
<yako_ip>.qgsynthc Inonyora synthesis parameters kutsigira kuwedzera patsva.
<yako_ip>.qip Iine ruzivo rwese rwunodiwa nezve IP chikamu chekubatanidza uye kuunganidza iyo IP chikamu muIntel Quartus Prime software.
<yako_ip>.sopcinfo Inotsanangura zvinongedzo uye IP chikamu parameterizations mune yako Platform Dhizaini system. Iwe unogona kupenengura zvirimo kuti uwane zvinodiwa paunogadzira madhiraivha esoftware ezvikamu zveIP.
Maturusi ekudzika akadai seNios® II chishandiso cheni shandisa izvi file. The .sopcinfo file uye hurongwa.h file inogadzirwa yeNios II chishandiso cheni inosanganisira kero mepu ruzivo rwemuranda wega wega hama kuna tenzi wega anowana muranda. Vatenzi vakasiyana vanogona kuve nemepu yekero yakasiyana yekuwana chimwe chikamu chevaranda.
<yako_ip>.csv Iine ruzivo rwekusimudzira mamiriro echikamu cheIP.
<yako_ip>.bsf A Block Symbol File (.bsf) inomiririra IP kusiyana kwekushandiswa muIntel Quartus Prime Block Diagram Files (.bdf).
<yako_ip>.spd Inodiwa kuiswa file ye ip-make-simscript kugadzira zvinyorwa zvekunyepedzera zvemasimulator anotsigirwa. The .spd file ine runyorwa rwe files inogadzirwa yekufananidza, pamwe neruzivo nezve ndangariro dzaunogona kutanga.
<yako_ip>.ppf The Pin Planner File (.ppf) inochengetedza chiteshi chengarava uye node mabasa eIP zvikamu zvakagadzirirwa kushandiswa nePin Planner.
<yako_ip>_bb.v Unogona kushandisa Verilog dema-bhokisi (_bb.v) file sechinhu chisina chinhu chiziviso chekushandisa sebhokisi dema.
<yako_ip>_inst.v kana _inst.vhd HDL example instantiation template. Unogona kukopa nekunamira zviri mukati meizvi file muHDL yako file kusimbisa IP kusiyanisa.
<yako_ip>.v kanayako_ip>.vhd HDL files inosimbisa imwe neimwe submodule kana mwana IP musimboti we synthesis kana simulation.
mudzidzisi/ Ine ModelSim* script msim_setup.tcl yekumisikidza uye kuita simulation.
synopys/vcs/synopsy/vcsmx/ Ine shell script vcs_setup.sh yekumisikidza nekumhanyisa VCS* simulation.
Ine shell script vcsmx_setup.sh uye synopsys_ sim.setup file kumisikidza uye kumhanya VCS MX * simulation.
cadence/ Iine shell script ncsim_setup.sh uye kumwe kuseta files kumisikidza uye kumhanya NCSIM* simulation.
aldec/ Ine shell script rivierapro_setup.sh yekuseta uye mhanyisa Aldec* simulation.
xcelium/ Iine shell script xcelium_setup.sh uye kumwe kuseta files kumisikidza uye kumhanya Xcelium * simulation.
submodules/ Iine HDL files yeiyo IP musimboti submodules.
<mwana IP cores>/ Kune yega yega inogadzirwa mwana IP musimboti dhairekitori, Platform Dhizaini inogadzira synth/ uye sim/ sub-dhairekitori.

Fronthaul Compression IP Inoshanda Tsananguro

Mufananidzo 4. Iyo Fronthaul Compression IP inosanganisira kudzvinyirira uye decompression. Fronthaul Compression IP Block DiagramIntel Fronthaul Compression FPGA IP fig 4

Compression uye Decompression
A preprocessing block-based bit shift block inogadzira iyo yakakwana bit-shifts kune resource block yegumi nembiri resource element (REs). Iyo block inoderedza quantization ruzha, kunyanya kune yakaderera-amplitude samples. Saka, inoderedza kukanganisa vector magnitude (EVM) iyo compression inouyisa. Iyo compression algorithm inenge yakazvimirira pane kukosha kwesimba. Tichifunga iyo yakaoma kuisa samples is x = x1 + jxQ, iyo yakanyanya kukosha kukosha kweiyo chaiyo uye yekufungidzira zvikamu zveiyo resource block ndeiyi:
Intel Fronthaul Compression FPGA IP fig 3Kuve nehupamhi hwekupedzisira kukosha kweiyo resource block, iyo inotevera equation inosarudza iyo yekuruboshwe yeshift kukosha yakagoverwa kune iyo resource block:Intel Fronthaul Compression FPGA IP fig 2Iko bitWidth ndiko kupinza bhiti upamhi.
IP inotsigira compression ratios ye8, 9, 10, 11, 12, 13, 14, 15, 16.
Mu-Law Compression uye Decompression
Iyo algorithm inoshandisa Mu-law kuenzanisa nzira, iyo yekumanikidza yekutaura inoshandisa zvakanyanya. Iyi nzira inopfuudza iyo yekuisa isina kudzvanywa chiratidzo, x, kuburikidza ne compressor ine basa, f (x), isati yatenderedza uye bit-truncation. Iyo tekinoroji inotumira yakamanikidzwa data, y, pamusoro peiyo interface. Iyo data yakagamuchirwa inopfuura kuburikidza nekuwedzera basa (inova inverse yecompressor, F-1 (y) Nzira iyi inoburitsa data isina kudzvanywa nekukanganisa kushoma kwehuwandu.
Equation 1. Compressor uye decompressor mabasa
Intel Fronthaul Compression FPGA IP fig 1Iyo Mu-law IQ compression algorithm inotevera iyo O-RAN yakatarwa.
Related Information
O-RAN website
3.1. Fronthaul Compression IP Signals
Batanidza uye kudzora IP.
Clock uye Reset Interface Signals=
Tafura 8. Clock uye Reset Interface Signals

Zita rechiratidzo Bitwidth Direction

Tsanangudzo

tx_clk 1 Input Transmitter wachi.
Clock frequency ndeye 390.625 MHz ye25 Gbps uye 156.25MHz yegumi Gbps. Yese transmitter interface masaini anowirirana kune ino wachi.
rx_clk 1 Input Wachi yekugamuchira.
Clock frequency ndeye 390.625 MHz ye25 Gbps uye 156.25MHz yegumi Gbps. Yese inogamuchira masaini masaini anowirirana kune ino wachi.
csr_clk 1 Input Wachi yeCSR interface. Wachi frequency ndeye 100 MHz.
tx_rst_n 1 Input Active low reset ye transmitter interface synchronous to tx_clk.
rx_rst_n 1 Input Inoshanda yakaderera reset yeanogamuchira interface synchronous kune rx_clk.
csr_rst_n 1 Input Active yakaderera reset yeCSR interface synchronous kune csr_clk.

Transmit Transport Interface Signals
Tafura 9. Transmit Transport Interface Signals
Mhando dzese dzechiratidzo hadzina kusaina nhamba yakazara.

Zita rechiratidzo

Bitwidth Direction

Tsanangudzo

tx_avst_source_valid 1 Output Kana zvasimbiswa, zvinoratidza kuti data inoshanda iripo pa avst_source_data.
tx_avst_source_data 64 Output PRB minda inosanganisira udCompParam, iSample uye qsample. Chikamu chinotevera PRB minda yakabatana kune yapfuura chikamu PRB ndima.
tx_avst_source_startofpacket 1 Output Inoratidza yekutanga byte yefuremu.
tx_avst_source_endofpacket 1 Output Inoratidza yekupedzisira byte yefuremu.
tx_avst_source_ready 1 Input Kana yasimbiswa, inoratidza iyo yekufambisa layer yakagadzirira kugamuchira data. readyLatency = 0 yeiyi interface.
tx_avst_source_empty 3 Output Inotsanangura huwandu hwemabhaiti asina chinhu pa avst_source_data kana avst_source_endofpacket ichinzi.
tx_udcomphdr_o 8 Output Mushandisi data compression musoro ndima. Zvinoenderana ne tx_avst_source_valid.
Inotsanangura nzira yekumanikidza uye IQ bit hupamhi
ye data yemushandisi muchikamu che data.
• [7:4] : udIqWidth
• 16 ye udIqWidth=0, zvimwe yakaenzana udIqWidth e,g,:
- 0000b zvinoreva kuti I uye Q imwe neimwe 16 bits yakafara;
- 0001b zvinoreva kuti ini naQ imwe neimwe 1 bit yakafara;
- 1111b zvinoreva kuti ini naQ imwe neimwe 15 bits yakafara
• [3:0] : udCompMeth
- 0000b - hapana compression
- 0001b - block-floating point
— 0011b – µ-mutemo
- vamwe - zvakachengeterwa nzira dzemangwana.
tx_metadata_o METADATA_WIDTH Output Conduit masaini passthrough uye haana kumanikidzwa.
Zvinoenderana ne tx_avst_source_valid. Inogadzirika bitwidth METADATA_WIDTH.
Paunobatidza O-RAN inoenderana, kureva Tafura 13 papeji 17.Paunodzima O-RAN inoenderana, chiratidzo ichi chinoshanda chete kana tx_avst_source_startofpacket iri 1. tx_metadata_o isina chiratidzo uye inoshandisa tx_avst_source_valid kuratidza kutenderera kuripo.
Haiwanikwi paunosarudza 0 Dzima Metadata Ports nokuti Metadata yakafara.

Gamuchira Transport Interface Signals
Tafura 10. Gamuchira Transport Interface Signals
Hapana backpressure pane ino interface. Avalon yekufambisa isina chinhu chiratidzo haidiwi mune ino interface nekuti inogara iri zero.

Zita rechiratidzo Bitwidth Direction

Tsanangudzo

rx_avst_sink_valid 1 Input Kana zvasimbiswa, zvinoratidza kuti data inoshanda iripo pa avst_sink_data.
Hapana avst_sink_ready chiratidzo pane ino interface.
rx_avst_sink_data 64 Input PRB minda inosanganisira udCompParam, iSample uye qsample. Chikamu chinotevera PRB minda yakabatana kune yapfuura chikamu PRB ndima.
rx_avst_sink_startofpacket 1 Input Inoratidza yekutanga byte yefuremu.
rx_avst_sink_endofpacket 1 Input Inoratidza yekupedzisira byte yefuremu.
rx_avst_sink_error 1 Input Kana yakasimbiswa mukutenderera kumwechete se avst_sink_endofpacket, inoratidza pakiti iripo ikanganiso packet.
rx_udcomphdr_i 8 Input Mushandisi data compression musoro ndima. Zvinoenderana ne rx_metadata_valid_i.
Inotsanangura nzira yekumanikidza uye IQ bit hupamhi kune data remushandisi muchikamu chedata.
• [7:4] : udIqWidth
• 16 ye udIqWidth=0, zvimwe yakaenzana udIqWidth. eg
- 0000b zvinoreva kuti I uye Q imwe neimwe 16 bits yakafara;
- 0001b zvinoreva kuti ini naQ imwe neimwe 1 bit yakafara;
- 1111b zvinoreva kuti ini naQ imwe neimwe 15 bits yakafara
• [3:0] : udCompMeth
- 0000b - hapana compression
- 0001b - block inoyangarara nzvimbo
— 0011b – µ-mutemo
- vamwe - zvakachengeterwa nzira dzemangwana.
rx_metadata_i METADATA_WIDTH Input Uncompressed conduit inoratidza kupfuura.
rx_metadata_i masiginecha anoshanda kana rx_metadata_valid_i ichinzi, inopindirana ne rx_avst_sink_valid.
Inogadzirika bitwidth METADATA_WIDTH.
Paunobatidza O-RAN inoenderana, kureva Tafura 15 papeji 18.
Paunodzima O-RAN inoenderana, iyi rx_metadata_i siginecha inoshanda chete kana ese rx_metadata_valid_i uye rx_avst_sink_startofpacket akaenzana ne1. Haipo paunosarudza 0 Dzima Metadata Ports nokuti Metadata yakafara.
rx_metadata_valid_i 1 Input Inoratidza kuti misoro (rx_udcomphdr_i uye rx_metadata_i) inoshanda. Zvinoenderana ne rx_avst_sink_valid. Chiratidzo chinomanikidzwa. Nekuenderana neO-RAN kumashure, taura rx_metadata_valid_i kana IP iine maIE emusoro akajairika uye anodzokororwa chikamu maIE. Pakupa chikamu chitsva chemuviri wezvekushandisa block (PRB) minda mu rx_avst_sink_data, ipa chikamu chitsva maIE mune rx_metadata_i yekuisa pamwe ne rx_metadata_valid_i.

Tumira maApplication Interface Signals
Tafura 11. Transmit Application Interface Signals

Zita rechiratidzo

Bitwidth Direction

Tsanangudzo

tx_avst_sink_valid 1 Input Kana zvichinzi, zvinoratidza minda yePRB iripo mune ino interface.
Paunenge uchishanda mukutepfenyura modhi, ita shuwa kuti hapana kwakakodzera siginecha dessertion pakati pekutanga kwepacket uye kupera kwepakiti Inongosarudzika ndeye kana chiratidzo chakagadzirira chabviswa.
tx_avst_sink_data 128 Input Dhata kubva kune application layer mune network byte order.
tx_avst_sink_startofpacket 1 Input Ratidza yekutanga PRB byte yepakiti
tx_avst_sink_endofpacket 1 Input Ratidza yekupedzisira PRB byte yepakiti
tx_avst_sink_ready 1 Output Kana yasimbiswa, inoratidza iyo O-RAN IP yakagadzirira kugamuchira data kubva kune application interface. readyLatency = 0 yeiyi interface
tx_udcomphdr_i 8 Input Mushandisi data compression musoro ndima. Zvinoenderana ne tx_avst_sink_valid.
Inotsanangura nzira yekumanikidza uye IQ bit hupamhi kune data remushandisi muchikamu chedata.
• [7:4] : udIqWidth
• 16 ye udIqWidth=0, zvimwe yakaenzana udIqWidth. eg
- 0000b zvinoreva kuti I uye Q imwe neimwe 16 bits yakafara;
- 0001b zvinoreva kuti ini naQ imwe neimwe 1 bit yakafara;
- 1111b zvinoreva kuti ini naQ imwe neimwe 15 bits yakafara
• [3:0] : udCompMeth
- 0000b - hapana compression
- 0001b - block-floating point
— 0011b – µ-mutemo
- vamwe - zvakachengeterwa nzira dzemangwana.
tx_metadata_i METADATA_WIDTH Input Conduit masaini passthrough uye haana kumanikidzwa. Zvinoenderana ne tx_avst_sink_valid.
Inogadzirika bitwidth METADATA_WIDTH.
Paunobatidza O-RAN inoenderana, kureva Tafura 13 papeji 17.
Paunodzima O-RAN inoenderana, chiratidzo ichi chinoshanda chete kana tx_avst_sink_startofpacket yakaenzana ne1.
tx_metadata_i haina chiratidzo chinoshanda uye mashandisiro
tx_avst_sink_valid kuratidza kutenderera kuripo.
Haiwanikwi paunosarudza 0 Dzima Metadata Ports nokuti Metadata yakafara.

Gamuchira maApplication Interface Signals
Tafura 12. Gamuchira Application Interface Signals

Zita rechiratidzo

Bitwidth Direction

Tsanangudzo

rx_avst_source_valid 1 Output Kana zvichinzi, zvinoratidza minda yePRB iripo mune ino interface.
Hapana avst_source_ready siginecha pane ino interface.
rx_avst_source_data 128 Output Dhata kune application layer mune network byte order.
rx_avst_source_startofpacket 1 Output Inoratidza yekutanga PRB byte yepakiti
rx_avst_source_endofpacket 1 Output Inoratidza yekupedzisira PRB byte yepakiti
rx_avst_source_error 1 Output Inoratidza mapaketi ane kukanganisa
rx_udcomphdr_o 8 Output Mushandisi data compression musoro ndima. Zvinoenderana ne rx_avst_source_valid.
Inotsanangura nzira yekumanikidza uye IQ bit hupamhi kune data remushandisi muchikamu chedata.
• [7:4] : udIqWidth
• 16 ye udIqWidth=0, zvimwe yakaenzana udIqWidth. eg
- 0000b zvinoreva kuti I uye Q imwe neimwe 16 bits yakafara;
- 0001b zvinoreva kuti ini naQ imwe neimwe 1 bit yakafara;
- 1111b zvinoreva kuti ini naQ imwe neimwe 15 bits yakafara
• [3:0] : udCompMeth
- 0000b - hapana compression
- 0001b - block inoyangarara nzvimbo (BFP)
— 0011b – µ-mutemo
- vamwe - zvakachengeterwa nzira dzemangwana.
rx_metadata_o METADATA_WIDTH Output Uncompressed conduit inoratidza kupfuura.
rx_metadata_o masiginecha anoshanda kana rx_metadata_valid_o ichinzi, inopindirana ne rx_avst_source_valid.
Inogadzirika bitwidth METADATA_WIDTH. Paunobatidza O-RAN inoenderana, kureva Tafura 14 papeji 18.
Paunodzima O-RAN inoenderana, rx_metadata_o inoshanda chete kana rx_metadata_valid_o yakaenzana ne1.
Haiwanikwi paunosarudza 0 Dzima Metadata Ports nokuti Metadata yakafara.
rx_metadata_valid_o 1 Output Inoratidza kuti misoro (rx_udcomphdr_o uye
rx_metadata_o) inoshanda.
rx_metadata_valid_o inosimbiswa kana rx_metadata_o ichishanda, inopindirana ne rx_avst_source_valid.

Metadata Meta yeO-RAN Kumashure Kuenderana
Tafura 13. tx_metadata_i 128-bit kuisa

Zita rechiratidzo

Bitwidth Direction Tsanangudzo

Metadata Mapping

Reserved 16 Input Reserved. tx_metadata_i[127:112]
tx_u_size 16 Input U-ndege packet size mumabhaiti ekutepfenyura modhi. tx_metadata_i[111:96]
tx_u_seq_id 16 Input SeqID yepakiti, iyo inotorwa kubva eCPRI yekufambisa musoro. tx_metadata_i[95:80]
tx_u_pc_id 16 Input PCID ye eCPRI yekufambisa uye RoEflowId
yekufambisa kweredhiyo pamusoro peethernet (RoE).
tx_metadata_i[79:64]
Reserved 4 Input Reserved. tx_metadata_i[63:60]
tx_u_dataDirection 1 Input gNB data nzira.
Kukosha zvakasiyana: {0b=Rx (kureva kurodha), 1b=Tx (kureva kudhawunirodha)}
tx_metadata_i[59]
tx_u_filterIndex 4 Input Inotsanangura index kune chiteshi sefa kuti ishandiswe pakati peIQ data nemhepo interface.
Kukosha kwemhando: {0000b-1111b}
tx_metadata_i[58:55]
tx_u_frameId 8 Input Kaunda yegumi ms mafuremu (kupeta nguva 10 masekondi), kunyanya frameId= furemu nhamba modulo 2.56.
Kukosha kwemhando: {0000 0000b-1111 1111b}
tx_metadata_i[54:47]
tx_u_subframeId 4 Input Kaunda ye 1 ms subframes mukati me10 ms furemu. Kukosha kwemhando: {0000b-1111b} tx_metadata_i[46:43]
tx_u_slotID 6 Input Iyi parameter ndiyo nhamba ye slot mukati me 1 ms subframe. Yese slots mune imwe subframe inoverengerwa neiyi parameter.
Kukosha kwakasiyana: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Zvakachengetwa}
tx_metadata_i[42:37]
tx_u_symbolid 6 Input Inozivisa nhamba yechiratidzo mukati me slot. Kukosha kwemhando: {00 0000b-11 1111b} tx_metadata_i[36:31]
tx_u_sectionId 12 Input Iyo chikamuID mepu U-ndege data zvikamu kune inoenderana C-ndege meseji (uye Chikamu Rudzi) ine chekuita nedata.
Kukosha kwemhando: {0000 0000 0000b-11111111 1111b}
tx_metadata_i[30:19]
tx_u_rb 1 Input Resource block chiratidzo.
Ratidza kana chese chivharo chezvishandiso chichishandiswa kana chimwe chese chivharo chinoshandiswa.
Kukosha kwemhando: {0b=chivharo chese chinoshandiswa; 1b = chese chivharo chekushandisa chinoshandiswa}
tx_metadata_i[18]
tx_u_startPrb 10 Input Iyo yekutanga PRB yemushandisi ndege data chikamu.
Kukosha kwemhando: {00 0000 0000b-11 1111 1111b}
tx_metadata_i[17:8]
tx_u_numPrb 8 Input Tsanangura maPRB apo chikamu che data data data chinoshanda. tx_metadata_i[7:0]
      Kukosha kwemhando: {0000 0001b-1111 1111b, 0000 0000b = ese maPRB mune yakatsanangurwa subcarrier spacing (SCS) uye mutakuri bandwidth }  
tx_u_udCompHdr 8 Input Tsanangura nzira yekumanikidza uye IQ bit upamhi hwe data remushandisi muchikamu che data. Kukosha kwemhando: {0000 0000b-1111 1111b} N/A (tx_udcomphdr_i)

Tafura 14. rx_metadata_valid_i/o

Zita rechiratidzo

Bitwidth Direction Tsanangudzo

Metadata Mapping

rx_sec_hdr_valid 1 Output Kana rx_sec_hdr_valid iri 1, chikamu cheU-ndege data minda inoshanda.
Wemusoro musoro maIEs anoshanda kana rx_sec_hdr_valid ichinzi, inopindirana neavst_sink_u_startofpacket uye avst_sink_u_valid.
Akadzokororwa chikamu maIE anoshanda kana rx_sec_hdr_valid ichinzi, inopindirana neavst_sink_u_valid.
Pakupa chikamu chitsva chePRB minda mu avst_sink_u_data, ipa chikamu chitsva maIE ane rx_sec_hdr_valid yakasimbiswa.
rx_metadata_valid_o

Tafura 15. rx_metadata_o 128-bit kubuda

Zita rechiratidzo Bitwidth Direction Tsanangudzo

Metadata Mapping

Reserved 32 Output Reserved. rx_metadata_o[127:96]
rx_u_seq_id 16 Output SeqID yepakiti, iyo inotorwa kubva eCPRI yekufambisa musoro. rx_metadata_o[95:80]
rx_u_pc_id 16 Output PCID ye eCPRI transport uye RoEflowId yeRoE transport rx_metadata_o[79:64]
reserved 4 Output Reserved. rx_metadata_o[63:60]
rx_u_dataDirection 1 Output gNB data nzira. Kukosha zvakasiyana: {0b=Rx (kureva kurodha), 1b=Tx (kureva kudhawunirodha)} rx_metadata_o[59]
rx_u_filterIndex 4 Output Inotsanangura index kune chiteshi sefa yekushandisa pakati peIQ data nemhepo interface.
Kukosha kwemhando: {0000b-1111b}
rx_metadata_o[58:55]
rx_u_frameId 8 Output Kaunda yegumi ms mafuremu (nguva yekupeta masekonzi 10), kunyanya frameId= furemu nhamba modulo 2.56. Kukosha: {256 0000b-0000 1111b} rx_metadata_o[54:47]
rx_u_subframeId 4 Output Kaunda ye 1ms subframes mukati me 10 ms furemu. Kukosha kwemhando: {0000b-1111b} rx_metadata_o[46:43]
rx_u_slotID 6 Output Iyo slot nhamba mukati meiyo 1ms subframe. Yese slots mune imwe subframe inoverengerwa neiyi parameter. Kukosha kwemhando: {00 0000b-00 1111b=slotID, 01 0000b-111111b=Zvakachengetwa} rx_metadata_o[42:37]
rx_u_symbolid 6 Output Inozivisa nhamba yechiratidzo mukati me slot.
Kukosha kwemhando: {00 0000b-11 1111b}
rx_metadata_o[36:31]
rx_u_sectionId 12 Output Iyo chikamuID mepu U-ndege data zvikamu kune inoenderana C-ndege meseji (uye Chikamu Rudzi) ine chekuita nedata.
Kukosha kwemhando: {0000 0000 0000b-1111 1111 1111b}
rx_metadata_o[30:19]
rx_u_rb 1 Output Resource block chiratidzo.
Inoratidza kana chese chivharo chekushandisa chinoshandiswa kana zvimwe zvese zvinoshandiswa.
Kukosha kwemhando: {0b=chivharo chese chinoshandiswa; 1b = chese chivharo chekushandisa chinoshandiswa}
rx_metadata_o[18]
rx_u_startPrb 10 Output Iyo yekutanga PRB yemushandisi ndege data chikamu.
Kukosha kwemhando: {00 0000 0000b-11 1111 1111b}
rx_metadata_o[17:8]
rx_u_numPrb 8 Output Inotsanangura maPRB apo chikamu che data data chemushandisi chinoshanda.
Kukosha kwemhando: {0000 0001b-1111 1111b, 0000 0000b = ese maPRB muSCS yakatsanangurwa uye mutakuri bandwidth }
rx_metadata_o[7:0]
rx_u_udCompHdr 8 Output Inotsanangura nzira yekumanikidza uye IQ bit upamhi hwe data remushandisi muchikamu che data.
Kukosha kwemhando: {0000 0000b-1111 1111b}
N/A (rx_udcomphdr_o)

CSR Interface Signals
Tafura 16. CSR Interface Signals

Zita rechiratidzo Bit Width Direction

Tsanangudzo

csr_address 16 Input Kero yekugadziridza rejista.
csr_write 1 Input Configuration register kunyora gonesa.
csr_writedata 32 Input Configuration rejista nyora data.
csr_readdata 32 Output Configuration register kuverenga data.
csr_verenga 1 Input Configuration register kuverenga inogonesa.
csr_readdatavalid 1 Output Configuration register verenga data inoshanda.
csr_waitrequest 1 Output Configuration register chikumbiro chekumirira.

Fronthaul Compression IP Registers

Dzora uye tarisa fronthaul compression mashandiro kuburikidza nekutonga uye chimiro chimiro.
Tafura 17. Nyora Mepu

CSR_ADDRESS (Word Offset) Register Zita
0x0 compression_mode
0x1 tx_error
0x2 rx_error

Tafura 18. compression_mode Register

Bit Width Tsanangudzo Access

HW Reset Kukosha

31:9 Reserved RO 0x0
8:8 Maitiro ekushanda:
• 1'b0 is static compression mode
• 1'b1 i dynamic compression mode
RW 0x0
7:0 Static mushandisi data compression musoro:
• 7:4 ndiyo udIqWidth
- 4'b0000 i16 bits
- 4'b1111 i15 bits
-:
- 4'b0001 i1 bit
• 3:0 ndiyo udCompMeth
- 4'b0000 haisi compression
- 4'b0001 inzvimbo inoyangarara
- 4'b0011 ndiyo µ-mutemo
• Zvimwe zvakachengetwa
RW 0x0

Tafura 19. tx Kunyoresa Kukanganisa

Bit Width Tsanangudzo Access

HW Reset Kukosha

31:2 Reserved RO 0x0
1:1 IqWidth isiriyo. IP inoisa Iqwidth kusvika 0 (16-bit Iqwidth) kana yaona Iqwidth isiriyo kana isingatsigirwe. RW1C 0x0
0:0 Nzira yekumanikidza haisiyo. IP inodonhedza pakiti. RW1C 0x0

Tafura 20. rx Error Register

Bit Width Tsanangudzo Access

HW Reset Kukosha

31:8 Reserved RO 0x0
1:1 IqWidth isiriyo. IP inodonhedza pakiti. RW1C 0x0
0:0 Nzira yekumanikidza haisiyo. Iyo IP inoisa nzira yekumanikidza kune inotevera default inotsigirwa nzira yekumanikidza:
• Inogonesa block-inoyangarara nzvimbo chete: default kune block-inoyangarara nzvimbo.
• Inogoneswa μ-mutemo chete: default ku μ-law.
• Yakagonesa zvese block-inoyangarara poindi uye μ-mutemo: default kune block-inoyangarara nzvimbo.
RW1C 0x0

Fronthaul Compression Intel FPGA IPs User Guide Archive

Kune ichangoburwa uye yapfuura vhezheni yegwaro iri, tarisa kune: Fronthaul Compression Intel FPGA IP User Guide. Kana IP kana software vhezheni isina kunyorwa, gwaro remushandisi rekare IP kana software shanduro inoshanda.

Gwaro Revision Nhoroondo yeFrontaul Compression Intel FPGA IP Mushandisi Wekushandisa

Document Version

Intel Quartus Prime Version IP Version

Kuchinja

2022.08.08 21.4 1.0.1 Yakagadziriswa metadata hupamhi 0 kusvika 0 (Dyisa Metadata Ports).
2022.03.22 21.4 1.0.1 • tsananguro dzemasaini akachinjaniswa:
— tx_avst_sink_data uye tx_avst_source_data
— rx_avst_sink_data uye rx_avst_source_data
• Yakawedzerwa Mudziyo Unotsigirwa Speed ​​​​Magiredhi table
• Yakawedzerwa Performance uye Resource Kushandiswa
2021.12.07 21.3 1.0.0 Kodhi yekuodha yakagadziridzwa.
2021.11.23 21.3 1.0.0 Kusunungurwa kwekutanga.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

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ID: 709301
UG-20346
Shanduro: 2022.08.08
ISO 9001:2015 Yakanyoreswa

Zvinyorwa / Zvishandiso

Intel Fronthaul Compression FPGA IP [pdf] Bhuku reMushandisi
Fronthaul Compression FPGA IP, Fronthaul, Compression FPGA IP, FPGA IP
Intel Fronthaul Compression FPGA IP [pdf] Bhuku reMushandisi
UG-20346, 709301, Fronthaul Compression FPGA IP, Fronthaul FPGA IP, Compression FPGA IP, FPGA IP

References

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