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Intel® FPGA Fronthaul Compression IP User Guide

Overview

This guide details the Intel® FPGA Fronthaul Compression IP, offering compression and decompression for U-plane IQ data. It supports μ-law and block floating-point compression, adheres to O-RAN specifications, and is updated for Intel® Quartus® Prime Design Suite 21.4 (IP Version 1.0.1).

Learn about device support (Intel® Agilex™, Arria® 10, Stratix® 10), installation via Intel's SSLC, IP parameterization, functional blocks, signals, and registers.

Key Features

μ-law and block floating-point compression/decompression
IQ width 8-bit to 16-bit
Static and dynamic configuration
O-RAN compliant multisections packet support

Related Information

For O-RAN standards, visit the O-RAN website.

Models: Fronthaul Compression FPGA IP, Fronthaul, Compression FPGA IP, FPGA IP

File Info : application/pdf, 23 Pages, 379.60KB

723909?fileName=ug20346 comp-709301-723909

References

Antenna House PDF Output Library 6.6.1359 (Linux64)

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