Fronthaul Compression FPGA IP
Jagorar Mai Amfani

Fronthaul Compression FPGA IP

Fronthaul Compression Intel® FPGA IP Jagorar mai amfani
An sabunta don Intel® Quartus® Prime
Design Suite: 21.4 IP
Shafin: 1.0.1

Game da Fronthaul Compression Intel® FPGA IP

Fronthaul Compression IP ya ƙunshi matsawa da ragewa don bayanan U-jirgin IQ. Injin matsawa yana ƙididdige µ-doka ko toshe matsi-matsawa dangane da matsi na bayanan mai amfani (udCompHdr). Wannan IP tana amfani da ƙa'idar raɗaɗin raɗaɗi ta Avalon don bayanan IQ, sigina na sigina, da don metadata da siginar gefen gefe, da ƙirar ƙwaƙwalwar ajiyar Avalon don sarrafawa da rijistar matsayi (CSRs).
Taswirorin IP sun matsa IQs da ma'aunin matsawa bayanan mai amfani (udCompParam) kamar kowane sashi na tsarin biyan kuɗi da aka ƙayyade a cikin ƙayyadaddun O-RAN O-RAN Fronthaul Control, Mai amfani da Tsarin Jirgin Jirgin Aiki tare 3.0 Afrilu 2020 (O-RAN-WG4.CUS) .0-v03.00). Avalon streaming nutse da faɗin bayanan mu'amalar tushen tushen shine 128-bits don ƙirar aikace-aikacen da 64 ragowa don jigilar jigilar kayayyaki don tallafawa matsakaicin ƙimar kwamfara na 2: 1.
Bayanai masu alaƙa
O-RAN website
1.1. Fronthaul Compression Intel® FPGA IP Features

• -doka da toshe matsi-matsawa da ragewa
• Nisa IQ 8-bit zuwa 16-bit
• A tsaye da tsauri na tsarin U-jirgin IQ da matsi mai taken
• Fakitin Multisections (idan O-RAN Compliant yana kunne)

1.2. Fronthaul Compression Intel® FPGA IP Support Family Support
Intel yana ba da matakan tallafin na'ura masu zuwa don Intel FPGA IP:

• Tallafin gaba – akwai IP ɗin don kwaikwaya da haɗawa don dangin wannan na'urar. FPGA shirye-shirye file (.pof) baya samun tallafi don software na Quartus Prime Pro Stratix 10 Edition Beta kuma saboda haka ba za a iya garantin rufe lokacin IP ba. Samfuran lokaci sun haɗa da ƙididdiga na injiniya na farko na jinkiri dangane da bayanan farko na bayan fage. Samfuran lokaci suna iya canzawa yayin da gwajin siliki ke haɓaka alaƙa tsakanin ainihin siliki da ƙirar lokaci. Kuna iya amfani da wannan tushen IP don tsarin gine-gine da nazarin amfani da albarkatu, kwaikwaiyo, pinout, ƙididdigar latency na tsarin, ƙididdigar lokaci na asali (tsarin kasafin kuɗi), da dabarun canja wurin I/O (faɗin-hanyar bayanai, zurfin fashe, ƙa'idodin I / O ciniki. ).
• Tallafin farko-Intel yana tabbatar da ainihin IP tare da ƙirar lokacin farko don dangin wannan na'urar. Babban IP ɗin ya cika duk buƙatun aiki, amma har yanzu ana iya yin nazarin lokaci don dangin na'urar. Kuna iya amfani da shi a cikin ƙirar samarwa tare da taka tsantsan.
• Taimako na ƙarshe-Intel yana tabbatar da IP tare da ƙirar lokaci na ƙarshe don wannan dangin na'urar. IP ɗin ya cika duk buƙatun aiki da lokaci don dangin na'urar. Kuna iya amfani da shi a cikin ƙirar samarwa.

Tebur 1. Tallafin Iyali na Na'urar IP na Fronthaul

Iyalin Na'ura	Taimako
Intel® Agilex™ (E-tile)	Na farko
Intel Agilex (F-tile)	Gaba
Intel Arria® 10	Karshe
Intel Stratix® 10 (H-, da E-tile na'urorin kawai)	Karshe
Sauran iyalai na na'ura	Babu tallafi

Tebur 2. Makin Gudun Gudun Na'urar Taimakawa

Iyalin Na'ura	Girman Gudun Fabric FPGA
Intel Agilex	3
Intel Arria 10	2
Intel Stratix 10	2

1.3. Bayanin Sakin don Ƙarfafawar Fronthaul Intel FPGA IP
Siffofin IP na Intel FPGA sun dace da nau'ikan software na Intel Quartus® Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga.
Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime. Canji a:

• X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
• Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
• Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.

Tebur 3. Bayanin Sakin IP na Fronthaul Compression

Abu	Bayani
Sigar	1.0.1
Kwanan watan saki	Fabrairu 2022
Lambar yin oda	IP-FH-COMP

1.4. Ayyukan Matsi na Fronthaul da Amfani da Albarkatu
Abubuwan da ke cikin IP suna niyya na'urar Intel Agilex, na'urar Intel Arria 10, da na'urar Intel Stratix 10
Tebur 4. Ayyukan Matsi na Fronthaul da Amfani da Albarkatu
Duk shigarwar don matsawa ne da yanke bayanan bayanan IP

Na'ura	IP	ALMs	Logic rajista		M20K
			Firamare	Sakandare
Intel Agilex	Toshe-tasowa	14,969	25,689	6,093	0
	µ-dokar	22,704	39,078	7,896	0
	Toshe-masoya da µ-doka	23,739	41,447	8,722	0
	Wuri mai toshewa, µ-doka, da faɗin IQ mai tsayi	23,928	41,438	8,633	0
Intel Arria 10	Toshe-tasowa	12,403	16,156	5,228	0
	µ-dokar	18,606	23,617	5,886	0
	Toshe-masoya da µ-doka	19,538	24,650	6,140	0
	Wuri mai toshewa, µ-doka, da faɗin IQ mai tsayi	19,675	24,668	6,141	0
Intel Stratix 10	Toshe-tasowa	16,852	30,548	7,265	0
	µ-dokar	24,528	44,325	8,080	0
	Toshe-masoya da µ-doka	25,690	47,357	8,858	0
	Wuri mai toshewa, µ-doka, da faɗin IQ mai tsayi	25,897	47,289	8,559	0

Farawa tare da Fronthaul Compression Intel FPGA IP

Yana bayyana shigarwa, daidaitawa, simulating, da ƙaddamar da Fronthaul Compression IP.
2.1. Samun, Shigarwa, da Lasisi na Fronthaul Compression IP
Fronthaul Compression IP shine tsawaita Intel FPGA IP wanda ba a haɗa shi da sakin Intel Quartus Prime ba.

1. Ƙirƙiri asusun Intel nawa idan ba ku da ɗaya.
2. Shiga don samun damar Cibiyar Lasisi ta Sabis ta Kai (SSLC).
3. Sayi Fronthaul Compression IP.
4. A kan SSLC shafi, danna Run don IP. SSLC tana ba da akwatin maganganun shigarwa don jagorantar shigar da IP ɗin ku.
5. Shigar zuwa wuri ɗaya da babban fayil ɗin Intel Quartus Prime.

Tebur 5. Wuraren Shigar da Matsi na Fronthaul

Wuri	Software	Dandalin
:\intelFPGA_pro\quartus\ip \altera_cloud	Intel Quartus Prime Pro Edition	Windows *
:/intelFPGA_pro// quartus/ip/altera_cloud	Intel Quartus Prime Pro Edition	Linux *

Hoto 1. Fronthaul Compression IP Shigar Jagorar Tsarin Tsarin Intel Quartus Prime directory directory

The Fronthaul Compression Intel FPGA IP yanzu yana bayyana a cikin IP Catalog.
Bayanai masu alaƙa

• Intel FPGA website
  
• Cibiyar Ba da Lasisi ta Sabis ta Kai (SSLC)

2.2. Daidaitawar Fronthaul Compression IP
Da sauri saita bambancin IP na al'ada a cikin Editan Sigar IP.

1. Ƙirƙiri aikin Intel Quartus Prime Pro Edition wanda a cikinsa zai haɗa ainihin IP ɗin ku.
   a. A cikin Intel Quartus Prime Pro Edition, danna File Sabon Project Wizard don ƙirƙirar sabon aikin Intel Quartus Prime, ko File Buɗe Project don buɗe aikin Quartus Prime da ke akwai. Mayen yana tambayarka don saka na'ura.
   b. Ƙayyade dangin na'urar da suka dace da buƙatun ƙimar saurin IP.
   c. Danna Gama.
2. A cikin IP Catalog, zaɓi Fronthaul Compression Intel FPGA IP. Sabuwar taga Bambancin IP yana bayyana.
3. Ƙayyade sunan babban matakin don sabon bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
4. Danna Ok. Editan siga ya bayyana.
   Hoto 2. Fronthaul Compression IP Parameter Edita
5. Ƙayyade sigogi don bambancin IP ɗin ku. Koma zuwa Siga don bayani game da takamaiman sigogin IP.
6. Danna Zane Example tab kuma saka sigogi don ƙirar ku example.
   Hoto 3. Zane ExampEditan Parameter
7. Danna Ƙirƙirar HDL. Akwatin maganganu na Generation ya bayyana.
8. Ƙayyade fitarwa file zažužžukan tsara, sa'an nan kuma danna Generate. Bambancin IP files samar bisa ga ƙayyadaddun ku.
9. Danna Gama. Editan siga yana ƙara babban matakin .ip file zuwa aikin na yanzu ta atomatik. Idan an sa ka ƙara da .ip file zuwa aikin, danna Project Ƙara / Cire Files a cikin Project don ƙara da file.
10. Bayan ƙirƙira da ƙaddamar da bambancin IP ɗin ku, yi ayyukan fil ɗin da suka dace don haɗa tashoshin jiragen ruwa kuma saita kowane sigogin RTL na kowane misali.

2.2.1. Matsalolin IP na Fronthaul Compression
Table 6. Fronthaul matsawa IP Siga

Suna	Madaidaitan Dabi'u	Bayani
Hanyar bayanai	TX da RX, TX kawai, RX kawai	Zaɓi TX don matsawa; RX don ragewa.
Hanyar matsawa	BFP, mu-Law, ko BFP da mu-Law	Zaɓi toshe-point, µ-doka, ko duka biyun.

Faɗin metadata	0 (A kashe Metadata Ports), 32, 64, 96, 128 (bit)	Ƙayyade ɗan nisa na bas ɗin metadata (bayanan da ba a haɗa su ba).
Kunna faɗin IQ mai tsayi	Kunnawa ko kashewa	Kunna don tallafin IqWidth na 8-bit zuwa 16-bit. Kashe don tallafin IqWidth na 9, 12, 14 da 16-bits.
O-RAN mai yarda	Kunnawa ko kashewa	Kunna don bin taswirar IP na ORAN don tashar jiragen ruwa na metadata kuma tabbatar da ingantaccen siginar metadata ga kowane taken sashe. IP ɗin yana goyan bayan metadata mai faɗin 128-bit kawai. IP ɗin yana goyan bayan sashe ɗaya da sassa da yawa a kowane fakiti. Metadata yana aiki a kowane sashe tare da ingantaccen tabbaci na metadata. Kashe don haka IP ta yi amfani da metadata azaman sigina na hanyar wucewa ba tare da buƙatar taswira ba (misali: U-jirgin numPrb ana ɗauka 0). IP ɗin yana goyan bayan faɗin metadata na 0 (A kashe Metadata Ports), 32, 64, 96, 128 bits. IP ɗin yana goyan bayan sashe ɗaya a kowace fakiti. Metadata yana aiki sau ɗaya kawai a ingantaccen tabbacin metadata na kowane fakiti.

2.3. An ƙirƙira IP File Tsarin
Software na Intel Quartus Prime Pro Edition yana haifar da fitowar ainihin IP mai zuwa file tsari.
Tebur 7. An ƙirƙira IP Files

File Suna	Bayani
<ka_ip> .ip	Tsarin Platform Designer ko babban matakin IP bambancin file.ka_ip> shine sunan da kuke ba da bambancin IP naku.
<ka_ip> cmp	Sanarwar Bangaren VHDL (.cmp) file rubutu ne file wanda ya ƙunshi jigon gida da ma'anar tashar jiragen ruwa waɗanda zaku iya amfani da su a ƙirar VHDL files.
<ka_ip>.html	Rahoton da ya ƙunshi bayanan haɗin kai, taswirar ƙwaƙwalwar ajiya da ke nuna adireshin kowane bawa dangane da kowane ubangidan da aka haɗa shi da shi, da ayyukan sigina.
<ka_ip>_generation.rpt	Login tsararrun IP ko Platform Designer file. Takaitacciyar saƙon yayin tsara IP.
<ka_ip>.qgsimc	Yana lissafin sigogin kwaikwaiyo don tallafawa haɓaka haɓakawa.
<ka_ip>.qgsynthc	Ya lissafa sigogin haɗin kai don tallafawa haɓaka haɓakawa.
<ka_ip>.qip	Ya ƙunshi duk bayanan da ake buƙata game da bangaren IP don haɗawa da haɗa bangaren IP a cikin software na Intel Quartus Prime.
<ka_ip> .sopcinfo	Yana bayyana haɗin kai da ma'auni na abubuwan IP a cikin tsarin Mai tsara Platform ɗin ku. Kuna iya rarraba abubuwan da ke cikin sa don samun buƙatu lokacin da kuke haɓaka direbobin software don abubuwan IP. Kayan aikin ƙasa kamar sarkar kayan aikin Nios® II suna amfani da wannan file. The .sopcinfo file da tsarin.h file An ƙirƙira don sarkar kayan aiki na Nios II sun haɗa da bayanan taswirar adireshi ga kowane bawa dangi ga kowane maigidan da ya isa ga bawa. Masters daban-daban na iya samun taswirar adireshin daban don samun damar wani ɓangaren bawa.
<ka_ip> csv	Ya ƙunshi bayani game da haɓakawa na bangaren IP.
<ka_ip> bsf	Alamar Block File (.bsf) wakilcin bambancin IP don amfani a cikin Intel Quartus Prime Block diagram Files (.bdf).
<ka_ip>.spd	Shigar da ake buƙata file don ip-make-simscript don samar da rubutun kwaikwayo don na'urorin kwaikwayo masu goyan baya. Da .spd file ya ƙunshi jerin fileAn ƙirƙira don kwaikwayo, tare da bayanai game da abubuwan da za ku iya farawa.

<ka_ip> ppf	Mai Tsara Pin File (.ppf) yana adana tashar tashar jiragen ruwa da ayyukan kumburi don abubuwan IP da aka ƙirƙira don amfani tare da Mai tsara Pin.
<ka_ip> _bb.v	Kuna iya amfani da akwatin Verilog black-box (_bb.v) file a matsayin shela mara komai don amfani azaman akwatin baki.
<ka_ip> _inst.v ko _inst.vhd	HDL misaliampda instantiation samfuri. Kuna iya kwafa da liƙa abubuwan da ke cikin wannan file cikin HDL ku file don aiwatar da bambance-bambancen IP.
<ka_ip> v koka_ip> vhd	HDL files wanda ke hanzarta kowane ƙaramin abu ko ainihin IP na yara don haɗawa ko kwaikwaya.
jagora/	Ya ƙunshi rubutun ModelSim* msim_setup.tcl don saita da gudanar da simulation.
synopsys / vcs / synopsys / vcsmx /	Ya ƙunshi rubutun harsashi vcs_setup.sh don saita da gudanar da simintin VCS*. Ya ƙunshi rubutun harsashi vcsmx_setup.sh da synopsys_ sim.setup file don saita da gudanar da simintin VCS MX*.
kasada/	Ya ƙunshi rubutun harsashi ncsim_setup.sh da sauran saitin files don saita da gudanar da simintin NCSIM*.
aldec/	Ya ƙunshi rubutun harsashi rivierapro_setup.sh don saitawa da gudanar da simintin Aldec*.
xcelium/	Ya ƙunshi rubutun harsashi xcelium_setup.sh da sauran saitin files don saita da gudanar da simintin Xcelium*.
submodules/	Ya ƙunshi HDL files don IP core submodules.
<yara IP Cores>/	Ga kowane ɗan littafin adireshi na IP, Platform Designer yana haifar da synth/da sim/ sub-directories.

Bayanin Aiki na IP na Fronthaul Compression

Hoto 4. The Fronthaul Compression IP ya ƙunshi matsawa da raguwa. Tsarin Fronthaul Compression IP Block zane

Damuwa da Ragewa
Toshe-tushe na tushen juzu'in juzu'i yana haifar da ingantattun sauye-sauye don toshe albarkatu na abubuwan albarkatu 12 (REs). Toshe yana rage hayaniyar ƙididdigewa, musamman don ƙananan-amplitude samples. Don haka, yana rage girman girman kuskure (EVM) wanda matsawa ke gabatarwa. Algorithm na matsawa ya kusan zama mai zaman kansa daga ƙimar wutar lantarki. Tsammanin shigar da hadaddun samples shine x = x1 + jxQ, matsakaicin madaidaicin ƙimar haƙiƙanin abubuwan haƙiƙanin abin toshe albarkatu shine:
Samun madaidaicin ƙimar toshe albarkatu, ma'auni mai zuwa yana ƙayyade ƙimar canjin hagu da aka sanya wa wannan toshe albarkatu:Inda bitWidth shine faɗin abin shigarwa.
IP ɗin yana goyan bayan ƙimar matsawa na 8, 9, 10, 11, 12, 13, 14, 15, 16.
Mu-Law Compression and Decompression
Algorithm ɗin yana amfani da dabarar haɗar Mu-law, wacce damtse magana ke amfani da ita sosai. Wannan dabara tana wuce siginar shigar da ba a matsawa ba, x, ta hanyar kwampreso mai aiki, f(x), kafin a zagaya da tsagi. Dabarar tana aika bayanan da aka matsa, y, akan hanyar sadarwa. Bayanan da aka karɓa suna wucewa ta aikin faɗaɗawa (wanda shine juzu'in compressor, F-1(y) Dabarar tana sake haifar da bayanan da ba a matsawa tare da ƙaramin kuskuren ƙididdigewa ba.
Equation 1. Kwamfuta da decompressor ayyuka
Algorithm matsawa na Mu-law IQ yana bin ƙayyadaddun O-RAN.
Bayanai masu alaƙa
O-RAN website
3.1. Siginan IP na Fronthaul Compression
Haɗa kuma sarrafa IP.
Agogo da Sake saita Siginonin Sadarwa =
Tebura 8. Agogo da Sake saita Siginonin Sadarwa

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani
tx_clk	1	Shigarwa	Agogon watsawa. Mitar agogo shine 390.625 MHz don 25 Gbps da 156.25MHz akan 10 Gbps. Duk sigina na mu'amala na watsawa suna aiki tare da wannan agogon.
rx_clk	1	Shigarwa	Agogon karɓa. Mitar agogo shine 390.625 MHz don 25 Gbps da 156.25MHz akan 10 Gbps. Duk sigina masu mu'amala da mai karɓa suna aiki tare da wannan agogon.
csr_clk	1	Shigarwa	Agogo don dubawar CSR. Mitar agogo shine 100 MHz.

tx_rst_n	1	Shigarwa	Ƙarƙashin sake saiti mai aiki don dubawar watsawa mai aiki tare da tx_clk.
rx_rst_n	1	Shigarwa	Ƙarƙashin sake saiti mai aiki don ƙirar mai karɓa yana aiki tare da rx_clk.
csr_rst_n	1	Shigarwa	Ƙarƙashin sake saiti mai aiki don ƙirar CSR mai aiki tare da csr_clk.

Isar da Siginonin Sadarwar Sufuri
Tebur 9. Isar da Siginonin Sadarwar Sadarwa
Duk nau'ikan sigina lamba ce mara sa hannu.

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani
tx_avst_source_mai inganci	1	Fitowa	Lokacin da aka tabbatar, yana nuna ingantaccen bayanai yana samuwa akan avst_source_data.
tx_avst_source_data	64	Fitowa	Filayen PRB ciki har da udCompParam, iSampda qSample. Sashe na gaba filayen PRB an haɗa su zuwa filin PRB na baya.
tx_avst_source_startofpacket	1	Fitowa	Yana nuna farkon byte na firam.
tx_avst_source_endofpacket	1	Fitowa	Yana nuna byte na ƙarshe na firam.
tx_avst_source_shirye	1	Shigarwa	Lokacin da aka tabbatar, yana nuna layin sufuri yana shirye don karɓar bayanai. readyLatency = 0 don wannan keɓancewa.
tx_avst_source_empty	3	Fitowa	Yana ƙayyadad da adadin fakitin bytes akan avst_source_data lokacin da aka tabbatar da avst_source_endofpacket.
tx_udcomphdr_o	8	Fitowa	Filin matsi bayanan mai amfani. Aiki tare da tx_avst_source_valid. Yana bayyana hanyar matsawa da faɗin bit IQ don bayanan mai amfani a cikin sashin bayanan. [7:4]: udIqWidth • 16 na udIqWidth=0, in ba haka ba yana daidai da udIqWidth e,g,: - 0000b yana nufin I da Q kowannensu yana da fadi 16; - 0001b yana nufin I da Q kowannensu yana da faɗin bit 1; - 1111b yana nufin I da Q kowannensu yakai 15 fadi [3:0]: udCompMeth - 0000b - babu matsawa - 0001b - toshe-matsayin iyo - 0011b - µ-doka - wasu - an tanada don hanyoyin gaba.
tx_metadata_o	METADATA_WIDTH	Fitowa	Conduit sigina na wucewa kuma ba a matsawa ba. Aiki tare da tx_avst_source_valid. METADATA_WIDTH mai iya daidaitawa. Lokacin da kuka kunna O-RAN mai yarda, koma zuwa Tebur 13 shafi na 17.Lokacin da ka kashe O-RAN mai yarda, wannan siginar yana aiki ne kawai idan tx_avst_source_startofpacket shine 1. tx_metadata_o bashi da sigina mai inganci kuma yana amfani da tx_avst_source_valid don nuna ingantaccen zagayowar. Babu lokacin da kuka zaɓa 0 Kashe Tashoshin Metadata domin Faɗin metadata.

Karɓi Siginonin Mu'amalar sufuri
Tebur 10. Karɓi Siginonin Sadarwar Sadarwa
Babu matsi na baya a wannan ƙa'idar. Avalon streaming siginar wofi ba lallai ba ne a cikin wannan keɓancewa saboda koyaushe sifili ne.

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani
rx_avst_sink_mai inganci	1	Shigarwa	Lokacin da aka tabbatar, yana nuna ingantaccen bayanai yana samuwa akan avst_sink_data. Babu siginar avst_sink_ready a wannan haɗin gwiwa.
rx_avst_sink_data	64	Shigarwa	Filayen PRB ciki har da udCompParam, iSampda qSample. Sashe na gaba filayen PRB an haɗa su zuwa filin PRB na baya.
rx_avst_sink_startofpacket	1	Shigarwa	Yana nuna farkon byte na firam.
rx_avst_sink_endofpacket	1	Shigarwa	Yana nuna byte na ƙarshe na firam.
rx_avst_sink_error	1	Shigarwa	Lokacin da aka tabbatar a cikin zagayowar guda ɗaya kamar avst_sink_endofpacket, yana nuna fakitin na yanzu fakitin kuskure ne.
rx_udcomphdr_i	8	Shigarwa	Filin matsi bayanan mai amfani. Aiki tare da rx_metadata_valid_i. Yana bayyana hanyar matsawa da faɗin bit IQ don bayanan mai amfani a cikin sashin bayanai. [7:4]: udIqWidth • 16 don udIqWidth=0, in ba haka ba yana daidai da udIqWidth. misali - 0000b yana nufin I da Q kowannensu yana da fadi 16; - 0001b yana nufin I da Q kowannensu yana da faɗin bit 1; - 1111b yana nufin I da Q kowannensu yakai 15 fadi [3:0]: udCompMeth - 0000b - babu matsawa - 0001b - toshe wurin iyo - 0011b - µ-doka - wasu - an tanada don hanyoyin gaba.
rx_metadata_i	METADATA_WIDTH	Shigarwa	Rarraba magudanar ruwa yana siginar wucewa. Siginonin rx_metadata_i suna aiki lokacin da aka tabbatar da rx_metadata_valid_i, suna aiki tare da rx_avst_sink_valid. METADATA_WIDTH mai iya daidaitawa. Lokacin da kuka kunna O-RAN mai yarda, koma zuwa Tebur 15 shafi na 18. Lokacin da kuka kashe O-RAN mai yarda, wannan siginar rx_metadata_i tana aiki ne kawai lokacin da rx_metadata_valid_i da rx_avst_sink_startofpacket daidai yake da 1. Babu lokacin da kuka zaɓa. 0 Kashe Tashoshin Metadata domin Faɗin metadata.
rx_metadata_valid_i	1	Shigarwa	Yana nuna cewa masu kai (rx_udcomphdr_i da rx_metadata_i) suna aiki. Aiki tare da rx_avst_sink_valid. Alamar dole. Don daidaitawar O-RAN na baya, tabbatar da rx_metadata_valid_i idan IP yana da ingantaccen IEs na gama gari da maimaita sashe IE. Akan samar da sabbin filayen toshe albarkatu na zahiri (PRB) a cikin rx_avst_sink_data, samar da sabon sashe IEs a cikin shigarwar rx_metadata_i tare da rx_metadata_valid_i.

Isar da Siginonin Sadarwar Aikace-aikacen
Tebur 11. Maida Siginonin Sadarwar Aikace-aikacen

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani
tx_avst_sink_mai inganci	1	Shigarwa	Lokacin da aka tabbatar, yana nuna ingantattun filayen PRB suna cikin wannan haɗin gwiwa. Lokacin aiki a yanayin yawo, tabbatar da cewa babu ingantaccen siginar deasserting tsakanin fara fakiti da ƙarshen fakiti Banda kawai lokacin da siginar da aka shirya ya dena.
tx_avst_sink_data	128	Shigarwa	Bayanai daga Layer na aikace-aikace a cikin odar byte na cibiyar sadarwa.
tx_avst_sink_startofpacket	1	Shigarwa	Nuna farkon PRB byte na fakiti
tx_avst_sink_endofpacket	1	Shigarwa	Nuna ƙarshen PRB byte na fakiti
tx_avst_sink_a shirye	1	Fitowa	Lokacin da aka tabbatar, yana nuna O-RAN IP yana shirye don karɓar bayanai daga aikace-aikacen mu'amala. readyLatency = 0 don wannan keɓancewa
tx_udcomphdr_i	8	Shigarwa	Filin matsi bayanan mai amfani. Aiki tare da tx_avst_sink_valid. Yana bayyana hanyar matsawa da faɗin bit IQ don bayanan mai amfani a cikin sashin bayanai. [7:4]: udIqWidth • 16 don udIqWidth=0, in ba haka ba yana daidai da udIqWidth. misali - 0000b yana nufin I da Q kowannensu yana da fadi 16; - 0001b yana nufin I da Q kowannensu yana da faɗin bit 1; - 1111b yana nufin I da Q kowannensu yakai 15 fadi [3:0]: udCompMeth - 0000b - babu matsawa - 0001b - toshe-matsayin iyo - 0011b - µ-doka - wasu - an tanada don hanyoyin gaba.
tx_metadata_i	METADATA_WIDTH	Shigarwa	Conduit sigina na wucewa kuma ba a matsawa ba. Aiki tare da tx_avst_sink_valid. METADATA_WIDTH mai iya daidaitawa. Lokacin da kuka kunna O-RAN mai yarda, koma zuwa Tebur 13 shafi na 17. Lokacin da kuka kashe O-RAN mai yarda, wannan siginar yana aiki ne kawai lokacin da tx_avst_sink_startofpacket yayi daidai da 1. tx_metadata_i bashi da ingantaccen sigina da amfani tx_avst_sink_valid don nuna ingantaccen zagayowar. Babu lokacin da kuka zaɓa 0 Kashe Tashoshin Metadata domin Faɗin metadata.

Karɓi Siginonin Sadarwar Aikace-aikacen
Tebur 12. Karɓi Siginonin Sadarwar Aikace-aikacen

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani
rx_avst_source_inganci	1	Fitowa	Lokacin da aka tabbatar, yana nuna ingantattun filayen PRB suna cikin wannan haɗin gwiwa. Babu siginar avst_source_ready a wannan ƙa'idar.
rx_avst_source_data	128	Fitowa	Bayanai zuwa Layer na aikace-aikace a cikin odar byte na cibiyar sadarwa.
rx_avst_source_startofpacket	1	Fitowa	Yana nuna farkon PRB byte na fakiti
rx_avst_source_endofpacket	1	Fitowa	Yana nuna ƙarshen PRB byte na fakiti
rx_avst_source_error	1	Fitowa	Yana nuna fakitin sun ƙunshi kuskure
rx_udcomphdr_o	8	Fitowa	Filin matsi bayanan mai amfani. Aiki tare da rx_avst_source_valid. Yana bayyana hanyar matsawa da faɗin bit IQ don bayanan mai amfani a cikin sashin bayanai. [7:4]: udIqWidth • 16 don udIqWidth=0, in ba haka ba yana daidai da udIqWidth. misali - 0000b yana nufin I da Q kowannensu yana da fadi 16; - 0001b yana nufin I da Q kowannensu yana da faɗin bit 1; - 1111b yana nufin I da Q kowannensu yakai 15 fadi [3:0]: udCompMeth - 0000b - babu matsawa - 0001b - toshe wurin iyo (BFP) - 0011b - µ-doka - wasu - an tanada don hanyoyin gaba.
rx_metadata_o	METADATA_WIDTH	Fitowa	Rarraba magudanar ruwa yana siginar wucewa. rx_metadata_o sigina suna aiki lokacin da aka tabbatar da rx_metadata_valid_o, suna aiki tare da rx_avst_source_valid. METADATA_WIDTH mai iya daidaitawa. Lokacin da kuka kunna O-RAN mai yarda, koma zuwa Tebur 14 shafi na 18. Lokacin da kuka kashe O-RAN mai yarda, rx_metadata_o yana aiki ne kawai lokacin da rx_metadata_valid_o yayi daidai da 1. Babu lokacin da kuka zaɓa 0 Kashe Tashoshin Metadata domin Faɗin metadata.
rx_metadata_valid_o	1	Fitowa	Yana nuna cewa masu kai (rx_udcomphdr_o da rx_metadata_o) suna aiki. Ana tabbatar da rx_metadata_valid_o lokacin da rx_metadata_o ke aiki, yana aiki tare da rx_avst_source_valid.

Taswirar Metadata don Daidaita Baya ga O-RAN
Table 13. tx_metadata_i 128-bit shigar

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani	Taswirar metadata
Ajiye	16	Shigarwa	Ajiye	tx_metadata_i[127:112]
tx_u_size	16	Shigarwa	Girman fakitin jirgin sama a cikin bytes don yanayin yawo.	tx_metadata_i[111:96]
tx_u_seq_id	16	Shigarwa	SeqID na fakitin, wanda aka ciro daga taken jigilar eCPRI.	tx_metadata_i[95:80]
tx_u_pc_id	16	Shigarwa	PCID don jigilar eCPRI da RoEflowId don jigilar radiyo akan ethernet (RoE).	tx_metadata_i[79:64]
Ajiye	4	Shigarwa	Ajiye	tx_metadata_i[63:60]
tx_u_dataDirection	1	Shigarwa	Hanyar bayanan gNB. Kewayon ƙimar: {0b=Rx (watau upload), 1b=Tx (watau zazzagewa)}	tx_metadata_i[59]
tx_u_filterIndex	4	Shigarwa	Yana bayyana ma'anar fihirisa zuwa tace tashar da za a yi amfani da ita tsakanin bayanan IQ da yanayin iska. Kewayon ƙimar: {0000b-1111b}	tx_metadata_i[58:55]
tx_u_frameId	8	Shigarwa	Ma'auni na firam 10 ms (lokacin nannade 2.56 seconds), musamman frameId = lambar firam modulo 256. Kewayon ƙimar: {0000 0000b-1111 1111b}	tx_metadata_i[54:47]
tx_u_subframeId	4	Shigarwa	Ma'auni don ƙananan firam 1 ms a cikin firam 10 ms. Kewayon ƙimar: {0000b-1111b}	tx_metadata_i[46:43]
tx_u_slotID	6	Shigarwa	Wannan siga ita ce lambar ramuwa a cikin ƙaramin yanki na 1 ms. Duk ramummuka a cikin ƙaramin yanki ɗaya ana ƙidaya su ta wannan siga. Kewayon ƙimar: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Ajiye}	tx_metadata_i[42:37]
tx_u_alama	6	Shigarwa	Gano lambar alama a cikin ramin. Kewayon ƙimar: {00 0000b-11 1111b}	tx_metadata_i[36:31]
tx_u_sectionId	12	Shigarwa	Sashe ID yana tsara sassan bayanan U-jirgin sama zuwa saƙon C-jirgin daidai (da Nau'in Sashe) mai alaƙa da bayanan. Kewayon ƙimar: {0000 0000 0000b-11111111 1111b}	tx_metadata_i[30:19]
tx_u_rb	1	Shigarwa	Alamar toshe albarkatu. Nuna idan an yi amfani da kowane toshe albarkatu ko kuma an yi amfani da kowane toshe albarkatu. Kewayon ƙimar: {0b=kowane katangar albarkatun da aka yi amfani da su; 1b=Kowace katangar albarkatun da aka yi amfani da su}	tx_metadata_i[18]
tx_u_startPrb	10	Shigarwa	Farkon PRB na sashin bayanan jirgin mai amfani. Kewayon ƙimar: {00 0000 0000b-11 1111 1111b}	tx_metadata_i[17:8]
tx_u_numPrb	8	Shigarwa	Ƙayyade PRBs inda sashin bayanan jirgin mai amfani ke aiki.	tx_metadata_i[7:0]

			Kewayon ƙimar: {0000 0001b-1111 1111b, 0000 0000b = duk PRBs a cikin ƙayyadadden tazarar mai ɗaukar kaya (SCS) da bandwidth mai ɗaukar kaya }
tx_u_udCompHdr	8	Shigarwa	Ƙayyade hanyar matsawa da faɗin bit IQ na bayanan mai amfani a cikin sashin bayanai. Kewayon ƙimar: {0000 0000b-1111 1111b}	N/A (tx_udcomphdr_i)

Tebur 14. rx_metadata_valid_i/o

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani	Taswirar metadata
rx_sec_hdr_mai inganci	1	Fitowa	Lokacin da rx_sec_hdr_valid shine 1, filayen bayanan sashen U-jirgin suna aiki. IE na gama gari yana aiki lokacin da aka tabbatar da rx_sec_hdr_valid, yana aiki tare da avst_sink_u_startofpacket da avst_sink_u_valid. Sashen da aka maimaita IE yana aiki lokacin da aka tabbatar da rx_sec_hdr_valid, yana aiki tare da avst_sink_u_valid. Akan samar da sabbin filayen PRB a cikin avst_sink_u_data, samar da sabon sashe IEs tare da tabbatar da rx_sec_hdr_valid.	rx_metadata_valid_o

Tebur 15. rx_metadata_o 128-bit fitarwa

Sunan siginar	Tsawon Tsayi	Hanyar	Bayani	Taswirar metadata
Ajiye	32	Fitowa	Ajiye	rx_metadata_o[127:96]
rx_u_seq_id	16	Fitowa	SeqID na fakitin, wanda aka ciro daga taken jigilar eCPRI.	rx_metadata_o[95:80]
rx_u_pc_id	16	Fitowa	PCID don jigilar eCPRI da RoEflowId don jigilar RoE	rx_metadata_o[79:64]
tanada	4	Fitowa	Ajiye	rx_metadata_o[63:60]
rx_u_dataDirection	1	Fitowa	Hanyar bayanan gNB. Kewayon ƙimar: {0b=Rx (watau upload), 1b=Tx (watau zazzagewa)}	rx_metadata_o[59]
rx_u_filterIndex	4	Fitowa	Yana bayyana ma'anar fihirisa zuwa tace tasha don amfani tsakanin bayanan IQ da mu'amalar iska. Kewayon ƙimar: {0000b-1111b}	rx_metadata_o[58:55]
rx_u_frameId	8	Fitowa	Ma'auni na firam 10 ms (lokacin nannade 2.56 seconds), musamman frameId= lambar firam modulo 256. Kewayon ƙimar: {0000 0000b-1111 1111b}	rx_metadata_o[54:47]
rx_u_subframeId	4	Fitowa	Ma'auni don ƙananan firam 1ms a cikin firam 10 ms. Kewayon ƙimar: {0000b-1111b}	rx_metadata_o[46:43]
rx_u_slotID	6	Fitowa	Lamban ramin a cikin ƙaramin yanki na 1ms. Duk ramummuka a cikin ƙaramin yanki ɗaya ana ƙidaya su ta wannan siga. Kewayon ƙimar: {00 0000b-00 1111b=slotID, 01 0000b-111111b=Ajiye}	rx_metadata_o[42:37]
rx_u_alama	6	Fitowa	Gano lambar alama a cikin ramin. Kewayon ƙimar: {00 0000b-11 1111b}	rx_metadata_o[36:31]

rx_u_sectionId	12	Fitowa	Sashe ID yana tsara sassan bayanan U-jirgin sama zuwa saƙon C-jirgin daidai (da Nau'in Sashe) mai alaƙa da bayanan. Kewayon ƙimar: {0000 0000 0000b-1111 1111 1111b}	rx_metadata_o[30:19]
rx_u_rb	1	Fitowa	Alamar toshe albarkatu. Yana nuna idan an yi amfani da kowane shingen albarkatu ko kuma an yi amfani da kowane kayan aiki. Kewayon ƙimar: {0b=kowane katangar albarkatun da aka yi amfani da su; 1b=Kowace katangar albarkatun da aka yi amfani da su}	rx_metadata_o[18]
rx_u_faraPrb	10	Fitowa	Farkon PRB na sashin bayanan jirgin mai amfani. Kewayon ƙimar: {00 0000 0000b-11 1111 1111b}	rx_metadata_o[17:8]
rx_u_numPrb	8	Fitowa	Yana bayyana PRBs inda sashin bayanan jirgin mai amfani ke aiki. Kewayon ƙimar: {0000 0001b-1111 1111b, 0000 0000b = duk PRBs a cikin ƙayyadadden SCS da bandwidth mai ɗaukar kaya }	rx_metadata_o[7:0]
rx_u_udCompHdr	8	Fitowa	Yana bayyana hanyar matsawa da nisa bit IQ na bayanan mai amfani a cikin sashin bayanai. Kewayon ƙimar: {0000 0000b-1111 1111b}	N/A (rx_udcomphdr_o)

Sigina na Interface CSR
Table 16. CSR Interface Sigina

Sunan siginar	Nisa Bit	Hanyar	Bayani
csr_address	16	Shigarwa	Adireshin rajista na Kanfigareshan.
csr_rubuta	1	Shigarwa	Rubutun rajista na Kanfigareshan yana kunna.
csr_writedata	32	Shigarwa	Rubutun rajista na Kanfigareshan.
csr_readata	32	Fitowa	Yin rajistar rajistar bayanan karantawa.
csr_karanta	1	Shigarwa	Kunna rajistar saiti.
csr_readadatavalid	1	Fitowa	Rijistar Kanfigareshan karanta bayanan yana aiki.
csr_waitquest	1	Fitowa	Buƙatun jiran rajistar saiti.

Fronthaul Compression IP Rajista

Sarrafa da saka idanu da ayyukan matsawa na gaba ta hanyar sarrafawa da matsayi.
Tebur 17. Taswirar Rajista

CSR_ADDRESS (Kayyade Kalma)	Sunan Rajista
0 x0	yanayin matsawa
0 x1	tx_error
0 x2	rx_error

Table 18. compression_mode Rajista

Nisa Bit	Bayani	Shiga	Sake saita ƙimar HW
31:9	Ajiye	RO	0 x0
8:8	Yanayin aiki: • 1'b0 yanayin matsawa ne a tsaye 1'b1 yanayin matsawa ne mai ƙarfi	RW	0 x0
7:0	Matsakaicin matsi na bayanan mai amfani: • 7:4 udIqWidth ne - 4'b0000 shine 16 bits - 4'b1111 shine 15 bits -: - 4'b0001 shine 1 bit • 3:0 ne udCompMeth - 4'b0000 ba matsawa bane - 4'b0001 shine toshe wurin iyo - 4'b0011 doka ce An kebe wasu	RW	0 x0

Table 19. tx Kuskuren Rajista

Nisa Bit	Bayani	Shiga	Sake saita ƙimar HW
31:2	Ajiye	RO	0 x0
1:1	IqWidth mara inganci. IP ɗin yana saita Iqwidth zuwa 0 (16-bit Iqwidth) idan ya gano Iqwidth mara inganci ko mara tallafi.	RW1C	0 x0
0:0	Hanyar matsawa mara inganci. IP ɗin yana sauke fakitin.	RW1C	0 x0

Table 20. rx Kuskuren Rajista

Nisa Bit	Bayani	Shiga	Sake saita ƙimar HW
31:8	Ajiye	RO	0 x0
1:1	IqWidth mara inganci. IP ɗin yana sauke fakitin.	RW1C	0 x0
0:0	Hanyar matsawa mara inganci. IP ɗin yana saita hanyar matsawa zuwa tsohuwar hanyar matsawa mai goyan baya: • Wurin toshe-takewa kawai: tsoho zuwa wurin toshe- iyo. • An kunna μ-law kawai: tsoho zuwa μ-law. • An kunna duka madaidaicin toshe-sashe da μ-law: tsoho zuwa wurin toshe- iyo.	RW1C	0 x0

Fronthaul Compression Intel FPGA IPs Taskar Jagorar Mai Amfani

Don sabbin juzu'ai da na baya na wannan takaddar, koma zuwa: Fronthaul Compression Intel FPGA IP Jagorar Mai amfani. Idan ba a jera sigar IP ko software ba, jagorar mai amfani na IP ɗin da ta gabata ko sigar software ta shafi.

Tarihin Bita na Takardu don Matsi na Fronthaul Intel FPGA IP Jagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2022.08.08	21.4	1.0.1	Faɗin metadata da aka gyara 0 zuwa 0 (A kashe Metadata Ports).
2022.03.22	21.4	1.0.1	Bayanin siginar da aka canza: - tx_avst_sink_data da tx_avst_source_data - rx_avst_sink_data da rx_avst_source_data • Ƙara Makin Gudun da Na'urar ke Tallafawa tebur • Ƙara Ayyuka da Amfani da Albarkatu
2021.12.07	21.3	1.0.0	An sabunta lambar oda.
2021.11.23	21.3	1.0.0	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Online Version
Aika da martani
Saukewa: 709301
Saukewa: UG-20346
Shafin: 2022.08.08
ISO 9001: 2015 Rajista

Takardu / Albarkatu

	intel Fronthaul Compression FPGA IP [pdf] Jagorar mai amfani Fronthaul matsawa FPGA IP, Fronthaul, matsawa FPGA IP, FPGA IP
	intel Fronthaul Compression FPGA IP [pdf] Jagorar mai amfani UG-20346, 709301, Fronthaul matsawa FPGA IP, Fronthaul FPGA IP, matsawa FPGA IP, FPGA IP

Magana

• Manual mai amfani