intel Fronthaul Compression FPGA IP User Guide

User Guide for intel models including: UG-20346, 709301, Fronthaul Compression FPGA IP, Fronthaul FPGA IP, Compression FPGA IP, FPGA IP

Fronthaul Compression Intel FPGA IP User Guide

Updated for Intel Quartus Prime Design Suite: 21.3, IP Version: 1.0.0. The O-RAN IP implements control and user plane protocol specified in O-RAN-FH.CUS.0-v03.00. You can instantiate the O-RAN IP in both lower-layer split (LLS)-CU and RU modes..

eCPRI, IEEE 1914.3 RoE , O-RAN, E-Tile, H-Tile

Intel Corporation

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2.3. Generated IP File Structure

1.2. Fronthaul Compression Intel FPGA IP Device Family Support

1. About the Fronthaul Compression Intel FPGA IP

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Fronthaul Compression Intel® FPGA IP User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.3 IP Version: 1.0.0

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UG-20346

ID: 709301 Version: 2021.12.07

Contents
Contents
1. About the Fronthaul Compression Intel® FPGA IP...........................................................3 1.1. Fronthaul Compression Intel® FPGA IP Features........................................................ 3 1.2. Fronthaul Compression Intel® FPGA IP Device Family Support..................................... 4 1.3. Release Information for the Fronthaul Compression Intel FPGA IP................................ 4
2. Getting Started with the Fronthaul Compression Intel FPGA IP...................................... 6 2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP................................6 2.2. Parameterizing the Fronthaul Compression IP............................................................ 7 2.2.1. Fronthaul Compression IP Parameters.......................................................... 8 2.3. Generated IP File Structure..................................................................................... 9
3. Fronthaul Compression IP Functional Description.........................................................11 3.1. Fronthaul Compression IP Signals.......................................................................... 12
4. Fronthaul Compression IP Registers............................................................................. 20 5. Fronthaul Compression Intel FPGA IPs User Guide Archive...........................................22 6. Document Revision History for the Fronthaul Compression Intel FPGA IP User Guide.. 23

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1. About the Fronthaul Compression Intel® FPGA IP
The Fronthaul Compression IP consists of compression and decompression for U-plane IQ data. The compression engine computes µ-law or block floating-point compression based on user data compression header (udCompHdr). This IP uses an Avalon streaming interface for IQ data, conduit signals, and for metadata and sideband signals, and Avalon memory-mapped interface for control and status registers (CSRs). The IP maps compressed IQs and the user data compression parameter (udCompParam) as per the section payload frame format specified in the O-RAN specification O-RAN Fronthaul Control, User and Synchronization Plane Version 3.0 April 2020 (O-RAN-WG4.CUS.0-v03.00). Avalon streaming sink and source interface data width are 128-bits for the application interface and 64 bits for the transport interface to support maximum compressoin ratio of 2:1.
Related Information O-RAN website
1.1. Fronthaul Compression Intel® FPGA IP Features
· -law and block floating-point compression and decompression IQ width 8-bit to 16-bit Static and dynamic configuration of U-plane IQ format and compression header Multisections packet (if O-RAN Compliant is on)

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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1.2. Fronthaul Compression Intel® FPGA IP Device Family Support

Intel offers the following device support levels for Intel FPGA IP:
· Advance support--the IP is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus Prime Pro Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
· Preliminary support--Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.
· Final support--Intel verifies the IP with final timing models for this device family. The IP meets all functional and timing requirements for the device family. You can use it in production designs.

Table 1.

Fronthaul Compression IP Device Family Support

Device Family Intel® AgilexTM (E-tile) Intel Agilex (F-tile) Intel Arria® 10 Intel Stratix® 10 (H-, and E-tile devices only)

Preliminary Advance Final Final

Other device families

No support

Support

1.3. Release Information for the Fronthaul Compression Intel FPGA IP
Intel FPGA IP versions match the Intel Quartus® Prime Design Suite software versions until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP has a new versioning scheme.
The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime software version. A change in:
· X indicates a major revision of the IP. If you update the Intel Quartus Prime software, you must regenerate the IP.
· Y indicates the IP includes new features. Regenerate your IP to include these new features.
· Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

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Table 2.

Fronthaul Compression IP Release Information

Item

Version

1.0.0

Release date

November 2021

Ordering code

IP-FH-COMP

Description

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2. Getting Started with the Fronthaul Compression Intel FPGA IP

Describes installing, parameterizing, simulating, and initializing the Fronthaul Compression IP.

2.1. Obtaining, Installing, and Licensing the Fronthaul Compression IP

The Fronthaul Compression IP is an extended Intel FPGA IP that is not included with the Intel Quartus Prime release.
1. Create a My Intel account if you do not have one.
2. Log in to access the Self-Service Licensing Center (SSLC).
3. Purchase the Fronthaul Compression IP.
4. On the SSLC page, click Run for the IP. The SSLC provides an installation dialog box to guide your installation of the IP.
5. Install to the same location as Intel Quartus Prime folder.

Table 3.

Fronthaul Compression Installation Locations

Location

Software

<drive>:\intelFPGA_pro\<version>\quartus\ip \altera_cloud

Intel Quartus Prime Pro Edition

<home directory>:/intelFPGA_pro/<version>/ quartus/ip/altera_cloud

Intel Quartus Prime Pro Edition

Platform Windows*
Linux*

Figure 1.

Fronthaul Compression IP Installation Directory Structure Intel Quartus Prime installation directory

ip Contains the Intel FPGA IP Library and third-party IP
altera_cloud Contains the Intel FPGA extended IP that you install
<ip_name> Contains the O-RAN Intel FPGA IP files The Fronthaul Compression Intel FPGA IP now appears in the IP Catalog.
Related Information · Intel FPGA website

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· Self-Service Licensing Center (SSLC)
2.2. Parameterizing the Fronthaul Compression IP
Quickly configure your custom IP variation in the IP Parameter Editor. 1. Create an Intel Quartus Prime Pro Edition project in which to integrate your IP
core. a. In the Intel Quartus Prime Pro Edition, click File New Project Wizard to
create a new Intel Quartus Prime project, or File Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device. b. Specify the device family that meets the speed grade requirements for the IP. c. Click Finish. 2. In the IP Catalog, select Fronthaul Compression Intel FPGA IP. The New IP Variation window appears. 3. Specify a top-level name for your new custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip. 4. Click OK. The parameter editor appears.
Figure 2. Fronthaul Compression IP Parameter Editor

5. Specify the parameters for your IP variation. Refer to Parameters for information about specific IP parameters.
6. Click the Design Example tab and specify the parameters for your design example.

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Figure 3. Design Example Parameter Editor

7. Click Generate HDL. The Generation dialog box appears.
8. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
9. Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project Add/Remove Files in Project to add the file.
10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.
2.2.1. Fronthaul Compression IP Parameters

Table 4.

Fronthaul Compression IP Parameters

Name

Valid Values

Description

Data direction

TX and RX, TX only, RX only

Select TX for compression; RX for decompression.

Compression method

BFP, mu-Law, or BFP and mu-Law

Select block floating-point, µ-law, or both.

continued...

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Name Metadata width
Enable extended IQ width O-RAN compliant

Valid Values 0, 32, 64, 96, 128 (bit) On or off
On or off

Description
Specify the bit width of the metadata bus (uncompressed data).
Turn on for supported IqWidth of 8-bit to 16-bit. Turn off for supported IqWidth of 9, 12, 14 and 16-bits.
Turn on to follow ORAN IP mapping for metadata port and assert metadata valid signal for each section header. The IP supports 128-bit width metadata only. The IP supports single section and multiple sections per packet. Metadata is valid at each section with metadata valid assertion. Turn off so the IP uses metadata as passthrough conduit signals with no mapping requirement (e.g.: U-plane numPrb is assumed 0). The IP supports metadata widths of 0, 32, 64, 96, 128 bits. The IP supports single section per packet. Metadata is valid only once at the metadata valid assertion for each packet.

2.3. Generated IP File Structure

The Intel Quartus Prime Pro Edition software generates the following IP core output file structure.

Table 5.

Generated IP Files

File Name

<your_ip>.ip

<your_ip>.cmp

<your_ip>.html

<your_ip>_generation.rpt
<your_ip>.qgsimc <your_ip>.qgsynthc <your_ip>.qip
<your_ip>.sopcinfo

<your_ip>.csv <your_ip>.bsf
<your_ip>.spd

Description
The Platform Designer system or top-level IP variation file. <your_ip> is the name that you give your IP variation.
The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.
IP or Platform Designer generation log file. A summary of the messages during IP generation.
Lists simulation parameters to support incremental regeneration.
Lists synthesis parameters to support incremental regeneration.
Contains all the required information about the IP component to integrate and compile the IP component in the Intel Quartus Prime software.
Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components. Downstream tools such as the Nios® II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.
Contains information about the upgrade status of the IP component.
A Block Symbol File (.bsf) representation of the IP variation for use in Intel Quartus Prime Block Diagram Files (.bdf).
Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.
continued...

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File Name <your_ip>.ppf <your_ip>_bb.v <your_ip>_inst.v or _inst.vhd <your_ip>.v or <your_ip>.vhd mentor/ synopsys/vcs/ synopsys/vcsmx/ cadence/ aldec/ xcelium/ submodules/ <child IP cores>/

Description
The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.
HDL files that instantiate each submodule or child IP core for synthesis or simulation.
Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX* simulation.
Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM* simulation.
Contains a shell script rivierapro_setup.sh to setup and run an Aldec* simulation.
Contains a shell script xcelium_setup.sh and other setup files to set up and run an Xcelium* simulation.
Contains HDL files for the IP core submodules.
For each generated child IP core directory, Platform Designer generates synth/ and sim/ sub-directories.

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3. Fronthaul Compression IP Functional Description

Figure 4.

The Fronthaul Compression IP comprises compression and decompression. Fronthaul Compression IP Block Diagram
Fronthaul Compression IP

Receiver Transport Interface

Decompression Decompression
Metadata

Error Reporting

Receiver Application Interface
irq

Transmitter Transport Interface

Compression Compression
Metadata

Registers

CSR Interface
Transmitter Application Interface

Compression and Decompression
A preprocessing block-based bit shift block generates the optimum bit-shifts for a resource block of 12 resource elements (REs). The block reduces the quantization noise, especially for low-amplitude samples. Hence, it reduces the error vector magnitude (EVM) that compression introduces. The compression algorithm is almost independent of the power value. Assuming the complex input samples is x = x1 + jxQ, the maximum absolute value of the real and imaginary components for the resource block is:
maxIn = max xI12 n - 1 + 1 , xI12 n - 1 + 2 , ..., xI12n
maxQn = max xQ12 n - 1 + 1 , xQ12 n - 1 + 2 , ..., xQ12n
The maximum value of the resource block n is:
maxValn = max maxIn , maxQn

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Having the maximum absolute value for the resource block, the following equation determines the left shift value assigned to that resource block:

lsi f tn = bitWidt - log2 maxValn - 1 0

i f maxValn < 2bitWidt - 1 else

Where bitWidth is the input bit width.

The IP supports compression ratios of 8, 9, 10, 11, 12, 13, 14, 15, 16.

Mu-Law Compression and Decompression

The algorithm uses Mu-law companding technique, which speech compression widely uses. This technique passes the input uncompressed signal, x, through a compressor with function, f(x), before rounding and bit-truncation. The technique sends compressed data, y, over the interface. The received data passes through an expanding function (which is the inverse of the compressor, F-1(y). The technique reproduces the uncompressed data with minimal quantization error.

Equation 1. Compressor and decompressor functions

The Mu-law IQ compression algorithm follows the O-RAN specification. Related Information O-RAN website
3.1. Fronthaul Compression IP Signals
Connect and control the IP.

Clock and Reset Interface Signals

Table 6.

Clock and Reset Interface Signals

Signal Name Bitwidth Direction

Description

tx_clk

rx_clk

csr_clk

Input Input Input

Transmitter clock. Clock frequency is 390.625 MHz for 25 Gbps and 156.25MHz for 10 Gbps. All transmitter interface signals are synchronous to this clock.

Receiver clock. Clock frequency is 390.625 MHz for 25 Gbps and 156.25MHz for 10 Gbps. All receiver interface signals are synchronous to this clock.

Clock for CSR interface. Clock frequency is 100 MHz.

continued...

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Signal Name Bitwidth Direction

Description

tx_rst_n

Input

Active low reset for transmitter interface synchronous to tx_clk.

rx_rst_n

Input

Active low reset for receiver interface synchronous to rx_clk.

csr_rst_n 1

Input

Active low reset for CSR interface synchronous to csr_clk.

Transmit Transport Interface Signals

Table 7.

Transmit Transport Interface Signals
All signal types are unsigned integer.

Signal Name

Bitwidth

Direction

Description

tx_avst_source_valid

Output

When asserted, indicates valid data is available on avst_source_data.

tx_avst_source_data

Output Data to transport layer in network byte order.

tx_avst_source_startofpacket 1

Output Indicates first byte of a frame.

tx_avst_source_endofpacket 1

Output Indicates last byte of a frame.

tx_avst_source_ready

Input

When asserted, indicates the transport layer is ready to accept data. readyLatency = 0 for this interface.

tx_avst_source_empty

Output

Specifies the number of empty bytes on avst_source_data when avst_source_endofpacket is asserted.

tx_udcomphdr_o

Output User data compression header field.

Synchronous with tx_avst_source_valid.

Defines the compression method and IQ bit width for the user data in a data section.

· [7:4] : udIqWidth

· 16 for udIqWidth=0, otherwise equals udIqWidth e,g,:

-- 0000b means I and Q are each 16 bits wide;

-- 0001b means I and Q are each 1 bit wide;

-- 1111b means I and Q are each 15 bits wide

· [3:0] : udCompMeth

-- 0000b - no compression

-- 0001b - block-floating point

-- 0011b - µ-law

-- others - reserved for future methods.

tx_metadata_o

METADATA_WIDTH Output

Conduit signals passthrough and are not compressed.
Synchronous with tx_avst_source_valid.
Configurable bitwidth METADATA_WIDTH.
When you turn on O-RAN compliant, refer to Table 11 on page 16.
When you turn off O-RAN compliant, this signal is only valid when tx_avst_source_startofpacket is 1.
tx_metadata_o does not have valid signal and uses tx_avst_source_valid to indicate valid cycle.

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Receive Transport Interface Signals

Table 8.

Receive Transport Interface Signals
No backpressure at this interface. Avalon streaming empty signal is not necessary in this interface because it is always zero.

Signal Name

Bitwidth

Direction

Description

rx_avst_sink_valid

Input

When asserted, indicates valid data is available on avst_sink_data.
No avst_sink_ready signal at this interface.

rx_avst_sink_data

Input

Data from transport layer in network byte order.

rx_avst_sink_startofpacket 1

Input

Indicates first byte of a frame.

rx_avst_sink_endofpacket 1

Input

Indicates last byte of a frame.

rx_avst_sink_error

Input

When asserted in the same cycle as avst_sink_endofpacket, indicates the current packet is an error packet

rx_udcomphdr_i

Input

User data compression header field. Synchronous with rx_metadata_valid_i. Defines the compression method and IQ bit width for the user data in a data section. · [7:4] : udIqWidth · 16 for udIqWidth=0, otherwise equals
udIqWidth. e.g. -- 0000b means I and Q are each 16 bits wide; -- 0001b means I and Q are each 1 bit wide; -- 1111b means I and Q are each 15 bits wide · 3:0] : udCompMeth -- 0000b - no compression -- 0001b - block floating point -- 0011b - µ-law -- others - reserved for future methods.

rx_metadata_i

METADATA_WIDTH Input

Uncompressed conduit signals passthrough.
rx_metadata_i signals are valid when rx_metadata_valid_i is asserted, synchronous with rx_avst_sink_valid.
Configurable bitwidth METADATA_WIDTH.
When you turn on O-RAN compliant, refer to Table 13 on page 18.
When you turn off O-RAN compliant, this rx_metadata_i signal is only valid when both rx_metadata_valid_i and rx_avst_sink_startofpacket equal to 1.

rx_metadata_valid_i

Input

Indicates that the headers (rx_udcomphdr_i and rx_metadata_i) are valid.
Synchronous with rx_avst_sink_valid.
Compulsory signal.
For O-RAN backward compatibility, assert rx_metadata_valid_i if the IP has valid common header IEs and repeated section IEs. On providing new section physical resource block (PRB) fields in rx_avst_sink_data, provide new section IEs in rx_metadata_i input together with rx_metadata_valid_i.

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Transmit Application Interface Signals

Table 9.

Transmit Application Interface Signals

Signal Name

Bitwidth

Direction

Description

tx_avst_sink_valid

Input

When asserted, indicates valid PRB fields are available in this interface.
When operating in streaming mode, ensure no valid signal deassertion between start ofpacket and end of packet The only exception is when the ready signal deasserted.

tx_avst_sink_data

128

Input

PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to previous section PRB field.

tx_avst_sink_startofpacket 1

Input

Indicate the first PRB byte of a packet

tx_avst_sink_endofpacket 1

Input

Indicate the last PRB byte of a packet

tx_avst_sink_ready

Output

When asserted, indicates the O-RAN IP is ready to accept data from application interface. readyLatency = 0 for this interface

tx_udcomphdr_i

Input

User data compression header field. Synchronous with tx_avst_sink_valid. Defines the compression method and IQ bit width for the user data in a data section. · [7:4] : udIqWidth · 16 for udIqWidth=0, otherwise equals
udIqWidth. e.g. -- 0000b means I and Q are each 16 bits wide; -- 0001b means I and Q are each 1 bit wide; -- 1111b means I and Q are each 15 bits wide · [3:0] : udCompMeth -- 0000b - no compression -- 0001b - block-floating point -- 0011b - µ-law -- others - reserved for future methods.

tx_metadata_i

METADATA_WIDTH Input

Conduit signals passthrough and are not compressed.
Synchronous with tx_avst_sink_valid.
Configurable bitwidth METADATA_WIDTH.
When you turn on O-RAN compliant, refer to Table 11 on page 16. When you turn off O-RAN compliant, this signal only valid when tx_avst_sink_startofpacket equals to 1.
tx_metadata_i does not have valid signal and uses tx_avst_sink_valid to indicate valid cycle.

Receive Application Interface Signals

Table 10.

Receive Application Interface Signals
No backpressure at this interface.

Signal Name

Bitwidth

Direction

Description

rx_avst_source_valid

Output

When asserted, indicates valid PRB fields are available in this interface.
continued...

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Signal Name

Bitwidth

Direction

Description

No avst_source_ready signal at this interface.

rx_avst_source_data

128

Output

PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to previous section PRB field.

rx_avst_source_startofpacket 1

Output Indicates the first PRB byte of a packet

rx_avst_source_endofpacket 1

Output Indicates the last PRB byte of a packet

rx_avst_source_error

Output Indicates the packets contains error

rx_udcomphdr_o

Output User data compression header field.

Synchronous with rx_avst_source_valid.

Defines the compression method and IQ bit width for the user data in a data section.

· [7:4] : udIqWidth

· 16 for udIqWidth=0, otherwise equals udIqWidth. e.g.

-- 0000b means I and Q are each 16 bits wide;

-- 0001b means I and Q are each 1 bit wide;

-- 1111b means I and Q are each 15 bits wide

· [3:0] : udCompMeth

-- 0000b - no compression

-- 0001b - block floating point (BFP)

-- 0011b - µ-law

-- others - reserved for future methods.

rx_metadata_o

METADATA_WIDTH Output

Uncompressed conduit signals passthrough.
rx_metadata_o signals are valid when rx_metadata_valid_o is asserted, synchronous with rx_avst_source_valid.
Configurable bitwidth METADATA_WIDTH.
When you turn on O-RAN compliant, refer to Table 12 on page 17.
When you turn off O-RAN compliant, rx_metadata_o is only valid when rx_metadata_valid_o equals 1.

rx_metadata_valid_o

Output

Indicates that the headers (rx_udcomphdr_o and rx_metadata_o) are valid.
rx_metadata_valid_o is asserted when rx_metadata_o is valid, synchronous with rx_avst_source_valid.

Metadata Mapping for O-RAN Backward Compatibility

Table 11. tx_metadata_i 128-bit input

Signal Name

Bitwidth Direction

Description

Reserved

Input

Reserved.

tx_u_size

Input

U-plane packet size in bytes for streaming

mode.

tx_u_seq_id

Input

SeqID of the packet, which is extracted

from eCPRI transport header.

tx_u_pc_id

Input

PCID for eCPRI transport and RoEflowId

for radio over ethernet (RoE) transport.

Metadata Mapping tx_metadata_i[127:112] tx_metadata_i[111:96]
tx_metadata_i[95:80]
tx_metadata_i[79:64] continued...

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Signal Name

Bitwidth Direction

Description

Metadata Mapping

Reserved

Input

Reserved.

tx_metadata_i[63:60]

tx_u_dataDirection 1

Input

gNB data direction.
Value range: {0b=Rx (i.e. upload), 1b=Tx (i.e. download)}

tx_metadata_i[59]

tx_u_filterIndex 4

Input

Defines an index to the channel filter to be used between IQ data and air interface.
Value range: {0000b-1111b}

tx_metadata_i[58:55]

tx_u_frameId

Input

A counter for 10 ms frames (wrapping

tx_metadata_i[54:47]

period 2.56 seconds), specifically frameId=

frame number modulo 256.

Value range: {0000 0000b-1111 1111b}

tx_u_subframeId

Input

A counter for 1 ms subframes within 10 ms frame.
Value range: {0000b-1111b}

tx_metadata_i[46:43]

tx_u_slotID

Input

This parameter is the slot number within a tx_metadata_i[42:37]

1 ms subframe. All slots in one subframe

are counted by this parameter.

Value range: {00 0000b-00

1111b=slotID, 01 0000b-11 1111b=Reserved}

tx_u_symbolid

Input

Identifies a symbol number within a slot.

tx_metadata_i[36:31]

Value range: {00 0000b-11 1111b}

tx_u_sectionId

Input

The sectionID maps U-plane data sections to the corresponding C-plane message (and Section Type) associated with the data.
Value range: {0000 0000 0000b-1111 1111 1111b}

tx_metadata_i[30:19]

tx_u_rb

Input

Resource block indicator.

tx_metadata_i[18]

Indicate if every resource block is used or every other resource block is used.

Value range: {0b=every resource block used; 1b=every other resource block used}

tx_u_startPrb

Input

The starting PRB of a user plane data

section.

tx_metadata_i[17:8]

Value range: {00 0000 0000b-11 1111 1111b}

tx_u_numPrb

Input

Define the PRBs where the user plane data tx_metadata_i[7:0]

section is valid.

Value range: {0000 0001b-1111 1111b, 0000 0000b = all PRBs in the specified subcarrier spacing (SCS) and carrier bandwidth }

tx_u_udCompHdr

Input

Define the compression method and IQ bit width of the user data in a data section.
Value range: {0000 0000b-1111 1111b}

N/A (tx_udcomphdr_i)

Table 12. rx_metadata_valid_i/o

Signal Name

Bitwidth Direction

Description

rx_sec_hdr_valid 1

Output

When rx_sec_hdr_valid is 1, the U-plane section data fields are valid.

Metadata Mapping rx_metadata_valid_o

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Signal Name

Bitwidth Direction

Description

Common header IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_sink_u_startofpacket and avst_sink_u_valid.
Repeated section IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_sink_u_valid.
On providing new section PRB fields in avst_sink_u_data, provide new section IEs with rx_sec_hdr_valid asserted.

Metadata Mapping

Table 13. rx_metadata_o 128-bit output

Signal Name

Bitwidth Direction

Description

Metadata Mapping

Reserved

Output Reserved.

rx_metadata_o[127:96]

rx_u_seq_id

Output SeqID of the packet, which is extracted

rx_metadata_o[95:80]

from eCPRI transport header.

rx_u_pc_id

Output PCID for eCPRI transport and RoEflowId

rx_metadata_o[79:64]

for RoE transport

reserved

Output Reserved.

rx_metadata_o[63:60]

rx_u_dataDirection 1

Output

gNB data direction.
Value range: {0b=Rx (i.e. upload), 1b=Tx (i.e. download)}

rx_metadata_o[59]

rx_u_filterIndex 4

Output

Defines an index to the channel filter to use between IQ data and air interface.
Value range: {0000b-1111b}

rx_metadata_o[58:55]

rx_u_frameId

Output A counter for 10 ms frames (wrapping period rx_metadata_o[54:47]

2.56 seconds), specifically frameId= frame

number modulo 256.

Value range: {0000 0000b-1111 1111b}

rx_u_subframeId

Output

A counter for 1ms subframes within 10 ms frame.
Value range: {0000b-1111b}

rx_metadata_o[46:43]

rx_u_slotID

Output The slot number within a 1ms subframe. All rx_metadata_o[42:37]

slots in one subframe are counted by this

parameter.

Value range: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Reserved}

rx_u_symbolid

Output Identifies a symbol number within a slot.

rx_metadata_o[36:31]

Value range: {00 0000b-11 1111b}

rx_u_sectionId

Output The sectionID maps U-plane data sections rx_metadata_o[30:19]

to the corresponding C-plane message (and

Section Type) associated with the data.

Value range: {0000 0000 0000b-1111 1111 1111b}

rx_u_rb

Output Resource block indicator.

rx_metadata_o[18]

Indicates if every resource block is used or every other resource is used.

Value range: {0b=every resource block used; 1b=every other resource block used}

continued...

Fronthaul Compression Intel® FPGA IP User Guide 18

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3. Fronthaul Compression IP Functional Description 709301 | 2021.12.07

Signal Name rx_u_startPrb rx_u_numPrb
rx_u_udCompHdr

Bitwidth Direction

Description

Output The starting PRB of a user plane data

section.

Value range: {00 0000 0000b-11 1111 1111b}

Output Defines the PRBs where the user plane data

section is valid.

Value range: {0000 0001b-1111 1111b, 0000 0000b = all PRBs in the specified SCS and carrier bandwidth }

Output Defines the compression method and IQ bit

width of the user data in a data section.

Value range: {0000 0000b-1111 1111b}

Metadata Mapping rx_metadata_o[17:8] rx_metadata_o[7:0]
N/A (rx_udcomphdr_o)

CSR Interface Signals

Table 14. CSR Interface Signals

Signal Name

Bit Width

csr_address

csr_write

csr_writedata

csr_readdata

csr_read

csr_readdatavalid

csr_waitrequest

Direction Input Input Input Output Input Output Output

Description Configuration register address. Configuration register write enable. Configuration register write data. Configuration register read data. Configuration register read enable. Configuration register read data valid. Configuration register wait request.

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4. Fronthaul Compression IP Registers

Table 15.
0x0 0x1 0x2

Control and monitor fronthaul compression functionality through the control and status interface.

Table 16. compression_mode Register

Bit Width 31:9 8:8
7:0

Description
Reserved
Functional mode: · 1'b0 is static compression mode · 1'b1 is dynamic compression mode
Static user data compression header: · 7:4 is udIqWidth
-- 4'b0000 is 16 bits -- 4'b1111 is 15 bits --: -- 4'b0001 is 1 bit · 3:0 is udCompMeth -- 4'b0000 is no compression -- 4'b0001 is block floating point -- 4'b0011 is µ-law · Others are reserved

Access RO RW

HW Reset Value 0x0 0x0

0x0

Table 17. tx Error Register

Bit Width

Description

31:2

Reserved

1:1

Invalid IqWidth. The IP sets Iqwidth to 0 (16-bit Iqwidth) if it detects invalid or

unsupported Iqwidth.

0:0

Invalid compression method. The IP drops the packet.

Access HW Reset Value

0x0

RW1C 0x0

ISO 9001:2015 Registered

4. Fronthaul Compression IP Registers 709301 | 2021.12.07

Table 18. rx Error Register

Bit Width

Description

31:8 1:1 0:0

Reserved
Invalid IqWidth. The IP drops the packet.
Invalid compression method. The IP sets the compression method to the following default supported compression method: · Enabled block-floating point only: default to block-floating point. · Enabled -law only: default to -law. · Enabled both block-floating point and -law: default to block-floating point.

Access

HW Reset Value

0x0

RW1C 0x0

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5. Fronthaul Compression Intel FPGA IPs User Guide Archive

If the table does not list an IP version, the user guide for the previous IP version applies.

Table 19. Fronthaul Compression IP Intel FPGA IPs User Guide Archive

Intel Quartus Prime Version

User Guide

21.3

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6. Document Revision History for the Fronthaul Compression Intel FPGA IP User Guide

Document Version
2021.12.07 2021.11.23

Intel Quartus Prime Version
21.3
21.3

IP Version
1.0.0 1.0.0

Changes
Updated ordering code. Initial release.

ISO 9001:2015 Registered

References

O-RAN ALLIANCE e.V

Antenna House PDF Output Library 6.6.1359 (Linux64)