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Cov neeg siv phau ntawv qhiaIntel Fronthaul Compression FPGA IP

Cov ntsiab lus zais
1 Fronthaul Compression FPGA IP
2 Txog Fronthaul Compression Intel® FPGA IP
3 Pib nrog Fronthaul Compression Intel FPGA IP
4 Fronthaul Compression IP Functional Description
5 Fronthaul Compression IP Sau npe
6 Fronthaul Compression Intel FPGA IPs Cov Neeg Siv Phau Ntawv Qhia Archive
7 Cov ntaub ntawv kho dua tshiab rau Fronthaul Compression Intel FPGA IP Tus Neeg Siv Qhia
8 Cov ntaub ntawv / Cov ntaub ntawv
8.1 Cov ntaub ntawv
9 Related Posts

Fronthaul Compression FPGA IP

Fronthaul Compression Intel® FPGA IP Tus Neeg Siv Qhia
Hloov tshiab rau Intel® Quartus® Prime
Tsim Suite: 21.4 IP
Version: 1.0.1

Txog Fronthaul Compression Intel® FPGA IP

Fronthaul Compression IP muaj compression thiab decompression rau U-plane IQ cov ntaub ntawv. Lub cav compression suav µ-txoj cai lossis thaiv ntab-point compression raws li cov neeg siv cov ntaub ntawv compression header (udCompHdr). Tus IP no siv Avalon streaming interface rau IQ cov ntaub ntawv, conduit signals, thiab rau metadata thiab sideband signals, thiab Avalon nco-mapped interface rau kev tswj thiab cov xwm txheej sau npe (CSRs).
IP daim duab qhia compressed IQs thiab cov neeg siv cov ntaub ntawv compression parameter (udCompParam) raws li ib feem payload ncej hom ntawv teev nyob rau hauv lub O-RAN specification O-RAN Fronthaul Control, Neeg siv thiab Synchronization Plane Version 3.0 Plaub Hlis Ntuj 2020 (O-RAN-WG4.CUS 0-v03.00 Nws. Avalon streaming dab dej thiab qhov chaw interface cov ntaub ntawv dav yog 128-ntsis rau daim ntawv thov interface thiab 64 khoom rau kev thauj mus los los txhawb qhov siab tshaj plaws compressoin piv ntawm 2: 1.
Cov ntaub ntawv ntsig txog
O-RAN webqhov chaw
1.1. Fronthaul Compression Intel® FPGA IP Nta

  • -txoj cai thiab thaiv ntab-point compression thiab decompression
  • IQ dav 8-ntsis rau 16-ntsis
  • Static thiab dynamic configuration ntawm U-plane IQ hom thiab compression header
  • Multisections pob ntawv (yog tias O-RAN Ua raws)

1.2. Fronthaul Compression Intel® FPGA IP Device Family Support
Intel muab cov cuab yeej txhawb nqa hauv qab no rau Intel FPGA IP:

  • Kev them nyiaj yug ua ntej-tus IP yog muaj rau simulation thiab muab tso ua ke rau tsev neeg cov cuab yeej no. FPGA programming file (.pof) kev txhawb nqa tsis muaj rau Quartus Prime Pro Stratix 10 Edition Beta software thiab vim li no IP lub sijhawm kaw tsis tuaj yeem lav. Sijhawm qauv suav nrog kev kwv yees thawj zaug engineering ntawm kev ncua raws li cov ntaub ntawv tom qab kev teeb tsa thaum ntxov. Cov qauv sij hawm yuav raug hloov pauv raws li kev sim silicon txhim kho kev sib raug zoo ntawm cov silicon tiag tiag thiab cov qauv sij hawm. Koj tuaj yeem siv tus IP core no rau kev tshawb fawb txog kev tsim vaj tsev thiab kev siv cov peev txheej, simulation, pinout, kev ntsuas lub sijhawm latency, kev ntsuas lub sijhawm yooj yim (pipeline peev nyiaj), thiab I / O hloov cov tswv yim (cov ntaub ntawv-txoj kab dav, tawg qhov tob, I / O cov qauv kev lag luam. ).
  • Kev txhawb nqa ua ntej-Intel txheeb xyuas tus IP tseem ceeb nrog cov qauv ua ntej lub sijhawm rau tsev neeg cov cuab yeej no. Cov tub ntxhais IP ua tau raws li txhua qhov kev xav tau ua haujlwm, tab sis tseem tuaj yeem tshawb xyuas lub sijhawm rau tsev neeg lub cuab yeej. Koj tuaj yeem siv nws hauv kev tsim khoom tsim nrog ceev faj.
  • Kev txhawb nqa zaum kawg-Intel txheeb xyuas tus IP nrog lub sijhawm kawg ua qauv rau tsev neeg cov cuab yeej no. IP ua tau raws li txhua qhov kev ua haujlwm thiab lub sijhawm ua haujlwm rau tsev neeg lub cuab yeej. Koj tuaj yeem siv nws hauv kev tsim khoom tsim.

Rooj 1. Fronthaul Compression IP Device Family Support

Device Family Txhawb nqa
Intel® Agilex™ (E-tile) Ua ntej
Intel Agilex (F-tile) Ua ntej
Intel Arria® 10 Kawg
Intel Stratix® 10 (H-, thiab E-tile li xwb) Kawg
Lwm cov cuab yeej cuab tam Tsis muaj kev txhawb nqa

Table 2. Ntaus Txhawb Cov Qib Siab

Device Family FPGA Fabric Ceev Qib
Intel Agilex 3
Intel Arria 10 2
Intel Stratix 10 2

1.3. Tshaj tawm cov ntaub ntawv rau Fronthaul Compression Intel FPGA IP
Intel FPGA IP versions phim Intel Quartus® Prime Design Suite software versions txog v19.1. Pib hauv Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP muaj cov txheej txheem tshiab.
Intel FPGA IP version (XYZ) tus lej tuaj yeem hloov pauv nrog txhua Intel Quartus Prime software version. Kev hloov hauv:

  • X qhia txog kev hloov kho loj ntawm IP. Yog tias koj hloov kho Intel Quartus Prime software, koj yuav tsum rov tsim dua tus IP.
  • Y qhia tias tus IP suav nrog cov yam ntxwv tshiab. Rov tsim koj tus IP kom suav nrog cov yam ntxwv tshiab no.
  • Z qhia tias IP suav nrog kev hloov pauv me me. Rov tsim koj tus IP kom suav nrog cov kev hloov pauv no.

Table 3. Fronthaul Compression IP Tso Tawm Cov Ntaub Ntawv

Yam khoom Kev piav qhia
Version 1.0.1
Hnub tso tawm Lub Ob Hlis 2022
Ordering code IP-FH-COMP

1.4. Fronthaul Compression Performance thiab Kev Pabcuam
Cov peev txheej ntawm IP tsom rau Intel Agilex ntaus ntawv, Intel Arria 10 ntaus ntawv, thiab Intel Stratix 10 ntaus ntawv
Table 4. Fronthaul Compression Performance thiab Kev Pabcuam
Txhua qhov nkag yog rau compression thiab decompression cov ntaub ntawv qhia IP

Ntaus ntawv IP ALMs Logic sau npe M20K
  Thawj Secondary
Intel Agilex Thaiv-floating point 14,969 25,689 6,093 0
µ-law 22,704 39,078 7,896 0
Thaiv-floating point thiab µ-txoj cai 23,739 41,447 8,722 0
Thaiv-floating point, µ-txoj cai, thiab ncua IQ dav 23,928 41,438 8,633 0
Intel Arria 10 Thaiv-floating point 12,403 16,156 5,228 0
µ-law 18,606 23,617 5,886 0
Thaiv-floating point thiab µ-txoj cai 19,538 24,650 6,140 0
Thaiv-floating point, µ-txoj cai, thiab ncua IQ dav 19,675 24,668 6,141 0
Intel Stratix 10 Thaiv-floating point 16,852 30,548 7,265 0
µ-law 24,528 44,325 8,080 0
Thaiv-floating point thiab µ-txoj cai 25,690 47,357 8,858 0
Thaiv-floating point, µ-txoj cai, thiab ncua IQ dav 25,897 47,289 8,559 0

Pib nrog Fronthaul Compression Intel FPGA IP

Piav txog kev txhim kho, parameterizing, simulating, thiab pib Fronthaul Compression IP.
2.1. Tau txais, txhim kho, thiab tso cai rau Fronthaul Compression IP
Fronthaul Compression IP yog qhov txuas ntxiv Intel FPGA IP uas tsis suav nrog Intel Quartus Prime tso tawm.

  1. Tsim kuv tus account Intel yog tias koj tsis muaj.
  2. Nkag mus nkag mus rau Chaw Pabcuam Tus Kheej Licensing Center (SSLC).
  3. Yuav lub Fronthaul Compression IP.
  4. Ntawm nplooj ntawv SSLC, nyem Khiav rau IP. SSLC muab lub thawv teeb tsa los qhia koj qhov kev teeb tsa ntawm IP.
  5. Nruab rau tib qhov chaw raws li Intel Quartus Prime nplaub tshev.

Table 5. Fronthaul Compression Installation Qhov chaw

Qhov chaw Software Platform
:\intelFPGA_pro\\quartus\ip \altera_cloud Intel Quartus Prime Pro Edition Qhov rai*
:/intelFPGA_pro//quartus/ip/altera_cloud Intel Quartus Prime Pro Edition Linux *

Daim duab 1. Fronthaul Compression IP Installation Directory Structure Intel Quartus Prime installation directory

intel Fronthaul Compression FPGA IP daim duab 7
Fronthaul Compression Intel FPGA IP tam sim no tshwm hauv IP Catalog.
Cov ntaub ntawv ntsig txog

  • Intel FPGA Cov webqhov chaw
  • Self-Service Licensing Center (SSLC)

2.2. Parameterizing Fronthaul Compression IP
Yooj yim teeb tsa koj tus IP kev cai hloov pauv hauv IP Parameter Editor.

  1. Tsim ib qhov project Intel Quartus Prime Pro Edition uas los ua ke koj tus IP core.
    a. Hauv Intel Quartus Prime Pro Edition, nyem File New Project Wizard los tsim ib qhov tshiab Intel Quartus Prime project, los yog File Qhib Project qhib qhov project Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
    b. Qhia rau tsev neeg cov cuab yeej uas ua tau raws li qib kev ceev rau tus IP.
    c. Nyem Ua kom tiav.
  2. Hauv IP Catalog, xaiv Fronthaul Compression Intel FPGA IP. Lub qhov rais tshiab IP Variation tshwm.
  3. Qhia meej lub npe saum toj kawg nkaus rau koj qhov kev hloov pauv IP tshiab. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
  4. Nyem OK. Cov parameter editor tshwm.
    intel Fronthaul Compression FPGA IP daim duab 6Daim duab 2. Fronthaul Compression IP Parameter Editor
  5. Qhia qhov tsis haum rau koj qhov kev hloov pauv IP. Xa mus rau Parameters rau cov ntaub ntawv hais txog tus IP tshwj xeeb.
  6. Nyem qhov Tsim Example tab thiab qhia cov parameters rau koj tus tsim example.
    intel Fronthaul Compression FPGA IP daim duab 5Daim duab 3. Tsim Examplos ntawm Parameter Editor
  7. Nyem Tsim HDL. Lub Generation dialog box tshwm.
  8. Qhia cov zis file tiam xaiv, thiab ces nias Tsim. Tus IP variation files tsim raws li koj specifications.
  9. Nyem Ua kom tiav. Cov parameter editor ntxiv rau sab saum toj-theem .ip file mus rau qhov project tam sim no tau txais. Yog tias koj raug ceeb toom kom manually ntxiv .ip file mus rau qhov project, nyem qhov Project Add/Remove Files hauv Project ntxiv rau file.
  10. Tom qab tsim thiab ua kom koj qhov kev hloov pauv IP sai sai, ua cov haujlwm tsim nyog tus pin los txuas cov chaw nres nkoj thiab teeb tsa qhov tsim nyog ib qho piv txwv RTL.

2.2.1. Fronthaul Compression IP Parameters
Table 6. Fronthaul Compression IP Parameters

Lub npe Muaj nuj nqis

Kev piav qhia
Cov ntaub ntawv qhia TX and RX, TX xwb, RX xwb Xaiv TX rau compression; RX rau decompression.
Txoj kev compression BFP, mu-Law, or BFP and mu-Law Xaiv thaiv ntab-point, µ-txoj cai, lossis ob qho tib si.
Metadata dav 0 (Disable Metadata Ports), 32, 64, 96, 128 (ntsis) Qhia qhov dav me ntsis ntawm lub tsheb npav metadata (cov ntaub ntawv tsis tau sau).
Pab kom ncua IQ dav Tawm los yog tawm Qhib rau kev txhawb nqa IqWidth ntawm 8-ntsis rau 16-ntsis.
Tua tawm rau kev txhawb nqa IqWidth ntawm 9, 12, 14 thiab 16-ntsis.
O-RAN ua raws Tawm los yog tawm Tig rau ua raws li ORAN IP daim ntawv qhia rau qhov chaw nres nkoj metadata thiab lees paub metadata siv tau cov teeb liab rau txhua ntu header. IP txhawb nqa 128-ntsis dav metadata nkaus xwb. IP txhawb nqa ib ntu thiab ntau ntu ntawm ib pob ntawv. Metadata siv tau ntawm txhua ntu nrog metadata siv tau.
Tig tawm yog li tus IP siv metadata raws li passthrough conduit signals uas tsis muaj daim ntawv qhia yuav tsum tau (xws li: U-plane numPrb yog assumed 0). IP txhawb cov metadata dav ntawm 0 (Disable Metadata Ports), 32, 64, 96, 128 khoom. IP txhawb nqa ib ntu ntawm ib pob ntawv. Metadata tsuas yog siv tau ib zaug ntawm cov ntaub ntawv metadata siv tau rau txhua pob ntawv.

2.3. Tsim IP File Qauv
Intel Quartus Prime Pro Edition software tsim tawm IP cov ntsiab lus hauv qab no file qauv.
Table 7. Tsim IP Files

File Lub npe

Kev piav qhia
<koj_ip>.ip Lub Platform Designer system lossis qib siab IP hloov pauv file.koj_ip> yog lub npe uas koj muab koj tus IP variation.
<koj_ip>.cmp VHDL Component Tshaj Tawm (.cmp) file yog ntawv file uas muaj cov ntsiab lus hauv zos thiab chaw nres nkoj uas koj tuaj yeem siv hauv VHDL tsim files.
<koj_ip>.html Ib daim ntawv tshaj tawm uas muaj cov ntaub ntawv sib txuas, daim ntawv qhia nco uas qhia qhov chaw nyob ntawm txhua tus qhev nrog rau txhua tus tswv uas nws tau txuas nrog, thiab cov haujlwm parameter.
<koj_ip>_generation.rpt IP lossis Platform Designer tiam cav file. Cov ntsiab lus ntawm cov lus thaum lub sijhawm IP tsim.
<koj_ip>.qgsimc Sau cov simulation tsis tau los txhawb kev tsim dua tshiab.
<koj_ip>.qgsynthc Sau cov synthesis parameter los pab txhawb kev tsim dua tshiab.
<koj_ip>.qib Muaj tag nrho cov ntaub ntawv xav tau txog tus IP tivthaiv los ua ke thiab sau cov IP tivthaiv hauv Intel Quartus Prime software.
<koj_ip>.sopcinfo Piav qhia txog kev sib txuas thiab IP tivthaiv tsis ua haujlwm hauv koj lub Platform Designer system. Koj tuaj yeem txheeb xyuas nws cov ntsiab lus kom tau txais cov cai thaum koj tsim software tsav tsheb rau cov khoom siv IP.
Cov cuab yeej qis qis xws li Nios® II cov cuab yeej siv no file. Lub .sopcinfo file thiab system.h file tsim los rau Nios II cov cuab yeej muaj xws li cov ntaub ntawv qhia chaw nyob rau txhua tus qhev txheeb ze rau txhua tus tswv uas nkag mus rau tus qhev. Cov tswv sib txawv tuaj yeem muaj daim ntawv qhia chaw sib txawv kom nkag mus rau ib qho kev ua qhev tshwj xeeb.
<koj_ip>.tsv Muaj cov ntaub ntawv hais txog kev hloov kho cov xwm txheej ntawm IP tivthaiv.
<koj_ip>.bsf Ib Block Symbol File (.bsf) sawv cev ntawm tus IP hloov pauv rau siv hauv Intel Quartus Prime Block Diagram Files (.bdf).
<koj_ip>.spd Yuav tsum tau nkag file rau ip-make-simscript los tsim cov ntawv simulation rau kev txhawb nqa simulators. Cov .spd file muaj ib daim ntawv teev npe files generated rau simulation, nrog rau cov ntaub ntawv hais txog kev nco uas koj tuaj yeem pib.
<koj_ip>.ppf Pin Planner File (.ppf) khaws cov chaw nres nkoj thiab node assignments rau IP Cheebtsam tsim rau siv nrog tus Pin Planner.
<koj_ip>_bb.v Koj tuaj yeem siv Verilog black-box (_bb.v) file raws li qhov khoob module tshaj tawm rau siv los ua lub thawv dub.
<koj_ip>_inst.v or _inst.vhd HDL ua exampthiab instantiation template. Koj tuaj yeem luam thiab muab cov ntsiab lus ntawm qhov no file nyob rau hauv koj HDL file kom instantiate tus IP variation.
<koj_ip>.v oskoj_ip>.vhd HDL files uas instantiate txhua submodule los yog me nyuam IP core rau synthesis los yog simulation.
tus cob qhia/ Muaj ModelSim * tsab ntawv msim_setup.tcl los teeb tsa thiab khiav qhov simulation.
synopsys/vcs/synopsys/vcsmx/ Muaj lub plhaub ntawv vcs_setup.sh los teeb tsa thiab khiav VCS * simulation.
Muaj cov ntawv plhaub vcsmx_setup.sh thiab synopsys_ sim.setup file teeb tsa thiab khiav VCS MX* simulation.
cadence/ Muaj cov ntawv plhaub ncsim_setup.sh thiab lwm yam teeb tsa files los teeb tsa thiab khiav NCSIM * simulation.
aldec/ Muaj lub plhaub ntawv rivierapro_setup.sh los teeb tsa thiab khiav Aldec* simulation.
xcelium / Muaj lub plhaub ntawv xcelium_setup.sh thiab lwm yam teeb tsa files teeb tsa thiab khiav Xcelium * simulation.
submodules/ Muaj HDL files rau IP core submodules.
<tus me nyuam IP cores>/ Rau txhua tus me nyuam cov ntaub ntawv tus IP core, Platform Designer generates synth / thiab sim / sub-directories.

Fronthaul Compression IP Functional Description

Daim duab 4. Lub Fronthaul Compression IP muaj compression thiab decompression. Fronthaul Compression IP Block Diagramintel Fronthaul Compression FPGA IP daim duab 4

Compression thiab decompression
Ib qho kev ua haujlwm ua ntej-raws li kev hloov pauv me ntsis ua rau qhov zoo tshaj plaws me ntsis-hloov rau cov peev txheej ntawm 12 cov khoom siv (REs). Lub block txo cov suab nrov quantization, tshwj xeeb tshaj yog rau qis-amplus samples. Li no, nws txo qhov yuam kev vector magnitude (EVM) uas compression qhia. Lub compression algorithm yog yuav luag ywj siab ntawm lub hwj chim tus nqi. Piv txwv li lub complex input samples yog x = x1 + jxQ, qhov siab tshaj plaws tus nqi ntawm cov khoom tiag tiag thiab kev xav rau cov peev txheej thaiv yog:
intel Fronthaul Compression FPGA IP daim duab 3Muaj tus nqi siab tshaj plaws rau cov peev txheej thaiv, cov kab zauv hauv qab no txiav txim siab tus nqi hloov pauv mus rau qhov kev pab cuam block:intel Fronthaul Compression FPGA IP daim duab 2Qhov twg bitWidth yog input ntsis dav.
IP txhawb nqa compression piv ntawm 8, 9, 10, 11, 12, 13, 14, 15, 16.
Mu-Law Compression thiab Decompression
Lub algorithm siv Mu-txoj cai companding txheej txheem, uas hais lus compression dav siv. Cov txheej txheem no dhau lub input uncompressed teeb liab, x, los ntawm ib tug compressor muaj nuj nqi, f (x), ua ntej rounding thiab me ntsis-truncation. Cov txheej txheem xa cov ntaub ntawv compressed, y, hla lub interface. Cov ntaub ntawv tau txais dhau los ntawm kev nthuav dav muaj nuj nqi (uas yog qhov hloov pauv ntawm lub compressor, F-1(y)).
Kev sib npaug 1. Compressor thiab decompressor muaj nuj nqi
intel Fronthaul Compression FPGA IP daim duab 1Mu-txoj cai IQ compression algorithm ua raws li O-RAN specification.
Cov ntaub ntawv ntsig txog
O-RAN webqhov chaw
3.1. Fronthaul Compression IP Signals
Txuas thiab tswj tus IP.
Clock thiab Reset Interface Signals =
Table 8. Clock thiab Reset Interface Signals

Lub Npe Lub Npe Bitwidth Kev taw qhia

Kev piav qhia
tx_clk 1 Tswv yim Transmitter moos.
Lub moos zaus yog 390.625 MHz rau 25 Gbps thiab 156.25MHz rau 10 Gbps. Tag nrho cov transmitter interface signals yog synchronous rau lub moos no.
rx_clk ua 1 Tswv yim Lub moos txais.
Lub moos zaus yog 390.625 MHz rau 25 Gbps thiab 156.25MHz rau 10 Gbps. Tag nrho cov receiver interface signals yog synchronous rau lub moos no.
csr_clk ua 1 Tswv yim moos rau CSR interface. Lub moos zaus yog 100 MHz.
tx_rst_n 1 Tswv yim Active low reset rau transmitter interface synchronous rau tx_clk.
rx_rst_n 1 Tswv yim Active qis pib dua rau receiver interface synchronous rau rx_clk.
csr_rst_n 1 Tswv yim Active qis pib dua rau CSR interface synchronous rau csr_clk.

Transmit Transport Interface Signals
Table 9. Transmit Transport Interface Signals
Tag nrho cov teeb liab hom yog unsigned integer.

Lub Npe Lub Npe

 Bitwidth Kev taw qhia

Kev piav qhia
tx_avst_source_valid 1 Tso zis Thaum lees paub, qhia tias cov ntaub ntawv siv tau muaj nyob ntawm avst_source_data.
tx_avst_source_data 64 Tso zis PRB teb suav nrog udCompParam, iSample os qample. Tshooj tom ntej PRB teb yog txuas mus rau seem PRB teb.
tx_avst_source_startofpacket 1 Tso zis Qhia thawj byte ntawm tus ncej.
tx_avst_source_endofpacket 1 Tso zis Qhia qhov kawg byte ntawm tus ncej.
tx_avst_source_ready 1 Tswv yim Thaum lees paub, qhia tias cov txheej txheem thauj khoom npaj tau txais cov ntaub ntawv. readyLatency = 0 rau qhov interface no.
tx_avst_source_empty 3 Tso zis Qhia tus lej ntawm cov bytes khoob ntawm avst_source_data thaum avst_source_endofpacket tau lees paub.
tx_udcomphdr_o 8 Tso zis Cov neeg siv cov ntaub ntawv compression header teb. Synchronous nrog tx_avst_source_valid.
Txhais txoj kev compression thiab IQ ntsis dav
rau cov neeg siv cov ntaub ntawv nyob rau hauv cov ntaub ntawv seem.
• [7:4] : udIqWidth
• 16 rau udIqWidth=0, txwv tsis pub sib npaug udIqWidth e,g,:
- 0000b txhais tau tias kuv thiab Q yog txhua 16 qhov dav;
- 0001b txhais tau tias kuv thiab Q yog 1 ntsis dav;
- 1111b txhais tau tias kuv thiab Q yog txhua 15 qhov dav
• [3:0] : udCompMeth
- 0000b - tsis muaj compression
- 0001b - block-floating point
— 0011b – µ-law
- lwm tus - tshwj tseg rau cov txheej txheem yav tom ntej.
tx_metadata_o METADATA_WIDTH Tso zis Conduit signals passthrough thiab tsis compressed.
Synchronous nrog tx_avst_source_valid. Configurable bitwidth METADATA_WIDTH.
Thaum koj qhib O-RAN ua raws, xa mus Table 13 ntawm nplooj 17.Thaum koj tua O-RAN ua raws, cov teeb liab no tsuas siv tau thaum tx_avst_source_startofpacket yog 1. tx_metadata_o tsis muaj teeb liab siv tau thiab siv tx_avst_source_valid los qhia txog lub voj voog siv tau.
Tsis muaj thaum koj xaiv 0 Disable Metadata Ports rau Metadata dav.

Tau txais kev thauj mus los Interface Signals
Table 10. Tau txais kev thauj mus los interface
Tsis muaj backpressure ntawm no interface. Avalon streaming npliag teeb liab tsis tsim nyog nyob rau hauv no interface vim nws yog ib txwm xoom.

Lub Npe Lub Npe Bitwidth Kev taw qhia

Kev piav qhia
rx_avst_sink_valid 1 Tswv yim Thaum lees paub, qhia tias cov ntaub ntawv siv tau muaj nyob ntawm avst_sink_data.
Tsis muaj avst_sink_ready teeb liab ntawm no interface.
rx_avst_sink_data 64 Tswv yim PRB teb suav nrog udCompParam, iSample os qample. Tshooj tom ntej PRB teb yog txuas mus rau seem PRB teb.
rx_avst_sink_startofpacket 1 Tswv yim Qhia thawj byte ntawm tus ncej.
rx_avst_sink_endofpacket 1 Tswv yim Qhia qhov kawg byte ntawm tus ncej.
rx_avst_sink_error 1 Tswv yim Thaum lees paub hauv tib lub voj voog raws li avst_sink_endofpacket, qhia tias pob ntawv tam sim no yog pob ntawv yuam kev
rx_udcomphdr_i 8 Tswv yim Cov neeg siv cov ntaub ntawv compression header teb. Synchronous nrog rx_metadata_valid_i.
Txhais txoj kev compression thiab IQ ntsis dav rau cov neeg siv cov ntaub ntawv hauv cov ntaub ntawv seem.
• [7:4] : udIqWidth
• 16 rau udIqWidth=0, txwv tsis pub sib npaug udIqWidth. eg
- 0000b txhais tau tias kuv thiab Q yog txhua 16 qhov dav;
- 0001b txhais tau tias kuv thiab Q yog 1 ntsis dav;
- 1111b txhais tau tias kuv thiab Q yog txhua 15 qhov dav
• [3:0] : udCompMeth
- 0000b - tsis muaj compression
- 0001b - thaiv ntab taw tes
— 0011b – µ-law
- lwm tus - tshwj tseg rau cov txheej txheem yav tom ntej.
rx_metadata_i METADATA_WIDTH Tswv yim Uncompressed conduit signals hla dhau.
rx_metadata_i cov teeb liab siv tau thaum rx_metadata_valid_i tau lees paub, synchronous nrog rx_avst_sink_valid.
Configurable bitwidth METADATA_WIDTH.
Thaum koj qhib O-RAN ua raws, xa mus Rooj 15 pe paj 18.
Thaum koj tua O-RAN ua raws, qhov teeb liab rx_metadata_i no tsuas siv tau thaum ob qho tib si rx_metadata_valid_i thiab rx_avst_sink_startofpacket sib npaug rau 1. Tsis muaj thaum koj xaiv 0 Disable Metadata Ports rau Metadata dav.
rx_metadata_valid_i 1 Tswv yim Qhia tias cov headers (rx_udcomphdr_i thiab rx_metadata_i) siv tau. Synchronous nrog rx_avst_sink_valid. Yuav tsum teeb liab. Rau O-RAN rov qab sib raug zoo, lees paub rx_metadata_valid_i yog tias tus IP muaj qhov siv tau zoo ntawm cov header IEs thiab rov ua ntu IEs. Ntawm kev muab cov seem tshiab lub cev muaj peev xwm thaiv (PRB) teb hauv rx_avst_sink_data, muab ntu tshiab IEs hauv rx_metadata_i cov tswv yim ua ke nrog rx_metadata_valid_i.

Transmit Application Interface Signals
Table 11. Transmit Application Interface Signals

Lub Npe Lub Npe

 Bitwidth Kev taw qhia

Kev piav qhia
tx_avst_sink_valid 1 Tswv yim Thaum lees paub, qhia tau hais tias siv tau PRB teb muaj nyob rau hauv no interface.
Thaum kev khiav hauj lwm hauv streaming hom, xyuas kom tsis muaj teeb meem siv tau deassertion ntawm pib ntawm pob ntawv thiab qhov kawg ntawm pob ntawv Qhov tsuas yog qhov tshwj xeeb yog thaum lub teeb liab npaj tau deasserted.
tx_avst_sink_data 128 Tswv yim Cov ntaub ntawv los ntawm daim ntawv thov txheej hauv network byte xaj.
tx_avst_sink_startofpacket 1 Tswv yim Qhia thawj PRB byte ntawm ib pob ntawv
tx_avst_sink_endofpacket 1 Tswv yim Qhia qhov kawg PRB byte ntawm ib pob ntawv
tx_avst_sink_ready 1 Tso zis Thaum lees paub, qhia tias O-RAN IP yog npaj los txais cov ntaub ntawv los ntawm daim ntawv thov interface. readyLatency = 0 rau qhov interface no
tx_udcomphdr_i 8 Tswv yim Cov neeg siv cov ntaub ntawv compression header teb. Synchronous nrog tx_avst_sink_valid.
Txhais txoj kev compression thiab IQ ntsis dav rau cov neeg siv cov ntaub ntawv hauv cov ntaub ntawv seem.
• [7:4] : udIqWidth
• 16 rau udIqWidth=0, txwv tsis pub sib npaug udIqWidth. eg
- 0000b txhais tau tias kuv thiab Q yog txhua 16 qhov dav;
- 0001b txhais tau tias kuv thiab Q yog 1 ntsis dav;
- 1111b txhais tau tias kuv thiab Q yog txhua 15 qhov dav
• [3:0] : udCompMeth
- 0000b - tsis muaj compression
- 0001b - block-floating point
— 0011b – µ-law
- lwm tus - tshwj tseg rau cov txheej txheem yav tom ntej.
tx_metadata_i METADATA_WIDTH Tswv yim Conduit signals passthrough thiab tsis compressed. Synchronous nrog tx_avst_sink_valid.
Configurable bitwidth METADATA_WIDTH.
Thaum koj qhib O-RAN ua raws, xa mus Rooj 13 pe paj 17.
Thaum koj tua O-RAN ua raws, qhov teeb liab no tsuas siv tau thaum tx_avst_sink_startofpacket sib npaug rau 1.
tx_metadata_i tsis muaj teeb liab siv tau thiab siv
tx_avst_sink_valid to indicator valid cycle.
Tsis muaj thaum koj xaiv 0 Disable Metadata Ports rau Metadata dav.

Txais Daim Ntawv Thov Interface Signals
Table 12. Tau txais daim ntawv thov Interface Signals

Lub Npe Lub Npe

 Bitwidth Kev taw qhia

Kev piav qhia
rx_avst_source_valid 1 Tso zis Thaum lees paub, qhia tau hais tias siv tau PRB teb muaj nyob rau hauv no interface.
Tsis muaj avst_source_ready teeb liab ntawm qhov interface no.
rx_avst_source_data 128 Tso zis Cov ntaub ntawv rau daim ntawv thov txheej hauv network byte xaj.
rx_avst_source_startofpacket 1 Tso zis Qhia thawj PRB byte ntawm ib pob ntawv
rx_avst_source_endofpacket 1 Tso zis Qhia qhov kawg PRB byte ntawm ib pob ntawv
rx_avst_source_error 1 Tso zis Qhia tias cov pob ntawv muaj qhov yuam kev
rx_udcomphdr_o 8 Tso zis Cov neeg siv cov ntaub ntawv compression header teb. Synchronous nrog rx_avst_source_valid.
Txhais txoj kev compression thiab IQ ntsis dav rau cov neeg siv cov ntaub ntawv hauv cov ntaub ntawv seem.
• [7:4] : udIqWidth
• 16 rau udIqWidth=0, txwv tsis pub sib npaug udIqWidth. eg
- 0000b txhais tau tias kuv thiab Q yog txhua 16 qhov dav;
- 0001b txhais tau tias kuv thiab Q yog 1 ntsis dav;
- 1111b txhais tau tias kuv thiab Q yog txhua 15 qhov dav
• [3:0] : udCompMeth
- 0000b - tsis muaj compression
- 0001b - block floating point (BFP)
— 0011b – µ-law
- lwm tus - tshwj tseg rau cov txheej txheem yav tom ntej.
rx_metadata_o METADATA_WIDTH Tso zis Uncompressed conduit signals hla dhau.
rx_metadata_o cov teeb liab siv tau thaum rx_metadata_valid_o tau lees paub, synchronous nrog rx_avst_source_valid.
Configurable bitwidth METADATA_WIDTH. Thaum koj qhib O-RAN ua raws, xa mus Table 14 pe paj 18.
Thaum koj tua O-RAN ua raws, rx_metadata_o tsuas yog siv tau thaum rx_metadata_valid_o sib npaug 1.
Tsis muaj thaum koj xaiv 0 Disable Metadata Ports rau Metadata dav.
rx_metadata_valid_o 1 Tso zis Qhia tias cov headers (rx_udcomphdr_o thiab
rx_metadata_o) siv tau.
rx_metadata_valid_o tau lees paub thaum rx_metadata_o siv tau, synchronous nrog rx_avst_source_valid.

Metadata Mapping rau O-RAN Backward Compatibility
Table 13. tx_metadata_i 128-ntsis input

Lub Npe Lub Npe

 Bitwidth Kev taw qhia Kev piav qhia

Metadata Mapping
Khaws tseg 16 Tswv yim Khaws tseg. tx_metadata_i[127:112]
tx_u_size 16 Tswv yim U-plane pob ntawv loj hauv bytes rau streaming hom. tx_metadata_i[111:96]
tx_u_seq_id 16 Tswv yim SeqID ntawm pob ntawv, uas yog muab rho tawm los ntawm eCPRI thauj header. tx_metadata_i[95:80]
tx_u_pc_id 16 Tswv yim PCID rau eCPRI thauj thiab RoEflowId
rau xov tooj cua tshaj ethernet (RoE) thauj.		 tx_metadata_i[79:64]
Khaws tseg 4 Tswv yim Khaws tseg. tx_metadata_i[63:60]
tx_u_dataDirection 1 Tswv yim gNB data direction.
Tus nqi ntau: {0b = Rx (ie upload), 1b = Tx (ie download)}		 tx_metadata_i[59]
tx_u_filterIndex 4 Tswv yim Txhais qhov Performance index rau cov lim lim los siv ntawm IQ cov ntaub ntawv thiab huab cua interface.
Tus nqi ntau: {0000b-1111b}		 tx_metadata_i[58:55]
tx_u_frameId 8 Tswv yim Ib lub txee rau 10 ms thav ntawv (wrapping lub sijhawm 2.56 vib nas this), tshwj xeeb yog frameId = thav duab tus lej modulo 256.
Tus nqi ntau: {0000 0000b-1111 1111b}		 tx_metadata_i[54:47]
tx_u_subframeId 4 Tswv yim Ib lub txee rau 1 ms subframes hauv 10 ms ncej. Tus nqi ntau: {0000b-1111b} tx_metadata_i[46:43]
tx_u_slotID 6 Tswv yim Qhov parameter no yog tus lej qhov nyob hauv 1 ms subframe. Tag nrho cov slots hauv ib qho subframe raug suav los ntawm qhov ntsuas no.
Tus nqi ntau: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Reserved}		 tx_metadata_i[42:37]
tx_u_symbolid 6 Tswv yim Qhia tus lej cim hauv ib lub qhov. Tus nqi ntau: {00 0000b-11 1111b} tx_metadata_i[36:31]
tx_u_sectionId 12 Tswv yim SectionID maps U-dav hlau cov ntaub ntawv seem rau cov lus C-dav hlau sib txuas (thiab Tshooj Hom) cuam tshuam nrog cov ntaub ntawv.
Tus nqi ntau: {0000 0000 0000b-11111111 1111b}		 tx_metadata_i[30:19]
tx_u_rb 1 Tswv yim Resource Block Indicator.
Qhia yog tias txhua qhov kev pabcuam thaiv tau siv lossis txhua qhov kev pabcuam thaiv tau siv.
Tus nqi ntau: {0b = txhua qhov chaw thaiv siv; 1b = txhua lwm yam kev siv thaiv siv}		 tx_metadata_i[18]
tx_u_startPrb 10 Tswv yim Qhov pib PRB ntawm tus neeg siv dav hlau cov ntaub ntawv seem.
Tus nqi ntau: {00 0000 0000b-11 1111 1111b}		 tx_metadata_i[17:8]
tx_u_numPrb 8 Tswv yim Txhais cov PRBs qhov twg cov neeg siv dav hlau cov ntaub ntawv seem siv tau. tx_metadata_i[7:0]
      Tus nqi ntau: {0000 0001b-1111 1111b, 0000 0000b = tag nrho PRBs nyob rau hauv qhov teev subcarrier spacing (SCS) thiab carrier bandwidth }  
tx_u_udCompHdr 8 Tswv yim Txhais txoj kev compression thiab IQ me ntsis dav ntawm tus neeg siv cov ntaub ntawv hauv cov ntaub ntawv seem. Tus nqi ntau: {0000 0000b-1111 1111b} N/A (tx_udcomphdr_i)

Table 14. rx_metadata_valid_i/o

Lub Npe Lub Npe

 Bitwidth Kev taw qhia Kev piav qhia

Metadata Mapping
rx_sec_hdr_valid 1 Tso zis Thaum rx_sec_hdr_valid yog 1, U-plane seem cov ntaub ntawv teb siv tau.
Cov header IEs siv tau thaum rx_sec_hdr_valid tau lees paub, synchronous nrog avst_sink_u_startofpacket thiab avst_sink_u_valid.
Rov ua ntu IEs siv tau thaum rx_sec_hdr_valid tau lees paub, synchronous nrog avst_sink_u_valid.
Ntawm kev muab ntu tshiab PRB teb hauv avst_sink_u_data, muab ntu tshiab IEs nrog rx_sec_hdr_valid asserted.		 rx_metadata_valid_o

Table 15. rx_metadata_o 128-ntsis tso zis

Lub Npe Lub Npe Bitwidth Kev taw qhia Kev piav qhia

Metadata Mapping
Khaws tseg 32 Tso zis Khaws tseg. rx_metadata_o[127:96] xwm
rx_u_seq_id 16 Tso zis SeqID ntawm pob ntawv, uas yog muab rho tawm los ntawm eCPRI thauj header. rx_metadata_o[95:80] xwm
rx_u_pc_id 16 Tso zis PCID rau eCPRI thauj thiab RoEflowId rau RoE thauj rx_metadata_o[79:64] xwm
tseg 4 Tso zis Khaws tseg. rx_metadata_o[63:60] xwm
rx_u_dataDirection 1 Tso zis gNB data direction. Tus nqi ntau: {0b = Rx (ie upload), 1b = Tx (ie download)} rx_metadata_o[59]
rx_u_filterIndex 4 Tso zis Txhais qhov Performance index rau cov lim lim siv ntawm IQ cov ntaub ntawv thiab huab cua interface.
Tus nqi ntau: {0000b-1111b}		 rx_metadata_o[58:55] xwm
rx_u_frameId 8 Tso zis Ib lub txee rau 10 ms ntas (wrapping lub sij hawm 2.56 vib nas this), tshwj xeeb frameId = thav duab naj npawb modulo 256. Tus nqi ntau: {0000 0000b-1111 1111b} rx_metadata_o[54:47] xwm
rx_u_subframeId 4 Tso zis Lub txee rau 1ms subframes hauv 10 ms ncej. Tus nqi ntau: {0000b-1111b} rx_metadata_o[46:43] xwm
rx_u_slotID 6 Tso zis Tus lej qhov nyob hauv 1ms subframe. Tag nrho cov slots hauv ib qho subframe raug suav los ntawm qhov ntsuas no. Tus nqi ntau: {00 0000b-00 1111b=slotID, 01 0000b-111111b=Reserved} rx_metadata_o[42:37] xwm
rx_u_symbolid 6 Tso zis Qhia tus lej cim hauv ib lub qhov.
Tus nqi ntau: {00 0000b-11 1111b}		 rx_metadata_o[36:31] xwm
rx_u_sectionId 12 Tso zis SectionID maps U-dav hlau cov ntaub ntawv seem rau cov lus C-dav hlau sib txuas (thiab Tshooj Hom) cuam tshuam nrog cov ntaub ntawv.
Tus nqi ntau: {0000 0000 0000b-1111 1111 1111b}		 rx_metadata_o[30:19] xwm
rx_u_rb 1 Tso zis Resource Block Indicator.
Qhia yog tias txhua qhov kev pab cuam thaiv tau siv los yog siv lwm cov peev txheej.
Tus nqi ntau: {0b = txhua qhov chaw thaiv siv; 1b = txhua lwm yam kev siv thaiv siv}		 rx_metadata_o[18]
rx_u_startPrb 10 Tso zis Qhov pib PRB ntawm tus neeg siv dav hlau cov ntaub ntawv seem.
Tus nqi ntau: {00 0000 0000b-11 1111 1111b}		 rx_metadata_o[17:8] xwm
rx_u_numPrb 8 Tso zis Txhais cov PRBs qhov twg cov neeg siv dav hlau cov ntaub ntawv seem siv tau.
Tus nqi ntau: {0000 0001b-1111 1111b, 0000 0000b = tag nrho PRBs hauv SCS tau teev tseg thiab cov cab kuj bandwidth }		 rx_metadata_o[7:0] xwm
rx_u_udCompHdr 8 Tso zis Txhais txoj kev compression thiab IQ me ntsis dav ntawm tus neeg siv cov ntaub ntawv hauv cov ntaub ntawv seem.
Tus nqi ntau: {0000 0000b-1111 1111b}		 N/A (rx_udcomphdr_o)

CSR Interface Signals
Table 16. CSR Interface Signals

Lub Npe Lub Npe Qhov dav me ntsis Kev taw qhia

Kev piav qhia
csr_ chaw nyob 16 Tswv yim Configuration register chaw nyob.
csr_write 1 Tswv yim Configuration register sau enable.
csr_writedata 32 Tswv yim Configuration sau npe sau cov ntaub ntawv.
csr_readdata 32 Tso zis Configuration sau npe nyeem cov ntaub ntawv.
csr_ nyeem 1 Tswv yim Configuration register read enable.
csr_readdata siv tau 1 Tso zis Configuration register nyeem cov ntaub ntawv siv tau.
csr_waitrequest 1 Tso zis Configuration register tos thov.

Fronthaul Compression IP Sau npe

Tswj thiab saib xyuas fronthaul compression functionality los ntawm kev tswj thiab xwm txheej interface.
Table 17. Sau npe daim ntawv qhia

CSR_ADDRESS (Word Offset) Sau npe
0 x 0 compression_mode
0 x 1 tx_error
0 x 2 rx_ yuam kev

Table 18. compression_mode Sau npe

Qhov dav me ntsis Kev piav qhia Nkag mus

HW Reset Value
31:9 ua Khaws tseg RO 0 x 0
8:8 ua Hom kev ua haujlwm:
• 1'b0 yog hom compression zoo li qub
• 1'b1 yog dynamic compression hom		 RW 0 x 0
7:0 ua Static neeg siv cov ntaub ntawv compression header:
• 7:4 yog udIqWidth
- 4'b0000 yog 16 ntsis
- 4'b1111 yog 15 ntsis
-:
- 4'b0001 yog 1 ntsis
• 3:0 yog udCompMeth
- 4'b0000 tsis muaj compression
- 4'b0001 yog thaiv ntab taw tes
— 4'b0011 yog µ-law
• Lwm tus tau tshwj tseg		 RW 0 x 0

Table 19. tx Register yuam kev

Qhov dav me ntsis Kev piav qhia Nkag mus

HW Reset Value
31:2 ua Khaws tseg RO 0 x 0
1:1 ua Invalid IqWidth. IP teeb tsa Iqwidth rau 0 (16-ntsis Iqwidth) yog tias nws pom qhov tsis raug lossis tsis txhawb Iqwidth. RWB 1C 0 x 0
0:0 ua Txoj kev compression tsis raug. IP poob lub pob ntawv. RWB 1C 0 x 0

Rooj 20. rx yuam kev Register

Qhov dav me ntsis Kev piav qhia Nkag mus

HW Reset Value
31:8 ua Khaws tseg RO 0 x 0
1:1 ua Invalid IqWidth. IP poob lub pob ntawv. RWB 1C 0 x 0
0:0 ua Txoj kev compression tsis raug. Tus IP teeb tsa txoj kev compression rau hauv qab no default txhawb compression txoj kev:
• Enabled block-floating point xwb: default to block-floating point.
• Enabled µ-law xwb: default to μ-law.
• Enabled ob qho tib si thaiv-floating point thiab μ-txoj cai: default rau thaiv-floating point.		 RWB 1C 0 x 0

Fronthaul Compression Intel FPGA IPs Cov Neeg Siv Phau Ntawv Qhia Archive

Rau qhov tseeb thiab yav dhau los versions ntawm daim ntawv no, xa mus rau: Fronthaul Compression Intel FPGA IP Tus Neeg Siv Qhia. Yog tias tus IP lossis software version tsis tau teev tseg, cov lus qhia siv rau tus IP yav dhau los lossis software version siv.

Cov ntaub ntawv kho dua tshiab rau Fronthaul Compression Intel FPGA IP Tus Neeg Siv Qhia

Cov ntaub ntawv Version

 Intel Quartus Prime Version IP Version

Hloov
2022.08.08 21.4 1.0.1 Kho metadata dav 0 txog 0 (Xaiv Metadata Ports).
2022.03.22 21.4 1.0.1 • Swapped signal piav qhia:
— tx_avst_sink_data and tx_avst_source_data
— rx_avst_sink_data thiab rx_avst_source_data
• Ntxiv Device Supported Ceev Qib rooj
• Ntxiv Kev ua tau zoo thiab kev siv peev txheej
2021.12.07 21.3 1.0.0 Hloov kho kev txiav txim code.
2021.11.23 21.3 1.0.0 Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Intel logoIntel Fronthaul Compression FPGA IP icon 2 Online Version
Intel Fronthaul Compression FPGA IP icon 1 Xa lus tawm tswv yim
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Version: 2022.08.08
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