Fronthaul Compression FPGA IP
Ke alakaʻi hoʻohana
Fronthaul Compression FPGA IP
Fronthaul Compression Intel® FPGA IP alakaʻi hoʻohana
Hōʻano hou ʻia no Intel® Quartus® Prime
Hana Hana: 21.4 IP
Manaʻo: 1.0.1
E pili ana i ka Fronthaul Compression Intel® FPGA IP
Aia ka Fronthaul Compression IP i ka hoʻopili a me ka decompression no ka ʻikepili U-plane IQ. Hoʻopili ka ʻenekini hoʻopiʻi i ka µ-law a i ʻole ka poloka floating-point compression ma muli o ke poʻo hoʻopiʻi ʻikepili mea hoʻohana (udCompHdr). Ke hoʻohana nei kēia IP i kahi interface streaming Avalon no ka ʻikepili IQ, nā hōʻailona conduit, a no nā hōʻailona metadata a me nā hōʻailona sideband, a me Avalon hoʻomanaʻo-mapped interface no ka mana a me nā papa inoa kūlana (CSRs).
Ua hoʻopili ʻia nā palapala IP IP i nā IQ a me ka helu hoʻopaʻa ʻikepili mea hoʻohana (udCompParam) e like me ke ʻano o ka ʻāpana uku uku i hōʻike ʻia ma ka kikoʻī O-RAN O-RAN Fronthaul Control, User and Synchronization Plane Version 3.0 ʻApelila 2020 (O-RAN-WG4.CUS .0-v03.00). ʻO Avalon streaming sink a me ka laula o ka ʻikepili kumu kumu he 128-bits no ka interface noi a me 64 bits no ke kaʻa lawe e kākoʻo i ka ratio compressoin kiʻekiʻe o 2:1.
ʻIke pili
O-RAN webpaena
1.1. Fronthaul Compression Intel® FPGA IP hiʻohiʻona
- -kānāwai a poloka i ka hoʻopiʻi ʻana a me ka decompression
- IQ laula 8-bit a 16-bit
- ʻO ka hoʻonohonoho paʻa a me ka ikaika o ka format U-plane IQ a me ke poʻo hoʻoemi
- ʻO nā ʻāpana ʻāpana he nui (inā ʻā ʻo O-RAN Compliant)
1.2. Kākoʻo ʻohana ʻohana Fronthaul Compression Intel® FPGA IP Device
Hāʻawi ʻo Intel i kēia mau pae kākoʻo no ka Intel FPGA IP:
- Kākoʻo mua—loaʻa ka IP no ka hoʻohālikelike a me ka hoʻohui ʻana no kēia ʻohana hāmeʻa. FPGA papahana file ʻAʻole loaʻa ke kākoʻo (.pof) no ka polokalamu Quartus Prime Pro Stratix 10 Edition Beta a no laila ʻaʻole hiki ke hōʻoia ʻia ka pani ʻana o ka manawa IP. Hoʻokomo ʻia nā kumu hoʻohālike manawa i nā kuhi ʻenekinia mua o nā lohi e pili ana i ka ʻike ma hope o ka hoʻonohonoho mua ʻana. Hiki ke hoʻololi ʻia nā hiʻohiʻona manawa no ka hoʻomaikaʻi ʻana o ka hoʻāʻo silika i ka pilina ma waena o ke silikona maoli a me nā kumu hoʻohālike manawa. Hiki iā ʻoe ke hoʻohana i kēia IP core no ka hoʻolālā ʻōnaehana a me nā haʻawina hoʻohana waiwai, simulation, pinout, system latency assessments, basic time assessments (pipeline budgeting), a me I/O transfer strategy (data-alanui width, burst depth, I/O standard tradeoffs). ).
- Kākoʻo mua–E hōʻoia ʻo Intel i ka IP core me nā hiʻohiʻona manawa mua no kēia ʻohana hāmeʻa. Hoʻokō ka IP core i nā pono hana āpau, akā ke hele nei paha ka nānā ʻana i ka manawa no ka ʻohana hāmeʻa. Hiki iā ʻoe ke hoʻohana iā ia i nā hoʻolālā hana me ka akahele.
- Kākoʻo hope–E hōʻoia ʻo Intel i ka IP me nā hiʻohiʻona manawa hope no kēia ʻohana hāmeʻa. Hoʻokō ka IP i nā pono hana a me ka manawa no ka ʻohana hāmeʻa. Hiki iā ʻoe ke hoʻohana iā ia i nā hoʻolālā hana.
Papa 1. Fronthaul Compression IP Device Support Family Support
| ʻOhana Mea Hana | Kākoʻo |
| Intel® Agilex™ (E-tile) | Hoʻomaka |
| Intel Agilex (F-tile) | Holomua |
| Intel Arria® 10 | hope loa |
| ʻO Intel Stratix® 10 (H-, a me nā polokalamu E-tile wale nō) | hope loa |
| Nā ʻohana mea hana ʻē aʻe | ʻAʻohe kākoʻo |
Papa 2. Kākoʻo ʻia nā māka māmā
| ʻOhana Mea Hana | FPGA Māmā Māmā |
| Intel Agilex | 3 |
| ʻO Intel Arria 10 | 2 |
| ʻO Intel Stratix 10 | 2 |
1.3. Hoʻokuʻu i ka ʻike no ka Fronthaul Compression Intel FPGA IP
Kūlike nā mana Intel FPGA IP me nā mana polokalamu polokalamu Intel Quartus® Prime Design Suite a hiki i ka v19.1. E hoʻomaka ana ma Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP he polokalamu hoʻololi hou.
Hiki ke loli ka helu Intel FPGA IP (XYZ) me kēlā me kēia polokalamu polokalamu Intel Quartus Prime. He hoʻololi i:
- Hōʻike ʻo X i kahi hoʻoponopono nui o ka IP. Inā hōʻano hou ʻoe i ka polokalamu Intel Quartus Prime, pono ʻoe e hana hou i ka IP.
- Hōʻike ʻo Y i ka IP me nā hiʻohiʻona hou. E hana hou i kāu IP e hoʻokomo i kēia mau hiʻohiʻona hou.
- Hōʻike ʻo Z i ka IP me nā loli liʻiliʻi. E hana hou i kāu IP e hoʻokomo i kēia mau hoʻololi.
Papa 3. Fronthaul Compression IP Release Information
| 'ikamu | wehewehe |
| Manao | 1.0.1 |
| lā hoʻokuʻu | Pepeluali 2022 |
| Kāhea helu | IP-FH-COMP |
1.4. ʻO Fronthaul Compression Performance a me ka hoʻohana waiwai
ʻO nā kumuwaiwai o ka IP e ʻimi ana i kahi polokalamu Intel Agilex, Intel Arria 10, a me Intel Stratix 10.
Papa 4. Fronthaul Compression Performance a me ka hoohana waiwai
ʻO nā mea komo a pau no ka hoʻopili a me ka decompression ʻikepili kuhikuhi IP
| Mea lako | IP | ALM | Hoʻopaʻa inoa loiloi | M20K | |
| Papahana | lua | ||||
| Intel Agilex | Poka-lele wahi | 14,969 | 25,689 | 6,093 | 0 |
| µ-kānāwai | 22,704 | 39,078 | 7,896 | 0 | |
| Poka-lele kiko a me µ-law | 23,739 | 41,447 | 8,722 | 0 | |
| Poka-lele kiko, µ-law, a me IQ laula | 23,928 | 41,438 | 8,633 | 0 | |
| ʻO Intel Arria 10 | Poka-lele wahi | 12,403 | 16,156 | 5,228 | 0 |
| µ-kānāwai | 18,606 | 23,617 | 5,886 | 0 | |
| Poka-lele kiko a me µ-law | 19,538 | 24,650 | 6,140 | 0 | |
| Poka-lele kiko, µ-law, a me IQ laula | 19,675 | 24,668 | 6,141 | 0 | |
| ʻO Intel Stratix 10 | Poka-lele wahi | 16,852 | 30,548 | 7,265 | 0 |
| µ-kānāwai | 24,528 | 44,325 | 8,080 | 0 | |
| Poka-lele kiko a me µ-law | 25,690 | 47,357 | 8,858 | 0 | |
| Poka-lele kiko, µ-law, a me IQ laula | 25,897 | 47,289 | 8,559 | 0 | |
E hoʻomaka me ka Fronthaul Compression Intel FPGA IP
E wehewehe ana i ka hoʻouka ʻana, hoʻohālikelike, hoʻohālikelike, a me ka hoʻomaka ʻana i ka Fronthaul Compression IP.
2.1. Loaʻa, hoʻokomo, a me ka laikini ʻana i ka Fronthaul Compression IP
ʻO ka Fronthaul Compression IP kahi Intel FPGA IP lōʻihi ʻaʻole i hoʻokomo ʻia me ka hoʻokuʻu ʻana o Intel Quartus Prime.
- E hana i kaʻu moʻokāki Intel inā ʻaʻohe āu.
- E komo i loko e komo i ka Self-Service Licensing Center (SSLC).
- E kūʻai i ka Fronthaul Compression IP.
- Ma ka ʻaoʻao SSLC, kaomi Holo no ka IP. Hāʻawi ka SSLC i kahi pahu kamaʻilio hoʻonohonoho e alakaʻi i kāu hoʻokomo ʻana i ka IP.
- E hoʻouka i ka wahi like me ka waihona Intel Quartus Prime.
Papa 5. Nā wahi i hoʻokomo ʻia ʻo Fronthaul Compression
| Wahi | lako polokalamu | Papahana |
| :\intelFPGA_pro\\quartus\ip \altera_cloud | ʻO Intel Quartus Prime Pro Edition | ʻO Windows * |
| :/intelFPGA_pro// quartus/ip/altera_cloud | ʻO Intel Quartus Prime Pro Edition | Linux * |
Kiʻi 1. Fronthaul Compression IP Installation Directory Structure Intel Quartus Prime install directory
Hōʻike ʻia ka Fronthaul Compression Intel FPGA IP i ka IP Catalog.
ʻIke pili
- Intel FPGA webpaena
- Kikowaena Laikini Hana Ponoi (SSLC)
2.2. Hoʻohālikelike i ka IP Compression Fronthaul
E hoʻonohonoho koke i kāu hoʻololi IP maʻamau ma ka IP Parameter Editor.
- E hana i kahi papahana Intel Quartus Prime Pro Edition kahi e hoʻohui ai i kāu kumu IP.
a. Ma ka Intel Quartus Prime Pro Edition, kaomi File Hoʻokumu i kahi papahana Intel Quartus Prime hou, a i ʻole File Open Project e wehe i kahi papahana Quartus Prime. Koi ka wizard iā ʻoe e kuhikuhi i kahi mea hana.
b. E wehewehe i ka ʻohana hāmeʻa i kūpono i nā koi o ka māka wikiwiki no ka IP.
c. Kaomi Hoʻopau. - Ma ka IP Catalog, koho Fronthaul Compression Intel FPGA IP. Hōʻike ʻia ka puka aniani IP Variation hou.
- E wehewehe i kahi inoa kiʻekiʻe no kāu hoʻololi IP maʻamau hou. Mālama ka mea hoʻoponopono hoʻoponopono i nā hoʻonohonoho hoʻololi IP ma kahi file inoa ʻia .ip.
- Kaomi OK. Hōʻike ʻia ka mea hoʻoponopono hoʻohālikelike.
Kiʻi 2. Fronthaul Compression IP Parameter Lunahooponopono - E wehewehe i nā ʻāpana no kāu hoʻololi IP. E nānā i nā ʻāpana no ka ʻike e pili ana i nā ʻāpana IP kikoʻī.
- Kaomi i ka Design Example tab a kuhikuhi i nā ʻāpana no kāu hoʻolālā example.
Kiʻi 3. Hoʻolālā Example Lunahooponopono Parameter - Kaomi i ka Generate HDL. Hōʻike ʻia ka pahu kamaʻilio Generation.
- E wehewehe i ka puka file nā koho hanauna, a laila kaomi i ka Generate. ʻO ka hoʻololi IP files hana e like me kāu mau kikoʻī.
- Kaomi Hoʻopau. Hoʻohui ka mea hoʻoponopono hoʻohālikelike i ka .ip kiʻekiʻe file i ka papahana o kēia manawa. Inā koi ʻia ʻoe e hoʻohui lima i ka .ip file i ka papahana, kaomi Project Add/Remove Files i Project e hoʻohui i ka file.
- Ma hope o ka hana ʻana a me ka hoʻololi koke ʻana i kāu hoʻololi IP, e hana i nā hana pine kūpono e hoʻopili i nā awa a hoʻonohonoho i nā ʻāpana RTL kūpono i kēlā me kēia manawa.
2.2.1. Nā Kūlana IP Compression Fronthaul
Papa 6. Fronthaul Compression IP Parameter
| inoa | Waiwai Pono |
wehewehe |
| Kuhikuhi ʻikepili | ʻO TX a me RX, TX wale nō, RX wale nō | E koho i ka TX no ka hoʻopili ʻana; RX no ka decompression. |
| ʻano hoʻoemi | BFP, mu-Law, a i ʻole BFP a me mu-Law | E koho i ke kiko lana, µ-law, a i ʻole nā mea ʻelua. |
| laulā metadata | 0 (Hoʻopau i nā Awa Metadata), 32, 64, 96, 128 (bit) | E wehewehe i ka laula iki o ke kaʻa kaʻa metadata (ʻikepili i hoʻopaʻa ʻole ʻia). |
| Hoʻā i ka laula IQ hoʻonui | Pau a i ʻole | E ho'ā no ka IqWidth kākoʻo o 8-bit a 16-bit. Hoʻopau no ka IqWidth kākoʻo o 9, 12, 14 a me 16-bits. |
| ʻO-RAN kūpono | Pau a i ʻole | E ho'ā e hahai i ka palapala 'āina IP ORAN no ke awa metadata a e hō'oia i ka hō'ailona kūpono no kēlā me kēia po'omana'o. Kākoʻo ka IP i ka metadata ākea 128-bit wale nō. Kākoʻo ka IP i ka ʻāpana hoʻokahi a me nā ʻāpana he nui i kēlā me kēia ʻeke. Pono ka metadata ma kēlā me kēia ʻāpana me ka manaʻo kūpono metadata. E hoʻopau i ka hoʻohana ʻana o ka IP i ka metadata ma ke ʻano he hōʻailona alahele passthrough me ka ʻole o ke koi palapala palapala (e like me: U-plane numPrb is assumed 0). Kākoʻo ka IP i nā laulā metadata o 0 (Hoʻopau i nā awa Metadata), 32, 64, 96, 128 mau bits. Kākoʻo ka IP i ka ʻāpana hoʻokahi no ka ʻeke. Hoʻokahi wale nō mana o ka metadata ma ka ʻōlelo hōʻoia kūpono no kēlā me kēia ʻeke. |
2.3. IP hana ʻia File Hoʻolālā
Hoʻopuka ka polokalamu Intel Quartus Prime Pro Edition i ka hopena IP kumu file hale kūkulu.
Papa 7. Hanaia IP Files
| File inoa |
wehewehe |
| <kou_ip>.ip | ʻO ka ʻōnaehana Platform Designer a i ʻole ka hoʻololi IP pae kiʻekiʻe file.kou_ip> ʻo ia ka inoa āu e hāʻawi ai i kāu hoʻololi IP. |
| <kou_ip>.cmp | ʻO ka VHDL Component Declaration (.cmp) file he kikokikona file Loaʻa nā wehewehe kikoʻī kūloko a me nā awa hiki iā ʻoe ke hoʻohana i ka hoʻolālā VHDL files. |
| <kou_ip>.html | He hōʻike e loaʻa ana ka ʻike pili, kahi palapala hoʻomanaʻo e hōʻike ana i ka helu o kēlā me kēia kauā e pili ana i kēlā me kēia haku i hoʻopili ʻia ai, a me nā ʻāpana koho. |
| <kou_ip>_generation.rpt | IP a i ʻole ka papa hana hoʻolālā papahana file. He hōʻuluʻulu o nā memo i ka wā o ka hana IP. |
| <kou_ip>.qgsimc | Papa inoa i nā ʻāpana hoʻohālikelike e kākoʻo i ka hana hou ʻana. |
| <kou_ip>.qgsynthc | Papa inoa i nā ʻāpana synthesis e kākoʻo i ka hoʻonui hou ʻana. |
| <kou_ip>.qip | Loaʻa i nā ʻike āpau e pono ai e pili ana i ka ʻāpana IP e hoʻohui a hoʻohui i ka ʻāpana IP i ka polokalamu Intel Quartus Prime. |
| <kou_ip>.sopcinfo | Hōʻike i nā pili a me nā ʻāpana ʻāpana IP i kāu ʻōnaehana Platform Designer. Hiki iā ʻoe ke hoʻokaʻawale i kāna mau ʻike e kiʻi i nā koi ke kūkulu ʻoe i nā mea hoʻokele polokalamu no nā ʻāpana IP. Hoʻohana nā mea hana i lalo e like me ke kaulahao mea hana Nios® II i kēia file. ʻO ka .sopcinfo file a me ka ʻōnaehana.h file i hana ʻia no ke kaulahao mea hana Nios II me ka ʻike palapala ʻāina no kēlā me kēia kauā e pili ana i kēlā me kēia haku e komo i ke kauā. Loaʻa paha i nā haku ʻokoʻa kahi palapala ʻāina ʻē aʻe e komo ai i kahi ʻāpana kauā. |
| <kou_ip>.csv | Loaʻa ka ʻike e pili ana i ke kūlana hoʻonui o ka mea IP. |
| <kou_ip>.bsf | He Hoailona Block File (.bsf) hōʻike i ka hoʻololi IP no ka hoʻohana ʻana ma Intel Quartus Prime Block Diagram Files (.bdf). |
| <kou_ip>.spd | Koi komo file no ka ip-make-simscript e hana i nā palapala hoʻohālikelike no nā simulators i kākoʻo ʻia. ʻO ka .spd file he papa inoa o files i hana ʻia no ka simulation, me ka ʻike e pili ana i nā hoʻomanaʻo i hiki iā ʻoe ke hoʻomaka. |
| <kou_ip>.ppf | Ka Pin Planner File (.ppf) mālama i ke awa a me ka node i nā ʻāpana IP i hana ʻia no ka hoʻohana ʻana me ka Pin Planner. |
| <kou_ip>_bb.v | Hiki iā ʻoe ke hoʻohana i ka pahu ʻeleʻele Verilog (_bb.v) file ma ke ʻano he ʻōlelo hoʻolaha ʻokoʻa no ka hoʻohana ʻana ma ke ʻano he pahu ʻeleʻele. |
| <kou_ip>_inst.v a i ʻole _inst.vhd | HDL example instantiation template. Hiki iā ʻoe ke kope a paʻi i nā mea o kēia file i kāu HDL file e hoʻololi koke i ka hoʻololi IP. |
| <kou_ip>.v pahakou_ip>.vhd | HDL files e hoʻomaka koke i kēlā me kēia submodule a i ʻole keiki IP core no ka synthesis a i ʻole ka hoʻohālikelike. |
| kumu aʻo/ | Loaʻa i kahi palapala ModelSim* msim_setup.tcl e hoʻonohonoho a holo i kahi hoʻohālike. |
| nā huaʻōlelo/vcs/ synopsys/vcsmx/ | Loaʻa i kahi hōʻailona shell vcs_setup.sh e hoʻonohonoho a holo i kahi hoʻohālike VCS*. Loaʻa i kahi hōʻailona shell vcsmx_setup.sh a me synopsys_ sim.setup file e hoʻonohonoho a holo i kahi hoʻohālike VCS MX*. |
| cadence/ | Loaʻa i ka shell script ncsim_setup.sh a me nā hoʻonohonoho ʻē aʻe files e hoʻonohonoho a holo i kahi hoʻohālike NCSIM*. |
| aldec/ | Loaʻa i kahi hōʻailona shell rivierapro_setup.sh e hoʻonohonoho a holo i kahi hoʻohālike Aldec*. |
| xcelium/ | Loaʻa i ka shell script xcelium_setup.sh a me nā hoʻonohonoho ʻē aʻe files e hoʻonohonoho a holo i kahi hoʻohālike Xcelium*. |
| submodules/ | Loaʻa iā HDL files no nā submodules kumu IP. |
| <keiki IP cores>/ | No kēlā me kēia papa kuhikuhi IP keiki i hana ʻia, hana ʻo Platform Designer i nā synth/ a me sim/ sub-directories. |
ʻO Fronthaul Compression IP wehewehe hana
Kiʻi 4. Aia ka Fronthaul Compression IP i ka hoʻopili a me ka decompression. Fronthaul Compression IP Block Diagram
Hoʻopiʻi a me ka Decompression
Hoʻopuka ʻia nā ʻāpana hoʻololi ʻokoʻa no ka poloka kumu waiwai o 12 mau mea waiwai (RE). Hoʻemi ka poloka i ka walaʻau quantization, ʻoi aku hoʻi no nā haʻahaʻa haʻahaʻa.ampliʻiliʻi samples. No laila, hoʻemi ia i ka nui o ka vector error (EVM) i hoʻokomo ʻia ka hoʻoemi. ʻAneʻane kūʻokoʻa ka algorithm compression i ka waiwai o ka mana. Ke manaʻo nei i ka hoʻokomo paʻakikī samples he x = x1 + jxQ, ka nui loa o ka waiwai o na mea maoli a me na mea noonoo no ka poloka kumu waiwai:
No ka loaʻa ʻana o ka waiwai kūʻokoʻa kiʻekiʻe loa no ka poloka kumu waiwai, e hoʻoholo ka hoohalike ma lalo nei i ka waiwai hoʻololi hema i hāʻawi ʻia i kēlā poloka kumu waiwai:
ʻO kahi bitWidth ka laulā bit komo.
Kākoʻo ka IP i nā lakio kōmike o 8, 9, 10, 11, 12, 13, 14, 15, 16.
Mu-Law Compression and Decompression
Hoʻohana ka algorithm i ka ʻenehana hoʻohālikelike Mu-law, kahi e hoʻohana nui ʻia ai ka hoʻopili ʻōlelo. Hāʻawi kēia ʻenehana i ka hōʻailona hoʻokomo ʻole ʻia, x, ma o ka mea hoʻoemi me ka hana, f(x), ma mua o ka hoʻopuni ʻana a me ka ʻoki-bit. Hoʻouna ka ʻenehana i ka ʻikepili i hoʻopaʻa ʻia, y, ma luna o ka interface. Ke hele nei ka ʻikepili i loaʻa ma kahi hana hoʻonui (ʻo ia ka hoʻohuli ʻana o ka mea hoʻopili, F-1(y).
Hoʻohālikelike 1. ʻO nā hana kaomi a me ka decompressor
ʻO ka Mu-law IQ compression algorithm e hahai ana i ka kikoʻī O-RAN.
ʻIke pili
O-RAN webpaena
3.1. Nā hōʻailona IP Compression Fronthaul
Hoʻohui a mālama i ka IP.
Uaki a hoʻonohonoho hou i nā hōʻailona Interface=
Papa 8. Uaki a hoʻonohonoho hou i nā hōʻailona Interface
| inoa hōʻailona | Bitwidth | Kuhikuhi |
wehewehe |
| tx_clk | 1 | Hookomo | Uaki hoʻouna. ʻO ka pinepine o ka uaki he 390.625 MHz no 25 Gbps a me 156.25MHz no 10 Gbps. Hoʻohui pū ʻia nā hōʻailona interface transmitter a pau i kēia uaki. |
| rx_clk | 1 | Hookomo | Uaki loaa. ʻO ka pinepine o ka uaki he 390.625 MHz no 25 Gbps a me 156.25MHz no 10 Gbps. Hoʻohui pū ʻia nā hōʻailona hoʻokipa a pau me kēia uaki. |
| csr_clk | 1 | Hookomo | Uaki no ka CSR interface. ʻO ka pinepine o ka uaki he 100 MHz. |
| tx_rst_n | 1 | Hookomo | Hoʻonohonoho haʻahaʻa haʻahaʻa no ka interface transmitter synchronous me tx_clk. |
| rx_mua_n | 1 | Hookomo | Hoʻihoʻi haʻahaʻa haʻahaʻa no ka mea hoʻokipa i hui pū ʻia me rx_clk. |
| csr_rst_n | 1 | Hookomo | Hoʻonohonoho haʻahaʻa haʻahaʻa no ka interface CSR i hui pū me csr_clk. |
Hoʻouna i nā hōʻailona Interface Transport
Papa 9. Hoʻouna i nā hōʻailona Interface Transport
ʻO nā ʻano hōʻailona āpau he helu helu ʻole.
|
inoa hōʻailona |
Bitwidth | Kuhikuhi |
wehewehe |
| tx_avst_source_valid | 1 | Hoʻopuka | Ke ʻōlelo ʻia, hōʻike ʻia aia ka ʻikepili kūpono ma avst_source_data. |
| tx_avst_source_data | 64 | Hoʻopuka | Nā kahua PRB me udCompParam, iSample a me qSample. Hoʻohui ʻia nā kahua PRB ʻāpana aʻe me ka māhele PRB ma mua. |
| tx_avst_source_startofpacket | 1 | Hoʻopuka | Hōʻike i ka byte mua o kahi kiʻi. |
| tx_avst_source_endofpacket | 1 | Hoʻopuka | Hōʻike i ka byte hope o kahi kiʻi. |
| tx_avst_source_ready | 1 | Hookomo | Ke hōʻoiaʻiʻo ʻia, e hōʻike ana ua mākaukau ka papa halihali e ʻae i ka ʻikepili. readyLatency = 0 no kēia pānaʻi. |
| tx_avst_source_empty | 3 | Hoʻopuka | Hōʻike i ka helu o nā byte kaʻawale ma avst_source_data ke hōʻoia ʻia ka avst_source_endofpacket. |
| tx_udcomphdr_o | 8 | Hoʻopuka | Kahua poʻomanaʻo kaomi ʻikepili mea hoʻohana. Hoʻohui pū me tx_avst_source_valid. E wehewehe i ke ʻano hoʻoemi a me ka laulā bit IQ no ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. • [7:4] : udIqWidth • 16 no udIqWidth=0, a i ole ia, ua like ia me udIqWidth e,g,: — 0000b 'o ia ho'i, 'o I a me Q he 16 bits ka laula; — 0001b 'o ia ho'i, 'o I a me Q he 1 bit laula; — 1111b 'o ia ho'i, 'o I a me Q he 15 bits ka laula • [3:0] : udCompMeth - 0000b - ʻaʻohe hoʻoemi — 0001b – wahi poloka-lele — 0011b – µ-kānāwai - nā mea ʻē aʻe - mālama ʻia no nā ala e hiki mai ana. |
| tx_metadata_o | METADATA_WIDTH | Hoʻopuka | Hōʻike ka conduit i nā hōʻailona passthrough a ʻaʻole i hoʻopaʻa ʻia. Hoʻohui pū me tx_avst_source_valid. Hiki ke hoʻonohonoho ʻia ka bitwidth METADATA_WIDTH. Ke hoʻā ʻoe ʻO-RAN kūpono, kuhikuhi i Papa 13 ma ka ʻaoʻao 17. Ke hoʻopau ʻoe ʻO-RAN kūpono, pono wale kēia hōʻailona inā he 1 ka tx_avst_source_startofpacket. ʻAʻole loaʻa ke koho ʻoe 0 Hoʻopau i nā Awa Metadata no ka mea laulā metadata. |
Loaʻa nā hōʻailona Interface Transport
Papa 10. Loaʻa nā hōʻailona Interface Transport
ʻAʻohe backpressure ma kēia interface. ʻAʻole pono ʻo Avalon e kahe ana i ka hōʻailona hakahaka i kēia interface no ka mea ʻaʻole mau.
| inoa hōʻailona | Bitwidth | Kuhikuhi |
wehewehe |
| rx_avst_sink_valid | 1 | Hookomo | Ke ʻōlelo ʻia, hōʻike i ka ʻikepili kūpono i loaʻa ma avst_sink_data. ʻAʻohe hōʻailona avst_sink_ready ma kēia interface. |
| rx_avst_sink_data | 64 | Hookomo | Nā kahua PRB me udCompParam, iSample a me qSample. Hoʻohui ʻia nā kahua PRB ʻāpana aʻe me ka māhele PRB ma mua. |
| rx_avst_sink_startofpacket | 1 | Hookomo | Hōʻike i ka byte mua o kahi kiʻi. |
| rx_avst_sink_endofpacket | 1 | Hookomo | Hōʻike i ka byte hope o kahi kiʻi. |
| rx_avst_sink_error | 1 | Hookomo | Ke ʻōlelo ʻia ma ka pōʻai like me avst_sink_endofpacket, e hōʻike ana i ka ʻeke o kēia manawa he ʻeke kuhi. |
| rx_udcomphdr_i | 8 | Hookomo | Kahua poʻomanaʻo kaomi ʻikepili mea hoʻohana. Hoʻohui pū me rx_metadata_valid_i. E wehewehe i ke ʻano hoʻoemi a me ka laula bit IQ no ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. • [7:4] : udIqWidth • 16 no ka udIqWidth=0, a i ole ia, ua like ia me udIqWidth. eg — 0000b 'o ia ho'i, 'o I a me Q he 16 bits ka laula; — 0001b 'o ia ho'i, 'o I a me Q he 1 bit laula; — 1111b 'o ia ho'i, 'o I a me Q he 15 bits ka laula • [3:0] : udCompMeth - 0000b - ʻaʻohe hoʻoemi — 0001b – poloka wahi lana — 0011b – µ-kānāwai - nā mea ʻē aʻe - mālama ʻia no nā ala e hiki mai ana. |
| rx_metadata_i | METADATA_WIDTH | Hookomo | Hōʻailona ke kahawai ʻole i hoʻopaʻa ʻia. Pono nā hōʻailona rx_metadata_i i ka wā e ʻōlelo ʻia ai ka rx_metadata_valid_i, i hui pū ʻia me rx_avst_sink_valid. Hiki ke hoʻonohonoho ʻia ka bitwidth METADATA_WIDTH. Ke hoʻā ʻoe ʻO-RAN kūpono, kuhikuhi i Papakaukau 15 ma ka aoao 18. Ke hoʻopau ʻoe ʻO-RAN kūpono, pono kēia hōʻailona rx_metadata_i i ka wā e like ai ka rx_metadata_valid_i a me rx_avst_sink_startofpacket me 1. ʻAʻole i loaʻa ke koho ʻia. 0 Hoʻopau i nā Awa Metadata no ka mea laulā metadata. |
| rx_metadata_valid_i | 1 | Hookomo | Hōʻike i ka pono o nā poʻo (rx_udcomphdr_i a me rx_metadata_i). Hoʻohui pū me rx_avst_sink_valid. Hoailona koi. No ka hoʻohālikelike ʻana o O-RAN i hope, e hōʻoia i ka rx_metadata_valid_i inā loaʻa i ka IP nā IE poʻomanaʻo maʻamau a me nā IE ʻāpana hou. Ma ka ho'olako 'ana i ka pauku hou physical resource block (PRB) mahina ma rx_avst_sink_data, e hoolako i ka pauku hou IE ma rx_metadata_i hookomo pu me rx_metadata_valid_i. |
Hoʻouna i nā hōʻailona Interface Application
Papa 11. Hoʻouna i nā hōʻailona Interface Application
|
inoa hōʻailona |
Bitwidth | Kuhikuhi |
wehewehe |
| tx_avst_sink_valid | 1 | Hookomo | Ke hōʻoiaʻiʻo ʻia, e hōʻike ana i loaʻa nā māla PRB kūpono i kēia interface. I ka hana ʻana ma ke ʻano streaming, e hōʻoia ʻaʻole hōʻailona deassertion kūpono ma waena o ka hoʻomaka ʻana o ka ʻeke a me ka hopena o ka ʻeke ʻO ka mea ʻē aʻe i ka wā i hoʻopau ʻia ka hōʻailona mākaukau. |
| tx_avst_sink_data | 128 | Hookomo | ʻIkepili mai ka papa noi ma ke ʻano byte pūnaewele. |
| tx_avst_sink_startofpacket | 1 | Hookomo | E hōʻike i ka byte PRB mua o kahi ʻeke |
| tx_avst_sink_endofpacket | 1 | Hookomo | E hōʻike i ka byte PRB hope loa o kahi ʻeke |
| tx_avst_sink_ready | 1 | Hoʻopuka | Ke hōʻoia ʻia, e hōʻike ana ua mākaukau ka O-RAN IP e ʻae i ka ʻikepili mai ke kikowaena noi. readyLatency = 0 no kēia pānaʻi |
| tx_udcomphdr_i | 8 | Hookomo | Kahua poʻomanaʻo kaomi ʻikepili mea hoʻohana. Hoʻohui pū me tx_avst_sink_valid. E wehewehe i ke ʻano hoʻoemi a me ka laula bit IQ no ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. • [7:4] : udIqWidth • 16 no ka udIqWidth=0, a i ole ia, ua like ia me udIqWidth. eg — 0000b 'o ia ho'i, 'o I a me Q he 16 bits ka laula; — 0001b 'o ia ho'i, 'o I a me Q he 1 bit laula; — 1111b 'o ia ho'i, 'o I a me Q he 15 bits ka laula • [3:0] : udCompMeth - 0000b - ʻaʻohe hoʻoemi — 0001b – wahi poloka-lele — 0011b – µ-kānāwai - nā mea ʻē aʻe - mālama ʻia no nā ala e hiki mai ana. |
| tx_metadata_i | METADATA_WIDTH | Hookomo | Hōʻike ka conduit i nā hōʻailona passthrough a ʻaʻole i hoʻopaʻa ʻia. Hoʻohui pū me tx_avst_sink_valid. Hiki ke hoʻonohonoho ʻia ka bitwidth METADATA_WIDTH. Ke hoʻā ʻoe ʻO-RAN kūpono, kuhikuhi i Papakaukau 13 ma ka aoao 17. Ke hoʻopau ʻoe ʻO-RAN kūpono, pono wale kēia hōʻailona inā like ka tx_avst_sink_startofpacket me 1. ʻAʻohe hōʻailona kūpono a me ka hoʻohana ʻana iā tx_metadata_i tx_avst_sink_valid e hōʻike i ka pōʻaiapuni kūpono. ʻAʻole loaʻa ke koho ʻoe 0 Hoʻopau i nā Awa Metadata no ka mea laulā metadata. |
Loaʻa nā hōʻailona Interface Application
Papa 12. Loaʻa i nā hōʻailona Interface Application
|
inoa hōʻailona |
Bitwidth | Kuhikuhi |
wehewehe |
| rx_avst_source_valid | 1 | Hoʻopuka | Ke hōʻoiaʻiʻo ʻia, e hōʻike ana i loaʻa nā māla PRB kūpono i kēia interface. ʻAʻohe hōʻailona avst_source_ready ma kēia interface. |
| rx_avst_source_data | 128 | Hoʻopuka | ʻIkepili i ka papa noi ma ke ʻano byte pūnaewele. |
| rx_avst_source_startofpacket | 1 | Hoʻopuka | Hōʻike i ka byte PRB mua o kahi ʻeke |
| rx_avst_source_endofpacket | 1 | Hoʻopuka | Hōʻike i ka paina PRB hope loa o kahi ʻeke |
| rx_avst_source_error | 1 | Hoʻopuka | Hōʻike i nā ʻeke he hewa |
| rx_udcomphdr_o | 8 | Hoʻopuka | Kahua poʻomanaʻo kaomi ʻikepili mea hoʻohana. Hoʻohui pū me rx_avst_source_valid. E wehewehe i ke ʻano hoʻoemi a me ka laula bit IQ no ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. • [7:4] : udIqWidth • 16 no ka udIqWidth=0, a i ole ia, ua like ia me udIqWidth. eg — 0000b 'o ia ho'i, 'o I a me Q he 16 bits ka laula; — 0001b 'o ia ho'i, 'o I a me Q he 1 bit laula; — 1111b 'o ia ho'i, 'o I a me Q he 15 bits ka laula • [3:0] : udCompMeth - 0000b - ʻaʻohe hoʻoemi — 0001b – poloka wahi lana (BFP) — 0011b – µ-kānāwai - nā mea ʻē aʻe - mālama ʻia no nā ala e hiki mai ana. |
| rx_metadata_o | METADATA_WIDTH | Hoʻopuka | Hōʻailona ke kahawai ʻole i hoʻopaʻa ʻia. Loaʻa nā hōʻailona rx_metadata_o i ka wā i ʻōlelo ʻia ai ka rx_metadata_valid_o, i hui pū ʻia me rx_avst_source_valid. Hiki ke hoʻonohonoho ʻia ka bitwidth METADATA_WIDTH. Ke hoʻā ʻoe ʻO-RAN kūpono, kuhikuhi i Papa 14 ma ka aoao 18. Ke hoʻopau ʻoe ʻO-RAN kūpono, pono wale ka rx_metadata_o ke like ka rx_metadata_valid_o me 1. ʻAʻole loaʻa ke koho ʻoe 0 Hoʻopau i nā Awa Metadata no ka mea laulā metadata. |
| rx_metadata_valid_o | 1 | Hoʻopuka | E hōʻike ana i nā poʻo (rx_udcomphdr_o a me rx_metadata_o) kūpono. Manaʻo ʻia ka rx_metadata_valid_o i ka wā i kūpono ai ka rx_metadata_o, i hui pū ʻia me rx_avst_source_valid. |
Palapala ʻikepili Metadata no ka hoʻohālikelike ʻana i hope o O-RAN
Papa 13. tx_metadata_i hookomo 128-bit
|
inoa hōʻailona |
Bitwidth | Kuhikuhi | wehewehe |
Palapala ʻikepili Metadata |
| Mālama ʻia | 16 | Hookomo | Mālama ʻia. | tx_metadata_i[127:112] |
| tx_u_size | 16 | Hookomo | ʻO ka nui o ka ʻeke U-plane ma nā bytes no ke ʻano kahe. | tx_metadata_i[111:96] |
| tx_u_seq_id | 16 | Hookomo | SeqID o ka ʻeke, i lawe ʻia mai ka poʻomanaʻo lawe eCPRI. | tx_metadata_i[95:80] |
| tx_u_pc_id | 16 | Hookomo | PCID no ka halihali eCPRI a me RoEflowId no ka lekiō ma luna o ka ethernet (RoE). |
tx_metadata_i[79:64] |
| Mālama ʻia | 4 | Hookomo | Mālama ʻia. | tx_metadata_i[63:60] |
| tx_u_dataDirection | 1 | Hookomo | kuhikuhi ʻikepili gNB. Laulā waiwai: {0b=Rx (ʻo ia hoʻi ka hoʻouka ʻana), 1b=Tx (ʻo ia hoʻi ka hoʻoiho ʻana)} |
tx_metadata_i[59] |
| tx_u_filterIndex | 4 | Hookomo | Wehewehe i ka papa kuhikuhi i ke ala kānana e hoʻohana ʻia ma waena o ka ʻikepili IQ a me ke kikowaena ea. Laulā waiwai: {0000b-1111b} |
tx_metadata_i[58:55] |
| tx_u_frameId | 8 | Hookomo | He papa helu no 10 ms mau kiʻi (ka wā ʻōwili 2.56 kekona), kikoʻī frameId= frame number modulo 256. Laulā waiwai: {0000 0000b-1111 1111b} |
tx_metadata_i[54:47] |
| tx_u_subframeId | 4 | Hookomo | He counter no 1 ms subframes i loko o 10 ms frame. Laulā waiwai: {0000b-1111b} | tx_metadata_i[46:43] |
| tx_u_slotID | 6 | Hookomo | ʻO kēia ʻāpana ka helu slot i loko o kahi subframe 1 ms. Ua helu ʻia nā māka a pau i hoʻokahi subframe e kēia ʻāpana. Laulā waiwai: {00 0000b-00 1111b=slotID, 01 0000b-11 1111b=Mālama ʻia} |
tx_metadata_i[42:37] |
| tx_u_symbolid | 6 | Hookomo | Hoʻomaopopo i kahi helu hōʻailona i loko o kahi slot. Laulā waiwai: {00 0000b-11 1111b} | tx_metadata_i[36:31] |
| tx_u_sectionId | 12 | Hookomo | Mālama ka sectionID i nā ʻāpana ʻikepili U-plane i ka memo C-plane e pili ana (a me ka ʻano ʻāpana) pili me ka ʻikepili. Laulā waiwai: {0000 0000 0000b-11111111 1111b} |
tx_metadata_i[30:19] |
| tx_u_rb | 1 | Hookomo | Hōʻailona poloka waiwai. E hōʻike inā hoʻohana ʻia kēlā me kēia poloka kumuwaiwai a i ʻole nā polokalamu waiwai ʻē aʻe. Laulā waiwai: {0b=nā poloka kumu waiwai i hoʻohana ʻia; 1b=ʻo kēlā me kēia poloka kumu waiwai i hoʻohana ʻia} |
tx_metadata_i[18] |
| tx_u_startPrb | 10 | Hookomo | ʻO ka PRB hoʻomaka o kahi ʻikepili mokulele mea hoʻohana. Laulā waiwai: {00 0000 0000b-11 1111 1111b} |
tx_metadata_i[17:8] |
| tx_u_numPrb | 8 | Hookomo | E wehewehe i nā PRB kahi i kūpono ai ka pauku ʻikepili mokulele mea hoʻohana. | tx_metadata_i[7:0] |
| Laulā waiwai: {0000 0001b-1111 1111b, 0000 0000b = nā PRB a pau i loko o ka spacing subcarrier i koho ʻia (SCS) a me ka bandwidth lawe } | ||||
| tx_u_udCompHdr | 8 | Hookomo | E wehewehe i ke ʻano hoʻoemi a me ka laulā bit IQ o ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. Laulā waiwai: {0000 0000b-1111 1111b} | N/A (tx_udcomphdr_i) |
Papa 14. rx_metadata_valid_i/o
|
inoa hōʻailona |
Bitwidth | Kuhikuhi | wehewehe |
Palapala ʻikepili Metadata |
| rx_sec_hdr_valid | 1 | Hoʻopuka | Ke 1 ka rx_sec_hdr_valid, pono nā kahua ʻikepili ʻāpana U-plane. Pono nā IE poʻomanaʻo maʻamau i ka wā i ʻōlelo ʻia ai ka rx_sec_hdr_valid, i hui pū ʻia me avst_sink_u_startofpacket a me avst_sink_u_valid. Pono nā ʻāpana IE i hoʻopaʻa ʻia i ka wā i ʻōlelo ʻia ai ka rx_sec_hdr_valid, i hui pū ʻia me avst_sink_u_valid. Ma ka hāʻawi ʻana i nā māhele PRB hou ma avst_sink_u_data, e hāʻawi i nā IE ʻāpana hou me ka rx_sec_hdr_valid i ʻōlelo ʻia. |
rx_metadata_valid_o |
Papa 15. rx_metadata_o puka 128-bit
| inoa hōʻailona | Bitwidth | Kuhikuhi | wehewehe |
Palapala ʻikepili Metadata |
| Mālama ʻia | 32 | Hoʻopuka | Mālama ʻia. | rx_metadata_o[127:96] |
| rx_u_seq_id | 16 | Hoʻopuka | SeqID o ka ʻeke, i lawe ʻia mai ka poʻomanaʻo lawe eCPRI. | rx_metadata_o[95:80] |
| rx_u_pc_id | 16 | Hoʻopuka | PCID no ka lawe ʻana i ka eCPRI a me ka RoEflowId no ka lawe ʻana iā RoE | rx_metadata_o[79:64] |
| mālama ʻia | 4 | Hoʻopuka | Mālama ʻia. | rx_metadata_o[63:60] |
| rx_u_dataDirection | 1 | Hoʻopuka | kuhikuhi ʻikepili gNB. Laulā waiwai: {0b=Rx (ʻo ia hoʻi ka hoʻouka ʻana), 1b=Tx (ʻo ia hoʻi ka hoʻoiho ʻana)} | rx_metadata_o[59] |
| rx_u_filterIndex | 4 | Hoʻopuka | Wehewehe i ka papa kuhikuhi i ka kānana ala e hoʻohana ai ma waena o ka ʻikepili IQ a me ke kikowaena ea. Laulā waiwai: {0000b-1111b} |
rx_metadata_o[58:55] |
| rx_u_frameId | 8 | Hoʻopuka | He helu helu no 10 ms mau kiʻi (ka wā ʻōwili 2.56 kekona), ʻo ia hoʻi frameId= frame number modulo 256. Kaulana waiwai: {0000 0000b-1111 1111b} | rx_metadata_o[54:47] |
| rx_u_subframeId | 4 | Hoʻopuka | He papa helu no 1ms subframes i loko o 10 ms kiʻi. Laulā waiwai: {0000b-1111b} | rx_metadata_o[46:43] |
| rx_u_slotID | 6 | Hoʻopuka | ʻO ka helu slot i loko o kahi subframe 1ms. Ua helu ʻia nā māka a pau i hoʻokahi subframe e kēia ʻāpana. Laulā waiwai: {00 0000b-00 1111b=slotID, 01 0000b-111111b=Mālama ʻia} | rx_metadata_o[42:37] |
| rx_u_symbolid | 6 | Hoʻopuka | Hoʻomaopopo i kahi helu hōʻailona i loko o kahi slot. Laulā waiwai: {00 0000b-11 1111b} |
rx_metadata_o[36:31] |
| rx_u_sectionId | 12 | Hoʻopuka | Mālama ka sectionID i nā ʻāpana ʻikepili U-plane i ka memo C-plane e pili ana (a me ka ʻano ʻāpana) pili me ka ʻikepili. Laulā waiwai: {0000 0000 0000b-1111 1111 1111b} |
rx_metadata_o[30:19] |
| rx_u_rb | 1 | Hoʻopuka | Hōʻailona poloka waiwai. Hōʻike inā hoʻohana ʻia kēlā me kēia poloka waiwai a i ʻole hoʻohana ʻia nā kumuwaiwai ʻē aʻe. Laulā waiwai: {0b=nā poloka kumu waiwai i hoʻohana ʻia; 1b=ʻo kēlā me kēia poloka kumu waiwai i hoʻohana ʻia} |
rx_metadata_o[18] |
| rx_u_startPrb | 10 | Hoʻopuka | ʻO ka PRB hoʻomaka o kahi ʻikepili mokulele mea hoʻohana. Laulā waiwai: {00 0000 0000b-11 1111 1111b} |
rx_metadata_o[17:8] |
| rx_u_numPrb | 8 | Hoʻopuka | Wehewehe i nā PRB kahi i kūpono ai ka pauku ʻikepili mokulele mea hoʻohana. Laulā waiwai: {0000 0001b-1111 1111b, 0000 0000b = nā PRB a pau i ka SCS i kuhikuhi ʻia a me ka bandwidth lawe } |
rx_metadata_o[7:0] |
| rx_u_udCompHdr | 8 | Hoʻopuka | Ho'ākāka i ke ʻano hoʻoemi a me ka laulā bit IQ o ka ʻikepili mea hoʻohana ma kahi ʻāpana ʻikepili. Laulā waiwai: {0000 0000b-1111 1111b} |
N/A (rx_udcomphdr_o) |
Nā hōʻailona Interface CSR
Papa 16. Nā hōʻailona Interface CSR
| inoa hōʻailona | Bit Laulā | Kuhikuhi |
wehewehe |
| csr_address | 16 | Hookomo | Helu helu helu hoʻonohonoho. |
| csr_write | 1 | Hookomo | Hiki ke kākau inoa hoʻonohonoho. |
| csr_writedata | 32 | Hookomo | ʻIkepili kākau kākau hoʻonohonoho. |
| csr_readdata | 32 | Hoʻopuka | Ka helu helu helu helu helu. |
| csr_heluhelu | 1 | Hookomo | Hiki ke heluhelu i ka palapala hoʻonohonoho. |
| csr_readdatavalid | 1 | Hoʻopuka | Pono ka helu helu helu helu helu. |
| csr_waitrequest | 1 | Hoʻopuka | Noi kali ka palapala hoʻonohonoho. |
Nā papa inoa IP Compression Fronthaul
E hoʻomalu a nānā i ka hana hoʻopiʻi fronthaul ma o ka mana a me ke kūlana kūlana.
Papa 17. Palapala Palapala
| CSR_ADDRESS (Hoʻopau Huaʻōlelo) | Kainoa inoa |
| 0x0 | ʻano_compression_mode |
| 0x1 | tx_hewa |
| 0x2 | rx_hewa |
Papa 18. compression_mode kakau inoa
| Bit Laulā | wehewehe | Komo |
HW Reset Value |
| 31:9 | Mālama ʻia | RO | 0x0 |
| 8:8 | ʻAno hana: • ʻO 1'b0 ke ʻano hoʻoemi paʻa • ʻO 1'b1 ke ʻano hoʻoemi ikaika |
RW | 0x0 |
| 7:0 | Poʻomanaʻo hoʻoemi ʻikepili mea hoʻohana static: • 7:4 ka udIqWidth — 4'b0000 he 16 mau bits — 4'b1111 he 15 mau bits -: — 4'b0001 he 1 bit • 3:0 ka udCompMeth — 4'b0000 ʻaʻole hoʻopaʻa — 4'b0001 kahi poloka lana — 4'b0011 he µ-law • Ua mālama ʻia nā mea ʻē aʻe |
RW | 0x0 |
Papa 19. tx Kakau Hapa
| Bit Laulā | wehewehe | Komo |
HW Reset Value |
| 31:2 | Mālama ʻia | RO | 0x0 |
| 1:1 | Helu IqWidth. Hoʻonohonoho ka IP i ka Iqwidth i ka 0 (16-bit Iqwidth) inā ʻike ia i ka Iqwidth kūpono ʻole a kākoʻo ʻole ʻia. | RW1C | 0x0 |
| 0:0 | ʻAʻole kūpono ke ʻano hoʻoemi. Hoʻokuʻu ka IP i ka ʻeke. | RW1C | 0x0 |
Papa 20. rx Kakau Hapa
| Bit Laulā | wehewehe | Komo |
HW Reset Value |
| 31:8 | Mālama ʻia | RO | 0x0 |
| 1:1 | Helu IqWidth. Hoʻokuʻu ka IP i ka ʻeke. | RW1C | 0x0 |
| 0:0 | ʻAʻole kūpono ke ʻano hoʻoemi. Hoʻonohonoho ka IP i ke ʻano hoʻoemi i ke ʻano paʻamau i kākoʻo ʻia: • Ua hoʻohana ʻia ke kiko palaka-lele wale nō: paʻamau i ka wahi poloka-lele. • Hoʻohana ʻia ka μ-law wale nō: paʻamau i ka μ-law. • Ua hoʻohana ʻia ke kiko palaka-floating a me ka μ-law: paʻamau i ke kiko lana-pale. |
RW1C | 0x0 |
Fronthaul Compression Intel FPGA IPs Guide Guide Archive
No nā mana hou loa o kēia palapala, e nānā i: Fronthaul Compression Intel FPGA IP User Guide. Inā ʻaʻole i helu ʻia kahi IP a i ʻole ka mana lako polokalamu, pili ke alakaʻi mea hoʻohana no ka IP mua a i ʻole ka mana polokalamu.
Moʻolelo Hoʻoponopono Hou no ka Fronthaul Compression Intel FPGA IP Guide Guide
|
Palapala Palapala |
ʻO Intel Quartus Prime Version | Manaʻo IP |
Nā hoʻololi |
| 2022.08.08 | 21.4 | 1.0.1 | Hoʻoponopono ʻia ka laulā metadata 0 a i 0 (Hoʻopaʻa i nā awa metadata). |
| 2022.03.22 | 21.4 | 1.0.1 | • Nā wehewehe hōʻailona hoʻololi: — tx_avst_sink_data a me tx_avst_source_data — rx_avst_sink_data a me rx_avst_source_data • Hoʻohui ʻia Kākoʻo ʻia nā māka māmā papaʻaina • Hoʻohui ʻia Hana a me ka hoʻohana waiwai |
| 2021.12.07 | 21.3 | 1.0.0 | Hoʻololi ʻia ke code kauoha. |
| 2021.11.23 | 21.3 | 1.0.0 | Hoʻokuʻu mua. |
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
Online Version
Hoʻouna Manaʻo
ID: 709301
UG-20346
Manaʻo: 2022.08.08
ISO 9001:2015 Kakau
Palapala / Punawai
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intel Fronthaul Compression FPGA IP [pdf] Ke alakaʻi hoʻohana Fronthaul Compression FPGA IP, Fronthaul, Compression FPGA IP, FPGA IP |
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intel Fronthaul Compression FPGA IP [pdf] Ke alakaʻi hoʻohana UG-20346, 709301. |
