Interlaken (2 Generation) Intel ®
ʻAgilex™ FPGA IP Design Example
Ke alakaʻi hoʻohana

Alakaʻi hoʻomaka wikiwiki

Hāʻawi ka Interlaken (2nd Generation) FPGA IP core i kahi hōʻike hōʻike simulation a me kahi hoʻolālā ʻenehana example e kākoʻo ana i ka hoʻopili ʻana a me ka hoʻāʻo ʻana i nā lako. Ke hana ʻoe i ka hoʻolālā example, hana 'akomi ka mea hooponopono parameter i ka files pono e simulate, hōʻuluʻulu, a ho'āʻo i ka hoʻolālā i ka lako. ʻO ka hoʻolālā exampLoaʻa ka le no ka hiʻohiʻona Interlaken Look-aside.
ʻO ka papa hōʻike a me ka hoʻolālā exampKākoʻo ʻo ia i ke ʻano NRZ a me PAM4 no nā polokalamu E-tile. Hoʻokumu ka Interlaken (2nd Generation) FPGA IP core i ka hoʻolālā examples no nā hui kākoʻo ʻia o ka helu o nā alahele a me nā helu ʻikepili.

Kiʻi 1. Nā ʻanuʻu hoʻomohala no ka Design Example

ʻO ka Interlaken (2nd Generation) IP core design exampLe kākoʻo i kēia mau hiʻohiʻona:

• Kūloko TX i RX mode loopback
• Hoʻopuka 'akomi i nā ʻeke nui paʻa
• Nā mea hiki ke hoʻopaʻa packet maʻamau
• Hiki ke hoʻohana i ka System Console e hoʻonohonoho hou i ka hoʻolālā no ka hoʻāʻo hou ʻana
• PMA hoʻololi

Kiʻi 2. Kiʻekiʻe-level Block Diagram no Interlaken (2nd Generation) Design Example

ʻIke pili

• Interlaken (2nd Generation) FPGA IP alakaʻi hoʻohana
• Interlaken (2nd Generation) Intel FPGA IP Release Notes

1.1. Pono nā lako lako a me nā lako polokalamu
E ho'āʻo i ka exampe hoʻolālā, e hoʻohana i ka lako a me ka lako polokalamu:

• Manao polokalamu polokalamu Intel® Prime Pro Edition 21.3
• Pūnaehana Console
• Nā simulators i kākoʻo ʻia:
  — Siemens* EDA ModelSim* SE a i ole QuestaSim*
  — Nā huaʻōlelo * VCS *
  — Kaʻiʻo * Xcelium *
• Intel Agilex® Quartus™ F-Series Transceiver-SoC Development Kit (AGFB014R24A2E2V)

ʻIke pili
Intel Agilex F-Series Transceiver-SoC Development Kit Ke alakaʻi hoʻohana
1.2. Papa kuhikuhi
ʻO ka Interlaken (2nd Generation) IP core design example file Aia nā papa kuhikuhi i nā mea i hana ʻia files no ka hoʻolālā example.
Kiʻi 3. Hoʻonohonoho Papa kuhikuhi o ka Generated Interlaken (2nd Generation) Example Hoʻolālā

ʻO ka hoʻonohonoho paʻa, simulation, a me ka hoʻāʻo files aia maample_installation_dir>/uflex_ilk_0_example_design.
Papa 1. Interlaken (2nd Generation) IP Core Hardware Design Example File Nā wehewehe
ʻO kēia mau mea files aia i loko o kaample_installation_dir>/uflex_ilk_0_example_design/ examppapa kuhikuhi le_design/quartus.

File Na inoa	wehewehe
example_design.qpf	Papahana Intel Quartus Prime file.
example_design.qsf	Nā hoʻonohonoho papahana Intel Quartus Prime file
example_design.sdc jtag_timing_template.sdc	Synopsys Design Constraint file. Hiki iā ʻoe ke kope a hoʻololi no kāu hoʻolālā ponoʻī.
sysconsole_testbench.tcl	Nui file no ke komo ʻana i ka System Console

Papa 2. Interlaken (2nd Generation) IP Core Testbench File wehewehe
ʻO kēia file aia ma kaample_installation_dir>/uflex_ilk_0_example_design/ examppapa kuhikuhi le_design/rtl.

File inoa	wehewehe
top_tb.sv	pae hoʻāʻo pae kiʻekiʻe file.

Papa 3. nterlaken (2nd Generation) IP Core Testbench Scripts
ʻO kēia mau mea files aia i loko o kaample_installation_dir>/uflex_ilk_0_example_design/ examppapa kuhikuhi le_design/testbench.

File inoa	wehewehe
vcstest.sh	ʻO ka palapala VCS e holo i ka papa hōʻike.
vlog_pro.do	ʻO ka ModelSim SE a i ʻole QuestaSim script e holo i ka papa hōʻike.
xcelium.sh	ʻO ka palapala Xcelium e holo i ka papa hōʻike.

1.3. Hoʻolālā Lako Paʻa Example Nā ʻāpana
ʻO ka exampHoʻopili ka hoʻolālā i ka ʻōnaehana a me nā wati kuhikuhi PLL a me nā mea hoʻolālā e pono ai. ʻO ka exampHoʻonohonoho ka hoʻolālā i ka IP core i loko o ke ʻano loopback kūloko a hoʻopuka i nā ʻeke ma ka IP core TX mea hoʻohana hoʻoili data hoʻololi. Hoʻouna ka IP core i kēia mau ʻeke ma ke ala loopback kūloko ma o ka transceiver.
Ma hope o ka loaʻa ʻana o ka mea hoʻokipa IP core i nā ʻeke ma ke ala loopback, hana ia i nā ʻeke Interlaken a hoʻouna iā lākou ma ke kikowaena hoʻoili data hoʻohana RX. ʻO ka exampʻO ka nānā ʻana o ka hoʻolālā i ka loaʻa ʻana o nā ʻeke a hoʻouna ʻia.
ʻO ka lako lako exampAia ka hoʻolālā i nā PLL waho. Hiki iā ʻoe ke nānā i ka kikokikona maopopo files i view sampka code e hoʻokō i kahi ala hiki ke hoʻopili i nā PLL waho i ka Interlaken (2nd Generation) FPGA IP.
ʻO ka hoʻolālā ʻenehana Interlaken (2nd Generation) example e komo i keia mau mea.

1. Interlaken (2nd Generation) FPGA IP
2. Packet Generator a me Packet Checker
3. JTAG mea hoʻoponopono e kamaʻilio me System Console. Ke kamaʻilio nei ʻoe me ka loiloi mea kūʻai aku ma o ka System Console.

Kiʻi 4. Interlaken (2nd Generation) Design Hardware Example Kiʻekiʻe Kiʻekiʻe Block Block no ka E-tile NRZ Mode Variations

ʻO ka hoʻolālā ʻenehana Interlaken (2nd Generation) exampʻO ka mea e kuhikuhi ana i nā ʻano hoʻololi ʻano E-tile PAM4 e pono ai i kahi mac_clkin hou aʻe i hana ʻia e ka IO PLL. Pono kēia PLL e hoʻohana i ka uaki kuhikuhi e hoʻokele i ka pll_ref_clk.

Kiʻi 5. Interlaken (2nd Generation) Design Hardware Example Papa Kiekie
Palekana no ka E-tile PAM4 Nā ʻano ʻano like ʻole

No nā ʻano hoʻololi E-tile PAM4, ke hiki iā ʻoe ke mālama i nā ala transceiver i hoʻohana ʻole ʻia no PAM4 parameter, ua hoʻohui ʻia kahi uaki kuhikuhi hou (pll_ref_clk [1]). Pono e hoʻokele ʻia kēia awa ma ka alapine like e like me ka wehewehe ʻana i ka mea hoʻoponopono IP parameter (Reference clock frequency no nā kahawai mālama ʻia). ʻO ka mālama ʻana i nā ala transceiver i hoʻohana ʻole ʻia no PAM4 he koho. ʻIke ʻia ka pine a me nā kaohi pili i hāʻawi ʻia i kēia uaki ma ka QSF ke koho ʻoe iā Intel Stratix® 10 a i ʻole Intel Agilex development kit no ka hana hoʻolālā.
No ka hoʻolālā exampʻO ka simulation, wehewehe mau ka testbench i ke alapine like no pll_ref_clk[0] a me pll_ref_clk[1].
ʻIke pili
Intel Agilex F-Series Transceiver-SoC Development Kit Ke alakaʻi hoʻohana
1.4. Hana i ka Hoʻolālā

Kiʻi 6. Kaʻina hana

E hahai i kēia mau ʻanuʻu no ka hoʻopuka ʻana i ka ʻenehana exampka hoʻolālā a me ka papa hōʻike:

1. Ma ka polokalamu Intel Quartus Prime Pro Edition, kaomi File ➤ New Project Wizard e hana i kahi papahana Intel Quartus Prime hou, a i ʻole kaomi File ➤ Open Project e wehe i kahi papahana Intel Quartus Prime. Koi ka wizard iā ʻoe e kuhikuhi i kahi mea hana.
2. E wehewehe i ka ʻohana ʻohana ʻo Agilex a koho i ka hāmeʻa no kāu hoʻolālā.
3. Ma ka IP Catalog, e huli a kaomi pālua Interlaken (2nd Generation) Intel FPGA IP. Hōʻike ʻia ka puka aniani IP Variant hou.
4. E wehewehe i kahi inoa kiʻekiʻe no kāu hoʻololi IP maʻamau. Mālama ka mea hoʻoponopono hoʻoponopono i nā hoʻonohonoho hoʻololi IP ma kahi file inoa ʻia .ip.
5. Kaomi OK. Hōʻike ʻia ka mea hoʻoponopono hoʻohālikelike.
   Kiʻi 7. Example Design Tab i ka Interlaken (2nd Generation) Intel FPGA IP Parameter Lunahooponopono
6. Ma ka ʻaoʻao IP, e kuhikuhi i nā ʻāpana no kāu hoʻololi kumu IP.
7. Ma ka ʻaoʻao PMA Adaptation, e kuhikuhi i nā ʻāpana hoʻololi PMA inā hoʻolālā ʻoe e hoʻohana i ka hoʻololi PMA no kāu mau ʻokoʻa E-tile.
   He koho kēia ʻanuʻu:
   • E koho Enable adaptation load soft IP koho.
   'Ōlelo Aʻo: Pono ʻoe e hoʻā i ke koho ʻana i ka Native PHY Debug Master Endpoint (NPDME) ma ka pā IP ke hiki ke hoʻololi ʻia ka PMA.
   • E koho i kahi hoʻonohonoho hoʻololi PMA no ka hoʻololi ʻana PMA E koho i ka ʻāpana.
   • Kaomi i ka PMA Adaptation Preload no ka hoʻouka ʻana i nā ʻāpana hoʻololi mua a hoʻomau.
   • E wehewehe i ka helu o nā hoʻonohonoho PMA e kākoʻo inā hoʻohana ʻia nā hoʻonohonoho PMA lehulehu me ka hoʻohana ʻana i ka helu o ka hoʻonohonoho hoʻonohonoho PMA.
   • E koho i ka hoʻonohonoho PMA e hoʻouka a mālama ʻia me ka hoʻohana ʻana E koho i kahi hoʻonohonoho PMA e hoʻouka a mālama paha.
   • Kaomi Load adaptation mai ka hoʻonohonoho PMA i koho ʻia e hoʻouka i nā hoʻonohonoho hoʻonohonoho PMA i koho ʻia.
   No ka 'ike hou aku e pili ana i ka PMA adaptation parameter, e nānā i ka E-tile Transceiver PHY User Guide.
8. Ma ka Example Design tab, koho i ke koho Simulation e hoʻohua i ka papa hoʻāʻo, a koho i ke koho Synthesis e hoʻohua i ka ʻenehana examphoʻolālā.
   Nānā: Pono ʻoe e koho i hoʻokahi o nā koho Simulation a i ʻole Synthesis e hoʻopuka i ka Example Hoʻolālā Files.
9. No ka Hōʻailona HDL i hana ʻia, ʻo Verilog wale nō ka mea i loaʻa.
10. No ka Target Development Kit e koho i ke koho kūpono.
    'Ōlelo Aʻo: Loaʻa wale ke koho Intel Agilex F-Series Transceiver SoC Development Kit i ka wā e kuhikuhi ai kāu papahana i ka inoa mea hana Intel Agilex e hoʻomaka ana me AGFA012 a i ʻole AGFA014. Ke koho ʻoe i ke koho Development Kit, ua hoʻonohonoho ʻia nā hana pine e like me ka helu ʻāpana ʻāpana Intel Agilex Development Kit AGFB014R24A2E2V a ʻokoʻa paha mai kāu hāmeʻa i koho ʻia. Inā manaʻo ʻoe e hoʻāʻo i ka hoʻolālā ʻana ma kahi PCB ʻē aʻe, koho ʻAʻole koho kit hoʻomohala a hana i nā kuhikuhi pine kūpono i ka .qsf file.
11. Kaomi Generate Example Hoʻolālā. ʻO ke koho Example Design Directory puka makani.
12. Inā makemake ʻoe e hoʻololi i ka hoʻolālā exampke ala papa kuhikuhi a i ʻole ka inoa mai nā kuhi hewa i hōʻike ʻia (uflex_ilk_0_example_design), e nānā i ke ala hou a paʻi i ka ex design houample inoa papa kuhikuhi.
13. Kaomi OK.

ʻIke pili

• Intel Agilex F-Series Transceiver-SoC Development Kit Ke alakaʻi hoʻohana
• E-tile Transceiver PHY alakaʻi hoʻohana

1.5. Hoʻohālike i ka Hoʻolālā Example Hōʻikeʻike
E nānā iā Interlaken (2nd Generation) Hardware Design Example Palena Kiʻekiʻe no ka E-tile NRZ Mode Variations a Interlaken (2nd Generation) Hardware Design Example Palena kiʻekiʻe no ka E-tile PAM4 Mode Variations block diagrams o ka simulation testbench.

Kiʻi 8. Kaʻina hana

E hahai i kēia mau ʻanuʻu e hoʻohālike i ka papa hoʻokolohua:

1. Ma ke kauoha kauoha, e hoʻololi i ka papa kuhikuhi simulation testbench. ʻO ka papa kuhikuhiample_installation_dir>/example_design/ testbench no nā polokalamu Intel Agilex.
2. E holo i ka palapala simulation no ka simulator kākoʻo o kāu koho. Hoʻopili ka ʻatikala a holo i ka papa hōʻike ma ka simulator. Pono kāu palapala e nānā i ka helu SOP a me EOP ma hope o ka pau ʻana o ka simulation. E nānā i ka papaʻaina Nā ʻanuʻu e holo i ka Simulation.
   Papa 4. Nā ʻanuʻu e holo i ka Simulation

   Mea hoʻomeamea	Nā kuhikuhi
   ModelSim SE a i ʻole QuestaSim	Ma ka laina kauoha, e kikokiko -do vlog_pro.do. Inā makemake ʻoe e hoʻohālikelike me ka lawe ʻole ʻana i ka ModelSim GUI, e ʻano vsim -c -do vlog_pro.do
   VCS	Ma ka laina kauoha, e kikokiko sh vcstest.sh
   Xcelium	Ma ka laina kauoha, e kikokiko sh xcelium.sh

3. E noʻonoʻo i nā hopena. Hoʻouna a loaʻa mai kahi simulation kūleʻa i nā ʻeke, a hōʻike iā "Test PASSED".

ʻO ka papa hōʻike no ka hoʻolālā example hoopau i keia mau hana:

• Hoʻomaka koke i ka Interlaken (2nd Generation) Intel FPGA IP.
• Paʻi i ke kūlana PHY.
• Nānā i ka hoʻonohonoho hoʻonohonoho metaframe (SYNC_LOCK) a me nā palena huaʻōlelo (block) (WORD_LOCK).
• E kali no ka laka ʻana a hoʻopaʻa ʻia nā alahele pākahi.
• Hoʻomaka ka hoʻouna ʻana i nā ʻeke.
• Ke nānā nei i nā helu ʻikepili:
  — Nā hewa CRC24
  — SOPs
  — EOPs

sampHōʻike ka leo i ka holo ʻana o ka hoʻāʻo simulation kūleʻa ma ke ʻano Interlaken:
*****************************************
INFO: Ke kali nei no ka hoʻolikelike ʻana o nā ala.
Hoʻopili ʻia nā ala hoʻokipa āpau a mākaukau no ka loaʻa ʻana o ke kaʻa.
*************************************************
*************************************************
INFO: E hoʻomaka i ka hoʻouna ʻana i nā ʻeke
*************************************************
*************************************************
INFO: Hooki i ka hoʻouna ʻana i nā ʻeke
*************************************************
*************************************************
INFO: Ke nānā ʻana i nā ʻikepili helu
*************************************************
Ua hōʻike ʻia nā hewa CRC 24: 0
Nā SOP i hoʻouna ʻia: 100
Nā EOP i hoʻouna ʻia: 100
Loaʻa nā SOP: 100
Loaʻa nā EOP: 100
Helu hewa ECC: 0
*************************************************
INFO: HALA ka hoao
*************************************************
Nānā: ʻO ka hoʻolālā Interlaken exampHoʻouna ʻo le simulation testbench i 100 mau ʻeke a loaʻa iā 100 mau ʻeke.
sampHōʻike ka hoʻopuka i ka holo ʻana o ka hoʻāʻo simulation kūleʻa ma Interlaken Look-aside mode:
E nānā iā TX a me RX Counter i like a i ʻole.
———————————————————-
READ_MM: helu wahi 4000014 = 00000001.
———————————————————-
Wehe i ka helu helu like.
———————————————————-
WRITE_MM: loaʻa ka helu helu 4000001 00000001.
WRITE_MM: loaʻa ka helu helu 4000001 00000000.
———————————————————-
RX_SOP COUNTER.
———————————————————-
READ_MM: helu helu 400000c = 0000006a.
———————————————————-
RX_EOP COUNTER.
READ_MM: helu wahi 400000d = 0000006a.
———————————————————-
READ_MM: helu wahi 4000010 = 00000000.
———————————————————-
Hōʻike Hōʻike Hope.
———————————————————-
0 Ua ʻike ʻia ka hewa
0 Ua hōʻike ʻia nā hewa CRC24
106 SOP i hoʻouna ʻia
106 EOP i hoʻouna ʻia
106 SOP i loaa
106 EOP i loaʻa
———————————————————-
Hoʻopau hoʻohālikelike
———————————————————-
UA HALA
———————————————————-
Nānā: ʻOkoʻa ka helu o nā ʻeke (SOP a me EOP) i kēlā me kēia ala ma Interlaken Lookaside design example simulation sample pukana.
ʻIke pili
Hoʻolālā Lako Paʻa Exampnā ʻāpana ma ka ʻaoʻao 6
1.6. Hoʻopili a hoʻonohonoho i ka Design Example ma Lako

Kiʻi 9. Kaʻina hana

No ka hōʻuluʻulu ʻana a me ka holo ʻana i kahi hōʻike hōʻike ma ka ʻenehana exampka hoʻolālā, e hahai i kēia mau ʻanuʻu:

1. E hōʻoia i ka lako kamepiula exampua pau ka hana hoʻolālā.
2. Ma ka polokalamu Intel Quartus Prime Pro Edition, wehe i ka papahana Intel Quartus Primeample_installation_dir>/example_design/quartus/ example_design.qpf>.
3. Ma ka papa kuhikuhi Processing, kaomi i ka Start Compilation.
4. Ma hope o ka hōʻuluʻulu kūleʻa, a .sof file loaʻa ma kāu papa kuhikuhi i kuhikuhi ʻia.
   E hahai i kēia mau ʻanuʻu e hoʻolālā i ka ʻenehana exampka hoʻolālā ma ka polokalamu Intel Agilex:
5. Hoʻohui i ka Intel Agilex F-Series Transceiver-SoC Development Kit i ke kamepiula hoʻokipa.
   b. E hoʻokuʻu i ka noi Clock Control, kahi ʻāpana o ka pahu hoʻomohala, a hoʻonohonoho i nā alapine hou no ka hoʻolālā example. Aia ma lalo iho ka hoʻonohonoho alapine ma ka noi Clock Control:
   • Si5338 (U37), CLK1- 100 MHz
   • Si5338 (U36), CLK2- 153.6 MHz
   • Si549 (Y2), OUT- Hoʻonoho i ka waiwai o pll_ref_clk (1) no kāu koi hoʻolālā.
   c. Ma ka papa kuhikuhi Tools, kaomi Programmer.
   d. I ka Programmer, kaomi Hardware Setup.
   e. E koho i kahi lako polokalamu.
   f. E koho a hoʻohui i ka Intel Agilex F-Series Transceiver-SoC Development Kit kahi e hiki ai i kāu hui Intel Quartus Prime ke hoʻohui.
   g. E hōʻoia ua hoʻonohonoho ʻia ke ʻano iā JTAG.
   h. E koho i ka polokalamu Intel Agilex a kaomi i ka Add Device. Hōʻike ka Programmer i kahi kiʻi poloka o nā pilina ma waena o nā mea hana ma kāu papa.
   i. Ma ka lālani me kāu .sof, e nānā i ka pahu no ka .sof.
   j. E nānā i ka pahu ma ke kolamu Program/Configure.
   k. Kaomi hoʻomaka.

ʻIke pili

• Hoʻopololei i nā mea hana Intel FPGA ma ka aoao 0
• Ka nānā 'ana a me ka Debugging Design me ka System Console
• Intel Agilex F-Series Transceiver-SoC Development Kit Ke alakaʻi hoʻohana

1.7. Ke ho'āʻo nei i ka Hoʻolālā Lako Paʻa Example
Ma hope o kou hōʻuluʻulu ʻana i ka Interlaken (2nd Generation) Intel FPGA IP core design exampa hoʻonohonoho i kāu hāmeʻa, hiki iā ʻoe ke hoʻohana i ka System Console e hoʻolālā i ka IP core a me kāna mau papa inoa koʻikoʻi PHY IP i hoʻokomo ʻia.
E hahai i kēia mau ʻanuʻu no ka lawe ʻana i ka System Console a hoʻāʻo i ka hoʻolālā ʻenehana example:

1. Ma ka polokalamu Intel Quartus Prime Pro Edition, ma ka papa kuhikuhi Tools, kaomi System Debugging Tools ➤ System Console.
2. E hoʻololi i kaample_installation_dir>example_design/ hwtest papa kuhikuhi.
3. No ka wehe ʻana i kahi pilina i ka JTAG haku, e kikokiko i keia kauoha: source sysconsole_testbench.tcl
4. Hiki iā ʻoe ke hoʻohuli i ke ʻano hana loopback serial me ke ʻano hoʻolālā e hiki mai anaample kauoha:
   a. stat: Paʻi i ka ʻike kūlana maʻamau.
   b. sys_reset: Hoʻoponopono hou i ka ʻōnaehana.
   c. loop_on: Huli i ka loopback serial kūloko.
   d. run_example_design: Holo i ka hoʻolālā example.
   'Ōlelo Aʻo: Pono ʻoe e holo i ke kauoha loop_on ma mua o ka run_exampkauoha le_design.
   ʻO ka run_exampholo ʻo le_design i kēia mau kauoha ma kahi ʻano:
   sys_reset->stat->gen_on->stat->gen_off.
   Nānā: Ke koho ʻoe i ka koho Enable adaptation load soft IP, ka run_exampʻO ke kauoha le_design e hana i ka calibration hoʻololi mua ma ka ʻaoʻao RX ma ka holo ʻana i ke kauoha run_load_PMA_configuration.
5. Hiki iā ʻoe ke hoʻopau i ka mode loopback serial me ka hoʻolālā hoʻolālā e hiki mai anaample kauoha:
   a. loop_off: Hoʻopau i ka loopback serial kūloko.
6. Hiki iā ʻoe ke hoʻolālā i ka IP core me ka hoʻolālā hoʻolālā hou aʻeample kauoha:
   a. gen_on: Ho'ā i ka mea hana packet.
   b. gen_off: Hoʻopaʻa i ka mea hana pūʻolo.
   c. run_test_loop: Holo i ka ho'āʻo no manawa no ka E-tile NRZ a me PAM4 hoʻololi.
   d. clear_err: Holoi i nā ʻāpana kuhi hewa a pau.
   e. hoʻonohonoho_hōʻoia : Hoʻonohonoho i ka hoʻāʻo e holo ma kahi ʻano kikoʻī.
   f. get_test_mode: Paʻi i ke ʻano hoʻāʻo o kēia manawa.
   g. set_burst_size : Hoʻonohonoho i ka nui pohā ma nā paita.
   h. get_burst_size: Paʻi i ka ʻike nui o ka pohā.

Paʻi ka hoʻāʻo kūleʻa i ka HW_TEST:PASS memo. Aia ma lalo iho nā pae hoʻoholo no ka holo hoʻāʻo:

• ʻAʻohe hewa no CRC32, CRC24, a me ka mea nānā.
• Pono nā SOP i hoʻouna ʻia a me nā EOP e kūlike me ka loaʻa.

sampHōʻike ka hoʻopuka i kahi holo hoʻāʻo kūleʻa ma ke ʻano Interlaken:
INFO: INFO: E hooki i ka hana ʻana i nā ʻeke
==== HOIKE KULA ====
TX KHz : 402813
RX KHz : 402813
Laka pinepine: 0x0000ff
TX PLL laka : 0x000001
Hoʻopololei: 0x00c10f
Rx LOA : 0x000000
Tx LOA : 0x000000
laka huaʻōlelo : 0x0000ff
laka sync : 0x0000ff
Nā hewa CRC32: 0
Nā hewa CRC24: 0
Nā kuhi hewa: 0
Nā hae hewa FIFO : 0x000000
Hoʻouna ʻia nā SOP: 1087913770
Hoʻouna ʻia nā EOP: 1087913770
Loaʻa nā SOP: 1087913770
Loaʻa nā EOP: 1087913770
Hoʻoponopono ʻia ʻo ECC: 0
Hewa ECC: 0
Ua hala he 161 kekona mai ka hoʻonui ʻana
HW_TEST : HALA
Paʻi ka hoʻāʻo kūleʻa i ka HW_TEST : memo PASS. Aia ma lalo iho nā pae hoʻoholo no ka holo hoʻāʻo:

• ʻAʻohe hewa no CRC32, CRC24, a me ka mea nānā.
• Pono nā SOP i hoʻouna ʻia a me nā EOP e kūlike me ka loaʻa.

sampHōʻike ka hoʻopuka i kahi holo hoʻāʻo kūleʻa ma Interlaken Lookaside mode:
INFO: INFO: E hooki i ka hana ʻana i nā ʻeke
==== HOIKE KULA ====
TX KHz : 402813
RX KHz : 402812
Laka pinepine: 0x000fff
TX PLL laka : 0x000001
Hoʻopololei: 0x00c10f
Rx LOA : 0x000000
Tx LOA : 0x000000
laka huaʻōlelo : 0x000fff
laka sync : 0x000fff
Nā hewa CRC32: 0
Nā hewa CRC24: 0
Nā kuhi hewa: 0
Hoʻouna ʻia nā SOP: 461
Hoʻouna ʻia nā EOP: 461
Loaʻa nā SOP: 461
Loaʻa nā EOP: 461
Ua hala he 171 kekona mai ka hoʻonui ʻana
HW_TEST : HALA

Hoʻolālā Example Wehewehe

ʻO ka hoʻolālā example hōʻike i nā hana o ka Interlaken IP core.
ʻIke pili
Interlaken (2nd Generation) FPGA IP alakaʻi hoʻohana
2.1. Hoʻolālā Example Kaulike
No ka hoʻāʻo ʻana i ka hoʻolālā ʻana i ka hāmeʻa, e kākau i kēia mau kauoha i ka System Console::

1. Kumu i ka hoʻonohonoho file:
   % kumuample>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
2. Holo i ka ho'āʻo:
   % run_example_design
3. ʻO ka hoʻolālā ʻenehana Interlaken (2nd Generation) example hoʻopau i kēia mau ʻanuʻu:
   a. Hoʻoponopono hou i ka Interlaken (2nd Generation) IP.
   b. Hoʻonohonoho i ka IP Interlaken (2nd Generation) ma ke ʻano loopback kūloko.
   c. Hoʻouna i kahi kahawai o nā ʻeke Interlaken me nā ʻikepili i koho mua ʻia i ka uku i ka TX mea hoʻohana hoʻoili ʻikepili hoʻololi o ka IP core.
   d. Nānā i nā ʻeke i loaʻa a hōʻike i ke kūlana. Hoʻokomo ʻia ka mea nānā packet i loko o ka hoʻolālā ʻenehana exampHāʻawi ʻo le i nā mea hiki ke nānā i ka ʻeke maʻamau:
   • Nānā i ka pololei o ke kaʻina o ka ʻeke i hoʻouna ʻia.
   • Nānā i ka ʻikepili i loaʻa e kūlike me nā waiwai i manaʻo ʻia ma ka hōʻoia ʻana i ka helu ʻana o ka helu hoʻomaka o ka ʻeke (SOP) a me ka helu hope o ka ʻeke (EOP) i ka wā e hoʻouna ʻia ana a loaʻa mai.

2.2. Nā hōʻailona Interface
Papa 5. Hoʻolālā Example Nā hōʻailona Interface

inoa awa	Kuhikuhi	Laulā (Bits)	wehewehe
mgmt_clk	Hookomo	1	Hoʻokomo uaki ʻōnaehana. ʻO ka pinepine o ka uaki he 100 MHz.
pll_ref_clk /pll_ref_clk[1:0] (2)	Hookomo	2-Ian	Uaki kuhikuhi Transceiver. Hoʻokele i ka RX CDR PLL.

inoa awa	Kuhikuhi	Laulā (Bits)	wehewehe
			Aia ka pll_ref_clk[1] ke hiki iā ʻoe E mālama pono ʻole Nānā: nā kaha transceiver no PAM4 ka palena ma ka E-tile PAM4 mode IP hoʻololi.
rx_pin	Hookomo	Ka helu o nā alahele	Mea loaʻa SERDES pine data.
tx_pin	Hoʻopuka	Ka helu o nā alahele	Hoʻouna i ka pine data SERDES.
rx_pin_n	Hookomo	Ka helu o nā alahele	Mea loaʻa SERDES pine data. Loaʻa kēia hōʻailona ma nā ʻano like ʻole o ka hāmeʻa E-tile PAM4.
tx_pin_n	Hoʻopuka	Ka helu o nā alahele	Hoʻouna i ka pine data SERDES. Loaʻa kēia hōʻailona ma nā ʻano like ʻole o ka hāmeʻa E-tile PAM4.
mac_clk_pll_ref	Hookomo	1	Pono e alakaʻi ʻia kēia hōʻailona e kahi PLL a pono e hoʻohana i ke kumu wati like e hoʻokele i ka pll_ref_clk. Loaʻa kēia hōʻailona ma nā ʻano like ʻole o ka hāmeʻa E-tile PAM4.
usr_pb_reset_n	Hookomo	1	Kau hoʻonohonoho ʻikepili.

ʻIke pili
Nā hōʻailona Interface
2.3. Palapala Palapala
Nānā:

• Hoʻolālā ExampHoʻomaka ka helu helu inoa me 0x20** ʻoiai hoʻomaka ka helu inoa inoa Interlaken IP core me 0x10**.
• Heluhelu komo: RO—Heluhelu wale, a me RW—Heluhelu/Kkau.
• Heluhelu ʻia ka console ʻōnaehana i ka hoʻolālā example kākau inoa a hōʻike i ke kūlana hoʻokolohua ma ka pale.

Papa 6. Hoʻolālā Example Palapala Palapala no Interlaken Design Example

Offset	inoa	Komo	wehewehe
8'h00	Mālama ʻia
8'h01	Mālama ʻia
8'h02	Pūnaehana PLL hou	RO	Ma hope o nā bits e hōʻike ana i ka ʻōnaehana PLL reset noi a hiki i ka waiwai: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	Hoʻopili ʻia ke ala RX	RO	Hōʻike i ka laina laina RX.
8'h04	WORD laka	RO	[NUM_LANES–1:0] – ʻIke ʻia nā palena ʻōlelo (block).

(2) Ke hiki iā ʻoe ke mālama i nā kaila transceiver i hoʻohana ʻole ʻia no ka pākuʻi PAM4, hoʻohui ʻia kahi uaki kuhikuhi hou e mālama ai i ke kahawai kauā PAM4 i hoʻohana ʻole ʻia.

Offset	inoa	Komo	wehewehe
8'h05	Paʻa ka hoʻopaʻa ʻana	RO	[NUM_LANES–1:0] – ʻO ka hoʻonohonoho hoʻonohonoho Metaframe.
8'h06 - 8'h09	helu kuhi hewa CRC32	RO	Hōʻike i ka helu kuhi hewa CRC32.
8'h0A	helu kuhi hewa CRC24	RO	Hōʻike i ka helu kuhi hewa CRC24.
8'h0B	Hōʻailona hoʻokahe/lalo	RO	Hōʻike nā bits ma hope nei: • Bit [3] – TX underflow hōʻailona • Bit [2] – hōʻailona overflow TX • Bit [1] – hōʻailona overflow RX
8'h0C	Helu SOP	RO	Hōʻike i ka helu o SOP.
8'h0D	helu EOP	RO	Hōʻike i ka helu o EOP
8'h0E	helu hewa	RO	Hōʻike i ka helu o nā hewa i lalo: • Nalo o ka laina ala • ʻŌlelo hoʻomalu hewa • ke kumu hoʻohalahala ʻole • Nalo ka hōʻailona SOP a i ʻole EOP
8'h0F	send_data_mm_clk	RW	Kākau i ka 1 a i ka bit [0] e hiki ai i ka hōʻailona hana.
8'h10	Kuhi hewa		Hōʻike i ka hewa o ka mea nānā. (Hino ka ʻikepili SOP, hewa helu Channel, a me ka hewa ʻikepili PLD)
8'h11	Laka PLL pūnaewele	RO	Hōʻike ka bit [0] i ka hōʻailona laka PLL.
8'h14	TX helu SOP	RO	Hōʻike i ka helu o ka SOP i hana ʻia e ka mea hana packet.
8'h15	TX EOP helu	RO	Hōʻike i ka helu o ka EOP i hana ʻia e ka mea hoʻopuka packet.
8'h16	ʻeke mau	RW	Kākau i ka 1 i ka bit [0] i hiki ai i ka ʻeke mau.
8'h39	helu kuhi hewa ECC	RO	Hōʻike i ka helu o nā hewa ECC.
8'h40	Ua hoʻoponopono ʻo ECC i ka helu hewa	RO	Hōʻike i ka helu o nā hewa ECC i hoʻoponopono ʻia.

Papa 7. Hoʻolālā Example Palapala Palapala no Interlaken Look-aside Design Example
E hoʻohana i kēia palapala hoʻopaʻa inoa i ka wā e hana ai ʻoe i ka hoʻolālā example me Enable Interlaken Look-aside mode parameter i ho'ā.

Offset	inoa	Komo	wehewehe
8'h00	Mālama ʻia
8'h01	Hoʻoponopono hou	RO	Kākau i ka 1 i ka bit [0] no ka hoʻomaʻemaʻe i ka TX a me ka RX counter bit like.
8'h02	Pūnaehana PLL hou	RO	Ma hope o nā bits e hōʻike ana i ka ʻōnaehana PLL reset noi a hiki i ka waiwai: • Bit [0] – sys_pll_rst_req • Bit [1] – sys_pll_rst_en
8'h03	Hoʻopili ʻia ke ala RX	RO	Hōʻike i ka laina laina RX.
8'h04	WORD laka	RO	[NUM_LANES–1:0] – ʻIke ʻia nā palena ʻōlelo (block).
8'h05	Paʻa ka hoʻopaʻa ʻana	RO	[NUM_LANES–1:0] – ʻO ka hoʻonohonoho hoʻonohonoho Metaframe.
8'h06 - 8'h09	helu kuhi hewa CRC32	RO	Hōʻike i ka helu kuhi hewa CRC32.
8'h0A	helu kuhi hewa CRC24	RO	Hōʻike i ka helu kuhi hewa CRC24.

Offset	inoa	Komo	wehewehe
8'h0B	Mālama ʻia
8'h0C	Helu SOP	RO	Hōʻike i ka helu o SOP.
8'h0D	helu EOP	RO	Hōʻike i ka helu o EOP
8'h0E	helu hewa	RO	Hōʻike i ka helu o nā hewa i lalo: • Nalo o ka laina ala • ʻŌlelo hoʻomalu hewa • ke kumu hoʻohalahala ʻole • Nalo ka hōʻailona SOP a i ʻole EOP
8'h0F	send_data_mm_clk	RW	Kākau i ka 1 a i ka bit [0] e hiki ai i ka hōʻailona hana.
8'h10	Kuhi hewa	RO	Hōʻike i ka hewa o ka mea nānā. (Hino ka ʻikepili SOP, hewa helu Channel, a me ka hewa ʻikepili PLD)
8'h11	Laka PLL pūnaewele	RO	Hōʻike ka bit [0] i ka hōʻailona laka PLL.
8'h13	Ka helu latency	RO	Hōʻike i ka helu o ka latency.
8'h14	TX helu SOP	RO	Hōʻike i ka helu o ka SOP i hana ʻia e ka mea hana packet.
8'h15	TX EOP helu	RO	Hōʻike i ka helu o ka EOP i hana ʻia e ka mea hoʻopuka packet.
8'h16	ʻeke mau	RO	Kākau i ka 1 i ka bit [0] i hiki ai i ka ʻeke mau.
8'h17	TX a me RX counter like	RW	Hōʻike i ka helu TX a me RX ua like.
8'h23	E ho'ā i ka latency	WO	Kākau i ka 1 a i ka bit [0] i hiki ke ana i ka latency.
8'h24	Mākaukau ka latency	RO	E hōʻike ana ua mākaukau ke ana latency.

Interlaken (2 Generation) Intel Agilex FPGA IP Design Example Nā waihona alakaʻi hoʻohana

No nā mana hou a me nā mana mua o kēia alakaʻi hoʻohana, e nānā i ka Interlaken (2nd Hanana) Intel Agilex FPGA IP Design Example alakaʻi hoʻohana HTML mana. E koho i ka mana a kaomi Download. Inā ʻaʻole i helu ʻia kahi IP a i ʻole ka mana lako polokalamu, pili ke alakaʻi mea hoʻohana no ka IP mua a i ʻole ka mana polokalamu.
Ua like nā mana IP me nā polokalamu polokalamu Intel Quartus Prime Design Suite a hiki i ka v19.1. Mai ka polokalamu polokalamu Intel Quartus Prime Design Suite 19.2 a i ʻole ma hope, loaʻa i nā cores IP kahi hoʻolālā hoʻololi IP hou.

Moʻolelo Hoʻoponopono Paʻi no Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example alakaʻi hoʻohana

Palapala Palapala	ʻO Intel Quartus Prime Version	Manaʻo IP	Nā hoʻololi
2022.08.03	21.3	20.0.1	Hoʻoponopono i ka mea OPN no ka Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04	21.3	20.0.1	• Hoʻohui kākoʻo no QuestaSim simulator. • Wehe 'ia ke kāko'o no NCSim simulator.
2021.02.24	20.4	20.0.1	• Hoʻohui ʻia ka ʻike e pili ana i ka mālama ʻana i ke kahawai transceiver i hoʻohana ʻole ʻia no PAM4 ma ka ʻāpana: Hardware Design Example Nā ʻāpana. • Hoʻohui i ka wehewehe hōʻailona pll_ref_clk[1] ma ka ʻāpana: Nā hōʻailona Interface.
2020.12.14	20.4	20.0.0	• Hoʻohou sampʻO ka hoʻāʻo ʻana o ka lako lako no ke ʻano Interlaken a me ka Interlaken Look-aside mode ma ka pauku E hoʻāʻo ana i ka Hardware Design Example. • ka palapala palapala hoʻopaʻa inoa hou no Interlaken Look-aside design example ma ka pauku Kakau Palapala Palapala. • Hoʻohui ʻia kahi pae hoʻohālikelike no ka holo ʻana o ka hoʻāʻo ʻana i ka lako lako ma ka ʻāpana Hoʻāʻo i ka Hardware Design Example.
2020.10.16	20.2	19.3.0	Hoʻoponopono ʻia ke kauoha e holo i ka calibration hoʻololi mua ma ka ʻaoʻao RX i ka hoʻāʻo ʻana i ka Hardware Design Example pauku.
2020.06.22	20.2	19.3.0	• ʻO ka hoʻolālā exampLoaʻa iā ia no ke ʻano Interlaken Look-side. • ka ho'āʻo paʻa o ka hoʻolālā exampLoaʻa ka le no nā ʻano like ʻole o ka polokalamu Intel Agilex. • Kiʻi Hoʻohui: Kiʻekiʻe-level Block Diagram no Interlaken (2nd Generation) Design Example. • Hōʻano hou ʻia nā ʻāpana ma hope: - Pono nā lako a me nā lako polokalamu – Hoʻonohonoho Papa kuhikuhi • Ua hoʻololi ʻia nā kiʻi ma lalo nei e hoʻokomo i nā mea hou e pili ana i Interlaken Look-aside: – Kiʻi: Interlaken (2nd Generation) Hoʻolālā Lako Example Kiekie Kiʻi Papa Palena no nā ʻano like ʻole o ke ʻano E-tile NRZ – Kiʻi: Interlaken (2nd Generation) Hoʻolālā Lako Example Kiʻekiʻe kiʻekiʻe Block Block no ka E- tile PAM4 mau ʻano like ʻole • Kiʻi Hou: IP Parameter Lunahooponopono. • Hoʻohui ʻia ka ʻike e pili ana i nā hoʻonohonoho alapine i ka noi hoʻomalu uaki ma ka ʻāpana Hoʻohui a hoʻonohonoho i ka Design Example ma Lako.

Palapala Palapala	ʻO Intel Quartus Prime Version	Manaʻo IP	Nā hoʻololi
			• Hoʻohui ʻia nā mea hoʻopuka hoʻāʻo no ka Interlaken Look-side ma nā ʻāpana aʻe: – Hoʻohālike i ka Hoʻolālā Example Hōʻikeʻike – Ke ho'āʻo nei i ka Hoʻolālā Lako Paʻa Example • Hoʻohui ʻia ma hope o nā hōʻailona hou ma ka ʻāpana Interface Signals: – mgmt_clk – rx_pin_n – tx_pin_n – mac_clk_pll_ref • Hoʻohui ʻia ka palapala palapala no Interlaken Look-aside design example ma ka pauku: Kakau Palapala Palapala.
2019.09.30	19.3	19.2.1	Wehe ia clk100. Hoʻohana ʻia ka mgmt_clk ma ke ʻano he uaki kuhikuhi i ka IO PLL ma kēia: • Kiʻi: Interlaken (2nd Generation) Design Hardware Example Kiʻekiʻe Kiʻekiʻe Block Block no ka E-tile NRZ Mode Variations. • Kiʻi: Interlaken (2nd Generation) Design Hardware Example Kiʻekiʻe Kiʻekiʻe Block Block no ka E-tile PAM4 Mode Variations.
2019.07.01	19.2	19.2	Hoʻokuʻu mua.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe.
* Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
ISO
9001:2015
Kakau inoa
Interlaken (2 Generation) Intel® Agilex™ FPGA IP Design Example alakaʻi hoʻohana

Online Version
Hoʻouna Manaʻo
ID: 683800
UG-20239
Manaʻo: 2022.08.03

Palapala / Punawai

intel Interlaken (2nd Generation) Agilex FPGA IP Design Example [pdf] Ke alakaʻi hoʻohana Interlaken 2nd Generation Agilex FPGA IP Design Example, Interlaken, 2nd Generation Agilex FPGA IP Design Example, Agilex FPGA IP Design Example, IP Design Example

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