Microsemi SmartFusion2 SoC FPGA Code Shadowing daga SPI Flash zuwa ƙwaƙwalwar DDR

Gabatarwa

Manufar
Wannan demo don na'urorin SmartFusion®2 tsarin-on-chip (SoC) filin shirye-shiryen kofa ne (FPGA). Yana ba da umarni kan yadda ake amfani da ƙirar ƙira mai dacewa.

Masu Sauraron Niyya
An yi nufin wannan jagorar demo don:

• Masu zanen FPGA
• Masu zanen kaya
• Masu tsara tsarin tsarin

Magana
Duba wadannan web shafi don cikakken kuma na yau da kullun na takaddun na'urar SmartFusion2:
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documentation

Ana magana da waɗannan takaddun a cikin wannan jagorar demo.

• UG0331: SmartFusion2 Jagorar Mai Amfani Subsystem Subsystem
• SmartFusion2 Jagorar Mai Amfani Mai Gina Tsarin

SmartFusion2 SoC FPGA - Shadowing Code daga SPI Flash zuwa Ƙwaƙwalwar DDR

Gabatarwa

Wannan ƙirar demo tana nuna damar na'urar SmartFusion2 SoC FPGA don inuwar lamba daga na'urar ƙwaƙwalwar walƙiya ta serial (SPI) zuwa ƙimar bayanai sau biyu (DDR) ƙwaƙwalwar ajiyar damar bazuwar bazuwar (SDRAM) da aiwatar da lambar daga DDR SDRAM.
Hoto 1 yana nuna zane na babban matakin toshe don inuwar lamba daga na'urar filasha ta SPI zuwa ƙwaƙwalwar ajiyar DDR.

Hoto 1 • Hoto na Babban Matsayi

Shadowing code hanya ce ta booting wacce ake amfani da ita don gudanar da hoto daga waje, sauri, da memories masu canzawa (DRAM). Yana da tsari na kwafin lambar daga ƙwaƙwalwar da ba ta da ƙarfi zuwa ƙwaƙwalwar mara ƙarfi don aiwatarwa.

Ana buƙatar inuwar lamba lokacin da žwažwalwar ajiyar mara maras ƙarfi da ke da alaƙa da mai sarrafawa baya goyan bayan damar bazuwar lambar don aiwatarwa a wuri, ko kuma rashin isassun žwažwalwar ajiyar damar bazuwar mara maras canzawa. A cikin aikace-aikace masu mahimmanci, ana iya inganta saurin aiwatarwa ta hanyar inuwar lamba, inda aka kwafi lambar zuwa mafi girman kayan aikin RAM don aiwatarwa cikin sauri.

Adadin bayanai guda ɗaya (SDR)/DDR SDRAM ana amfani da ƙwaƙwalwar ajiya a aikace-aikacen da ke da babban hoton aikace-aikacen aiwatarwa kuma yana buƙatar aiki mai girma. Yawanci, ana adana manyan hotunan da za a iya aiwatarwa a cikin ƙwaƙwalwar da ba ta da ƙarfi, irin su NAND flash ko SPI flash, kuma ana kwafi su zuwa ƙwaƙwalwar da ba ta da ƙarfi, kamar ƙwaƙwalwar SDR/DDR SDRAM, a ƙarfin aiwatarwa.

SmartFusion2 SoC FPGA na'urorin sun haɗa masana'anta na FPGA na ƙarni na huɗu na walƙiya, mai sarrafa ARM® Cortex®-M3, da manyan mu'amalar sadarwar aiki akan guntu ɗaya. Ana amfani da masu sarrafa ƙwaƙwalwar ajiyar sauri a cikin na'urorin SmartFusion2 SoC FPGA don yin mu'amala tare da ƙwaƙwalwar DDR2/DDR3/LPDDR na waje. Za a iya sarrafa ƙwaƙwalwar DDR2/DDR3 a matsakaicin saurin 333 MHz. Mai sarrafa Cortex-M3 na iya aiwatar da umarnin kai tsaye daga ƙwaƙwalwar DDR na waje ta hanyar tsarin microcontroller (MSS) DDR (MDDR). Mai sarrafa cache na FPGA da gadar MSS DDR suna ɗaukar kwararar bayanai don ingantacciyar aiki.

Zane Abubuwan bukatu
Table 1 yana nuna buƙatun ƙira don wannan demo.

Tebur 1 • Bukatun Zane

Bukatun ƙira	Bayani
Abubuwan Bukatun Hardware
SmartFusion2 Na'urar Haɓakawa ta Ci gaba: • adaftar 12 V • FlashPro5 USB A zuwa Mini – B kebul na USB	Rev A ko kuma daga baya
Desktop ko Laptop	Windows XP SP2 Tsarin aiki - 32-bit/64-bit Windows 7 Tsarin aiki - 32-bit/64-bit
Bukatun Software
Libero® System-on-Chip (SoC)	v11.7
FlashPro Programming Software	v11.7
SoftConsole	v3.4 SP1*
Direbobin PC	USB zuwa UART direbobi
Microsoft .NET Framework 4 abokin ciniki don ƙaddamar da demo GUI	_
Lura: *Don wannan koyawa, ana amfani da SoftConsole v3.4 SP1. Don amfani da SoftConsole v4.0, duba TU0546: SoftConsole v4.0 da Libero SoC v11.7 Koyawa.

Demo Design
Gabatarwa
Tsarin demo files suna samuwa don saukewa daga hanya mai zuwa a cikin Micro Semi website:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0386_liberov11p7_df

Tsarin demo filesun hada da:

• Libero SoC aikin
• STAPL shirye-shirye files
• GUI mai aiwatarwa
• Sample aikace-aikace images
• Rubutun Linker
• Tsarin DDR files
• Karantawa.txt file

Duba abin karantawa.txt file bayar a cikin zane files don cikakken tsarin tsarin.

Bayani
Wannan ƙirar demo tana aiwatar da dabarar inuwa don kora hoton aikace-aikacen daga ƙwaƙwalwar DDR. Wannan ƙirar kuma tana ba da ƙirar mai masaukin baki akan SmartFusion2 SoC FPGA multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) don loda hoton aikace-aikacen da za a iya aiwatarwa a cikin filasha ta SPI da aka haɗa da haɗin MSS SPI0.
Ana aiwatar da inuwar lambar ta hanyoyi biyu masu zuwa:

1. Multi-stage hanyar aiwatar da boot ta amfani da na'urar sarrafa Cortex-M3
2. Hanyar ingin taya kayan aiki ta amfani da masana'anta na FPGA

Multi-Stage Hanyar Tsarin Boot
Hoton aikace-aikacen yana gudana daga ƙwaƙwalwar DDR na waje a cikin waɗannan boot guda biyu masu zuwatage:

• Cortex-M3 processor yana yin takalma mai laushi mai laushi daga ƙwaƙwalwar ajiyar da ba ta da ƙarfi (eNVM), wanda ke aiwatar da canja wurin hoton lambar daga na'urar filasha ta SPI zuwa ƙwaƙwalwar DDR.
• Cortex-M3 processor yana ɗaukar hoton aikace-aikacen daga ƙwaƙwalwar DDR.

Wannan ƙirar tana aiwatar da shirin bootloader don ɗaukar hoto mai aiwatar da aikace-aikacen manufa daga na'urar filasha ta SPI zuwa ƙwaƙwalwar DDR don aiwatarwa. Shirin bootloader da ke gudana daga eNVM yana tsalle zuwa aikace-aikacen manufa da aka adana a cikin ƙwaƙwalwar DDR bayan an kwafi hoton aikace-aikacen da aka yi niyya zuwa ƙwaƙwalwar DDR.
Hoto 2 yana nuna cikakken zanen toshe na ƙirar demo.

Hoto 2 • Shadowing Code – Multi Stage Boot Process Demo Block zane

An saita MDDR don DDR3 don aiki a 320 MHz. "Ƙara: Tsarin DDR3" a shafi na 22 yana nuna saitunan daidaitawar DDR3. An saita DDR kafin aiwatar da babban lambar aikace-aikacen.

Bootloader
Bootloader yana aiwatar da ayyuka masu zuwa:

1. Kwafi hoton aikace-aikacen manufa daga ƙwaƙwalwar filasha ta SPI zuwa ƙwaƙwalwar DDR.
2. Remapping da DDR memory farawa adireshin daga 0xA0000000 zuwa 0x00000000 ta hanyar daidaita tsarin DDR_CR tsarin.
3. Ƙaddamar da ma'aunin tari na Cortex-M3 kamar yadda aka yi niyya. Wuri na farko na tebirin vector na aikace-aikacen yana ƙunshe da ƙimar ma'auni. Teburin vector na aikace-aikacen manufa yana samuwa yana farawa daga adireshin 0x00000000.
4. Load da na'urar shirin (PC) don sake saita mai sarrafa aikace-aikacen manufa don gudanar da hoton aikace-aikacen manufa daga ƙwaƙwalwar DDR. Sake saitin aikace-aikacen manufa yana samuwa a cikin tebur na vector a adireshin 0x00000004.
   Hoto na 3 yana nuna ƙirar demo.
   Hoto 3 • Tsarin Tsara don Multi-Stage Hanyar Tsarin Boot
   

Hanyar Injin Boot Hardware
A cikin wannan hanyar, Cortex-M3 yana ɗaukar hoton aikace-aikacen manufa kai tsaye daga ƙwaƙwalwar DDR na waje. Injin taya kayan masarufi yana kwafin hoton aikace-aikacen daga na'urar filasha ta SPI zuwa ƙwaƙwalwar ajiyar DDR, kafin a sake saitin processor na Cortex-M3. Bayan fitar da sake saiti, Cortex-M3 processor boots kai tsaye daga ƙwaƙwalwar DDR. Wannan hanyar tana buƙatar ƙasa da lokacin tashi sama fiye da multi-stage boot tsari kamar yadda ya kauce wa mahara boot stages da kwafi hoton aikace-aikacen zuwa ƙwaƙwalwar ajiyar DDR cikin ƙasan lokaci.

Wannan ƙirar demo tana aiwatar da dabarun ingin taya a cikin masana'anta na FPGA don kwafin aikace-aikacen da aka yi niyya don aiwatarwa daga filasha ta SPI zuwa ƙwaƙwalwar DDR don aiwatarwa. Wannan ƙira kuma tana aiwatar da loarar filasha ta SPI, wanda Cortex-M3 na iya aiwatar da shi don loda hoton aikace-aikacen da za a iya aiwatarwa a cikin na'urar filasha ta SPI ta amfani da ƙirar mai masaukin baki akan SmartFusion2 SoC FPGA MMUART_0. Ana iya amfani da maɓallin DIP1 akan SmartFusion2 Advanced Development Kit don zaɓar ko za a tsara na'urar filasha ta SPI ko don aiwatar da lambar daga ƙwaƙwalwar DDR.

Idan aikace-aikacen manufa mai aiwatarwa yana samuwa a cikin na'urar filasha ta SPI, lambar inuwa daga na'urar filasha ta SPI zuwa ƙwaƙwalwar ajiyar DDR tana farawa akan ƙarfin na'urar. Injin taya yana ƙaddamar da MDDR, yana kwafin Hoton daga na'urar filasha ta SPI zuwa ƙwaƙwalwar DDR, kuma yana rage sararin ƙwaƙwalwar ajiyar DDR zuwa 0x00000000 ta hanyar ajiye na'urar sarrafa Cortex-M3 a sake saiti. Bayan injin taya ya fito da sake saitin Cortex-M3, Cortex-M3 yana aiwatar da aikace-aikacen da aka yi niyya daga ƙwaƙwalwar DDR.

An saita FIC_0 a cikin yanayin Bayi don samun damar MSS SPI_0 daga FPGA masana'anta AHB master. An kunna ƙirar MDDR AXI (DDR_FIC) don samun damar ƙwaƙwalwar DDR daga FPGA masana'anta AXI master.

Hoto 4 yana nuna cikakken zanen toshe na ƙirar demo.
Hoto 4 • Shadowing Code – Hardware Boot Engine Demo Block diagram

Injin Boot
Wannan shine babban ɓangaren demo ɗin inuwa wanda ke kwafin hoton aikace-aikacen daga na'urar filasha ta SPI zuwa ƙwaƙwalwar ajiyar DDR. Injin taya yana aiwatar da ayyuka kamar haka:

1. Ƙaddamar da MDDR don samun damar DDR3 a 320 MHz ta hanyar ajiye na'ura mai sarrafa Cortex-M3 a sake saiti.
2. Kwafi hoton aikace-aikacen da aka yi niyya daga na'urar ƙwaƙwalwar filasha ta SPI zuwa ƙwaƙwalwar ajiyar DDR ta amfani da maigidan AXI a cikin masana'anta na FPGA ta hanyar dubawar MDDR AXI.
3. Remapping da DDR memory farawa adireshin daga 0xA0000000 zuwa 0x00000000 ta rubuta zuwa DDR_CR tsarin rajista.
4. Sakin sake saiti zuwa Cortex-M3 processor don taya daga ƙwaƙwalwar DDR.

Hoto na 5 yana nuna kwararar ƙirar demo.
Hoto 5 • Hoto na Babban Matsayi

Hoto 6 • Tsarin Tsara don Hanyar Boot Injin Hardware

Ƙirƙirar Hoton Aikace-aikacen Target don Ƙwaƙwalwar DDR
Ana buƙatar hoton da za a iya aiwatar da shi daga ƙwaƙwalwar DDR don gudanar da demo. Yi amfani da bayanin mahaɗin "samar-execute-in-place-externalDDR.ld". file wanda ke kunshe a cikin zane files don gina hoton aikace-aikacen. Bayanin mahaɗin file yana bayyana adireshin farawa na ƙwaƙwalwar DDR a matsayin 0x00000000 tun lokacin da injin bootloader/boot ke aiwatar da ragowar ƙwaƙwalwar DDR daga 0xA0000000 zuwa 0x00000000. Rubutun mahaɗin yana ƙirƙirar hoton aikace-aikacen tare da umarni, bayanai, da sassan BSS a cikin ƙwaƙwalwar ajiya waɗanda adireshin farawa shine 0x00000000. Sauƙaƙan diode mai haske mai haske (LED) mai kyalli, mai ƙidayar lokaci da hoton aikace-aikacen ƙirƙira tushen katsewa file an tanada don wannan demo.

SPI Flash Loader
Ana aiwatar da loarar filasha ta SPI don ɗora ƙwaƙwalwar ajiyar SPI a kan jirgi tare da hoton aikace-aikacen aikace-aikacen da za a iya aiwatarwa daga PC mai masaukin ta ta hanyar MMUART_0. Mai sarrafa Cortex-M3 yana yin buffer don bayanan da ke zuwa sama da mahaɗin MMUART_0 kuma yana ƙaddamar da na gefe DMA (PDMA) don rubuta bayanan buffered cikin filasha SPI ta hanyar MSS_SPI0.

Gudun Demo
Nunin yana nuna yadda ake loda hoton aikace-aikacen a cikin filasha SPI da aiwatar da hoton aikace-aikacen daga ƙwaƙwalwar DDR na waje. Yana bayar da wani example hoton aikace-aikacen "sample_image_DDR3.bin". Wannan hoton yana nuna saƙonnin maraba da saƙon katse mai ƙidayar lokaci akan serial console kuma yana lumshe LED1 zuwa LED8 akan SmartFusion2 Advanced Development Kit. Don ganin GPIO katse saƙonnin a kan serial console, danna maɓallin SW2 ko SW3.

Saita Tsarin Demo
Matakai masu zuwa suna bayyana yadda ake saita demo don SmartFusion2 Advanced Development Kit Board:

1. Haɗa Mai watsa shiri PC zuwa J33 Connector ta amfani da kebul A zuwa mini-B na USB. Ana gano direbobin gadar USB zuwa UART ta atomatik. Tabbatar idan an gano ganowa a cikin mai sarrafa na'urar kamar yadda aka nuna a hoto 7.
2. Idan ba a gano direbobin USB ta atomatik ba, shigar da direban USB.
3. Domin serial tasha sadarwa ta FTDI mini kebul na USB, shigar da FTDI D2XX direba. Zazzage direbobi da jagorar shigarwa daga:
   http://www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
   Hoto 7 • Kebul zuwa UART Direban gada
   
4. Haɗa masu tsalle a kan SmartFusion2 Advanced Development Kit Board, kamar yadda aka nuna a Tebu 2.
   Tsanaki: Kashe wutar lantarki, SW7 yayin haɗa masu tsalle.
   Tebur na 2 • SmartFusion2 Saitunan Jumper na Na'urar haɓaka ci gaba

   Jumper	Pin (Daga)	Pin (zuwa)	Sharhi
   J116, J353, J354, J54	1	2	Waɗannan su ne tsoffin saitunan jumper na Advanced Development Kit Board. Tabbatar an saita waɗannan jumpers daidai.
   J123	2	3
   J124, J121, J32	1	2	JTAG shirye-shirye ta hanyar FTDI
   j118, j119	1	2	Shirye-shiryen SPI Flash

5. A cikin SmartFusion2 Advanced Development Kit, haɗa wutar lantarki zuwa mai haɗin J42.
   Hoto 8. yana nuna saitin allon don gudanar da inuwar lambar daga SPI flash zuwa demo na DDR3 akan SmartFusion2 Advanced Development Kit.
   Hoto 8 • SmartFusion2 Saita Kayan Ci gaba na Ci gaba
   

SPI Flash Loader da Code Shadowing Demo GUI
Ana buƙatar GUI don gudanar da demo ɗin inuwa. SPI Flash Loader da Code Shadowing Demo GUI shine sauƙin mai amfani mai hoto mai sauƙi wanda ke gudana akan PC mai masaukin don tsara filasha ta SPI kuma tana gudanar da demo ɗin inuwa akan SmartFusion2 Advanced Development Kit. UART yarjejeniya ce ta sadarwa tsakanin PC mai masaukin baki da SmartFusion2 Advanced Development Kit. Hakanan yana ba da ɓangaren Serial Console don buga saƙon gyara da aka karɓa daga aikace-aikacen akan mahaɗin UART.
Hoto 9. yana nuna SPI Flash Loader da Lambar Shadowing Demo Window.
Hoto 9 • SPI Flash Loader da Lambar Shadowing Demo Window

GUI yana goyan bayan fasalulluka masu zuwa:

• Shirin SPI Flash: Yana tsara hoton file cikin SPI flash.
• Shirye-shirye da Shadowing Code daga SPI Flash zuwa DDR: Shirya hoton file cikin SPI flash, kwafa shi zuwa ƙwaƙwalwar ajiyar DDR, kuma ya ɗaga hoton daga ƙwaƙwalwar DDR.
• Shirye-shirye da Shadowing Code daga SPI Flash zuwa SDR: Shirya hoton file zuwa SPI flash, kwafe shi zuwa ƙwaƙwalwar ajiyar SDR, kuma yana ɗaukar hoton daga ƙwaƙwalwar SDR.
• Shadowing Code zuwa DDR: Kwafi hoton da ke akwai file daga SPI flash zuwa ƙwaƙwalwar ajiyar DDR kuma yana ɗaukar hoton daga ƙwaƙwalwar DDR.
• Shadowing Code zuwa SDR: Kwafi hoton data kasance file daga SPI flash zuwa ƙwaƙwalwar ajiyar SDR kuma yana ɗaukar hoton daga ƙwaƙwalwar SDR. Danna Taimako don ƙarin bayani akan GUI.

Gudanar da Tsarin Demo don Multi-Stage Hanyar Tsarin Boot
Matakan da ke gaba suna bayyana yadda ake gudanar da ƙirar demo don Multi-stage boot tsari Hanyar:

1. Kunna wutar lantarki, SW7.
2. Shirya na'urar SmarFusion2 SoC FPGA tare da shirye-shirye file bayar a cikin zane files (SF2_CodeShadowing_DDR3_DF\Programming Files \ MultiStageBoot_meothodCodeShadowing_top.stp ta amfani da software na ƙirar FlashPro).
3. Kaddamar da SPI Flash Loader da Code Shadowing Demo GUI mai aiwatarwa file samuwa a cikin zane files (SF2_CodeShadowing_DDR3_DF\GUI Executable\SF2_FlashLoader.exe).
4. Zaɓi tashar tashar COM da ta dace (wanda aka nuna masu kebul ɗin Serial ɗin zuwa gare shi) daga jerin zaɓuka na COM Port.
5. Danna Haɗa. Bayan kafa haɗin, Haɗa yana canzawa zuwa Cire haɗin.
6. Danna Browse don zaɓar tsohonample niyya hoto mai aiwatarwa file bayar da zane files
   (SF2_CodeShadowing_DDR3_DF/Sample Hotuna/s Aikace-aikaceample_image_DDR3.bin).
   Lura: Don samar da bin bin hoton aikace-aikacen file, duba “ Shafi: Samar da Ƙarfin Ƙarfafawa File” a shafi na 25.
7. Ajiye adireshin farawa na ƙwaƙwalwar filasha ta SPI azaman tsoho a 0x00000000.
8. Zaɓi Shirin da Shadowing Code daga SPI Flash zuwa zaɓi na DDR.
9. Danna Fara kamar yadda aka nuna a Hoto 10 don loda hoton da za'a iya aiwatarwa cikin filasha SPI da inuwar lambar daga ƙwaƙwalwar DDR.
   Hoto 10 • Fara Demo
   
10. Idan an tsara na'urar SmartFusion2 SoC FPGA tare da STAPL file wanda ba a saita MDDR don ƙwaƙwalwar DDR ba sannan yana nuna saƙon kuskure, kamar yadda aka nuna a hoto na 11.
    Hoto 11 • Na'urar da ba daidai ba ko Saƙon zaɓi
    
11. Sashen Console na Serial akan GUI yana nuna saƙon gyara kuma yana fara shirye-shiryen SPI flash akan nasarar goge filasha ta SPI. Hoto na 12 yana nuna matsayin rubutun filasha na SPI
    Hoto 12 • Load din filasha
    
12. A kan tsara filasha ta SPI cikin nasara, bootloader yana gudana akan SmartFusion2 SoC FPGA yana kwafin hoton aikace-aikacen daga SPI flash zuwa ƙwaƙwalwar ajiyar DDR kuma yana ɗaukar hoton aikace-aikacen. Idan hoton da aka bayar sample_image_DDR3.bin an zaɓi, serial console yana nuna saƙonnin maraba, katse katsewa da katsewar lokaci kamar yadda aka nuna a hoto na 13 a shafi na 18 da Hoto 14 a shafi na 18. Ana nuna alamar LED mai gudana akan LED1 zuwa LED8 akan SmartFusion2 Advanced Development Kit.
13. Latsa maɓallan SW2 da SW3 don ganin saƙon katsewa akan na'urar wasan bidiyo na serial.
    Hoto 13 • Gudanar da Hoton Aikace-aikacen Target daga Ƙwaƙwalwar DDR3
    Hoto 14 • Mai ƙidayar lokaci da Saƙonnin Katsewa a Serial Console
    

Gudanar da Tsarin Injin Boot Boot Hardware
Matakai masu zuwa suna bayyana yadda ake gudanar da ƙirar injin boot ɗin hardware:

1. Kunna wutar lantarki, SW7.
2. Shirya na'urar SmarFusion2 SoC FPGA tare da shirye-shirye file bayar a cikin zane files (SF2_CodeShadowing_DDR3_DF\Programming
   Files\HWBootEngine_methodCodeShadowing_Fabric.stp ta amfani da software na ƙirar FlashPro).
3. Don tsara SPI Flash yi DIP canza SW5-1 zuwa ON matsayi. Wannan zaɓin yana yin don taya Cortex-M3 daga eNVM. Latsa SW6 don sake saita na'urar SmartFusion2.
4. Kaddamar da SPI Flash Loader da Code Shadowing Demo GUI mai aiwatarwa file samuwa a cikin zane files (SF2_CodeShadowing_DDR3_DF\GUI Executable\SF2_FlashLoader.exe).
5. Zaɓi tashar tashar COM da ta dace (wanda aka nuna masu kebul ɗin Serial ɗin zuwa gare shi) daga jerin zaɓuka na COM Port.
6. Danna Haɗa. Bayan kafa haɗin, Haɗa yana canzawa zuwa Cire haɗin.
7. Danna Browse don zaɓar tsohonample niyya hoto mai aiwatarwa file bayar da zane files
   (SF2_CodeShadowing_DDR3_DF/Sample Hotuna/s Aikace-aikaceample_image_DDR3.bin).
   Lura: Don samar da bin bin hoton aikace-aikacen file, duba “ Shafi: Samar da Ƙarfin Ƙarfafawa File” a shafi na 25.
8. Zaɓi zaɓin Injin Boot na Hardware a Hanyar Shadowing Code.
9. Zaɓi zaɓin shirin SPI Flash daga menu na Zabuka.
10. Danna Fara, kamar yadda aka nuna a hoto na 15 don loda hoton da za'a iya aiwatarwa cikin filasha ta SPI.
    Hoto 15 • Fara Demo
    
11. Sashen Console na Serial akan GUI yana nuna saƙon gyara kuskure da matsayin rubutun filasha na SPI, kamar yadda aka nuna a Hoto 16.
    Hoto 16 • Load din filasha
    
12. Bayan shirya filasha SPI cikin nasara, canza canjin DIP SW5-1 zuwa matsayin KASHE. Wannan zaɓin yana yin don taya mai sarrafa Cortex-M3 daga ƙwaƙwalwar DDR.
13. Latsa SW6 don sake saita na'urar SmartFusion2. Injin taya yana kwafin hoton aikace-aikacen daga SPI flash zuwa ƙwaƙwalwar ajiyar DDR kuma yana sake saiti zuwa Cortex-M3, wanda ke ɗaukar hoton aikace-aikacen daga ƙwaƙwalwar DDR. Idan hoton da aka bayar “sample_image_DDR3.bin" an ɗora shi zuwa filasha na SPI, na'urar wasan bidiyo na serial yana nuna saƙonnin maraba, katse katsewa (latsa SW2 ko SW3) da kuma lokacin katse saƙonni kamar yadda aka nuna a hoto 17 kuma ana nuna alamar LED mai gudana akan LED1 zuwa LED8 akan SmartFusion2 Advanced. Kit ɗin haɓakawa.
    Hoto 17 • Gudanar da Hoton Aikace-aikacen Target daga Ƙwaƙwalwar DDR3
    

Kammalawa
Wannan demo yana nuna ikon SmartFusion2 SoC FPGA na'urar don yin mu'amala tare da ƙwaƙwalwar DDR kuma don gudanar da hoton aiwatarwa daga ƙwaƙwalwar DDR ta hanyar inuwa mai lamba daga na'urar ƙwaƙwalwar filasha ta SPI. Hakanan yana nuna hanyoyin aiwatar da inuwa guda biyu akan na'urar SmartFusion2.

Shafi: DDR3 Kanfigareshan

Alkaluman da ke gaba suna nuna saitunan daidaitawar DDR3.
Hoto 18 • Gabaɗaya Saitunan Kanfigareshan DDR

Hoto 19 • Saitunan Fara Ƙwaƙwalwar Ƙwaƙwalwa na DDR

Hoto 20 • Saitunan Lokacin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa na DDR

Karin Bayani: Samar da Bin Mai Aiwatarwa File

Bin mai aiwatarwa file ana buƙatar shirya filasha SPI don gudanar da demo inuwa. Don samar da bin mai aiwatarwa file daga "sample_image_DDR3” Soft Console, yi matakai masu zuwa:

1. Gina aikin Soft Console tare da samar da rubutun linker-aiki-a-wuri-na waje DDR.
2. Ƙara hanyar shigarwa mai laushi Console, misaliample, C:\MicrosemiLibero_v11.7SoftConsoleSourcery-G++\bin, zuwa 'Sababun Muhalli' kamar yadda aka nuna a Hoto na 21.
   Hoto 21 • Ƙara Hanyar Shigar da Console mai laushi
   
3. Danna tsari sau biyu file Bin-File-Generator.bat dake:
   SoftConsole/Shadowing_MSS_CM3/Sample_image_DDR3 babban fayil, kamar yadda aka nuna a hoto 22.
   Hoto 22 • Bin File Generator
   
4. Bin -File-Generator yana ƙirƙirar sample_image_DDR3.bin file.

Tarihin Bita

Tebu mai zuwa yana nuna mahimman canje-canjen da aka yi a cikin wannan takaddar don kowane bita.

Bita	Canje-canje
Bita 7 (Maris 2016)	An sabunta daftarin aiki don sakin software na Libero SoC v11.7 (SAR 77816).
Bita 6 (Oktoba 2015)	An sabunta daftarin aiki don sakin software na Libero SoC v11.6 (SAR 72424).
Bita 5 (Satumba 2014)	An sabunta daftarin aiki don sakin software na Libero SoC v11.4 (SAR 60592).
Bita 4 (Mayu 2014)	An sabunta daftarin aiki don sakin software na Libero SoC 11.3 (SAR 56851).
Bita 3 (Disamba 2013)	An sabunta daftarin aiki don sakin software na Libero SoC v11.2 (SAR 53019).
Bita 2 (Mayu 2013)	An sabunta daftarin aiki don sakin software na Libero SoC v11.0 (SAR 47552).
Bita 1 (Maris 2013)	An sabunta takaddun don Libero SoC v11.0 beta SP1 sakin software (SAR 45068).

Tallafin samfur

Microsemi SoC Products Group yana goyan bayan samfuran sa tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, lantarki mail, da kuma duniya tallace-tallace ofisoshin. Wannan karin bayani ya ƙunshi bayani game da tuntuɓar Rukunin Samfuran Microsemi SoC da amfani da waɗannan sabis ɗin tallafi.

Sabis na Abokin Ciniki
Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.

• Daga Arewacin Amirka, kira 800.262.1060
• Daga sauran duniya, kira 650.318.4460
• Fax, daga ko'ina cikin duniya, 408.643.6913

Cibiyar Taimakon Fasaha ta Abokin Ciniki
Ƙungiyar Samfuran SoC ta Microsemi tana aiki da Cibiyar Taimakon Fasaha ta Abokin Ciniki tare da ƙwararrun injiniyoyi waɗanda zasu iya taimakawa amsa kayan aikinku, software, da ƙira game da samfuran Microsemi SoC. Cibiyar Tallafawa Fasaha ta Abokin Ciniki tana ciyar da lokaci mai yawa don ƙirƙirar bayanin kula, amsoshi ga tambayoyin sake zagayowar ƙira, takaddun abubuwan da aka sani, da FAQ daban-daban. Don haka, kafin ku tuntube mu, da fatan za a ziyarci albarkatun mu na kan layi. Da alama mun riga mun amsa tambayoyinku.

Goyon bayan sana'a

Don Tallafin Kayayyakin Microsemi SoC, ziyarci
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.

Website
Kuna iya bincika bayanai na fasaha iri-iri da marasa fasaha akan shafin gida na Microsemi SoC Products Group, a http://www.microsemi.com/products/fpga-soc/fpga-and-soc.

Tuntuɓar Cibiyar Tallafin Fasaha ta Abokin Ciniki
ƙwararrun injiniyoyi suna aiki da Cibiyar Tallafawa Fasaha. Ana iya tuntuɓar Cibiyar Taimakon Fasaha ta imel ko ta Microsemi SoC Products Group website.

Imel
Kuna iya sadar da tambayoyin ku na fasaha zuwa adireshin imel ɗinmu kuma ku karɓi amsoshi ta imel, fax, ko waya. Hakanan, idan kuna da matsalolin ƙira, zaku iya imel ɗin ƙirar ku files don karɓar taimako. Muna saka idanu akan asusun imel a ko'ina cikin yini. Lokacin aika buƙatun ku zuwa gare mu, da fatan a tabbatar kun haɗa da cikakken sunan ku, sunan kamfani, da bayanan tuntuɓarku don ingantaccen sarrafa buƙatarku.
Adireshin imel ɗin tallafin fasaha shine soc_tech@microsemi.com.

Al'amurana
Abokan ciniki na Rukunin Samfuran SoC na Microsemi na iya ƙaddamarwa da bin diddigin shari'o'in fasaha akan layi ta hanyar zuwa Abubuwan Nawa.

Wajen Amurka
Abokan ciniki masu buƙatar taimako a wajen yankunan lokacin Amurka na iya tuntuɓar tallafin fasaha ta imel (soc_tech@microsemi.com) ko tuntuɓi ofishin tallace-tallace na gida. Ziyarci Game da Mu don lissafin ofisoshin tallace-tallace da lambobin kamfanoni.

Tallafin Fasaha na ITAR
Don goyan bayan fasaha akan RH da RT FPGAs waɗanda aka tsara ta hanyar Traffic in Arms Regulations (ITAR), tuntuɓe mu ta hanyar soc_tech@microsemi.com. A madadin, a cikin Harkoki Na, zaɓi Ee a cikin jerin zaɓuka na ITAR. Don cikakken jerin FPGAs Microsemi da ke sarrafa ITAR, ziyarci ITAR web shafi.

Babban Ofishin Kamfanin Microsemi
Ɗaya daga cikin Enterprise, Aliso Viejo,
CA 92656 Amurka
A cikin Amurka: +1 (800)
713-4113 Waje
Amurka: +1 949-380-6100
Talla: +1 949-380-6136
Fax: +1 949-215-4996
Imel: sales.support@microsemi.com
© 2016 Microsemi Corporation.
An kiyaye duk haƙƙoƙi. Microsemi da tambarin Microsemi alamun kasuwanci ne na Kamfanin Microsemi.
Duk sauran alamun kasuwanci da alamun sabis mallakin masu su ne.

Kamfanin Microsemi (Nasdaq: MSCC) yana ba da cikakkiyar fayil na semiconductor da mafita na tsarin don sadarwa, tsaro & tsaro, sararin samaniya da kasuwannin masana'antu. Kayayyakin sun haɗa da babban aiki da radiyo-tauraruwar analog gauran siginar hadedde, FPGAs, SoCs da ASICs; kayayyakin sarrafa wutar lantarki; lokaci da na'urorin aiki tare da madaidaicin mafita na lokaci, saita ƙa'idodin duniya don lokaci; na'urorin sarrafa murya; RF mafita; sassa masu hankali; Ma'ajiyar kasuwanci da hanyoyin sadarwar sadarwa, fasahar tsaro da scalable anti-tampsamfurori; Hanyoyin Ethernet; Power-over-Ethernet ICs da midspans; kazalika da al'ada ƙira iyawa da kuma ayyuka. Microsemi yana da hedikwata a Aliso Viejo, Calif, kuma yana da kusan ma'aikata 4,800 a duniya. Ƙara koyo a www.microsemi.com.

Microsemi baya bayar da garanti, wakilci, ko garanti game da bayanin da ke ƙunshe a ciki ko dacewa da samfuransa da sabis ɗin sa don kowane dalili na musamman, haka nan Microsemi baya ɗaukar wani alhaki duk abin da ya taso daga aikace-aikacen ko amfani da kowane samfur ko kewaye. Kayayyakin da aka siyar a ƙarƙashinsa da duk wasu samfuran da Microsemi ke siyarwa sun kasance ƙarƙashin ƙayyadaddun gwaji kuma bai kamata a yi amfani da su tare da kayan aiki masu mahimmanci ko aikace-aikace ba. An yi imanin duk wani ƙayyadaddun ƙayyadaddun aiki na abin dogaro ne amma ba a tabbatar da su ba, kuma mai siye dole ne ya gudanar da kammala duk ayyuka da sauran gwajin samfuran, shi kaɗai kuma tare da, ko shigar da su, kowane samfuran ƙarshe. Mai siye ba zai dogara da kowane bayanai da ƙayyadaddun ayyuka ko sigogi da Microsemi ya bayar ba. Alhakin Mai siye ne don ƙayyade dacewa da kowane samfur da kansa kuma don gwadawa da tabbatar da iri ɗaya. Bayanin da Microsemi ya bayar a nan an bayar da shi "kamar yadda yake, inda yake" kuma tare da duk kuskure, kuma duk haɗarin da ke tattare da irin wannan bayanin gaba ɗaya yana tare da mai siye. Microsemi baya ba, a bayyane ko a fakaice, ga kowace ƙungiya kowane haƙƙin haƙƙin mallaka, lasisi, ko kowane haƙƙin IP, ko dangane da irin wannan bayanin da kansa ko wani abu da irin wannan bayanin ya bayyana. Bayanin da aka bayar a cikin wannan takaddun mallakar Microsemi ne, kuma Microsemi yana da haƙƙin yin kowane canje-canje ga bayanin da ke cikin wannan takaddar ko zuwa kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba.

Takardu / Albarkatu

Microsemi SmartFusion2 SoC FPGA Code Shadowing daga SPI Flash zuwa ƙwaƙwalwar DDR [pdf] Littafin Mai shi SmartFusion2 SoC FPGA Code Shadowing daga SPI Flash zuwa DDR Memory, SmartFusion2 SoC, FPGA Code Shadowing daga SPI Flash zuwa DDR Memory, Flash zuwa DDR Memory

Magana

• Manual mai amfani