Cov ntsiab lus zais
1 Microsemi SmartFusion2 SoC FPGA Code Duab ntxoov ntxoo los ntawm SPI Flash rau DDR Nco
2 Ua ntej
3 SmartFusion2 SoC FPGA - Code Shadowing los ntawm SPI Flash rau DDR Nco
3.1 Taw qhia
4 Cov ntawv ntxiv: DDR3 Configurations
5 Daim Ntawv Ntxiv: Tsim Cov Txiaj Ntsig executable Bin File
6 Kev kho keeb kwm
7 Khoom txhawb
7.1 Kev pab txhawb nqa
8 Cov ntaub ntawv / Cov ntaub ntawv
8.1 Cov ntaub ntawv
9 Related Posts

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-los ntawm-SPI-Flash-rau-DDR-Memory-logo

Microsemi SmartFusion2 SoC FPGA Code Duab ntxoov ntxoo los ntawm SPI Flash rau DDR Nco

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-los ntawm-SPI-Flash-to-DDR-Memory-product-iamge

Ua ntej

Lub hom phiaj
Qhov no demo yog rau SmartFusion®2 system-on-chip (SoC) teb programmable rooj vag array (FPGA) cov khoom siv. Nws muab cov lus qhia txog yuav ua li cas siv tus qauv siv coj los siv.

Lub Hom Phiaj
Daim ntawv qhia demo no yog npaj rau:

  • FPGA designers
  • Embedded designers
  • System-level designers

Cov ntaub ntawv
Saib hauv qab no web nplooj ntawv rau cov npe ua tiav thiab hloov tshiab ntawm SmartFusion2 cov ntaub ntawv ntaus ntawv:
http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documentation

Cov ntaub ntawv hauv qab no raug xa mus rau hauv phau ntawv qhia demo no.

  • UG0331: SmartFusion2 Microcontroller Subsystem Tus Neeg Siv Qhia
  • SmartFusion2 System Builder User Guide

SmartFusion2 SoC FPGA - Code Shadowing los ntawm SPI Flash rau DDR Nco

Taw qhia

Qhov kev tsim qauv no qhia tau hais tias SmartFusion2 SoC FPGA cov cuab yeej muaj peev xwm rau cov duab ntxoov ntxoo los ntawm serial peripheral interface (SPI) flash nco ntaus ntawv kom muab ob npaug rau cov ntaub ntawv tus nqi (DDR) synchronous dynamic random access memory (SDRAM) thiab ua tiav cov cai los ntawm DDR SDRAM.
Daim duab 1 qhia cov duab thaiv saum toj kawg nkaus rau cov duab ntxoov ntxoo los ntawm SPI flash ntaus ntawv mus rau DDR nco.

Daim duab 1 • Sab saum toj-Level Block Diagram

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-01

Code shadowing yog ib txoj kev booting uas yog siv los khiav ib tug duab los ntawm sab nraud, sai dua, thiab volatile nco (DRAM). Nws yog tus txheej txheem ntawm kev luam cov cai los ntawm lub cim xeeb uas tsis yog-volatile mus rau lub volatile nco rau kev tua.

Code shadowing yuav tsum tau thaum lub cim xeeb uas tsis yog-volatile txuam nrog ib tug processor tsis txhawb random nkag mus rau hauv lub code rau execute-nyob rau hauv-qhov chaw, los yog tsis txaus tsis-volatile random access nco. Hauv cov ntawv thov kev ua haujlwm tseem ceeb, kev ua tiav nrawm tuaj yeem txhim kho los ntawm cov duab ntxoov ntxoo, qhov twg cov lej tau theej rau ntau dua ntawm RAM kom ua tiav sai.

Tib cov ntaub ntawv tus nqi (SDR) / DDR SDRAM nco tau siv rau hauv cov ntawv thov uas muaj daim ntawv thov loj ua tau zoo thiab xav tau kev ua haujlwm siab dua. Feem ntau, cov duab ua tiav loj yog khaws cia rau hauv lub cim xeeb tsis hloov pauv, xws li NAND flash lossis SPI flash, thiab theej rau lub cim xeeb tsis zoo, xws li SDR / DDR SDRAM nco, ntawm lub zog rau kev tua.

SmartFusion2 SoC FPGA cov cuab yeej sib txuas ua ke plaub tiam flash-based FPGA npuag, ARM® Cortex®-M3 processor, thiab kev sib txuas lus ua haujlwm siab ntawm ib nti. Cov tswj kev nco ceev ceev hauv SmartFusion2 SoC FPGA cov cuab yeej siv los cuam tshuam nrog lwm yam DDR2 / DDR3 / LPDDR nco. DDR2 / DDR3 nco tuaj yeem ua haujlwm ntawm qhov siab tshaj plaws ntawm 333 MHz. Cortex-M3 processor tuaj yeem ncaj qha khiav cov lus qhia los ntawm lwm lub cim xeeb DDR los ntawm microcontroller subsystem (MSS) DDR (MDDR). FPGA cache maub los thiab MSS DDR choj tuav cov ntaub ntawv ntws rau kev ua haujlwm zoo dua.

Tsim Kev xav tau
Table 1 qhia txog kev tsim qauv rau qhov demo no.

Table 1 • Cov Qauv Tsim Qauv

Kev tsim qauv tsim Kev piav qhia
Hardware Requirements
SmartFusion2 Advanced Development Kit:
• 12 V adapter
• FlashPro5
• USB A rau Mini – B USB cable		 Rev A los yog tom qab
Desktop lossis Laptop Windows XP SP2 Operating System - 32-ntsis / 64-ntsis Windows 7 Operating System - 32-ntsis / 64-ntsis
Software Yuav Tsum Tau
Libero® System-on-Chip (SoC) v11.7 ua
FlashPro Programming Software v11.7 ua
SoftConsole v3.4 SP1*
PC Drivers USB rau UART tsav tsheb
Microsoft .NET Framework 4 tus thov kev pab rau launching demo GUI _
Nco tseg: *Rau qhov kev qhia no, SoftConsole v3.4 SP1 yog siv. Rau kev siv SoftConsole v4.0, saib cov TU0546: SoftConsole v4.0 thiab Libero SoC v11.7 Tutorial.

Demo Tsim
Taw qhia
Tus qauv tsim files muaj rau rub tawm los ntawm txoj kev hauv qab no hauv Micro semi webqhov chaw:
http://soc.microsemi.com/download/rsc/?f=m2s_dg0386_liberov11p7_df

Tus qauv tsim files suav nrog:

  • Libero SoC qhov project
  • STAPL programming files
  • GUI executable
  • Sample application images
  • Linker scripts
  • DDR configuration files
  • Readme.txt file

Saib cov readme.txt file muab nyob rau hauv tus tsim files rau daim ntawv teev npe tiav.

Kev piav qhia
Qhov kev tsim qauv no siv cov txheej txheem duab ntxoov ntxoo rau khau raj daim ntawv thov duab los ntawm DDR nco. Qhov kev tsim no kuj muab tus tswv tsev sib tham dhau SmartFusion2 SoC FPGA ntau hom universal asynchronous / synchronous receiver / transmitter (MMUART) txhawm rau thauj cov phiaj xwm daim ntawv thov ua tiav rau hauv SPI flash txuas nrog MSS SPI0 interface.
Code shadowing yog siv nyob rau hauv ob txoj kev hauv qab no:

  1. Ntau-stage khau raj txheej txheem siv Cortex-M3 processor
  2. Hardware khau raj cav txoj kev siv FPGA ntaub

Ntau-Stage Boot Process Method
Daim ntawv thov daim duab yog khiav los ntawm sab nraud DDR nco hauv ob lub khau raj nram qab notages:

  • Lub Cortex-M3 processor boots lub khau raj khau raj los ntawm embedded non-volatile memory (eNVM), uas ua cov code duab hloov los ntawm SPI flash ntaus ntawv mus rau DDR nco.
  • Cortex-M3 processor boots daim ntawv thov duab los ntawm DDR nco.

Qhov kev tsim no siv cov kev pab cuam bootloader los thauj cov phiaj xwm ua tiav daim duab los ntawm SPI flash ntaus ntawv mus rau DDR nco rau kev tua. Qhov kev pab cuam bootloader khiav los ntawm eNVM dhia mus rau lub hom phiaj daim ntawv thov khaws cia hauv DDR nco tom qab lub hom phiaj daim ntawv thov duab tau theej rau DDR nco.
Daim duab 2 qhia cov ncauj lus kom ntxaws daim duab qhia ntawm tus qauv demo.

Daim duab 2 • Code Shadowing – Multi Stage Boot Process Demo Block Diagram

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-02

MDDR tau teeb tsa rau DDR3 ua haujlwm ntawm 320 MHz. "Cov Ntawv Ntxiv: DDR3 Configurations" ntawm nplooj 22 qhia txog DDR3 teeb tsa. DDR tau teeb tsa ua ntej ua tiav daim ntawv thov tseem ceeb code.

Bootloader
Lub bootloader ua cov haujlwm hauv qab no:

  1. Luam lub hom phiaj daim ntawv thov duab los ntawm SPI flash nco rau DDR nco.
  2. Remapping lub cim xeeb DDR pib qhov chaw nyob ntawm 0xA0000000 rau 0x00000000 los ntawm kev teeb tsa DDR_CR kev sau npe.
  3. Pib lub Cortex-M3 processor pawg pointer raws li lub hom phiaj daim ntawv thov. Thawj qhov chaw ntawm lub hom phiaj daim ntawv thov vector table muaj cov pawg pointer tus nqi. Cov lus vector ntawm lub hom phiaj daim ntawv thov muaj pib los ntawm qhov chaw nyob 0x00000000.
  4. Loading the program counter (PC) reset handler of the target application for run the target application image from the DDR memory. Reset handler ntawm lub hom phiaj daim ntawv thov muaj nyob rau hauv lub rooj vector ntawm qhov chaw nyob 0x00000004.
    Daim duab 3 qhia txog tus qauv tsim.
    Daim duab 3 • Tsim Flow rau Multi-Stage Boot Process Method
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-03

Hardware Boot Engine Method
Hauv cov qauv no, Cortex-M3 ncaj qha khau raj lub hom phiaj daim ntawv thov duab los ntawm lwm yam DDR nco. Lub tshuab khau raj tshuab luam theej daim ntawv thov daim duab los ntawm SPI flash ntaus ntawv rau DDR nco, ua ntej tso Cortex-M3 processor rov pib dua. Tom qab tso qhov rov pib dua, Cortex-M3 processor khau raj ncaj qha los ntawm DDR nco. Txoj kev no yuav tsum muaj lub sijhawm khau raj tsawg dua li ntau-stage khau raj txheej txheem raws li nws zam ntau khau raj stages thiab luam daim ntawv thov duab rau DDR nco hauv lub sijhawm tsawg.

Qhov kev tsim qauv no siv lub cav cav logic hauv FPGA ntaub los luam cov phiaj xwm daim ntawv thov ua tiav daim duab los ntawm SPI flash rau DDR nco rau kev tua. Qhov kev tsim no tseem siv SPI flash loader, uas tuaj yeem ua tiav los ntawm Cortex-M3 processor los thauj cov phiaj xwm daim ntawv thov ua tiav cov duab rau hauv SPI flash ntaus ntawv siv tus tswv tsev interface dhau SmartFusion2 SoC FPGA MMUART_0. Lub DIP switch1 ntawm SmartFusion2 Advanced Development Kit tuaj yeem siv los xaiv seb puas yuav ua haujlwm rau SPI flash ntaus ntawv lossis ua tiav cov cai los ntawm DDR nco.

Yog tias daim ntawv thov ua tiav lub hom phiaj muaj nyob rau hauv SPI flash ntaus ntawv, cov cai shadowing los ntawm SPI flash ntaus ntawv mus rau DDR nco yog pib ntawm lub zog-up. Lub tshuab khau raj pib pib lub MDDR, luam cov duab los ntawm SPI flash ntaus ntawv rau DDR nco, thiab remaps DDR nco qhov chaw rau 0x00000000 los ntawm kev ua kom lub Cortex-M3 processor nyob rau hauv pib dua. Tom qab lub tshuab khau raj tso tawm Cortex-M3 rov pib dua, Cortex-M3 ua tiav daim ntawv thov phiaj los ntawm DDR nco.

FIC_0 tau teeb tsa hauv hom qhev kom nkag mus rau MSS SPI_0 los ntawm FPGA ntaub AHB tus tswv. MDDR AXI interface (DDR_FIC) tau qhib kom nkag mus rau DDR nco los ntawm FPGA ntaub AXI tus tswv.

Daim duab 4 qhia cov ncauj lus kom ntxaws daim duab qhia ntawm tus qauv demo.
Daim duab 4 • Code Shadowing – Hardware Boot Engine Demo Block Diagram

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-04

Boot Cav
Qhov no yog qhov tseem ceeb ntawm txoj cai shadowing demo uas theej daim ntawv thov daim duab los ntawm SPI flash ntaus ntawv mus rau DDR nco. Lub tshuab khau raj ua haujlwm hauv qab no:

  1. Pib MDDR rau kev nkag mus rau DDR3 ntawm 320 MHz los ntawm kev ua kom lub Cortex-M3 processor hauv kev pib dua.
  2. Luam lub hom phiaj daim ntawv thov duab los ntawm SPI flash nco ntaus ntawv rau DDR nco siv AXI tus tswv hauv FPGA ntaub los ntawm MDDR AXI interface.
  3. Remapping DDR nco pib chaw nyob los ntawm 0xA0000000 mus rau 0x00000000 los ntawm kev sau ntawv rau DDR_CR system sau npe.
  4. Tso rov pib dua rau Cortex-M3 processor kom khau raj ntawm DDR nco.

Daim duab 5 qhia tau hais tias demo tsim ntws.
Daim duab 5 • Sab saum toj-Level Block Diagram

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-05

Daim duab 6 • Design Flow for Hardware Boot Engine Method

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-06

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-07

Tsim Lub Hom Phiaj Daim Ntawv Thov Duab rau DDR Nco
Ib daim duab uas tuaj yeem ua tiav los ntawm DDR lub cim xeeb yog yuav tsum tau khiav lub demo. Siv qhov "production-execute-in-place-externalDDR.ld" linker piav qhia file uas yog suav nrog hauv kev tsim files los tsim daim ntawv thov duab. Qhov linker piav qhia file txhais DDR lub cim xeeb pib qhov chaw nyob li 0x00000000 txij li thaum lub bootloader / khau raj cav ua lub DDR nco remapping ntawm 0xA0000000 rau 0x00000000. Cov ntawv txuas txuas tsim cov duab daim ntawv thov nrog cov lus qhia, cov ntaub ntawv, thiab BSS ntu hauv lub cim xeeb uas nws qhov chaw pib yog 0x00000000. Ib qho yooj yim lub teeb-emitting diode (LED) blinking, timer thiab hloov raws li cuam tshuam tiam daim ntawv thov daim duab file yog muab rau no demo.

SPI Flash Loader
SPI flash loader yog siv los thauj cov on-board SPI flash nco nrog lub hom phiaj daim ntawv thov daim duab los ntawm tus tswv PC los ntawm MMUART_0 interface. Lub Cortex-M3 processor ua rau tsis muaj rau cov ntaub ntawv los ntawm MMUART_0 interface thiab pib lub peripheral DMA (PDMA) los sau cov ntaub ntawv buffered rau hauv SPI flash los ntawm MSS_SPI0.

Si laim Demo
Lub demo qhia tau hais tias yuav ua li cas thauj daim ntawv thov duab hauv SPI flash thiab ua tiav daim ntawv thov daim duab los ntawm sab nraud DDR nco. Nws muab ib tug example application image “sample_image_DDR3.bin". Cov duab no qhia txog cov lus txais tos thiab timer cuam tshuam cov lus ntawm lub serial console thiab blinks LED1 rau LED8 ntawm SmartFusion2 Advanced Development Kit. Txhawm rau pom GPIO cuam tshuam cov lus ntawm lub serial console, nias SW2 lossis SW3 hloov.

Kev teeb tsa Demo Design
Cov kauj ruam hauv qab no piav qhia yuav ua li cas teeb tsa lub demo rau SmartFusion2 Advanced Development Kit board:

  1. Txuas lub party PC rau J33 Connector siv USB A rau mini-B cable. Lub USB rau UART choj tsav tsheb tau raug kuaj pom. Txheeb xyuas yog tias qhov kev tshawb pom tau ua nyob rau hauv tus tswj ntaus ntawv raws li qhia hauv daim duab 7.
  2. Yog tias USB tsav tsheb tsis raug kuaj pom tau, nruab tus tsav tsheb USB.
  3. Rau serial davhlau ya nyob twg kev sib txuas lus los ntawm FTDI mini USB cable, nruab FTDI D2XX tsav tsheb. Rub tawm cov tsav tsheb thiab cov lus qhia kev teeb tsa los ntawm:
    http://www.microsemi.com/soc/documents/CDM_2.08.24_WHQL_Certified.zip.
    Daim duab 7 • USB rau UART Choj Tsav Tsheb
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-08
  4. Txuas cov jumpers ntawm SmartFusion2 Advanced Development Kit board, raws li qhia hauv Table 2.
    Ceev faj: Hloov OFF lub zog hloov pauv, SW7 thaum txuas cov jumpers.
    Table 2 • SmartFusion2 Advanced Development Kit Jumper Settings
    Jumper Pin (los ntawm) Pin (To) Cov lus pom
    J116,J353,J354,J54 1 2 Cov no yog lub neej ntawd jumper nqis ntawm Advanced Development Kit Board. Xyuas kom tseeb tias cov jumpers tau teeb tsa raws li.
    j123 ua 2 3
    J124,J121,J32 1 2 JTAG programming los ntawm FTDI
    j118,j 119 1 2 Programming SPI Flash
  5. Hauv SmartFusion2 Advanced Development Kit, txuas lub hwj huam mov mus rau J42 connector.
    Daim duab 8. qhia txog kev teeb tsa lub rooj tsavxwm rau kev khiav cov cai shadowing los ntawm SPI flash rau DDR3 demo ntawm SmartFusion2 Advanced Development Kit.
    Daim duab 8 • SmartFusion2 Advanced Development Kit Setup
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-09

SPI Flash Loader thiab Code Shadowing Demo GUI
Lub GUI yuav tsum tau khiav cov code shadowing demo. SPI Flash Loader thiab Code Shadowing Demo GUI yog ib qho yooj yim graphic neeg siv interface uas khiav ntawm tus tswv PC los ua haujlwm rau SPI flash thiab khiav cov code shadowing demo ntawm SmartFusion2 Advanced Development Kit. UART yog kev sib txuas lus raws tu qauv ntawm tus tswv PC thiab SmartFusion2 Advanced Development Kit. Nws kuj tseem muab ntu Serial Console los luam tawm cov lus debug tau txais los ntawm daim ntawv thov dhau UART interface.
Daim duab 9. qhia txog SPI Flash Loader thiab Code Shadowing Demo Window.
Daim duab 9 • SPI Flash Loader thiab Code Shadowing Demo Window

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-10

GUI txhawb nqa cov yam ntxwv hauv qab no:

  • Program SPI Flash: Programs duab file hauv SPI flash.
  • Program thiab Code Shadowing los ntawm SPI Flash rau DDR: Programs duab file rau hauv SPI flash, theej nws mus rau DDR nco, thiab khau raj cov duab los ntawm DDR nco.
  • Program thiab Code Shadowing los ntawm SPI Flash rau SDR: Programs duab file rau hauv SPI flash, luam nws mus rau SDR nco, thiab khau raj cov duab los ntawm SDR nco.
  • Code Shadowing rau DDR: Luam cov duab uas twb muaj lawm file los ntawm SPI flash rau DDR nco thiab khau raj cov duab los ntawm DDR nco.
  • Code Shadowing rau SDR: Luam cov duab uas twb muaj lawm file los ntawm SPI flash rau SDR nco thiab khau raj cov duab los ntawm SDR nco. Nyem Pab kom paub ntau ntxiv ntawm GUI.

Khiav lub Demo Tsim rau Multi-Stage Boot Process Method
Cov kauj ruam hauv qab no piav qhia yuav ua li cas khiav lub demo tsim rau ntau-stage khau raj txheej txheem txheej txheem:

  1. Hloov ON lub hwj chim hloov, SW7.
  2. Program lub SmarFusion2 SoC FPGA ntaus ntawv nrog cov programming file muab nyob rau hauv tus tsim files (SF2_CodeShadowing_DDR3_DF\Programming Files\MultiStageBoot_meothod\CodeShadowing_top.stp siv FlashPro tsim software).
  3. Tua tawm SPI Flash Loader thiab Code Shadowing Demo GUI executable file muaj nyob rau hauv tus tsim files (SF2_CodeShadowing_DDR3_DF\GUI Executable\SF2_FlashLoader.exe).
  4. Xaiv qhov chaw nres nkoj COM uas tsim nyog (uas yog USB Serial tsav tau taw qhia) los ntawm COM Port nco-down daim ntawv teev npe.
  5. Nyem Txuas. Tom qab tsim qhov kev sib txuas, Txuas hloov mus rau Disconnect.
  6. Nyem Saib mus xaiv tus example phiaj executable duab file muab nrog tus tsim files
    (SF2_CodeShadowing_DDR3_DF/Sample Application Images/sample_image_DDR3.bin).
    Nco tseg: Txhawm rau tsim daim ntawv thov duab rau hauv file, saib “Appendix: Generating Executable Bin File” nyob rau nplooj 25.
  7. Khaws qhov chaw pib ntawm SPI flash nco ua lub neej ntawd ntawm 0x00000000.
  8. Xaiv qhov Program thiab Code Shadowing los ntawm SPI Flash rau DDR kev xaiv.
  9. Nyem Pib raws li qhia hauv daim duab 10 txhawm rau thauj cov duab ua tiav rau hauv SPI flash thiab code shadowing los ntawm DDR nco.
    Daim duab 10 • Pib lub Demo
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-11
  10. Yog hais tias SmartFusion2 SoC FPGA ntaus ntawv yog programmed nrog STAPL file nyob rau hauv uas MDDR tsis tau teeb tsa rau DDR nco ces nws pom cov lus yuam kev, raws li pom hauv daim duab 11.
    Daim duab 11 • Cov khoom siv tsis raug lossis lus xaiv
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-12
  11. Ntu Serial Console ntawm GUI qhia cov lus debug thiab pib programming SPI flash ntawm kev ua tiav kev tshem tawm SPI flash. Daim duab 12 qhia txog cov xwm txheej ntawm SPI flash sau
    Daim duab 12 • Flash Loading
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-13
  12. Ntawm qhov programming SPI flash ua tiav, lub bootloader khiav ntawm SmartFusion2 SoC FPGA luam daim ntawv thov duab los ntawm SPI flash rau DDR nco thiab khau raj daim ntawv thov duab. Yog cov duab muab sample_image_DDR3.bin raug xaiv, lub serial console qhia cov lus txais tos, hloov kev cuam tshuam thiab timer cuam tshuam cov lus raws li qhia hauv daim duab 13 ntawm nplooj ntawv 18 thiab daim duab 14 ntawm nplooj ntawv 18. Ib qho qauv LED khiav yog tshwm sim ntawm LED1 rau LED8 ntawm SmartFusion2 Advanced Development Kit.
  13. Nias SW2 thiab SW3 keyboards kom pom cov lus cuam tshuam ntawm serial console.
    Daim duab 13 • Khiav lub Hom Phiaj Daim Ntawv Thov Duab los ntawm DDR3 Nco
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-14Daim duab 14 • Timer thiab cuam tshuam cov lus hauv Serial Console
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-15

Khiav Hardware Boot Engine Method Design
Cov kauj ruam hauv qab no piav qhia yuav ua li cas khiav hardware khau raj cav txoj kev tsim:

  1. Hloov ON lub hwj chim hloov, SW7.
  2. Program lub SmarFusion2 SoC FPGA ntaus ntawv nrog cov programming file muab nyob rau hauv tus tsim files (SF2_CodeShadowing_DDR3_DF\Programming
    Files\HWBootEngine_method\CodeShadowing_Fabric.stp siv FlashPro tsim software).
  3. Txhawm rau program SPI Flash ua DIP hloov SW5-1 rau ON txoj haujlwm. Qhov kev xaiv no ua rau khau raj Cortex-M3 los ntawm eNVM. Nias SW6 kom rov pib dua SmartFusion2 ntaus ntawv.
  4. Tua tawm SPI Flash Loader thiab Code Shadowing Demo GUI executable file muaj nyob rau hauv tus tsim files (SF2_CodeShadowing_DDR3_DF\GUI Executable\SF2_FlashLoader.exe).
  5. Xaiv qhov chaw nres nkoj COM uas tsim nyog (uas yog USB Serial tsav tau taw qhia) los ntawm COM Port nco-down daim ntawv teev npe.
  6. Nyem Txuas. Tom qab tsim qhov kev sib txuas, Txuas hloov mus rau Disconnect.
  7. Nyem Saib mus xaiv tus example phiaj executable duab file muab nrog tus tsim files
    (SF2_CodeShadowing_DDR3_DF/Sample Application Images/sample_image_DDR3.bin).
    Nco tseg: Txhawm rau tsim daim ntawv thov duab rau hauv file, saib “Appendix: Generating Executable Bin File” nyob rau nplooj 25.
  8. Xaiv Hardware Boot Cav xaiv hauv Code Shadowing Method.
  9. Xaiv qhov Program SPI Flash xaiv los ntawm Options menu.
  10. Nyem Pib, raws li qhia hauv daim duab 15 txhawm rau thauj cov duab ua tiav rau hauv SPI flash.
    Daim duab 15 • Pib lub Demo
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-16
  11. Ntu Serial Console ntawm GUI qhia cov lus debug thiab cov xwm txheej ntawm SPI flash sau, raws li pom hauv daim duab 16.
    Daim duab 16 • Flash Loading
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-17
  12. Tom qab programming SPI flash ua tiav, hloov DIP hloov SW5-1 rau OFF txoj haujlwm. Qhov kev xaiv no ua rau khau raj Cortex-M3 processor los ntawm DDR nco.
  13. Nias SW6 kom rov pib dua SmartFusion2 ntaus ntawv. Lub tshuab khau raj luam tawm daim ntawv thov daim duab los ntawm SPI flash rau DDR nco thiab tso tawm rov qab mus rau Cortex-M3, uas khau raj daim ntawv thov duab los ntawm DDR nco. Yog tias cov duab muab "sample_image_DDR3.bin" yog loaded rau SPI flash, serial console qhia cov lus txais tos, hloov kev cuam tshuam (nias SW2 lossis SW3) thiab timer cuam tshuam cov lus raws li qhia hauv daim duab 17 thiab cov qauv LED khiav yog tshwm sim ntawm LED1 rau LED8 ntawm SmartFusion2 Advanced Cov khoom siv txhim kho.
    Daim duab 17 • Khiav lub Hom Phiaj Daim Ntawv Thov Duab los ntawm DDR3 Nco
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-18

Xaus
Qhov no demo qhia txog lub peev xwm ntawm SmartFusion2 SoC FPGA ntaus ntawv los cuam tshuam nrog DDR nco thiab khiav cov duab ua tau zoo los ntawm DDR nco los ntawm shadowing code los ntawm SPI flash nco ntaus ntawv. Nws kuj tseem qhia tau hais tias ob txoj hauv kev ntawm kev ua raws li txoj cai shadowing ntawm SmartFusion2 ntaus ntawv.

Cov ntawv ntxiv: DDR3 Configurations

Cov duab hauv qab no qhia txog DDR3 teeb tsa.
Daim duab 18 • General DDR Configuration Settings

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-19

Daim duab 19 • DDR Memory Initialization Settings

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-20

Daim duab 20 • DDR Memory Timing Settings

Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-21

Daim Ntawv Ntxiv: Tsim Cov Txiaj Ntsig executable Bin File

Lub executable bin file yuav tsum tau ua qhov kev pab cuam SPI flash rau kev khiav cov code shadowing demo. Los tsim lub executable rau hauv file los ntawm "sample_image_DDR3 "Soft Console, ua cov kauj ruam hauv qab no:

  1. Tsim cov Soft Console project nrog cov linker tsab ntawv ntau lawm-execute-in-place-external DDR.
  2. Ntxiv rau Soft Console installation txoj kev, rau example, C:\Microsemi\Libero_v11.7\SoftConsole\Sourcery-G++\bin, mus rau 'Environment Variables' raws li qhia hauv daim duab 21.
    Daim duab 21 • Ntxiv Soft Console Installation Path
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-22
  3. Ob-nias lub batch file Bin-File-Generator.bat nyob ntawm:
    SoftConsole/CodeShadowing_MSS_CM3/Sample_image_DDR3 folder, raws li pom hauv daim duab 22.
    Daim duab 22 • Bin File Lub tshuab hluav taws xob
    Microsemi-SmartFusion2-SoC-FPGA-Code-Shadowing-from-SPI-Flash-rau-DDR-Memory-23
  4. Lub Bin-File-Generator tsim sample_image_DDR3.bin file.

Kev kho keeb kwm

Cov lus hauv qab no qhia txog kev hloov pauv tseem ceeb hauv daim ntawv no rau txhua qhov kev hloov kho.

Kev kho dua Hloov
Hloov kho 7
(Lub Peb Hlis 2016)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.7 software tso tawm (SAR 77816).
Hloov kho 6
(Lub Kaum Hli 2015)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.6 software tso tawm (SAR 72424).
Hloov kho 5
(Lub Cuaj Hlis 2014)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.4 software tso tawm (SAR 60592).
Hloov kho 4
(May 2014)		 Hloov kho cov ntaub ntawv rau Libero SoC 11.3 software tso tawm (SAR 56851).
Hloov kho 3
(Lub Kaum Ob Hlis 2013)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.2 software tso tawm (SAR 53019).
Hloov kho 2
(May 2013)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.0 software tso tawm (SAR 47552).
Hloov kho 1
(Lub Peb Hlis 2013)		 Hloov kho cov ntaub ntawv rau Libero SoC v11.0 beta SP1 software tso tawm (SAR 45068).

Khoom txhawb

Microsemi SoC Products Group rov qab nws cov khoom nrog ntau yam kev pabcuam, suav nrog Kev Pabcuam Cov Neeg Siv Khoom, Lub Chaw Pabcuam Cov Neeg Siv Khoom, a website, electronic mail, thiab chaw muag khoom thoob ntiaj teb. Cov ntawv txuas ntxiv no muaj cov ntaub ntawv hais txog kev tiv tauj Microsemi SoC Products Group thiab siv cov kev pabcuam txhawb nqa no.

Kev Pabcuam Cov Neeg Siv Khoom
Hu rau Lub Chaw Pabcuam Cov Neeg Siv Khoom rau kev txhawb nqa cov khoom lag luam uas tsis yog khoom siv, xws li cov nqi khoom, kev hloov khoom dua tshiab, cov ntaub ntawv hloov tshiab, kev txiav txim raws li txoj cai, thiab kev tso cai.

  • Los ntawm North America, hu rau 800.262.1060
  • Los ntawm lwm lub ntiaj teb, hu rau 650.318.4460
  • Fax, los ntawm txhua qhov chaw hauv ntiaj teb, 408.643.6913

Customer Technical Support Center
Microsemi SoC Products Group ua haujlwm rau nws Lub Chaw Pabcuam Cov Neeg Siv Khoom nrog cov kws tshaj lij engineers uas tuaj yeem pab teb koj cov khoom kho vajtse, software, thiab tsim cov lus nug txog Microsemi SoC Cov Khoom. Lub Chaw Pabcuam Cov Neeg Siv Khoom siv sijhawm ntau heev los tsim cov ntawv thov, cov lus teb rau cov lus nug txog kev tsim qauv, cov ntaub ntawv ntawm cov teeb meem paub, thiab ntau yam FAQs. Yog li, ua ntej koj tiv tauj peb, thov mus saib peb cov kev pabcuam hauv online. Nws zoo li peb twb tau teb koj cov lus nug.

Kev pab txhawb nqa

Rau Microsemi SoC Cov Khoom Txhawb Nqa, mus saib
http://www.microsemi.com/products/fpga-soc/design-support/fpga-soc-support.

Webqhov chaw
Koj tuaj yeem tshawb xyuas ntau yam ntawm cov ntaub ntawv kev tshaj lij thiab tsis yog txheej txheem ntawm Microsemi SoC Products Group lub vev xaib, ntawm http://www.microsemi.com/products/fpga-soc/fpga-and-soc.

Hu rau Customer Technical Support Center
Cov kws tshaj lij engineers ua haujlwm hauv Technical Support Center. Lub Chaw Pabcuam Kev Pabcuam tuaj yeem tiv tauj los ntawm email lossis los ntawm Microsemi SoC Products Group webqhov chaw.

Email
Koj tuaj yeem sib txuas lus koj cov lus nug txog kev ua haujlwm rau peb qhov chaw nyob email thiab tau txais cov lus teb rov qab los ntawm email, fax, lossis xov tooj. Tsis tas li, yog tias koj muaj teeb meem tsim, koj tuaj yeem xa email rau koj tus qauv tsim files tau txais kev pab. Peb niaj hnub saib xyuas tus email account txhua hnub. Thaum xa koj qhov kev thov rau peb, thov nco ntsoov suav nrog koj lub npe tag nrho, lub tuam txhab npe, thiab koj cov ntaub ntawv tiv toj kom ua tau zoo ntawm koj qhov kev thov.
Cov kev txhawb nqa email chaw nyob yog soc_tech@microsemi.com.

Kuv Cases
Microsemi SoC Products Group cov neeg siv khoom tuaj yeem xa thiab taug qab cov xwm txheej hauv online los ntawm kev mus rau My Cases.

Sab nraum Teb Chaws Asmeskas
Cov neeg siv khoom xav tau kev pab sab nraud Tebchaws Meskas cov sijhawm tuaj yeem hu rau kev txhawb nqa ntawm email (soc_tech@microsemi.com) lossis hu rau lub chaw muag khoom hauv zos. Mus saib Txog Peb rau cov npe chaw muag khoom thiab cov neeg koom tes.

ITAR Technical Support
Rau kev txhawb nqa ntawm RH thiab RT FPGAs uas tau tswj hwm los ntawm International Traffic in Arms Regulations (ITAR), tiv tauj peb ntawm soc_tech@microsemi.com. Xwb, hauv My Cases, xaiv Yes hauv ITAR drop-down list. Rau ib daim ntawv teev tag nrho ntawm ITAR-tswj Microsemi FPGAs, mus saib ITAR web nplooj.

Microsemi Corporate Lub Chaw Haujlwm
Ib Enterprise, Aliso Viejo,
CA 92656 Tebchaws Asmeskas
Hauv Tebchaws Meskas: +1 (800)
713-4113 Ib
USA: +1 949-380-6100 Ib
Kev muag khoom: +1 949-380-6136 Ib
Fax: + 1 949-215-4996 Ib
E-mail: sales.support@microsemi.com
© 2016 Microsemi Corporation.
Txhua txoj cai. Microsemi thiab Microsemi logo yog cov cim lag luam ntawm Microsemi Corporation.
Tag nrho lwm cov cim lag luam thiab cov cim kev pabcuam yog cov cuab yeej ntawm lawv cov tswv.

Microsemi Corporation (Nasdaq: MSCC) muaj cov ntaub ntawv nthuav dav ntawm cov khoom siv hluav taws xob thiab cov kev daws teeb meem rau kev sib txuas lus, kev tiv thaiv & kev ruaj ntseg, aerospace thiab kev lag luam kev lag luam. Cov khoom lag luam suav nrog kev ua haujlwm siab thiab hluav taws xob-hardened analog sib xyaw-cim sib xyaw ua ke, FPGAs, SoCs thiab ASICs; cov khoom tswj fais fab; sij hawm thiab synchronization pab kiag li lawm thiab lub sij hawm meej daws teeb meem, teeb lub ntiaj teb no tus qauv rau lub sij hawm; lub suab ua khoom siv; RF daws; discrete Cheebtsam; kev lag luam cia thiab kev sib txuas lus daws teeb meem, kev ruaj ntseg technologies thiab scalable anti-tampyog cov khoom; Ethernet kev daws teeb meem; Fais fab-over-Ethernet ICs thiab midspans; raws li kev cai tsim muaj peev xwm thiab kev pabcuam. Microsemi yog lub hauv paus hauv Aliso Viejo, Calif, thiab muaj kwv yees li 4,800 tus neeg ua haujlwm thoob ntiaj teb. Kawm ntxiv ntawm www.microsemi.com.

Microsemi tsis muaj kev lav phib xaub, kev sawv cev, lossis kev lees paub txog cov ntaub ntawv muaj nyob hauv no lossis qhov tsim nyog ntawm nws cov khoom thiab cov kev pabcuam rau ib lub hom phiaj tshwj xeeb, lossis Microsemi tsis lees paub txog kev lav phib xaub txhua yam uas tshwm sim ntawm daim ntawv thov lossis siv cov khoom lossis cov khoom siv. Cov khoom muag hauv qab no thiab lwm yam khoom muag los ntawm Microsemi tau raug kuaj sim thiab yuav tsum tsis txhob siv nrog rau lub hom phiaj-cov cuab yeej tseem ceeb lossis kev siv. Txhua qhov kev ua tau zoo tshwj xeeb yog ntseeg tau tias muaj kev ntseeg siab tab sis tsis tau lees paub, thiab Cov Neeg Yuav Khoom yuav tsum ua thiab ua kom tiav tag nrho cov kev ua tau zoo thiab lwm yam kev sim ntawm cov khoom, ib leeg thiab ua ke nrog, lossis muab tso rau hauv, txhua yam khoom kawg. Cov neeg yuav khoom yuav tsum tsis txhob cia siab rau cov ntaub ntawv thiab kev ua haujlwm tshwj xeeb lossis cov kev txwv uas muab los ntawm Microsemi. Nws yog tus neeg yuav khoom lub luag haujlwm los txiav txim siab txog qhov tsim nyog ntawm cov khoom lag luam thiab kuaj thiab txheeb xyuas qhov qub. Cov ntaub ntawv muab los ntawm Microsemi hereunder yog muab "raws li yog, qhov twg yog" thiab nrog rau tag nrho cov faults, thiab tag nrho cov kev pheej hmoo cuam tshuam nrog cov ntaub ntawv no yog tag nrho nrog tus neeg yuav khoom. Microsemi tsis tso cai, qhia meej lossis implicitly, rau ib tog twg muaj cai patent, ntawv tso cai, lossis lwm yam IP txoj cai, txawm hais tias hais txog cov ntaub ntawv no nws tus kheej lossis txhua yam uas tau piav qhia los ntawm cov ntaub ntawv no. Cov ntaub ntawv muab rau hauv daim ntawv no yog tus tswv ntawm Microsemi, thiab Microsemi muaj txoj cai los hloov pauv cov ntaub ntawv hauv daim ntawv no lossis rau cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom.

Cov ntaub ntawv / Cov ntaub ntawv

Microsemi SmartFusion2 SoC FPGA Code Duab ntxoov ntxoo los ntawm SPI Flash rau DDR Nco [ua pdf] Tus tswv phau ntawv
SmartFusion2 SoC FPGA Code Duab ntxoov ntxoo los ntawm SPI Flash rau DDR Nco, SmartFusion2 SoC, FPGA Code Duab ntxoov ntxoo los ntawm SPI Flash rau DDR Nco, Flash rau DDR Nco

Cov ntaub ntawv

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