AN 795 Kev Siv Cov Lus Qhia rau 10G
Ethernet Subsystem Siv Tsawg Latency 10G MAC
Cov neeg siv phau ntawv qhia
AN 795 Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC
AN 795: Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC Intel FPGA® IP hauv Intel ® Arria® 10 Devices
Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC Intel ® FPGA IP hauv Intel ® Arria® 10 Devices
Cov kev coj ua qhia koj yuav siv Intel's Low Latency 10G Media Access Controller (MAC) thiab PHY IPs.
Daim duab 1. Intel® Arria® 10 Tsawg Latency Ethernet 10G MAC System
Table 1. Intel® Arria® 10 Tsawg Latency Ethernet 10G MAC Tsim
Cov lus no teev tag nrho Intel ® Arria® 10 tsim rau Low Latency Ethernet 10G MAC Intel FPGA IP.
| Tsim Example | MAC Variant | PHY | Cov khoom siv txhim kho |
| 10GBase-R Ethernet | 10g ua | Native PHY | Intel Arria 10 GX Transceiver SI |
| 10GBase-R Sau npe hom Ethernet |
10g ua | Native PHY | Intel Arria 10 GX Transceiver SI |
| XAUI Ethernet | 10g ua | XAUI PHY | Intel Arria 10 GX FPGA |
| 1G / 10G Ethernet | 1G / 10G | 1G / 10GbE thiab 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G / 10G Ethernet nrog 1588 | 1G / 10G | 1G / 10GbE thiab 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet | 10M / 100M / 1G / 10G | 1G / 10GbE thiab 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 10M / 100M / 1G / 10G Ethernet nrog 1588 |
10M / 100M / 1G / 10G | 1G / 10GbE thiab 10GBASE-KR PHY | Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G Ethernet | 1G / 2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G Ethernet nrog 1588 | 1G / 2.5G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 1G / 2.5G / 10G Ethernet | 1G/2.5G/10G | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
| 10G USXGMII Ethernet | 1G/2.5G/5G/10G (USXGMII) | 1G/2.5G/5G/10G Multi-rate Ethernet PHY |
Intel Arria 10 GX Transceiver SI |
Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais cov khoom siv tshwj xeeb tshaj tawm ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
1. Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC Intel® FPGA IP hauv Intel® Arria® 10 Devices
683347 Nws 2020.10.28 ib
Nco tseg:
Koj tuaj yeem nkag mus rau txhua tus qauv tsim los ntawm Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor hauv Intel Quartus Prime software, tshwj tsis yog rau XAUI Ethernet siv tsim. Koj tuaj yeem tau txais XAUI Ethernet siv tsim los ntawm Lub Khw Tsim.
Intel muab cais MAC thiab PHY IPs rau 10M rau 1G Multi-rate Ethernet subsystems kom ntseeg tau tias kev siv tau yooj yim. Koj tuaj yeem instantiate Qhov Tsawg Latency Ethernet 10G MAC Intel FPGA IP nrog 1G / 2.5G / 5G / 10G Multi-rate Ethernet PHY, Intel Arria 10 1G / 10GbE thiab 10GBASE-KR PHY, lossis XAUI PHY thiab Intel Arria 10 PHY rau Native ua raws cov kev xav tau sib txawv.
Cov ntaub ntawv ntsig txog
- Tsawg Latency Ethernet 10G MAC Intel FPGA IP Tus Neeg Siv Qhia
Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing MAC IP. - Tsawg Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Tsim Example User Guide
Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing MAC tsim examples. - Intel Arria 10 Transceiver PHY Tus Neeg Siv Qhia
Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing PHY IP. - Tsawg Latency Ethernet 10G MAC Debug Checklist
- AN 699: Siv Altera Ethernet Design Toolkit
Cov cuab yeej no yuav pab koj teeb tsa thiab khiav Ethernet siv cov qauv tsim nrog rau kev debug tej teeb meem ntsig txog Ethernet. - Fault Tree Analysis rau Tsawg Latency 10G MAC Cov Ntaub Ntawv Kev Ua Txhaum Cai
- Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
Muab cov files rau tus qauv siv.
1.1. Tsawg Latency Ethernet 10G MAC thiab Intel Arria 10 Transceiver Native PHY Intel FPGA IPs
Koj tuaj yeem teeb tsa Intel Arria 10 Transceiver Native PHY Intel FPGA IP los siv 10GBASE-R PHY nrog Ethernet tshwj xeeb lub cev txheej khiav ntawm 10.3125 Gbps cov ntaub ntawv tus nqi raws li tau hais tseg hauv Tshooj 49 ntawm IEEE 802.3-2008 specification.
Qhov kev teeb tsa no muab XGMII rau Low Latency Ethernet 10G MAC Intel FPGA IP thiab siv ib leeg-channel 10.3 Gbps PHY muab kev sib txuas ncaj qha rau SFP + optical module siv SFI hluav taws xob specification.
Intel muab ob 10GBASE-R Ethernet subsystem tsim examples thiab koj tuaj yeem tsim cov qauv no dynamically siv Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Cov qauv tsim txhawb kev ua haujlwm simulation thiab kev sim kho vajtse ntawm cov khoom siv tsim Intel tsim.
Daim duab 2. Clocking thiab Reset Scheme rau Low Latency Ethernet 10G MAC thiab Intel Arria 10 Transceiver Native PHY hauv 10GBASE-R Design Example
Daim duab 3. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and Intel Arria 10 Transceiver Native PHY in 10GBASE-R Design Example Register Hom Enabled
Cov ntaub ntawv ntsig txog
Tsawg Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Tsim Example User Guide
Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing MAC tsim examples.
1.2. Tsawg Latency Ethernet 10G MAC thiab XAUI PHY Intel FPGA IPs
XAUI PHY Intel FPGA IP muab XGMII rau Low Latency Ethernet 10G MAC Intel FPGA IP thiab siv plaub txoj kab ntawm txhua qhov ntawm 3.125 Gbps ntawm PMD interface.
XAUI PHY yog ib qho kev siv lub cev tshwj xeeb ntawm 10 Gigabit Ethernet txuas tau teev tseg hauv IEEE 802.3ae-2008 specification.
Koj tuaj yeem tau txais cov qauv siv rau 10GbE subsystem siv siv Low Latency Ethernet 10G MAC thiab XAUI PHY Intel FPGA IPs los ntawm Tsim Khw. Tus qauv tsim txhawb kev ua haujlwm simulation thiab kuaj kho vajtse ntawm cov khoom tsim Intel tsim.
Daim duab 4. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and XAUI PHY Reference Design 
Cov ntaub ntawv ntsig txog
- Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
Muab cov files rau tus qauv siv. - AN 794: Arria 10 Low Latency Ethernet 10G MAC thiab XAUI PHY Reference Design
1.3. Tsawg Latency Ethernet 10G MAC thiab 1G / 10GbE thiab 10GBASEKR PHY Intel Arria 10 FPGA IPs
1G / 10GbE thiab 10GBASE-KR PHY Intel Arria 10 FPGA IP muab MII, GMII thiab XGMII rau Low Latency Ethernet 10G MAC Intel FPGA IP.
1G / 10GbE thiab 10GBASE-KR PHY Intel Arria 10 FPGA IP siv ib qho channel 10Mbps / 100Mbps / 1Gbps / 10Gbps serial PHY. Cov qauv tsim muab kev sib txuas ncaj qha rau 1G / 10GbE dual ceev SFP + pluggable modules, 10M–10GbE 10GBASE-T thiab 10M / 100M / 1G / 10GbE 1000BASE-T tooj liab sab nraud PHY li, lossis nti-rau-chip interfaces. Cov IP cores no txhawb nqa rov kho dua 10Mbps / 100Mbps / 1Gbps / 10Gbps cov ntaub ntawv tus nqi.
Intel muab dual-ceev 1G / 10GbE thiab ntau-ceev 10Mb / 100Mb / 1Gb / 10GbE tsim examples thiab koj tuaj yeem tsim cov qauv no dynamically siv lub Low Latency
Ethernet 10G MAC Intel FPGA IP parameter editor. Cov qauv tsim txhawb kev ua haujlwm simulation thiab kev sim kho vajtse ntawm cov khoom tsim Intel tsim.
Kev siv ntau-ceev Ethernet subsystem siv 1G/10GbE lossis 10GBASE-KR PHY Intel Arria 10 FPGA IP tsim yuav tsum tau siv phau ntawv SDC txwv rau sab hauv PHY IP moos thiab moos domain hla kev tuav. Xa mus rau altera_eth_top.sdc file hauv kev tsim example kom paub ntau ntxiv txog qhov yuav tsum tau tsim_generated_clock, set_clock_groups thiab set_false_path SDC txwv.
Daim duab 5. Clocking thiab Reset Scheme rau Low Latency Ethernet 10G MAC thiab Intel Arria 10 1G/10GbE thiab 10GBASE-KR Design Example (1G/10GbE Mode)
Daim duab 6. Clocking thiab Reset Scheme rau Low Latency Ethernet 10G MAC thiab Intel Arria 10 1G/10GbE thiab 10GBASE-KR Design Example (10Mb/100Mb/1Gb/10GbE hom)
Cov ntaub ntawv ntsig txog
Tsawg Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Tsim Example User Guide
Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing MAC tsim examples.
1.4. Tsawg Latency Ethernet 10G MAC thiab 1G / 2.5G / 5G / 10G MultiRate Ethernet PHY Intel FPGA IPs
1G/2.5G/5G/10G Multi-Rate Ethernet PHY Intel FPGA IP rau Intel Arria 10 li muab GMII thiab XGMII rau Low Latency Ethernet 10G MAC Intel FPGA IP.
Lub 1G / 2.5G / 5G / 10G Multi-Rate Ethernet PHY Intel FPGA IP rau Intel Arria 10 li siv ib leeg-channel 1G / 2.5G / 5G / 10Gbps serial PHY. Tus tsim muab kev sib txuas ncaj qha rau 1G / 2.5GbE dual ceev SFP + pluggable modules, MGBASE-T thiab NBASE-T tooj liab sab nraud PHY li, lossis chip-to-chip interfaces. Cov IPs no txhawb nqa 1G / 2.5G / 5G / 10Gbps cov ntaub ntawv tus nqi.
Intel muab dual-ceev 1G / 2.5GbE, ntau-ceev 1G / 2.5G / 10GbE MGBASE-T, thiab multispeed 1G / 2.5G / 5G / 10GbE MGBASE-T tsim examples thiab koj tuaj yeem tsim cov qauv no dynamically siv Low Latency Ethernet 10G MAC Intel FPGA IP parameter editor. Cov qauv tsim txhawb kev ua haujlwm simulation thiab kev sim kho vajtse ntawm cov khoom tsim Intel tsim.
Daim duab 7. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G Mode)
Rau ntau qhov ceev 1G / 2.5GbE thiab 1G / 2.5G / 10GbE MBASE-T Ethernet subsystem kev siv siv 1G / 2.5G / 5G / 10G Multi-rate Ethernet PHY Intel FPGA IP, Intel xav kom koj luam cov transceiver reconfiguration module (alt_mge_rrfg_ sv) muab nrog tus tsim example. Qhov no module reconfigures lub transceiver channel ceev ntawm 1G rau 2.5G, los yog mus rau 10G, thiab vice versa.
Kev siv ntau qhov ceev 1G / 2.5GbE thiab 1G / 2.5G / 10GbE MBASE-T Ethernet subsystem kev siv kuj yuav tsum tau siv phau ntawv SDC txwv rau PHY IP moos.
thiab moos domain hla kev tuav. Xa mus rau altera_eth_top.sdc file hauv kev tsim example kom paub ntau ntxiv txog qhov yuav tsum tau tsim_generated_clock, set_clock_groups thiab set_false_path SDC txwv.
Daim duab 8. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/ 2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/10GbE MBASE-T Mode) 
Daim duab 9. Clocking and Reset Scheme for Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-Rate Ethernet PHY Design Example (1G/2.5G/5G/10GbE NBASE-T Mode)
Cov ntaub ntawv ntsig txog
Tsawg Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Tsim Example User Guide Muab cov ncauj lus kom ntxaws txog instantiating thiab parameterizing MAC tsim examples.
1.5. Cov Ntaub Ntawv Hloov Kho Keeb Kwm rau AN 795: Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC Intel FPGA IP hauv Intel Arria 10 Devices
| Cov ntaub ntawv Version | Hloov |
| 2020.10.28 | • Rebranded li Intel. • Hloov npe cov ntaub ntawv raws li AN 795: Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC Intel FPGA IP hauv Intel Arria 10 Devices. |
| Hnub tim | Version | Hloov |
| Lub Ob Hlis-17 | 2017.02.01 | Kev tso tawm thawj zaug. |
AN 795: Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg
Latency 10G MAC Intel ® FPGA IP hauv Intel® Arria® 10 Devices
Online Version
Xa lus tawm tswv yim
PIB: 683347
Version: 2020.10.28
Cov ntaub ntawv / Cov ntaub ntawv
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intel AN 795 Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC [ua pdf] Cov neeg siv phau ntawv qhia AN 795 Kev Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC, AN 795, Siv Cov Lus Qhia rau 10G Ethernet Subsystem Siv Tsawg Latency 10G MAC, Ethernet Subsystem Siv Tsawg Latency 10G MAC, Tsawg Latency 10G MAC |
