MICROCHIP DDR AXI4 Arbiter

Iṣaaju: Boṣewa Ilana Ilana AXI4-Stream nlo Titunto si imọ-ọrọ ati Ẹrú. Awọn ọrọ-ọrọ Microchip deede ti a lo ninu iwe yii jẹ Olupilẹṣẹ ati Àkọlé, lẹsẹsẹ.
Akopọ: Tabili ti o tẹle n pese akopọ ti awọn abuda Arbiter DDR AXI4.

Iwa	Iye
Ẹya mojuto	DDR AXI4 Arbiter v2.2
Awọn idile Ẹrọ atilẹyin	–
Ti ṣe atilẹyin Iwe-aṣẹ Sisan Irinṣẹ	–

Awọn ẹya: DDR AXI4 Arbiter ni awọn ẹya bọtini wọnyi:

• IP mojuto gbọdọ fi sori ẹrọ si Katalogi IP ti sọfitiwia SoC Libero.
• A ṣe atunto mojuto, ti ipilẹṣẹ, ati lẹsẹkẹsẹ laarin ohun elo SmartDesign fun ifisi ninu atokọ iṣẹ akanṣe Libero.

Lilo Ẹrọ ati Ṣiṣẹ:

Awọn alaye ẹrọ	Idile	Ẹrọ	Oro	Iṣe (MHz)
LUTs DFF Ramu LSRAM SRAM Math ohun amorindun Chip Globals	PolarFire	MPF300T-1	5411 4202	266

Apejuwe iṣẹ-ṣiṣe

Apejuwe isẹ: Yi apakan apejuwe awọn alaye imuse ti DDR_AXI4_Arbiter. Nọmba ti o tẹle n ṣe afihan aworan-pin-jade ti oke-ipele ti DDR AXI4 Arbiter.

DDR_AXI4_Arbiter Parameters ati Interface awọn ifihan agbara

Eto Iṣeto:
Awọn eto atunto fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.

Awọn igbewọle ati Awọn ifihan agbara Ijade:
Awọn ifihan agbara titẹ sii ati iṣelọpọ fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.

Awọn aworan atọka akoko
Awọn aworan akoko fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.

Testbench

Iṣaṣeṣe:
Awọn alaye kikopa fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.
Àtúnyẹwò History
Itan atunyẹwo fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.
Microchip FPGA Support
Alaye Atilẹyin Microchip FPGA fun DDR_AXI4_Arbiter ko ni pato ninu iwe yii.

Awọn ilana Lilo ọja

1. Fi sori ẹrọ DDR AXI4 Arbiter v2.2 si Katalogi IP ti sọfitiwia SoC Libero.
2. Ṣe atunto, ṣe ina ati ṣe imudara mojuto laarin ohun elo SmartDesign fun ifisi ninu atokọ iṣẹ akanṣe Libero.

Ifaara (Beere ibeere kan)

Awọn iranti jẹ apakan pataki ti eyikeyi fidio aṣoju ati ohun elo eya aworan. Wọn lo fun fifi gbogbo awọn fireemu fidio silẹ nigbati iranti agbegbe ti FPGA ko to lati di gbogbo fireemu naa mu. Nigbati awọn kika pupọ ba wa ati kikọ ti awọn fireemu fidio sinu DDR, yoo nilo adari kan lati ṣe idajọ laarin awọn ibeere pupọ. DDR AXI4 Arbiter IP pese awọn ikanni kikọ 8 lati kọ awọn buffer fireemu sinu iranti DDR ita ati awọn ikanni kika 8 lati ka awọn fireemu lati iranti ita. Idajọ idajọ naa da lori ipilẹ-wa akọkọ, ipilẹ iṣẹ akọkọ. Ti awọn ibeere meji ba waye nigbakanna, ikanni pẹlu nọmba ikanni kekere yoo gba pataki. Arbiter sopọ si IP oludari DDR nipasẹ wiwo AXI4. DDR AXI4 Arbiter n pese wiwo Initiator AXI4 kan si awọn olutona lori-chip DDR. Adajọ ṣe atilẹyin awọn ikanni kikọ mẹjọ ati awọn ikanni kika mẹjọ. Àkọsílẹ naa ṣe idajọ laarin awọn ikanni kika mẹjọ lati pese iraye si ikanni kika AXI ni ọna akọkọ-wa, ọna iṣẹ akọkọ. Àkọsílẹ ṣe idajọ laarin awọn ikanni kikọ mẹjọ lati pese iraye si ikanni kikọ AXI ni ọna akọkọ-wa, ọna iṣẹ akọkọ. Gbogbo awọn ikanni kika-ati-kikọ mẹjọ ni pataki dogba. Ni wiwo Initiator AXI4 ti Arbiter IP le jẹ tunto fun ọpọlọpọ awọn iwọn data ti o wa lati awọn bit 64 si 512.
Pataki: Boṣewa Ilana AXI4-Stream nlo awọn ọrọ-ọrọ “Titunto” ati “Ẹrú”. Awọn ọrọ-ọrọ Microchip deede ti a lo ninu iwe yii jẹ Olupilẹṣẹ ati Àkọlé, lẹsẹsẹ.
Lakotan (Beere ibeere kan)
Tabili ti o tẹle n pese akopọ ti awọn abuda Arbiter DDR AXI4.

Table 1. DDR AXI4 Arbiter Abuda

Iwe yi kan si DDR AXI4 Arbiter v2.2.

• PolarFire® SoC
• PolarFire
• RTG4™
• IGLOO® 2
• SmartFusion® 2

Nilo Libero® SoC v12.3 tabi awọn idasilẹ nigbamii. IP le ṣee lo ni ipo RTL laisi iwe-aṣẹ eyikeyi. Fun alaye diẹ sii, wo DDR_AXI4_Arbiter.

Awọn ẹya ara ẹrọ (Beere ibeere kan)

DDR AXI4 Arbiter ni awọn ẹya bọtini wọnyi:

• Mẹjọ Kọ awọn ikanni
• Mẹjọ Ka awọn ikanni
• AXI4 Interface to DDR adarí
• Ìbú AXI4 atunto: 64, 128, 256, ati 512 die-die
• Iwọn Adirẹsi atunto: 32 si 64 die-die

Imuse ti IP Core ni Libero® Design Suite (Beere ibeere kan)
IP mojuto gbọdọ fi sori ẹrọ si Katalogi IP ti sọfitiwia SoC Libero. Eyi ti fi sori ẹrọ laifọwọyi nipasẹ iṣẹ imudojuiwọn Katalogi IP ninu sọfitiwia SoC Libero, tabi IP mojuto ti ṣe igbasilẹ pẹlu ọwọ lati inu katalogi naa. Ni kete ti a ti fi ipilẹ IP sori ẹrọ sọfitiwia Libero SoC IP Catalog, mojuto ti wa ni tunto, ipilẹṣẹ, ati lẹsẹkẹsẹ laarin ohun elo SmartDesign fun ifisi ninu atokọ iṣẹ akanṣe Libero.
Lilo Ẹrọ ati Ṣiṣẹ (Beere Ibeere kan)
Awọn wọnyi tabili awọn akojọ ti awọn ẹrọ iṣamulo fun DDR_AXI4_Arbiter.
Tabili 2. DDR_AXI4_Arbiter Iṣamulo

Ẹrọ Awọn alaye		Oro		Iṣe (MHz)	Awọn Ramu		Math ohun amorindun	Chip Agbaye
Idile	Ẹrọ	Awọn LUTs	DFF		LSRAM	μSRAM
PolarFire® SoC	MPFS250T-1	5411	4202	266	13	1	0	0
PolarFire	MPF300T-1	5411	4202	266	13	1	0	0
SmartFusion® 2	M2S150-1	5546	4309	192	15	1	0	0

Pataki:

• Awọn data ti o wa ninu tabili ti o ṣaju ni a gba pẹlu lilo iṣakojọpọ aṣoju ati awọn eto ifilelẹ. A tunto IP naa fun awọn ikanni kikọ mẹjọ, awọn ikanni kika mẹjọ, iwọn adirẹsi ti 32 bit, ati iwọn data ti iṣeto awọn bit 512.
• Aago ti ni ihamọ si 200 MHz lakoko ṣiṣe itupalẹ akoko lati ṣaṣeyọri awọn nọmba iṣẹ.

Apejuwe isẹ (Beere ibeere kan)
Yi apakan apejuwe awọn alaye imuse ti DDR_AXI4_Arbiter. Nọmba ti o tẹle n ṣe afihan aworan-pin-jade ti oke-ipele ti DDR AXI4 Arbiter. olusin 1-1. Oke-Ipele Pin-Jade Àkọsílẹ aworan atọka fun abinibi Arbiter Interface

Nọmba ti o tẹle yii fihan aworan atọka ipele-eto ti DDR_AXI4_Arbiter ni ipo wiwo Bus. olusin 1-2. Eto-Ipele Idina aworan ti DDR_AXI4_Arbiter

Idunadura kika kan jẹ okunfa nipasẹ tito ifihan agbara titẹ sii r (x) _req_i giga lori ikanni kika kan pato. Adajọ ṣe idahun nipasẹ ijẹwọgba nigbati o ba ṣetan lati ṣe iṣẹ ibeere kika naa. Lẹhinna o samples awọn ti o bere AXI adirẹsi ati ki o ka awọn ti nwaye iwọn ti o jẹ input lati ita initiator. Ikanni naa ṣe ilana awọn igbewọle ati ṣe ipilẹṣẹ awọn iṣowo AXI ti o nilo lati ka data lati iranti DDR. Ijade data kika lati ọdọ apaniyan jẹ wọpọ si gbogbo awọn ikanni kika. Lakoko kika data, data kika ti o wulo ti ikanni ti o baamu lọ ga. Ipari idunadura kika jẹ itọkasi nipasẹ ifihan agbara ti o ti pari nigbati gbogbo awọn baiti ti o beere ti firanṣẹ jade. Iru si idunadura kika, idunadura kikọ kan jẹ okunfa nipasẹ tito ifihan agbara titẹ sii w(x) _req_i giga. Paapọ pẹlu ifihan agbara ibeere, adirẹsi ibẹrẹ kikọ ati ipari ti nwaye gbọdọ wa ni ipese lakoko ibeere naa. Nigba ti apaniyan ba wa lati ṣe iṣẹ ibeere kikọ, o dahun nipa fifiranṣẹ ifihan agbara ifọwọsi lori ikanni ti o baamu. Lẹhinna olumulo ni lati pese data kikọ pẹlu ifihan agbara data lori ikanni naa. Nọmba awọn aago data to wulo akoko giga gbọdọ baramu gigun ti nwaye. Adajọ pari iṣẹ kikọ ati ṣeto ifihan agbara kikọ ti o ga ti o tọka si ipari idunadura kikọ.
Awọn paramita DDR_AXI4_Arbiter ati Awọn ifihan agbara Ni wiwo (Beere ibeere kan)
Yi apakan ti jiroro awọn paramita ni DDR_AXI4_Arbiter GUI configurator ati ki o Mo / O awọn ifihan agbara.
2.1 Eto Iṣeto (Beere ibeere kan)
Awọn wọnyi tabili awọn akojọ ti awọn apejuwe ti iṣeto ni sile lo ninu awọn hardware imuse ti DDR_AXI4_Arbiter. Iwọnyi jẹ awọn paramita jeneriki ati pe o le yatọ gẹgẹ bi ibeere ohun elo naa.

Table 2-1. Paramita iṣeto ni

Ifihan agbara Oruko	Apejuwe
Iwọn ID AXI	Awọn asọye AXI ID iwọn.
Iwọn Data AXI	Ṣe alaye iwọn data AXI.
AXI Iwọn Adirẹsi	Ṣe alaye iwọn adirẹsi AXI
Nọmba ti Ka awọn ikanni	Awọn aṣayan lati yan ko nilo fun awọn ikanni kikọ lati inu akojọ aṣayan-silẹ ti o wa lati ikanni kan si awọn ikanni kikọ mẹjọ.
Nọmba awọn ikanni Kọ	Awọn aṣayan lati yan ko nilo fun awọn ikanni kika lati inu akojọ aṣayan-isalẹ ti o wa lati ikanni kan si awọn ikanni kika mẹjọ.
AXI4_SELECTION	Awọn aṣayan lati yan laarin AXI4_MASTER ati AXI4_MIRRORED_SLAVE.
Arbiter Interface	Aṣayan lati yan wiwo bosi.

Awọn igbewọle ati Awọn ifihan agbara Ijade (Beere ibeere kan)
Tabili ti o tẹle ṣe atokọ awọn igbewọle ati awọn ebute okojade ti DDR AXI4 Arbiter fun wiwo Bus.
Table 2-2. Awọn ebute oko ti nwọle ati ti njade fun Arbiter Bus Interface

Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
atunto_i	Iṣawọle	—	Ifihan agbara atunto asynchronous Low ti nṣiṣe lọwọ si apẹrẹ
sys_ckl_i	Iṣawọle	—	Eto aago
ddr_ctrl_ready_i	Iṣawọle	—	Ngba ifihan agbara Input ti o ṣetan lati ọdọ oludari DDR
ARVALID_I_0	Iṣawọle	—	Ka ibeere lati ikanni kika 0
ARSIZE_I_0	Iṣawọle	8 die-die	ka iwọn ti nwaye lati ikanni kika 0
ARADDR_I_0	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 0
ARREADY_O_0	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 0
RVALID_O_0	Abajade	—	Ka data wulo lati ikanni kika 0
RDATA_O_0	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 0
RLAST_O_0	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 0
BUSER_O_r0	Abajade	—	Ka ipari lati ka ikanni 0
ARVALID_I_1	Iṣawọle	—	Ka ibeere lati ikanni kika 1
ARSIZE_I_1	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 1
ARADDR_I_1	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 1
ARREADY_O_1	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 1
RVALID_O_1	Abajade	—	Ka data wulo lati ikanni kika 1
RDATA_O_1	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 1
RLAST_O_1	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 1
BUSER_O_r1	Abajade	—	Ka ipari lati ka ikanni 1
ARVALID_I_2	Iṣawọle	—	Ka ibeere lati ikanni kika 2

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
ARSIZE_I_2	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 2
ARADDR_I_2	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 2
ARREADY_O_2	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 2
RVALID_O_2	Abajade	—	Ka data wulo lati ikanni kika 2
RDATA_O_2	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 2
RLAST_O_2	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 2
BUSER_O_r2	Abajade	—	Ka ipari lati ka ikanni 2
ARVALID_I_3	Iṣawọle	—	Ka ibeere lati ikanni kika 3
ARSIZE_I_3	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 3
ARADDR_I_3	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 3
ARREADY_O_3	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 3
RVALID_O_3	Abajade	—	Ka data wulo lati ikanni kika 3
RDATA_O_3	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 3
RLAST_O_3	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 3
BUSER_O_r3	Abajade	—	Ka ipari lati ka ikanni 3
ARVALID_I_4	Iṣawọle	—	Ka ibeere lati ikanni kika 4
ARSIZE_I_4	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 4
ARADDR_I_4	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 4
ARREADY_O_4	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 4
RVALID_O_4	Abajade	—	Ka data wulo lati ikanni kika 4
RDATA_O_4	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 4
RLAST_O_4	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 4
BUSER_O_r4	Abajade	—	Ka ipari lati ka ikanni 4
ARVALID_I_5	Iṣawọle	—	Ka ibeere lati ikanni kika 5
ARSIZE_I_5	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 5
ARADDR_I_5	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 5
ARREADY_O_5	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 5
RVALID_O_5	Abajade	—	Ka data wulo lati ikanni kika 5
RDATA_O_5	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 5
RLAST_O_5	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 5
BUSER_O_r5	Abajade	—	Ka ipari lati ka ikanni 5
ARVALID_I_6	Iṣawọle	—	Ka ibeere lati ikanni kika 6
ARSIZE_I_6	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 6
ARADDR_I_6	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 6
ARREADY_O_6	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 6
RVALID_O_6	Abajade	—	Ka data wulo lati ikanni kika 6
RDATA_O_6	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 6
RLAST_O_6	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 6

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
BUSER_O_r6	Abajade	—	Ka ipari lati ka ikanni 6
ARVALID_I_7	Iṣawọle	—	Ka ibeere lati ikanni kika 7
ARSIZE_I_7	Iṣawọle	8 die-die	Ka iwọn ti nwaye lati ikanni kika 7
ARADDR_I_7	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 7
ARREADY_O_7	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati ikanni kika 7
RVALID_O_7	Abajade	—	Ka data wulo lati ikanni kika 7
RDATA_O_7	Abajade	[AXI_DATA_WIDTH-1 : 0]	Ka data lati ikanni kika 7
RLAST_O_7	Abajade	—	Ka opin ifihan fireemu lati ikanni kika 7
BUSER_O_r7	Abajade	—	Ka ipari lati ka ikanni 7
AWSIZE_I_0	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 0
WDATA_I_0	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 0
WVALID_I_0	Iṣawọle	—	Kọ data wulo lati kọ ikanni 0
AWVALID_I_0	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 0
AWADDR_I_0	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 0
AWREADY_O_0	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 0
BUSER_O_0	Abajade	—	Kọ ipari lati kọ ikanni 0
AWSIZE_I_1	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 1
WDATA_I_1	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 1
WVALID_I_1	Iṣawọle	—	Kọ data wulo lati kọ ikanni 1
AWVALID_I_1	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 1
AWADDR_I_1	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 1
AWREADY_O_1	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 1
BUSER_O_1	Abajade	—	Kọ ipari lati kọ ikanni 1
AWSIZE_I_2	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 2
WDATA_I_2	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 2
WVALID_I_2	Iṣawọle	—	Kọ data wulo lati kọ ikanni 2
AWVALID_I_2	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 2
AWADDR_I_2	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 2
AWREADY_O_2	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 2
BUSER_O_2	Abajade	—	Kọ ipari lati kọ ikanni 2
AWSIZE_I_3	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 3
WDATA_I_3	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 3
WVALID_I_3	Iṣawọle	—	Kọ data wulo lati kọ ikanni 3
AWVALID_I_3	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 3
AWADDR_I_3	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 3
AWREADY_O_3	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 3
BUSER_O_3	Abajade	—	Kọ ipari lati kọ ikanni 3
AWSIZE_I_4	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 4

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
WDATA_I_4	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 4
WVALID_I_4	Iṣawọle	—	Kọ data wulo lati kọ ikanni 4
AWVALID_I_4	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 4
AWADDR_I_4	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 4
AWREADY_O_4	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 4
BUSER_O_4	Abajade	—	Kọ ipari lati kọ ikanni 4
AWSIZE_I_5	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 5
WDATA_I_5	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 5
WVALID_I_5	Iṣawọle	—	Kọ data wulo lati kọ ikanni 5
AWVALID_I_5	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 5
AWADDR_I_5	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 5
AWREADY_O_5	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 5
BUSER_O_5	Abajade	—	Kọ ipari lati kọ ikanni 5
AWSIZE_I_6	Iṣawọle	8 die-die	Kọ iwọn ti nwaye fun ikanni kikọ 6
WDATA_I_6	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 6
WVALID_I_6	Iṣawọle	—	Kọ data wulo lati kọ ikanni 6
AWVALID_I_6	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 6
AWADDR_I_6	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 6
AWREADY_O_6	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 6
BUSER_O_6	Abajade	—	Kọ ipari lati kọ ikanni 6
AWSIZE_I_7	Iṣawọle	8 die-die	Kọ iwọn ti nwaye lati ikanni kikọ 7
WDATA_I_7	Iṣawọle	[AXI_DATA_WIDTH-1:0]	Ti nwọle data fidio lati kọ ikanni 7
WVALID_I_7	Iṣawọle	—	Kọ data wulo lati kọ ikanni 7
AWVALID_I_7	Iṣawọle	—	Kọ ibeere lati ikanni kikọ 7
AWADDR_I_7	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 7
AWREADY_O_7	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati ikanni kikọ 7
BUSER_O_7	Abajade	—	Kọ ipari lati kọ ikanni 7

Tabili ti o tẹle ṣe atokọ awọn igbewọle ati awọn ebute okojade ti DDR AXI4 Arbiter fun wiwo abinibi.
Table 2-3. Awọn ebute oko igbewọle ati Ijade fun Ibaraẹnisọrọ Ilu abinibi

Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
atunto_i	Iṣawọle	—	Ifihan agbara atunto asynchronous kekere ti nṣiṣe lọwọ lati ṣe apẹrẹ
sys_clk_i	Iṣawọle	—	Eto aago
ddr_ctrl_ready_i	Iṣawọle	—	Ngba ifihan agbara titẹ sii ti o ṣetan lati ọdọ oludari DDR
r0_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 0
r0_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r0_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 0
r0_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 0

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
r0_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 0
r0_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 0
r1_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 1
r1_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r1_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 1
r1_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 1
r1_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 1
r1_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 1
r2_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 2
r2_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r2_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 2
r2_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 2
r2_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 2
r2_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 2
r3_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 3
r3_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r3_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 3
r3_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 3
r3_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 3
r3_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 3
r4_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 4
r4_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r4_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 4
r4_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 4
r4_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 4
r4_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 4
r5_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 5
r5_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r5_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 5
r5_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 5
r5_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 5
r5_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 5
r6_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 6
r6_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn
r6_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 6
r6_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 6
r6_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 6
r6_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 6
r7_req_i	Iṣawọle	—	Ka ìbéèrè lati olupilẹṣẹ 7
r7_burst_size_i	Iṣawọle	8 die-die	Ka ti nwaye iwọn

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
r7_rstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR lati ibiti o yẹ ki o bẹrẹ kika fun ikanni kika 7
r7_ack_o	Abajade	—	Ijẹwọgba Arbiter lati ka ibeere lati olupilẹṣẹ 7
r7_data_valid_o	Abajade	—	Ka data wulo lati ikanni kika 7
r7_ti ṣe_o	Abajade	—	Ka ipari si olupilẹṣẹ 7
rdata_o	Abajade	[AXI_DATA_WIDTH – 1:0]	Ijade data fidio lati ikanni kika
w0_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w0_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 0
w0_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 0
w0_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 0
w0_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 0
w0_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 0
w0_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 0
w1_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w1_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 1
w1_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 1
w1_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 1
w1_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 1
w1_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 1
w1_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 1
w2_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w2_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 2
w2_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 2
w2_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 2
w2_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 2
w2_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 2
w2_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 2
w3_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w3_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 3
w3_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 3
w3_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 3
w3_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 3
w3_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 3
w3_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 3
w4_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w4_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 4
w4_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 4
w4_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 4
w4_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 4

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
w4_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 4
w4_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 4
w5_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w5_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 5
w5_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 5
w5_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 5
w5_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 5
w5_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 5
w5_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 5
w6_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w6_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 6
w6_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 6
w6_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 6
w6_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 6
w6_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 6
w6_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 6
w7_burst_size_i	Iṣawọle	8 die-die	Kọ ti nwaye iwọn
w7_data_i	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Iṣagbewọle data fidio lati kọ ikanni 7
w7_data_valid_i	Iṣawọle	—	Kọ data wulo lati kọ ikanni 7
w7_req_i	Iṣawọle	—	Kọ ibeere lati olupilẹṣẹ 7
w7_wstart_addr_i	Iṣawọle	[AXI_ADDR_WIDTH – 1:0]	Adirẹsi DDR eyiti kikọ gbọdọ ṣẹlẹ lati ikanni kikọ 7
w7_ack_o	Abajade	—	Ijẹwọgba Arbiter lati kọ ibeere lati olupilẹṣẹ 7
w7_ti ṣe_o	Abajade	—	Kọ ipari si olupilẹṣẹ 7
AXI I/F Awọn ifihan agbara
Ka adirẹsi ikanni
ogbele_o	Abajade	[AXI_ID_WIDTH – 1:0]	Ka ID adirẹsi. Idanimọ tag fun ẹgbẹ adirẹsi kika ti awọn ifihan agbara.
araddr_o	Abajade	[AXI_ADDR_WIDTH – 1:0]	Ka adirẹsi. Pese ni ibẹrẹ adirẹsi ti a kika ti nwaye idunadura. Adirẹsi ibẹrẹ ti nwaye nikan ni a pese.
arlen_o	Abajade	[7:0]	Fonkaakiri ipari. Pese awọn gangan nọmba ti awọn gbigbe ni a ti nwaye. Alaye yii pinnu nọmba awọn gbigbe data ti o ni nkan ṣe pẹlu adirẹsi naa.
arsize_o	Abajade	[2:0]	Ti nwaye iwọn. Iwọn gbigbe kọọkan ni ti nwaye.
arburst_o	Abajade	[1:0]	Burst iru. Paapọ pẹlu alaye iwọn, awọn alaye bi adirẹsi fun gbigbe kọọkan laarin ti nwaye ti ṣe iṣiro. Ti o wa titi si 2'b01 à Adirẹsi Imudara ti nwaye.
arlock_o	Abajade	[1:0]	Titiipa iru. Pese afikun alaye nipa awọn abuda atomiki ti gbigbe. Ti o wa titi si 2'b00 à Wiwọle deede.

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
archache_o	Abajade	[3:0]	Iru kaṣe. Pese alaye ni afikun nipa awọn abuda cacheable ti gbigbe. Ti o wa titi si 4'b0000 à Kii-cacheable ati ti kii ṣe bufferable.
arprot_o	Abajade	[2:0]	Iru Idaabobo. Pese alaye ẹyọkan aabo fun idunadura naa. Ti o wa titi si 3'b000 à Deede, wiwọle data to ni aabo.
arvalid_o	Abajade	—	Ka adirẹsi wulo. Nigbati HIGH, adirẹsi kika ati alaye iṣakoso jẹ iwulo ati pe o wa ni giga titi ti ami adirẹsi adirẹsi, ti ṣetan, ga. 1 = Adirẹsi ati alaye iṣakoso wulo 0 = Adirẹsi ati alaye iṣakoso ko wulo
ti ṣetan_o	Iṣawọle	—	Ka adirẹsi setan. Ibi-afẹde naa ti ṣetan lati gba adirẹsi ati awọn ifihan agbara iṣakoso ti o somọ. 1 = afojusun setan 0 = ibi-afẹde ko ṣetan
Ka Data ikanni
yọ kuro	Iṣawọle	[AXI_ID_WIDTH – 1:0]	Ka ID tag. ID tag ti ẹgbẹ data kika ti awọn ifihan agbara. Iye yiyọ jẹ ipilẹṣẹ nipasẹ ibi-afẹde ati pe o gbọdọ baramu iye gbigbẹ ti idunadura kika si eyiti o n dahun.
rdata	Iṣawọle	[AXI_DATA_WIDTH – 1:0]	Ka data
rsp	Iṣawọle	[1:0]	Ka esi. Ipo gbigbe kika. Awọn idahun ti o gba laaye jẹ OKAY, EXOKAY, SLVERR, ati DECERR.
rlast	Iṣawọle	—	Ka kẹhin. Gbigbe to kẹhin ni ti nwaye kika.
rvalid	Iṣawọle	—	Ka wulo. Data kika ti a beere wa ati gbigbe kika le pari. 1 = kika data ti o wa 0 = data kika ko si
titan	Abajade	—	Ka setan. Olupilẹṣẹ le gba data kika ati alaye esi. 1= olupilẹṣẹ ṣetan 0 = olupilẹṣẹ ko ṣetan
Kọ adirẹsi ikanni
agba	Abajade	[AXI_ID_WIDTH – 1:0]	Kọ ID adirẹsi. Idanimọ tag fun awọn kikọ adirẹsi ẹgbẹ ti awọn ifihan agbara.
awaddr	Abajade	[AXI_ADDR_WIDTH – 1:0]	Kọ adirẹsi. Pese adirẹsi ti akọkọ gbigbe ni a Kọ ti nwaye idunadura. Awọn ifihan agbara iṣakoso ti o somọ ni a lo lati pinnu awọn adirẹsi ti awọn gbigbe ti o ku ninu ti nwaye.
àwon	Abajade	[7:0]	Fonkaakiri ipari. Pese awọn gangan nọmba ti awọn gbigbe ni a ti nwaye. Alaye yii pinnu nọmba awọn gbigbe data ti o ni nkan ṣe pẹlu adirẹsi naa.
awize	Abajade	[2:0]	Ti nwaye iwọn. Iwọn gbigbe kọọkan ni ti nwaye. Awọn ọna baiti strobes tọkasi gangan iru awọn ọna baiti lati ṣe imudojuiwọn.
aburu	Abajade	[1:0]	Burst iru. Paapọ pẹlu alaye iwọn, awọn alaye bi adirẹsi fun gbigbe kọọkan laarin ti nwaye ti ṣe iṣiro. Ti o wa titi si 2'b01 à Adirẹsi Imudara ti nwaye.

....... tesiwaju
Ifihan agbara Oruko	Itọsọna	Ìbú	Apejuwe
abọ	Abajade	[1:0]	Titiipa iru. Pese afikun alaye nipa awọn abuda atomiki ti gbigbe. Ti o wa titi si 2'b00 à Wiwọle deede.
awcache	Abajade	[3:0]	Iru kaṣe. Tọkasi bufferable, cacheable, kọ-nipasẹ, kọ-pada, ati pin awọn abuda ti idunadura naa. Ti o wa titi si 4'b0000 à Kii-cacheable ati ti kii ṣe bufferable.
afarape	Abajade	[2:0]	Iru Idaabobo. Ṣe afihan deede, anfani tabi ipele aabo aabo ti iṣowo naa ati boya idunadura naa jẹ iraye si data tabi iraye si itọnisọna. Ti o wa titi si 3'b000 à Deede, wiwọle data to ni aabo.
alailoye	Abajade	—	Kọ adirẹsi wulo. Tọkasi pe adirẹsi kikọ to wulo ati alaye iṣakoso wa. 1 = adirẹsi ati alaye iṣakoso ti o wa 0 = adirẹsi ati alaye iṣakoso ko si. Adirẹsi ati alaye iṣakoso wa ni iduroṣinṣin titi ti ami ami adirẹsi naa yoo jẹwọ, ti ṣetan, yoo lọ HIGH.
setan	Iṣawọle	—	Kọ adirẹsi setan. Tọkasi pe ibi-afẹde ti ṣetan lati gba adirẹsi ati awọn ifihan agbara iṣakoso ti o somọ. 1 = afojusun setan 0 = ibi-afẹde ko ṣetan
Kọ Data ikanni
wdata	Abajade	[AXI_DATA_WIDTH – 1:0]	Kọ data
wstrb	Abajade	[AXI_DATA_WIDTH – 8:0]	Kọ strobes. Ifihan agbara yi tọkasi iru awọn ọna baiti lati ṣe imudojuiwọn ni iranti. Strobe kikọ kan wa fun awọn die-die mẹjọ kọọkan ti ọkọ data kikọ.
wlast	Abajade	—	Kọ kẹhin. Gbigbe to kẹhin ninu ikọsilẹ kikọ.
wvalid	Abajade	—	Kọ wulo. Data kikọ to wulo ati awọn strobes wa. 1 = kọ data ati strobes wa 0 = kọ data ati strobes ko si
aja	Iṣawọle	—	Kọ setan. Àkọlé le gba data kikọ. 1 = afojusun setan 0 = ibi-afẹde ko ṣetan
Kọ Idahun ikanni
idu	Iṣawọle	[AXI_ID_WIDTH – 1:0]	Idahun ID. Idanimọ tag ti idahun kikọ. Iye idu gbọdọ baramu iye awid ti idunadura kikọ si eyiti ibi-afẹde naa n dahun.
bresp	Iṣawọle	[1:0]	Kọ esi. Ipo ti idunadura kikọ. Awọn idahun ti o gba laaye jẹ OKAY, EXOKAY, SLVERR, ati DECERR.
bvalid	Iṣawọle	—	Kọ esi wulo. Idahun kikọ to wulo wa. 1 = kọ esi wa 0 = kọ esi ko si
burẹdi	Abajade	—	Idahun setan. Olupilẹṣẹ le gba alaye esi. 1 = initiator setan 0 = olupilẹṣẹ ko ṣetan

Awọn aworan atọka akoko (Beere ibeere kan)
Yi apakan ti jiroro DDR_AXI4_Arbiter ìlà awọn aworan atọka. Awọn isiro atẹle ṣe afihan asopọ ti kika ati kikọ awọn igbewọle ibeere, ibẹrẹ adirẹsi iranti, kọ awọn igbewọle lati olupilẹṣẹ ita, ka tabi kọ ifọwọsi, ati ka tabi kọ awọn igbewọle ipari ti a fun nipasẹ apaniyan.
olusin 3-1. Aworan ti akoko fun Awọn ifihan agbara ti a lo ni Kikọ/kika nipasẹ AXI4 Interface

Testbench (Beere ibeere kan)
A ti lo testbench isokan lati rii daju ati idanwo DDR_AXI4_Arbiter ti a pe ni testbench olumulo. A pese Testbench lati ṣayẹwo iṣẹ ṣiṣe ti DDR_AXI4_Arbiter IP. Eleyi testbench ṣiṣẹ nikan fun meji kika awọn ikanni ati meji kikọ awọn ikanni pẹlu Bus Interface iṣeto ni.
 Simulation (Beere ibeere kan)
Awọn igbesẹ wọnyi ṣe apejuwe bi o ṣe le ṣe adaṣe mojuto nipa lilo testbench:

1. Ṣii taabu Libero® SoC Catalog, faagun Solusan-Video, tẹ DDR_AXI4_Arbiter lẹẹmeji, lẹhinna tẹ O DARA. Awọn iwe ti o ni nkan ṣe pẹlu IP ti wa ni akojọ labẹ Iwe. Pataki: Ti o ko ba ri taabu Catalog, lilö kiri si View > Akojọ Windows ki o si tẹ Katalogi lati jẹ ki o han.

olusin 4-1. DDR_AXI4_Arbiter IP mojuto ni Libero SoC Catalog

Ṣẹda window paati yoo han bi o ṣe han ni atẹle. Tẹ O DARA. Rii daju pe Orukọ naa jẹ DDR_AXI4_ARBITER_PF_C0.
olusin 4-2. Ṣẹda paati

Tunto IP fun awọn ikanni kika 2, 2 kọ awọn ikanni ki o yan Interface Bus bi o ṣe han ni nọmba atẹle ki o tẹ O DARA lati ṣe ipilẹṣẹ IP naa.
olusin 4-3. Iṣeto ni

Lori awọn Stimulus Hierarchy taabu, yan testbench (DDR_AXI4_ARBITER_PF_tb.v), tẹ-ọtun ati lẹhinna tẹ Simulate Pre-Synth Design> Ṣii Interactively.
Pataki: Ti o ko ba ri taabu Stimulus Hierarchy, lilö kiri si View > Akojọ aṣyn Windows ki o si tẹ Iṣọkan Iṣọkan lati jẹ ki o han.
olusin 4-4. Simulating Pre- Synthesis DesignModelSim ṣi pẹlu testbench file, bi o ṣe han ninu nọmba atẹle.
olusin 4-5. ModelSim Simulation Window

Pataki: Ti kikopa naa ba ni idilọwọ nitori opin akoko ṣiṣe ti a sọ pato ninu .do file, lo run -all pipaṣẹ lati pari kikopa.
Itan Atunyẹwo (Beere ibeere kan)
Itan atunyẹwo ṣe apejuwe awọn iyipada ti a ṣe imuse ninu iwe-ipamọ naa. Awọn iyipada ti wa ni atokọ nipasẹ atunyẹwo, bẹrẹ pẹlu atẹjade lọwọlọwọ julọ.
Table 5-1. Àtúnyẹwò History

Àtúnyẹwò	Ọjọ	Apejuwe
A	04/2023	Atẹle ni atokọ ti awọn ayipada ninu atunyẹwo A ti iwe naa: Iṣilọ iwe naa si awoṣe Microchip. • Ṣe imudojuiwọn nọmba iwe-ipamọ si DS00004976A lati 50200950. Fi kun 4. Testbench.
2.0	—	Atẹle ni atokọ ti awọn ayipada ninu atunyẹwo 2.0 ti iwe naa: Fi kun olusin 1-2. Fi kun Table 2-2. • Ṣe imudojuiwọn awọn orukọ ti diẹ ninu awọn titẹ sii ati awọn orukọ ifihan agbara jade ninu Table 2-2.
1.0	—	Itusilẹ akọkọ.

Atilẹyin Microchip FPGA (Beere ibeere kan)
Ẹgbẹ awọn ọja Microchip FPGA ṣe atilẹyin awọn ọja rẹ pẹlu ọpọlọpọ awọn iṣẹ atilẹyin, pẹlu Iṣẹ alabara, Ile-iṣẹ Atilẹyin Imọ-ẹrọ Onibara, a webojula, ati ni agbaye tita ifiweranṣẹ. A daba awọn alabara lati ṣabẹwo si awọn orisun ori ayelujara Microchip ṣaaju kikan si atilẹyin nitori o ṣee ṣe pupọ pe awọn ibeere wọn ti ni idahun tẹlẹ. Kan si Technical Support Center nipasẹ awọn webaaye ni www.microchip.com/support. Darukọ nọmba Apakan Ẹrọ FPGA, yan ẹka ọran ti o yẹ, ati apẹrẹ ikojọpọ files nigba ti ṣiṣẹda a imọ support irú. Kan si Iṣẹ Onibara fun atilẹyin ọja ti kii ṣe imọ-ẹrọ, gẹgẹbi idiyele ọja, awọn iṣagbega ọja, alaye imudojuiwọn, ipo aṣẹ, ati aṣẹ.

• Lati North America, pe 800.262.1060
• Lati iyoku agbaye, pe 650.318.4460
• Faksi, lati nibikibi ninu aye, 650.318.8044

Alaye Microchip (Beere ibeere kan)

Microchip naa Webaaye (Beere ibeere kan)
Microchip pese atilẹyin ori ayelujara nipasẹ wa webojula ni www.microchip.com/. Eyi webojula ti wa ni lo lati ṣe files ati alaye awọn iṣọrọ wa si awọn onibara. Diẹ ninu akoonu ti o wa pẹlu:

• Atilẹyin ọja - Awọn iwe data ati errata, awọn akọsilẹ ohun elo ati sampawọn eto, awọn orisun apẹrẹ, awọn itọsọna olumulo ati awọn iwe atilẹyin ohun elo, awọn idasilẹ sọfitiwia tuntun, ati sọfitiwia ti a fi pamọ
• Atilẹyin Imọ-ẹrọ Gbogbogbo - Awọn ibeere ti a beere nigbagbogbo (Awọn FAQ), awọn ibeere atilẹyin imọ-ẹrọ, awọn ẹgbẹ ijiroro lori ayelujara, atokọ awọn ọmọ ẹgbẹ eto alabaṣepọ apẹrẹ Microchip
• Iṣowo ti Microchip - Oluyan ọja ati awọn itọsọna aṣẹ, awọn idasilẹ atẹjade Microchip tuntun, atokọ ti awọn apejọ ati awọn iṣẹlẹ, awọn atokọ ti awọn ọfiisi tita Microchip, awọn olupin kaakiri, ati awọn aṣoju ile-iṣẹ

Iṣẹ Iwifunni Iyipada ọja (Beere ibeere kan)
Iṣẹ ifitonileti iyipada ọja Microchip ṣe iranlọwọ lati jẹ ki awọn alabara wa lọwọlọwọ lori awọn ọja Microchip. Awọn alabapin yoo gba awọn iwifunni imeeli nigbakugba ti awọn ayipada ba wa, awọn imudojuiwọn, awọn atunyẹwo tabi errata ti o ni ibatan si ẹbi ọja kan tabi ohun elo idagbasoke ti iwulo. Lati forukọsilẹ, lọ si www.microchip.com/pcn ki o si tẹle awọn ilana ìforúkọsílẹ.
Atilẹyin alabara (Beere ibeere kan)
Awọn olumulo ti awọn ọja Microchip le gba iranlọwọ nipasẹ awọn ikanni pupọ:

• Olupin tabi Aṣoju
• Agbegbe Sales Office
• Onimọ-ẹrọ Awọn ojutu ti a fi sii (ESE)
• Oluranlowo lati tun nkan se

Awọn onibara yẹ ki o kan si olupin wọn, aṣoju tabi ESE fun atilẹyin. Awọn ọfiisi tita agbegbe tun wa lati ṣe iranlọwọ fun awọn alabara. Atokọ ti awọn ọfiisi tita ati awọn ipo wa ninu iwe yii. Imọ support wa nipasẹ awọn webojula ni: www.microchip.com/support.
Microchip Ṣe agbekalẹ Ẹya Idaabobo koodu (Beere ibeere kan)
Ṣe akiyesi awọn alaye atẹle ti ẹya aabo koodu lori awọn ọja Microchip:

• Awọn ọja Microchip pade awọn pato ti o wa ninu Iwe Data Microchip pato wọn.
• Microchip gbagbọ pe ẹbi ti awọn ọja wa ni aabo nigba lilo ni ọna ti a pinnu, laarin awọn pato iṣẹ, ati labẹ awọn ipo deede.
• Awọn iye Microchip ati ibinu ṣe aabo awọn ẹtọ ohun-ini ọgbọn rẹ. Awọn igbiyanju lati irufin awọn ẹya aabo koodu ti ọja Microchip jẹ eewọ muna ati pe o le rú Ofin Aṣẹ-lori-ara DigitalMillennium.
• Bẹni Microchip tabi eyikeyi olupese semikondokito miiran le ṣe iṣeduro aabo koodu rẹ. Idaabobo koodu ko tumọ si pe a n ṣe iṣeduro ọja naa jẹ “aibikita”. Idaabobo koodu ti wa ni idagbasoke nigbagbogbo. Microchip ti pinnu lati ni ilọsiwaju nigbagbogbo awọn ẹya aabo koodu ti awọn ọja wa.

Akiyesi Ofin (Beere ibeere kan)
Atẹjade yii ati alaye ti o wa ninu rẹ le ṣee lo pẹlu awọn ọja Microchip nikan, pẹlu lati ṣe apẹrẹ, idanwo, ati ṣepọ awọn ọja Microchip pẹlu ohun elo rẹ. Lilo alaye yii ni ọna miiran ti o lodi si awọn ofin wọnyi. Alaye nipa awọn ohun elo ẹrọ ti pese fun irọrun rẹ nikan ati pe o le rọpo nipasẹ awọn imudojuiwọn. O jẹ ojuṣe rẹ lati rii daju pe ohun elo rẹ ba awọn pato rẹ mu. Kan si ọfiisi tita Microchip agbegbe rẹ fun atilẹyin afikun tabi, gba atilẹyin afikun ni www.microchip.com/en-us/support/design-help/ onibara-atilẹyin-awọn iṣẹ. ALAYE YI NI MICROCHIP “BI O SE WA”. MICROCHIP KO SE Aṣoju TABI ATILẸYIN ỌJA TI IRU KANKAN BOYA KIAKIA TABI TỌRỌ, KỌ TABI ẹnu, Ilana tabi Bibẹkọkọ, ti o jọmọ ALAYE NAA SUGBON KO NI OPIN SI KANKAN, LATI IKILỌWỌ, LATI IKILỌWỌ, FUN IDI PATAKI, TABI ATILẸYIN ỌJA JẸRẸ SI IPO RẸ, DARA, TABI IṢẸ. LAISI iṣẹlẹ ti yoo ṣe oniduro fun eyikeyi airotẹlẹ, PATAKI, ijiya, ijamba, tabi Abajade pipadanu, bibajẹ, iye owo, tabi inawo ti eyikeyi iru ohunkohun ti o jọmọ si awọn alaye tabi anfani, ti o ba ti lo, SED OF O SEESE TABI APAJỌ NAA NI IṢẸTẸ tẹlẹ? SI AWỌN NIPA NIPA NIPA TI OFIN, LAPAPA LAPAPO MICROCHIP LORI Gbogbo awọn ẹtọ ni eyikeyi ọna ti o jọmọ ALAYE TABI LILO RE KO NI JU NOMBA TI AWỌN ỌWỌ, TI O BA KAN, TI O ti san taara lati ṣe alaye. Lilo awọn ẹrọ Microchip ni atilẹyin igbesi aye ati/tabi awọn ohun elo aabo jẹ patapata ni ewu olura, ati pe olura gba lati daabobo, ṣe idalẹbi ati mu Microchip ti ko lewu lati eyikeyi ati gbogbo awọn bibajẹ, awọn ẹtọ, awọn ipele, tabi awọn inawo ti o waye lati iru lilo. Ko si awọn iwe-aṣẹ ti a gbe lọ, laisọtọ tabi bibẹẹkọ, labẹ eyikeyi awọn ẹtọ ohun-ini imọ Microchip ayafi bibẹẹkọ ti sọ.
Awọn aami-iṣowo (Beere ibeere kan)
Orukọ Microchip ati aami, aami Microchip, Adaptec, AVR, AVR logo, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXSty MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, logo PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Segenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ati XMEGA jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated ni AMẸRIKA ati awọn orilẹ-ede miiran. AgileSwitch, APT, ClockWorks, Ile-iṣẹ Awọn Solusan Iṣakoso ti a fi sinu, EtherSynch, Flashtec, Iṣakoso Iyara Hyper, fifuye HyperLight, Libero, motorBench, mTouch, Powermite 3, Edge Precision, ProASIC, ProASIC Plus, ProASIC Plus logo, Idakẹjẹ- Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, ati ZL jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated in the USA Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Eyikeyi Capacitor, AnyIn, AnyOut, Augmented Yiyipada , BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Ibadara Idaraya Iyipada, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, Serial, IN-CircuitIC Ti o jọra oye, IntelliMOS, Asopọmọra Chip Inter-Chip, JitterBlocker, Knob-on-Ifihan, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB aami ifọwọsi, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, GIDI ICE, Ripple Blocker, RTAX , RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Lapapọ Ifarada, Akoko Igbẹkẹle, TSHARC, USBCheck, VariSense, VectorBlox VeriPHY, ViewSpan, WiperLock, XpressConnect, ati ZENA jẹ aami-iṣowo ti Microchip Technology Incorporated ni AMẸRIKA ati awọn orilẹ-ede miiran. SQTP jẹ aami iṣẹ ti Microchip Technology Incorporated in the USA The Adaptec logo, Frequency on Demand, Silicon Storage Technology, ati Symmcom jẹ aami-iṣowo ti a forukọsilẹ ti Microchip Technology Inc. ni awọn orilẹ-ede miiran. GestIC jẹ aami-iṣowo ti a forukọsilẹ ti Microchip Technology Germany II GmbH & Co.KG, oniranlọwọ ti Microchip Technology Inc., ni awọn orilẹ-ede miiran. Gbogbo awọn aami-iṣowo miiran ti a mẹnuba ninu rẹ jẹ ohun-ini ti awọn ile-iṣẹ wọn. © 2023, Microchip Technology Incorporated ati awọn ẹka rẹ. Gbogbo awọn ẹtọ wa ni ipamọ.
ISBN: 978-1-6683-2302-1 Eto Isakoso Didara (Beere Ibeere) Fun alaye nipa Awọn ọna iṣakoso Didara Microchip, jọwọ ṣabẹwo si www.microchip.com/quality.

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MICROCHIP DDR AXI4 Arbiter [pdf] Itọsọna olumulo DDR AXI4 Arbiter, DDR AXI4, Arbiter

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