MICROCHIP DDR AXI4 Arbiter

Okwu mmalite: Ụkpụrụ protocol AXI4-Stream na-eji okwu okwu Master na Slave. Okwu Microchip kwekọrọ na nke a na-eji n'ime akwụkwọ a bụ Onye mmalite na Target, n'otu n'otu.
Nchịkọta: Tebụlụ na-esote na-enye nchịkọta nke njirimara DDR AXI4 Arbiter.

Njirimara	Uru
Ụdị isi	DDR AXI4 Arbiter v2.2
Ezinụlọ Ngwaọrụ akwadoro	–
Ịnweta ikike ịgbasa ngwa ọrụ akwadoro	–

Atụmatụ: DDR AXI4 Arbiter nwere atụmatụ isi ndị a:

• A ga-etinyerịrị isi IP na katalọgụ IP nke ngwanrọ Libero SoC.
• A na-ahazi isi ihe, mepụta, na ozugbo n'ime ngwa SmartDesign maka itinye na ndepụta ọrụ Libero.

Iji ngwaọrụ na arụ ọrụ:

Nkọwa ngwaọrụ	Ezinụlọ	Ngwaọrụ	Akụrụngwa	Arụmọrụ (MHz)
LUTs DFF RAM LSRAM SRAM Math Blocks Chip Globals	PolarFire	MPF300T-1	5411 4202	266

Nkọwa ọrụ

Nkọwa ọrụ: Akụkụ a na-akọwa nkọwa mmejuputa nke DDR_AXI4_Arbiter. Onu ogugu a na-egosi eserese pin-out nke DDR AXI4 Arbiter.

DDR_AXI4_Arbiter Parameters na akara ngosi

Ntọala nhazi:
akọwapụtaghị ntọala nhazi maka DDR_AXI4_Arbiter n'ime akwụkwọ a.

Ngosipụta ntinye na ntinye:
akọwapụtaghị akara ntinye na mmepụta maka DDR_AXI4_Arbiter n'ime akwụkwọ a.

Eserese oge
Edepụtaghị eserese oge maka DDR_AXI4_Arbiter n'ime akwụkwọ a.

Testbench

Simulation:
Edepụtaghị nkọwa simulation maka DDR_AXI4_Arbiter n'ime akwụkwọ a.
Akụkọ ngbanwe
Akọwapụtaghị akụkọ ngbanwe maka DDR_AXI4_Arbiter n'ime akwụkwọ a.
Nkwado FPGA Microchip
Ozi nkwado Microchip FPGA maka DDR_AXI4_Arbiter akọwapụtaghị n'ime akwụkwọ a.

Ntuziaka ojiji ngwaahịa

1. Wụnye DDR AXI4 Arbiter v2.2 na katalọgụ IP nke ngwanrọ Libero SoC.
2. Hazie, mepụta ma mee ngwa ngwa n'ime ngwa SmartDesign maka itinye na ndepụta ọrụ Libero.

Okwu mmalite (Jụọ ajụjụ)

Ncheta bụ akụkụ dị mkpa nke ngwa vidiyo na eserese ọ bụla. A na-eji ha maka ịchekwa okpokolo agba vidiyo niile mgbe ebe nchekwa mpaghara nke FPGA ezughi oke ijide etiti ahụ dum. Mgbe enwere ọtụtụ agụ na ide nke okpokolo agba vidiyo n'ime DDR, a ga-achọrọ onye na-ekpe ikpe ikpe ikpe n'etiti ọtụtụ arịrịọ. DDR AXI4 Arbiter IP na-enye ọwa ederede 8 iji dee ihe nchekwa etiti n'ime ebe nchekwa DDR mpụga yana 8 gụọ ọwa iji gụọ okpokolo agba site na ebe nchekwa mpụga. Mkpezi ikpe ahụ gbadoro ụkwụ n'ụkpụrụ-abịa, na-ebute ụzọ. Ọ bụrụ na arịrịọ abụọ emee n'otu oge, ọwa nwere nọmba ọwa ala ga-ebute ụzọ. Onye na-ekpe ikpe na-ejikọ na onye njikwa DDR IP site na interface AXI4. DDR AXI4 Arbiter na-enye AXI4 Initiator interface maka ndị na-ahụ maka mgbawa DDR. Onye na-ekpe ikpe na-akwado ihe ruru ọwa ederede asatọ na ọwa ọgụgụ asatọ. Mgbochi ahụ na-ekpe ikpe n'etiti ọwa ọgụgụ asatọ iji nye ohere ịnweta ọwa ọgụgụ AXI n'ụzọ mbụ-abịa, nke mbụ. Mgbochi ahụ na-ekpe ikpe n'etiti ọwa ederede asatọ iji nye ohere ịnweta ọwa ide AXI n'ụzọ mbụ bịara, nke mbụ. Ọwa ịgụ na ide ihe asatọ nwere mkpa nha anya. Enwere ike ịhazi interface AXI4 Initiator nke Arbiter IP maka obosara data dị iche iche sitere na bit 64 ruo 512.
Ihe dị mkpa: Ụkpụrụ protocol AXI4-Stream na-eji okwu okwu "Master" na "Ohu". Okwu Microchip kwekọrọ na nke a na-eji n'ime akwụkwọ a bụ Onye mmalite na Target, n'otu n'otu.
Nchịkọta (Jụọ ajụjụ)
Tebụlụ na-esote na-enye nchịkọta nke njirimara DDR AXI4 Arbiter.

Isiokwu 1. DDR AXI4 Arbiter Njirimara

Akwụkwọ a na-emetụta DDR AXI4 Arbiter v2.2.

• PolarFire® SoC
• PolarFire
• RTG4™
• IGLOO® 2
• SmartFusion® 2

Chọrọ mwepụta Libero® SoC v12.3 ma ọ bụ emechaa. Enwere ike iji IP na ọnọdụ RTL na-enweghị ikike ọ bụla. Maka ozi ndị ọzọ, hụ DDR_AXI4_Arbiter.

Atụmatụ (Jụọ ajụjụ)

DDR AXI4 Arbiter nwere atụmatụ isi ndị a:

• Asato Dee ọwa
• Ọwa ịgụ asatọ
• AXI4 Interface na onye njikwa DDR
• Obosara AXI4 nwere ike ịhazi: 64, 128, 256, na 512 bits
• Obosara adreesị nwere ike ịhazi: 32 ruo 64 bit

Mmejuputa IP Core na Libero® Design Suite (Jụọ ajụjụ)
A ga-etinyerịrị isi IP na katalọgụ IP nke ngwanrọ Libero SoC. A na-etinye nke a na-akpaghị aka site na ọrụ mmelite IP katalọgụ dị na ngwanrọ Libero SoC, ma ọ bụ jiri aka budata isi IP na katalọgụ ahụ. Ozugbo etinyere isi IP na Libero SoC software IP Catalog, a na-ahazi isi ya, mepụta ya na ozugbo n'ime ngwa SmartDesign maka itinye na ndepụta ọrụ Libero.
Iji ngwaọrụ na arụ ọrụ (Jụọ ajụjụ)
Tebụlụ na-esote depụtara ngwaọrụ eji eme DDR_AXI4_Arbiter.
Tebụl 2. DDR_AXI4_Arbiter ojiji

Ngwaọrụ Nkọwa		Akụrụngwa		Arụmọrụ (MHz)	RAM		Ihe mgbochi mgbakọ na mwepụ	Chip Gburugburu ụwa
Ezinụlọ	Ngwaọrụ	Ndị LUT	DFF		LSRAM	μSRAM
PolarFire® SoC	MPFS250T-1	5411	4202	266	13	1	0	0
PolarFire	MPF300T-1	5411	4202	266	13	1	0	0
SmartFusion® 2	M2S150-1	5546	4309	192	15	1	0	0

Ihe dị mkpa:

• A na-ejide data dị na tebụl bu ụzọ site na iji nhazi nhazi na nhazi nhazi. A haziri IP maka ọwa ederede asatọ, ọwa ọgụgụ asatọ, obosara adreesị nke 32 bit, na obosara data nke nhazi 512 bits.
• A na-amachibido elekere na 200 MHz ka ọ na-eme nyocha oge iji nweta ọnụọgụ ọrụ.

Nkọwa ọrụ (Jụọ ajụjụ)
Akụkụ a na-akọwa nkọwa mmejuputa nke DDR_AXI4_Arbiter. Onu ogugu a na-egosi eserese pin-out nke DDR AXI4 Arbiter. Ọgụgụ 1-1. Eserese ngọngọ Pin-Ọkwa dị elu maka interface Arbiter Arbiter

Ọnụọgụ na-esonụ na-egosi eserese ngọngọ sistemụ ọkwa nke DDR_AXI4_Arbiter na ọnọdụ interface ụgbọ ala. Ọgụgụ 1-2. Eserese-ọkwa ngọngọ nke DDR_AXI4_Arbiter

A na-akpalite azụmahịa agụ site na ịtọ akara ndenye r(x)_req_i elu n'otu ọwa ọgụgụ. Onye na-ekpe ikpe na-aza site na nnabata mgbe ọ dị njikere ijere arịrịọ agụ. Mgbe ahụ ọ samples mmalite AXI adreesị wee gụọ nha mgbawa nke bụ ntinye sitere na onye mbido mpụga. Ọwa ahụ na-ahazi ntinye ma na-ewepụta azụmahịa AXI achọrọ iji gụọ data sitere na ebe nchekwa DDR. Mpụta data agụ sitere na onye na-ekpe ikpe na-adịkarị na ọwa niile a na-agụ. N'oge a na-agụ data, data agụ nke ziri ezi nke ọwa kwekọrọ na-aga elu. A na-egosipụta njedebe nke azụmahịa gụpụtara site na mgbama emechara mgbe ezipụ bytes niile achọrọ. Dị ka azụmahịa ọgụgụ, a na-akpalite azụmahịa ederede site na ịtọ akara ntinye w(x)_req_i elu. Tinyere akara arịrịọ, adreesị mmalite dee na ogologo mgbawa ga-enwerịrị n'oge arịrịọ ahụ. Mgbe onye na-ekpe ikpe dị maka inye arịrịọ edere ede, ọ na-aza site na izipu mgbaama nkwenye na ọwa kwekọrọ. Mgbe ahụ onye ọrụ ga-enye data ederede yana akara ngosi data ziri ezi na ọwa. Ọnụọgụ nke clocks data ziri ezi oge dị elu ga-adakọrịrị n'ogologo gbawara. Onye na-ekpe ikpe na-emecha ọrụ ide ihe wee debe akara ngosi edere nke ọma na-egosi mmecha azụmahịa ederede.
DDR_AXI4_Arbiter Parameters na Interface Signals (Jụọ ajụjụ)
Akụkụ a na-atụle paramita dị na DDR_AXI4_Arbiter GUI configurator na akara I/O.
2.1 Ntọala nhazi (Jụọ ajụjụ)
Tebụlụ na-esote depụtara nkọwa nke paramita nhazi ejiri na mmejuputa ngwaike nke DDR_AXI4_Arbiter. Ndị a bụ parampat ma nwee ike ịdịgasị iche dịka ihe ngwa chọrọ.

Tebụl 2-1. Nhazi nhazi

Signal Aha	Nkọwa
Ogologo AXI ID	Na-akọwa obosara AXI ID.
Ogologo data AXI	Na-akọwa obosara data AXI.
Obosara adreesị AXI	Na-akọwa obosara adreesị AXI
Ọnụọgụ ọwa Gụọ	Nhọrọ iji họrọ enweghị ọwa ederede achọrọ site na menu ndọda sitere na otu ọwa ruo ọwa ide asatọ.
Ọnụọgụ nke ọwa Dee	Nhọrọ ịhọrọ ọwa ọgụgụ achọrọ site na menu ndọpụta sitere na otu ọwa ruo ọwa ọgụgụ asatọ.
AXI4_SELECTION	Nhọrọ iji họrọ n'etiti AXI4_MASTER na AXI4_MIRRORED_SLAVE.
Interface Arbiter	Nhọrọ ịhọrọ interface ụgbọ ala.

Ihe ntinye na ntinye aka (Jụọ ajụjụ)
Tebụlụ na-esote depụtara ntinye na ọdụ ụgbọ mmiri nke DDR AXI4 Arbiter maka interface ụgbọ ala.
Isiokwu 2-2. Ọdụ ụgbọ mmiri ntinye na ntinye maka interface ụgbọ ala Arbiter

Signal Aha	Ntuziaka	Obosara	Nkọwa
reset_i	Ntinye	—	Mgbama nrụpụta ihe nrụgharị adịghị arụ ọrụ iji chepụta
sys_ckl_i	Ntinye	—	Elekere sistemụ
ddr_ctrl_ready_i	Ntinye	—	Na-anata mgbama Ntinye dị njikere n'aka onye njikwa DDR
ARVALID_I_0	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 0
ARSIZE_I_0	Ntinye	8 ibeji	gụọ nha gbawara site na ọwa ọgụgụ 0
ARADDR_I_0	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 0
ARREADY_O_0	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 0
RVALID_O_0	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 0
RDATA_O_0	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 0
RLAST_O_0	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 0
BUSER_O_r0	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 0
ARVALID_I_1	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 1
ARSIZE_I_1	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 1
ARADDR_I_1	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 1
ARREADY_O_1	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 1
RVALID_O_1	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 1
RDATA_O_1	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 1
RLAST_O_1	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 1
BUSER_O_r1	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 1
ARVALID_I_2	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 2

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
ARSIZE_I_2	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 2
ARADDR_I_2	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 2
ARREADY_O_2	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 2
RVALID_O_2	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 2
RDATA_O_2	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 2
RLAST_O_2	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 2
BUSER_O_r2	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 2
ARVALID_I_3	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 3
ARSIZE_I_3	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 3
ARADDR_I_3	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 3
ARREADY_O_3	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 3
RVALID_O_3	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 3
RDATA_O_3	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 3
RLAST_O_3	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 3
BUSER_O_r3	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 3
ARVALID_I_4	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 4
ARSIZE_I_4	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 4
ARADDR_I_4	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 4
ARREADY_O_4	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 4
RVALID_O_4	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 4
RDATA_O_4	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 4
RLAST_O_4	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 4
BUSER_O_r4	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 4
ARVALID_I_5	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 5
ARSIZE_I_5	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 5
ARADDR_I_5	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 5
ARREADY_O_5	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 5
RVALID_O_5	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 5
RDATA_O_5	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 5
RLAST_O_5	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 5
BUSER_O_r5	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 5
ARVALID_I_6	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 6
ARSIZE_I_6	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 6
ARADDR_I_6	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 6
ARREADY_O_6	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 6
RVALID_O_6	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 6
RDATA_O_6	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 6
RLAST_O_6	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 6

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
BUSER_O_r6	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 6
ARVALID_I_7	Ntinye	—	Gụọ arịrịọ sitere na ọwa ọgụgụ 7
ARSIZE_I_7	Ntinye	8 ibeji	Gụọ nha gbawara site na ọwa ọgụgụ 7
ARADDR_I_7	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 7
ARREADY_O_7	Mpụta	—	Nkwenye onye ọka iwu ịgụ arịrịọ sitere na ọwa ọgụgụ 7
RVALID_O_7	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 7
RDATA_O_7	Mpụta	[AXI_DATA_WIDTH-1 : 0]	Gụọ data sitere na ọwa ọgụgụ 7
RLAST_O_7	Mpụta	—	Gụọ ngwụcha mgbama etiti site na ọwa ọgụgụ 7
BUSER_O_r7	Mpụta	—	Gụọ mmecha ka ị gụọ ọwa 7
AWSIZE_I_0	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 0
WDATA_I_0	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 0
WVALID_I_0	Ntinye	—	Dee data bara uru iji dee ọwa 0
AWVALID_I_0	Ntinye	—	Dee arịrịọ site na ọwa dee 0
AWADDR_I_0	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 0
AWREADY_O_0	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 0
BUSER_O_0	Mpụta	—	Dee mmecha iji dee ọwa 0
AWSIZE_I_1	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 1
WDATA_I_1	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 1
WVALID_I_1	Ntinye	—	Dee data bara uru iji dee ọwa 1
AWVALID_I_1	Ntinye	—	Dee arịrịọ site na ọwa dee 1
AWADDR_I_1	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 1
AWREADY_O_1	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 1
BUSER_O_1	Mpụta	—	Dee mmecha iji dee ọwa 1
AWSIZE_I_2	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 2
WDATA_I_2	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 2
WVALID_I_2	Ntinye	—	Dee data bara uru iji dee ọwa 2
AWVALID_I_2	Ntinye	—	Dee arịrịọ site na ọwa dee 2
AWADDR_I_2	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 2
AWREADY_O_2	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 2
BUSER_O_2	Mpụta	—	Dee mmecha iji dee ọwa 2
AWSIZE_I_3	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 3
WDATA_I_3	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 3
WVALID_I_3	Ntinye	—	Dee data bara uru iji dee ọwa 3
AWVALID_I_3	Ntinye	—	Dee arịrịọ site na ọwa dee 3
AWADDR_I_3	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 3
AWREADY_O_3	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 3
BUSER_O_3	Mpụta	—	Dee mmecha iji dee ọwa 3
AWSIZE_I_4	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 4

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
WDATA_I_4	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 4
WVALID_I_4	Ntinye	—	Dee data bara uru iji dee ọwa 4
AWVALID_I_4	Ntinye	—	Dee arịrịọ site na ọwa dee 4
AWADDR_I_4	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 4
AWREADY_O_4	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 4
BUSER_O_4	Mpụta	—	Dee mmecha iji dee ọwa 4
AWSIZE_I_5	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 5
WDATA_I_5	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 5
WVALID_I_5	Ntinye	—	Dee data bara uru iji dee ọwa 5
AWVALID_I_5	Ntinye	—	Dee arịrịọ site na ọwa dee 5
AWADDR_I_5	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 5
AWREADY_O_5	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 5
BUSER_O_5	Mpụta	—	Dee mmecha iji dee ọwa 5
AWSIZE_I_6	Ntinye	8 ibeji	Dee nha mgbawa maka ide ọwa 6
WDATA_I_6	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 6
WVALID_I_6	Ntinye	—	Dee data bara uru iji dee ọwa 6
AWVALID_I_6	Ntinye	—	Dee arịrịọ site na ọwa dee 6
AWADDR_I_6	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 6
AWREADY_O_6	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 6
BUSER_O_6	Mpụta	—	Dee mmecha iji dee ọwa 6
AWSIZE_I_7	Ntinye	8 ibeji	Dee nha mgbawa site na ọwa dee 7
WDATA_I_7	Ntinye	[AXI_DATA_WIDTH-1:0]	Ntinye data vidiyo iji dee ọwa 7
WVALID_I_7	Ntinye	—	Dee data bara uru iji dee ọwa 7
AWVALID_I_7	Ntinye	—	Dee arịrịọ site na ọwa dee 7
AWADDR_I_7	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke dee ga-emerịrị site na ọwa dee 7
AWREADY_O_7	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ site na ọwa ide 7
BUSER_O_7	Mpụta	—	Dee mmecha iji dee ọwa 7

Tebụlụ na-esonụ na-edepụta ntinye na ọdụ ụgbọ mmiri nke DDR AXI4 Arbiter maka interface obodo.
Isiokwu 2-3. Ọdụ ụgbọ mmiri ntinye na mmepụta maka interface Arbiter nke obodo

Signal Aha	Ntuziaka	Obosara	Nkọwa
reset_i	Ntinye	—	Mgbama nrụpụta asynchronous dị ala na-arụ ọrụ iji chepụta
sys_clk_i	Ntinye	—	Elekere sistemụ
ddr_ctrl_ready_i	Ntinye	—	Na-anata mgbama ntinye dị njikere site na onye njikwa DDR
r0_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 0
r0_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r0_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 0
r0_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 0

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
r0_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 0
r0_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 0
r1_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 1
r1_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r1_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 1
r1_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 1
r1_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 1
r1_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 1
r2_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 2
r2_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r2_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 2
r2_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 2
r2_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 2
r2_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 2
r3_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 3
r3_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r3_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 3
r3_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 3
r3_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 3
r3_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 3
r4_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 4
r4_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r4_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 4
r4_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 4
r4_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 4
r4_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 4
r5_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 5
r5_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r5_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 5
r5_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 5
r5_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 5
r5_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 5
r6_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 6
r6_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa
r6_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 6
r6_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 6
r6_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 6
r6_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 6
r7_req_i	Ntinye	—	Gụọ arịrịọ sitere n'aka onye mmalite 7
r7_burst_size_i	Ntinye	8 ibeji	Gụọ nha mgbawa

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
r7_rstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR ebe a ga-amalite ịgụ maka ọwa ịgụ 7
r7_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ịgụ arịrịọ sitere n'aka onye mbido 7
r7_data_valid_o	Mpụta	—	Gụọ data bara uru site na ọwa ọgụgụ 7
r7_emela_o	Mpụta	—	Gụọ mmecha nye onye mmalite 7
rdata_o	Mpụta	[AXI_DATA_WIDTH - 1:0]	Mbupụta data vidiyo sitere na ọwa ọgụgụ
w0_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w0_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 0
w0_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 0
w0_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 0
w0_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 0
w0_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 0
w0_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 0
w1_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w1_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 1
w1_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 1
w1_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 1
w1_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 1
w1_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 1
w1_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 1
w2_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w2_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 2
w2_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 2
w2_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 2
w2_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 2
w2_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 2
w2_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 2
w3_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w3_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 3
w3_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 3
w3_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 3
w3_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 3
w3_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 3
w3_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 3
w4_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w4_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 4
w4_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 4
w4_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 4
w4_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke dee ga-emerịrị site na ọwa dee 4

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
w4_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 4
w4_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 4
w5_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w5_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 5
w5_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 5
w5_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 5
w5_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 5
w5_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 5
w5_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 5
w6_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w6_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 6
w6_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 6
w6_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 6
w6_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 6
w6_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 6
w6_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 6
w7_burst_size_i	Ntinye	8 ibeji	Dee nha mgbawa
w7_data_i	Ntinye	[AXI_DATA_WIDTH - 1:0]	Ntinye data vidiyo iji dee ọwa 7
w7_data_valid_i	Ntinye	—	Dee data bara uru iji dee ọwa 7
w7_req_i	Ntinye	—	Dee arịrịọ sitere n'aka onye mmalite 7
w7_wstart_addr_i	Ntinye	[AXI_ADDR_WIDTH - 1:0]	Adreesị DDR nke ekwesịrị ime site na ọwa dee 7
w7_ack_o	Mpụta	—	Nkwenye onye ọka ikpe ide arịrịọ sitere n'aka onye mbido 7
w7_emela_o	Mpụta	—	Dee mmecha nye onye mmalite 7
Ihe ngosi AXI I/F
Gụọ ọwa adreesị
arid_o	Mpụta	[AXI_ID_WIDTH - 1:0]	Gụọ ID adreesị. njirimara tag maka ndị na-agụ adreesị otu akara.
araddr_o	Mpụta	[AXI_ADDR_WIDTH - 1:0]	Gụọ adreesị. Na-enye adreesị mbụ nke azụmahịa mwapụrụ agụ. Naanị adreesị mmalite nke mgbawa ka enyere.
arlen_o	Mpụta	[7:0]	Ogologo mgbawa. Na-enye ọnụ ọgụgụ nke mbufe na mgbawa. Ozi a na-ekpebi ọnụọgụ mbufe data metụtara adreesị.
arsize_o	Mpụta	[2:0]	Nha mgbawa. Ogo nke mbufe ọ bụla na mgbawa.
arburst_o	Mpụta	[1:0]	Ụdị mgbawa. Ejikọtara ya na ozi nha, kọwaa otu esi agbakọọ adreesị maka mbufe ọ bụla n'ime mgbawa ahụ. Edobere na 2'b01 à adreesị agbakwunyere gbawara.
arlock_o	Mpụta	[1:0]	Ụdị mkpọchi. Na-enye ozi ndị ọzọ gbasara njirimara atomic nke mbufe. Edobere na 2'b00 à Nnweta Nkịtị.

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
archache_o	Mpụta	[3:0]	Ụdị cache. Na-enye ozi ndị ọzọ gbasara njirimara cacheable nke mbufe. Edobere na 4'b0000 à Na-enweghị ike ịchekwa na nke anaghị echekwa ya.
arprot_o	Mpụta	[2:0]	Ụdị nchedo. Na-enye ozi otu nchekwa maka azụmahịa. Edobere na 3'b000 à Nkịtị, nweta data echekwara.
arvalid_o	Mpụta	—	Gụọ adreesị ziri ezi. Mgbe HIGH, adreesị na-agụ na ozi njikwa dị irè ma nọgide na-adị elu ruo mgbe adreesị kwetara mgbaàmà, dị njikere, dị elu. 1 = Adreesị na ozi njikwa dị irè 0 = Adreesị na ozi njikwa adịghị mma
njikere_o	Ntinye	—	Gụọ adreesị njikere. Ebumnuche dị njikere ịnakwere adreesị yana akara njikwa metụtara. 1 = ebumnuche dị njikere 0 = ebumnuche adịghị njikere
Gụọ Channel Data
kpochapu	Ntinye	[AXI_ID_WIDTH - 1:0]	Gụọ ID tag. NJ tag nke ndị na-agụ data otu mgbaàmà. A na-emepụta uru mkpochapụ site na ebumnuche ma ga-adaba na uru kpọrọ nkụ nke azụmahịa agụ nke ọ na-aza.
rdata	Ntinye	[AXI_DATA_WIDTH - 1:0]	Gụọ data
resp	Ntinye	[1:0]	Gụọ nzaghachi. Ọkwa nke mbufe ọgụgụ. Ọzịza ndị anabatara bụ OKAY, EXOKAY, SLVERR na DECERR.
rlast	Ntinye	—	Gụọ ikpeazụ. Nbufe ikpeazụ na mgbawa ọgụgụ.
rvalid	Ntinye	—	Gụọ nke ọma. Data ọgụgụ achọrọ dị na mbufe ọgụgụ nwere ike mezue. 1 = gụọ data dị 0 = gụọ data adịghị
ejikere	Mpụta	—	Gụọ njikere. Onye mbido nwere ike ịnakwere data agụ na ozi nzaghachi. 1= onye mmalite dị njikere 0 = onye mmalite adịghị njikere
Dee ọwa adreesị
ihe	Mpụta	[AXI_ID_WIDTH - 1:0]	Dee ID adreesị. njirimara tag maka ide adreesị otu akara.
awaddr	Mpụta	[AXI_ADDR_WIDTH - 1:0]	Dee adreesị. Na-enye adreesị nke mbufe mbu n'ime azụmahịa mwapu dee. A na-eji akara njikwa jikọtara ya iji chọpụta adreesị nke nnyefe ndị fọdụrụ na mgbawa ahụ.
agba	Mpụta	[7:0]	Ogologo mgbawa. Na-enye ọnụ ọgụgụ nke mbufe na mgbawa. Ozi a na-ekpebi ọnụọgụ mbufe data metụtara adreesị.
egwu	Mpụta	[2:0]	Nha mgbawa. Ogo nke mbufe ọ bụla na mgbawa. Ọkpụkpụ Byte na-egosi kpọmkwem ụzọ byte ga-emelite.
egwu	Mpụta	[1:0]	Ụdị mgbawa. Ejikọtara ya na ozi nha, kọwaa otu esi agbakọọ adreesị maka mbufe ọ bụla n'ime mgbawa ahụ. Edobere na 2'b01 à adreesị agbakwunyere gbawara.

………… gara n'ihu
Signal Aha	Ntuziaka	Obosara	Nkọwa
ujo	Mpụta	[1:0]	Ụdị mkpọchi. Na-enye ozi ndị ọzọ gbasara njirimara atomic nke mbufe. Edobere na 2'b00 à Nnweta Nkịtị.
awcache	Mpụta	[3:0]	Ụdị cache. Na-egosi ihe a na-echekwa, nke a na-echekwa echekwa, dee, dee azụ, ma kenye njiri mara azụmahịa ahụ. Edobere na 4'b0000 à Na-enweghị ike ịchekwa na nke anaghị echekwa ya.
emeghi	Mpụta	[2:0]	Ụdị nchedo. Na-egosi ọkwa nchekwa nkịtị, ihe ùgwù ma ọ bụ echekwabara nke azụmahịa yana ma azụmahịa ahụ bụ ịnweta data ma ọ bụ ohere ntụziaka. Edobere na 3'b000 na Normal, nweta data echekwara.
mma	Mpụta	—	Dee adreesị ziri ezi. Na-egosi na adreesị ederede na ozi njikwa dị. 1 = adreesị na ozi njikwa dị 0 = adreesị na ozi njikwa adịghị. Adreesị na ozi njikwa na-anọgide na-akwụsi ike ruo mgbe adreesị kwetara mgbama, ọ dịla njikere, ga-adị elu.
nke ọma	Ntinye	—	Dee adreesị njikere. Na-egosi na ebumnuche dị njikere ịnakwere adreesị yana akara njikwa metụtara. 1 = ebumnuche dị njikere 0 = ebumnuche adịghị njikere
Dee ọwa data
wdata	Mpụta	[AXI_DATA_WIDTH - 1:0]	Dee data
wstrb	Mpụta	[AXI_DATA_WIDTH - 8:0]	Dee strobes. Mgbama a na-egosi ụzọ byte ga-emelite na ebe nchekwa. Enwere otu strobe ederede maka ibeji asatọ ọ bụla nke ụgbọ ala dee data.
wlast	Mpụta	—	Dee ikpeazụ. Nbufe ikpeazụ na mwapu dee.
dị mma	Mpụta	—	Dee nke ọma. Data ide ziri ezi na strobes dị. 1 = dee data na strobes dị 0 = dee data na strobes adịghị
wready	Ntinye	—	Dee njikere. Ebumnuche nwere ike ịnakwere data ederede. 1 = ebumnuche dị njikere 0 = ebumnuche adịghị njikere
Dee ọwa nzaghachi
ikere	Ntinye	[AXI_ID_WIDTH - 1:0]	NJ nzaghachi. Ihe njirimara tag nke nzaghachi dee. Ọnụ ahịa ọnụahịa ahụ ga-adakọrịrị ọnụ ahịa azụmahịa ederede nke ebumnuche na-aza.
bresp	Ntinye	[1:0]	Dee nzaghachi. Ọnọdụ nke azụmahịa dee. Nzaghachi ndị a na-anabata bụ OKAY, EXOKAY, SLVERR, na DECERR.
bvalid	Ntinye	—	Dee nzaghachi bara uru. Nzaghachi ederede ziri ezi dị. 1 = dee nzaghachi dị 0 = dee nzaghachi adịghị
achịcha	Mpụta	—	Azịza dị njikere. Onye mbido nwere ike ịnakwere ozi nzaghachi. 1 = onye mmalite dị njikere 0 = onye mmalite adịghị njikere

Eserese oge (Jụọ ajụjụ)
Akụkụ a na-atụle eserese oge DDR_AXI4_Arbiter. Ọnụọgụ ndị a na-egosi njikọ nke ntinye arịrịọ na-agụ na ide, malite adreesị ebe nchekwa, dee ntinye sitere na onye mbido mpụga, gụọ ma ọ bụ dee nkwenye, ma gụọ ma ọ bụ dee ntinye mmecha nyere site n'aka onye ikpe.
Ọgụgụ 3-1. Eserese oge maka akara ngosi ejiri na Edemede/agụ site na Interface AXI4

Testbench (Jụọ ajụjụ)
A na-eji testbench jikọtara ọnụ iji nyochaa ma nwalee DDR_AXI4_Arbiter dị ka testbench onye ọrụ. Enyere Testbench iji lelee arụmọrụ nke DDR_AXI4_Arbiter IP. Testbench a na-arụ ọrụ naanị maka ọwa abụọ na-agụ na ọwa ederede abụọ nwere nhazi Interface Bus.
 Simulation (Jụọ ajụjụ)
Usoro ndị a na-akọwa otu esi eme ka isi na-eji testbench:

1. Mepee taabụ katalọgụ Libero® SoC, gbasaa Solutions-Video, pịa DDR_AXI4_Arbiter ugboro abụọ, wee pịa OK. Edepụtara akwụkwọ ejikọtara na IP n'okpuru Documentation. Ihe dị mkpa: Ọ bụrụ na ịhụghị taabụ katalọgụ, gaa na View > Menu Windows wee pịa katalọgụ ka a hụ ya.

Ọgụgụ 4-1. DDR_AXI4_Arbiter IP Core na Libero SoC katalọgụ

Mepụta windo akụrụngwa na-egosi dị ka egosiri na ndị a. Pịa OK. Gbaa mbọ hụ na aha ahụ bụ DDR_AXI4_ARBITER_PF_C0.
Ọgụgụ 4-2. Mepụta akụrụngwa

Hazie IP maka ọwa ịgụ 2, 2 dee ọwa wee họrọ Interface ụgbọ ala dị ka egosiri na foto a wee pịa OK iji mepụta IP.
Ọgụgụ 4-3. Nhazi

Na taabụ Stimulus Hierarchy, họrọ testbench (DDR_AXI4_ARBITER_PF_tb.v), pịa aka nri wee pịa Simulate Pre-Synth Design> Mepee Interactively.
Ihe dị mkpa: Ọ bụrụ na ịhụghị taabụ Stimulus Hierarchy, gaa na View > Menu Windows wee pịa Stimulus Hierarchy iji mee ka a hụ ya.
Ọgụgụ 4-4. Na-eme atụmatụ tupu synthesisModelSim meghere ya na testbench file, dị ka e gosiri na foto na-esonụ.
Ọgụgụ 4-5. Ohere Simulation Model

Ihe dị mkpa: Ọ bụrụ na akwụsịla ịme anwansị ahụ n'ihi oke oge ịgba ọsọ akọwapụtara na .do file, jiri ọsọ-niile iwu imezu simulation.
Akụkọ ngbanwe (Jụọ ajụjụ)
Akụkọ ngbanwe ahụ na-akọwa mgbanwe ndị etinyere na akwụkwọ ahụ. Edepụtara mgbanwe ndị a site na ntughari, malite na mbipụta kachasị ugbu a.
Isiokwu 5-1. Akụkọ ngbanwe

Ndozigharị	Ụbọchị	Nkọwa
A	04/2023	Nke a bụ ndepụta mgbanwe na ntughari A nke akwụkwọ ahụ: • Bugharịa akwụkwọ ahụ na ndebiri Microchip. • Emelitere nọmba akwụkwọ ahụ na DS00004976A site na 50200950. • agbakwunyere 4. Testbench.
2.0	—	Nke a bụ ndepụta mgbanwe na 2.0 nke akwụkwọ ahụ: • agbakwunyere Ọgụgụ 1-2. • agbakwunyere Tebụl 2-2. • Emelitere aha ụfọdụ ndenye na aha mgbaama mmepụta n'ime Tebụl 2-2.
1.0	—	Mwepụta mbụ.

Nkwado Microchip FPGA (Jụọ ajụjụ)
Otu ngwaahịa Microchip FPGA na-eji ọrụ nkwado dị iche iche kwado ngwaahịa ya, gụnyere Ọrụ Ndị Ahịa, Ụlọ Ọrụ Nkwado nka na ụzụ Ndị Ahịa, a websaịtị, na ụlọ ahịa ahịa zuru ụwa ọnụ. A na-atụ aro ka ndị ahịa gaa na akụrụngwa Microchip n'ịntanetị tupu ha akpọtụrụ nkwado n'ihi na o yikarịrị ka azaghachila ajụjụ ha. Kpọtụrụ Ụlọ Ọrụ Nkwado nka na ụzụ site na websaịtị na www.microchip.com/support. Kwuo nọmba akụkụ ngwaọrụ FPGA, họrọ udi ikpe dabara adaba, wee bulite imewe files mgbe ị na-ekepụta ikpe nkwado teknụzụ. Kpọtụrụ ọrụ ndị ahịa maka nkwado ngwaahịa na-abụghị teknụzụ, dị ka ọnụahịa ngwaahịa, nkwalite ngwaahịa, ozi emelitere, ọkwa ịtụ na ikike.

• Site na North America, kpọọ 800.262.1060
• Site na ụwa ndị ọzọ, kpọọ 650.318.4460
• Fax, si n'ebe ọ bụla n'ụwa, 650.318.8044

Ozi Microchip (Jụọ ajụjụ)

Microchip Websaịtị (Jụọ ajụjụ)
Microchip na-enye nkwado ntanetị site na anyị websaịtị na www.microchip.com/. Nke a weba na-eji saịtị eme ihe files na ozi dị mfe maka ndị ahịa. Ụfọdụ ọdịnaya dị gụnyere:

• Nkwado ngwaahịa - Akwụkwọ data na errata, ndetu ngwa na sampmmemme, akụrụngwa imewe, ntuziaka onye ọrụ na akwụkwọ nkwado ngwaike, ewepụtara sọftụwia kacha ọhụrụ, na ngwa ngwa echekwara
• Nkwado nka na ụzụ izugbe - Ajụjụ A na-ajụkarị (FAQ), arịrịọ nkwado teknụzụ, otu mkparịta ụka n'ịntanetị, ndepụta ndị otu mmemme mmebe Microchip
• Azụmahịa nke Microchip - Ntuziaka onye na-ahọpụta ngwaahịa na ịtụ ahịa, mbipụta akwụkwọ akụkọ Microchip kacha ọhụrụ, ndepụta nke nzukọ ọmụmụ na mmemme, ndepụta nke ụlọ ọrụ ire ahịa Microchip, ndị nkesa, na ndị nnọchi anya ụlọ ọrụ mmepụta ihe.

Ọrụ ngosi mgbanwe ngwaahịa (Jụọ ajụjụ)
Ọrụ ngosi mgbanwe ngwaahịa Microchip na-enyere ndị ahịa aka ugbu a na ngwaahịa Microchip. Ndị debanyere aha ga-enweta ọkwa ozi-e mgbe ọ bụla enwere mgbanwe, mmelite, nlegharị anya ma ọ bụ errata metụtara ezinụlọ ngwaahịa akọwapụtara ma ọ bụ ngwa mmepe nke mmasị. Iji debanye aha, gaa na www.microchip.com/pcn ma soro ntuziaka ndebanye aha.
Nkwado ndị ahịa (Jụọ ajụjụ)
Ndị na-eji ngwaahịa Microchip nwere ike ịnweta enyemaka site na ọtụtụ ọwa:

• Onye nkesa ma ọ bụ onye nnọchi anya
• Ụlọ ọrụ ire ahịa mpaghara
• Injinia Ngwọta agbakwunyere (ESE)
• Nkwado ndị teknuzu

Ndị ahịa kwesịrị ịkpọtụrụ onye nkesa ha, onye nnọchi anya ma ọ bụ ESE maka nkwado. Ọfịs ahịa mpaghara dịkwa maka inyere ndị ahịa aka. Agụnyere ndepụta ụlọ ọrụ ahịa na ebe n'ime akwụkwọ a. Nkwado nka na ụzụ dị site na websaịtị na: www.microchip.com/support.
Microchip na-emepụta atụmatụ nchedo koodu (Jụọ ajụjụ)
Rịba ama nkọwa ndị a nke njirimara nchedo koodu na ngwaahịa Microchip:

• Ngwaahịa Microchip na-ezute nkọwapụta dị na mpempe data Microchip ha.
• Microchip kwenyere na ezinaụlọ nke ngwaahịa ya nwere nchekwa mgbe ejiri ya n'ụzọ achọrọ, n'ime nkọwapụta ọrụ yana n'okpuru ọnọdụ nkịtị.
• Ụkpụrụ Microchip na-eji ike na-echebe ikike ikike ọgụgụ isi ya. Mgbalị imebi atụmatụ nchedo koodu nke ngwaahịa Microchip bụ nke amachibidoro nke ọma ma nwee ike imebi iwu nwebiisinka DigitalMillennium.
• Ma Microchip ma ọ bụ ndị nrụpụta semiconductor ọ bụla enweghị ike ikwe nkwa nchekwa nke koodu ya. Nchedo koodu apụtaghị na anyị na-ekwe nkwa na ngwaahịa a "enweghị ike imebi". Nchekwa koodu na-agbanwe mgbe niile. Microchip agba mbọ na-aga n'ihu na-emeziwanye njirimara nchedo koodu nke ngwaahịa anyị.

Ozi Iwu (Jụọ ajụjụ)
Enwere ike iji akwụkwọ a na ozi dị n'ime ya naanị site na ngwaahịa Microchip, gụnyere iji chepụta, nwalee ma jikọta ngwaahịa Microchip na ngwa gị. Iji ozi a n'ụzọ ọ bụla ọzọ mebiri usoro ndị a. A na-enye ozi gbasara ngwa ngwaọrụ naanị maka ịdị mma gị yana mmelite nwere ike dochie ya. Ọ bụ ọrụ gị ịhụ na ngwa gị mezuru nkọwapụta gị. Kpọtụrụ ụlọ ọrụ ịre ahịa Microchip mpaghara gị maka nkwado ọzọ ma ọ bụ nweta nkwado ọzọ na www.microchip.com/en-us/support/design-help/ ọrụ nkwado ndị ahịa. Ozi a bụ MICROCHIP “DỊ KA Ọ BỤ”. MICROCHIP emeghị nnochite anya ma ọ bụ akwụkwọ ikike n'ụdị ọ bụla ma ekwupụta ma ọ bụ kwupụta ya, edere ma ọ bụ n'ọnụ, usoro iwu ma ọ bụ ọzọ, metụtara ozi ahụ gụnyere mana ọnweghị oke n'iwu ọ bụla na-akwadoghị, iwu na-akwadoghị. NA ahụ dị mma maka ebumnuche pụrụ iche, ma ọ bụ akwụkwọ ikike metụtara ọnọdụ ya, ogo ya, ma ọ bụ arụmọrụ ya. Ọ BỤGHỊ ỌMỤNỤ Ọ BỤGHỊ MICROCHIP GA-AKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỌ Ọ BỤLA NKE Ọ BỤLA OZI Ọ BỤ Ọ BỤ Ọ BỤ Ọ BỤ Ọ BỤ Ọ BỤ Ọ BỤ Ọ BỤ KWESỊRỊ. NDỤMỌDỤ NDỊ DỊ MMADỤ N'ỤRỤ IKE MA Ọ BỤ NDỊ MMADỤ NDỊ A GA-ECHICHE? Ruo n'ụzọ zuru ezu iwu kwadoro, MICROCHIP'S TOTAL IBLIABILIBLEY NA N'ỤLỌ NCHE N'ỤZỌ Ọ BỤLA emetụtara ozi ahụ ma ọ bụ ojiji ya agaghị agafe ọnụọgụ ụgwọ, Ọ BỤRỤ Ọ BỤLA, na ị kwụọla ụgwọ ozugbo iji mebie ya. Iji ngwaọrụ Microchip na nkwado ndụ yana/ma ọ bụ ngwa nchekwa bụ kpamkpam n'ihe ize ndụ nke onye zụrụ ya, onye na-azụ ya kwenyere ịgbachitere, kwụọ ụgwọ ma jide Microchip na-adịghị emerụ ahụ site na mmebi ọ bụla, nkwuputa, uwe, ma ọ bụ mmefu sitere na ụdị ojiji ahụ. Ọnweghị ikike ebugara, n'ezoghị ọnụ ma ọ bụ n'ụzọ ọzọ, n'okpuru ikike ikike ọgụgụ isi Microchip ọ gwụla ma ekwuputara ya.
Akara ahia (Jụọ ajụjụ)
Aha Microchip na akara ngosi, akara Microchip, Adaptec, AVR, akara AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXXSty MediaLB, megaAVR, Microsemi, akara microsemi, akara kacha, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, akara PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Sengenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SynServer, Tachyon , TimeSource, obere AVR, UNI/O, Vectron, na XMEGA bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na USA na obodo ndị ọzọ. AgileSwitch, APT, ClockWorks, The agbakwunyere Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Waya, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, na ZL bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na USA n'akụkụ isi suppression, AKS, Analog-for-the-Digital Age, Capacitor ọ bụla, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication , CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Nkezi Nkezi Dị Dynamic, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, ọgụgụ isi myirịta, IntelliMOS, Inter-Chip Njikọta, JitterBlocker-Didiplay , KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Asambodo akara, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX Blocker , RTG4, SAMICE, Oghere Usoro Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, ngụkọta ntachi obi, oge ntụkwasị obi, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, na ZENA bụ ụghalaahịa nke Microchip Technology Incorporated na USA na obodo ndị ọzọ. SQTP bụ akara ọrụ nke Microchip Technology Incorporated na USA The Adaptec logo, Frequency on Demand, Silicon Storage Technology, na Symmcom bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Inc. na mba ndị ọzọ. GestIC bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Germany II GmbH & Co.KG, onye enyemaka Microchip Technology Inc., na mba ndị ọzọ. ụghalaahịa ndị ọzọ niile a kpọtụrụ aha n'ime ebe a bụ akụ nke ụlọ ọrụ ha. © 2023, Microchip Technology Incorporated na ndị enyemaka ya. Ikike niile echekwabara.
ISBN: 978-1-6683-2302-1 Sistemụ Njikwa Ogo (Jụọ ajụjụ) Maka ozi gbasara Sistemụ Njikwa Ogo nke Microchip, biko gaa na www.microchip.com/quality.

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