ASMI Parallel II Intel FPGA IP
ASMI Parallel II Intel® FPGA IP yana ba da dama ga na'urori masu daidaitawa na Intel FPGA, waɗanda sune tsarin quad-serial (EPCQ), ƙananan vol.tage quad-serial sanyi (EPCQ-L), da EPCQ-A serial sanyi. Kuna iya amfani da wannan IP don karantawa da rubuta bayanai zuwa na'urorin filasha na waje don aikace-aikace, kamar sabunta tsarin nesa da SEU Sensitivity Map Header. File (.smh) ajiya.
Baya ga fasalulluka da ASMI Parallel Intel FPGA IP ke goyan baya, ASMI Parallel II Intel FPGA IP kuma yana goyan bayan:
- Samun damar walƙiya kai tsaye (rubuta/karanta) ta hanyar dubawar ƙwaƙwalwar ajiyar Avalon®.
- Rijistar sarrafawa don wasu ayyuka ta hanyar rajistar matsayi na sarrafawa (CSR) a cikin ƙirar ƙwaƙwalwar ajiyar Avalon.
- Fassara jimillar umarni daga ƙirar ƙwaƙwalwar ajiyar Avalon zuwa lambobin umarnin na'urar.
ASMI Parallel II Intel FPGA IP yana samuwa ga duk iyalai na na'urar Intel FPGA gami da na'urorin Intel MAX® 10 waɗanda ke amfani da yanayin GPIO.
ASMI Parallel II Intel FPGA IP kawai tana goyan bayan na'urorin EPCQ, EPCQ-L, da EPCQ-A. Idan kana amfani da na'urorin filasha na ɓangare na uku, dole ne ka yi amfani da Generic Serial Flash Interface Intel FPGA IP.
Ana goyan bayan ASMI Parallel II Intel FPGA IP a cikin sigar software ta Intel Quartus® Prime 17.0 zuwa gaba.
Bayanai masu alaƙa
- Gabatarwa zuwa Intel FPGA IP Cores
- Yana ba da cikakken bayani game da duk na'urorin IP na Intel FPGA, gami da daidaitawa, haɓakawa, haɓakawa, da kwaikwaiyon bayanan IP.
- Ƙirƙirar Siffar-Independent IP da Qsys Simulation Scripts
- Ƙirƙirar rubutun kwaikwaiyo waɗanda baya buƙatar ɗaukakawar hannu don haɓaka software ko sigar IP.
- Mafi kyawun Ayyukan Gudanarwa
- Jagorori don ingantaccen gudanarwa da ɗaukar nauyin aikin ku da IP files.
- ASMI Parallel Intel FPGA IP Core Jagora Jagora
- Generic Serial Flash Interface Intel FPGA IP Jagorar Mai Amfani
- Yana ba da tallafi ga na'urorin filasha na ɓangare na uku.
- AN 720: Yin Kwatankwacin Tushen ASMI a Tsarin ku
Bayanin Saki
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP.
Lambar sigar IP (XYZ) na iya canzawa daga sigar software ta Intel Quartus Prime zuwa wani. Canji a:
- X yana nuna babban bita na IP. Idan ka sabunta software na Quartus Prime na Intel, dole ne ka sabunta IP ɗin.
- Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
- Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.
Tebur 1. ASMI Parallel II Intel FPGA IP Bayanin Sakin
| Abu | Bayani |
| Sigar IP | 18.0 |
| Intel Quartus Prime Pro Edition Version | 18.0 |
| Ranar Saki | 2018.05.07 |
Tashoshi
Hoto 1. Tsarin Toshe Tashoshi
Tebur 2. Bayanin Tashoshi
| Sigina | Nisa | Hanyar | Bayani |
| Interface Bawan Avalon Memory-Mapped don CSR (avl_csr) | |||
| avl_csr_addr | 6 | Shigarwa | Avalon memory-mapped interface bas. Bus ɗin adireshin yana cikin magana. |
| avl_csr_karanta | 1 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon tana karanta iko zuwa CSR. |
| avl_csr_rddata | 32 | Fitowa | Avalon memory-mapped interface karanta bas ɗin bayanai daga CSR. |
| avl_csr_rubuta | 1 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon rubuta iko zuwa CSR. |
| avl_csr_writedata | 32 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon rubuta bas ɗin bayanai zuwa CSR. |
| avl_csr_waitquest | 1 | Fitowa | Avalon memory-mapped interface waitrequest iko daga CSR. |
| avl_csr_rddata_valid | 1 | Fitowa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon tana karanta bayanan inganci wanda ke nuna bayanan karanta CSR yana samuwa. |
| Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwaƙwalwa na Ƙwaƙwalwa ) don Samun Ƙwaƙwalwa (avl_ mem) | |||
| avl_mem_rubuta | 1 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon rubuta iko zuwa ƙwaƙwalwar ajiya |
| avl_mem_burstcount | 7 | Shigarwa | Avalon memory-mapped interface fashe ƙidaya don ƙwaƙwalwar ajiya. Ƙimar ta kewayo daga 1 zuwa 64 (mafi girman girman shafi). |
| avl_mem_waitquest | 1 | Fitowa | Avalon-taswirar žwažwalwar ajiya na dubawa ikon jiran jiran aiki daga ƙwaƙwalwar ajiya. |
| avl_mem_karanta | 1 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon karanta iko zuwa ƙwaƙwalwar ajiya |
| avl_mem_addr | N | Shigarwa | Avalon memory-mapped interface bas. Bus ɗin adireshin yana cikin magana.
Faɗin adireshin ya dogara da yawan ƙwaƙwalwar walƙiya da aka yi amfani da ita. |
| avl_mem_writedata | 32 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon rubuta bas ɗin bayanai zuwa ƙwaƙwalwar ajiya |
| avl_mem_readddata | 32 | Fitowa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon tana karanta bas ɗin bayanai daga ƙwaƙwalwar ajiya. |
| avl_mem_rddata_valid | 1 | Fitowa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon tana karanta bayanan inganci wanda ke nuna akwai bayanan karanta ƙwaƙwalwar ajiya. |
| avl_mem_byteenble | 4 | Shigarwa | Ƙwaƙwalwar taswirar ƙwaƙwalwar ajiyar Avalon rubuta bayanai tana ba da damar bas zuwa ƙwaƙwalwar ajiya. A yayin yanayin fashewa, bas ɗin da za a iya ɗauka zai kasance mai girma, 4'b1111. |
| Agogo da Sake saiti | |||
| clk | 1 | Shigarwa | Agogon shigarwa don agogon IP. (1) |
| sake saiti_n | 1 | Shigarwa | Sake saitin Asynchronous don sake saita IP.(2) |
| Interface Interface(3) | |||
| fqspi_dataout | 4 | Bidire | Shigar da tashar fitarwa ko fitarwa don ciyar da bayanai daga na'urar filasha. |
| ci gaba… | |||
| Sigina | Nisa | Hanyar | Bayani |
| qspi_dclk | 1 | Fitowa | Yana ba da siginar agogo zuwa na'urar filasha. |
| qspi_scein | 1 | Fitowa | Yana ba da siginar ncs zuwa na'urar filasha.
Yana goyan bayan Stratix® V, Arria® V, Cyclone® V, da tsofaffin na'urori. |
| 3 | Fitowa | Yana ba da siginar ncs zuwa na'urar filasha.
Yana goyan bayan Intel Arria 10 da Intel Cyclone 10 GX na'urorin. |
- Kuna iya saita mitar agogo zuwa ƙasa ko daidai da 50 MHz.
- Riƙe siginar don aƙalla zagayowar agogo ɗaya don sake saita IP.
- Akwai lokacin da ka kunna Kashe ma'aunin mu'amalar Serial Active Serial.
Bayanai masu alaƙa
- Ƙirar bayanai na Na'urori masu Quad-Serial (EPCQ).
- EPCQ-L Serial Kanfigareshan Bayanan Bayanan na'urorin
- EPCQ-A Serial Kanfigareshan Bayanan Bayanan Na'urar
Siga
Tebur 3. Saitunan Siga
| Siga | Ƙimar Shari'a | Bayani |
| Nau'in na'urar daidaitawa | EPCQ16, EPCQ32, EPCQ64, EPCQ128, EPCQ256, EPCQ512, EPCQ-L256, EPCQ-L512, EPCQ-L1024, EPCQ4A, EPCQ16A, EPCQ32A, EPCQ64A, EPCQ128 | Yana ƙayyade nau'in na'urar EPCQ, EPCQ-L, ko EPCQ-A da kake son amfani da ita. |
| Zaɓi yanayin I/O | MATSAYIN AL'ADA DUAL QUAD | Yana zaɓar faɗin faɗin bayanai lokacin da kuka kunna aikin Karatu da sauri. |
| Kashe keɓancewar keɓancewa na Serial Active | — | Yana tafiyar da siginonin ASMIBLOCK zuwa saman matakin ƙirar ku. |
| Kunna madaidaicin fil na SPI | — | Yana Fassara siginonin ASMIBLOCK zuwa guntun SPI. |
| Kunna samfurin kwaikwayo na walƙiya | — | Yana amfani da tsoho samfurin kwaikwayo na EPCQ 1024 don kwaikwayo. Idan kana amfani da na'urar filasha ta ɓangare na uku, koma zuwa AN 720: Yin Kwatankwacin Tushen ASMI a Tsarin ku don ƙirƙirar abin rufewa don haɗa samfurin walƙiya tare da Block ASMI. |
| Adadin Chip Select da aka yi amfani da shi | 1
2(4) 3(4) |
Yana zaɓar lambar guntu zaɓin da aka haɗa zuwa filasha. |
- Ana goyan baya kawai a cikin na'urorin Intel Arria 10, na'urorin Intel Cyclone 10 GX, da sauran na'urori tare da Enable SPI interface a kunne.
Bayanai masu alaƙa
- Ƙirar bayanai na Na'urori masu Quad-Serial (EPCQ).
- EPCQ-L Serial Kanfigareshan Bayanan Bayanan na'urorin
- EPCQ-A Serial Kanfigareshan Bayanan Bayanan Na'urar
- AN 720: Yin Kwatankwacin Tushen ASMI a Tsarin ku
Rajista taswira
Tebur 4. Taswirar Rajista
- Kowane adireshi da aka soke a cikin tebur mai zuwa yana wakiltar kalma 1 na sararin adreshin ƙwaƙwalwar ajiya.
- Duk rijistar suna da tsohuwar ƙimar 0x0.
| Kashewa | Sunan Rajista | R/W | Sunan Filin | Bit | Nisa | Bayani |
| 0 | WR_ENABLE | W | WR_ENABLE | 0 | 1 | Rubuta 1 don kunna ikon rubutawa. |
| 1 | WR_KASHE | W | WR_KASHE | 0 | 1 | Rubuta 1 don yin kashe rubutu. |
| 2 | WR_MATSAYI | W | WR_MATSAYI | 7:0 | 8 | Ya ƙunshi bayanin don rubutawa zuwa rijistar matsayi. |
| 3 | RD_MATSAYI | R | RD_MATSAYI | 7:0 | 8 | Ya ƙunshi bayanin daga aikin rajistar halin karantawa. |
| 4 | SECTOR_ERASE | W | Darajar Sashin | 23:0
ko 31: 0 |
24 ko
32 |
Ya ƙunshi adireshin ɓangaren da za a goge dangane da yawan na'urar.(5) |
| 5 | SUBSECTOR_ERASE | W | Ƙimar Ƙarfafa | 23:0
ko 31: 0 |
24 ko
32 |
Ya ƙunshi adreshin ɓangaren da za a goge dangane da yawan na'urar.(6) |
| 6-7 | Ajiye | |||||
| 8 | MULKI | W/R | ZABIN CHIP | 7:4 | 4 | Yana zaɓar na'urar filasha. Ƙimar da ta dace ita ce 0, wanda ke kaiwa na'urar filasha ta farko. Don zaɓar na'ura ta biyu, saita ƙimar zuwa 1, don zaɓar na'ura ta uku, saita ƙimar zuwa 2. |
| Ajiye | ||||||
| W/R | KASHE | 0 | 1 | Saita wannan zuwa 1 don kashe siginar SPI na IP ta hanyar sanya duk siginar fitarwa zuwa babban-Z jihar. | ||
| ci gaba… | ||||||
| Kashewa | Sunan Rajista | R/W | Sunan Filin | Bit | Nisa | Bayani |
| Ana iya amfani da wannan don raba bas tare da wasu na'urori. | ||||||
| 9-12 | Ajiye | |||||
| 13 | WR_NON_VOLATILE_CONF_REG | W | Babban darajar NVCR | 15:0 | 16 | Yana rubuta ƙima zuwa rijistar daidaitawa mara ƙarfi. |
| 14 | RD_NON_VOLATILE_CONF_REG | R | Babban darajar NVCR | 15:0 | 16 | Yana karanta ƙima daga rijistar daidaitawa mara ƙarfi |
| 15 | RD_ FLAG_ MATSAYI_REG | R | RD_ FLAG_ MATSAYI_REG | 8 | 8 | Yana karanta rajistar matsayin tuta |
| 16 | CLR_FLAG_ MATSAYI REG | W | CLR_FLAG_ MATSAYI REG | 8 | 8 | Yana share rijistar matsayin tuta |
| 17 | BULK_ERASE | W | BULK_ERASE | 0 | 1 | Rubuta 1 don goge gaba ɗaya guntu (don na'urar mutu ɗaya).(7) |
| 18 | DIE_ERASE | W | DIE_ERASE | 0 | 1 | Rubuta 1 don goge gaba ɗaya mutu (don na'urar stack-die).(7) |
| 19 | 4BYTES_ADDR_EN | W | 4BYTES_ADDR_EN | 0 | 1 | Rubuta 1 don shigar da yanayin adireshin bytes 4 |
| 20 | 4BYTES_ADDR_EX | W | 4BYTES_ADDR_EX | 0 | 1 | Rubuta 1 don fita 4 bytes yanayin adireshin |
| 21 | SECTOR_PROTECT | W | Ƙimar kariyar sashi | 7:0 | 8 | Darajar rubutawa zuwa rijistar matsayi don kare wani yanki. (8) |
| 22 | RD_MEMORY_CAPACITY_ID | R | Ƙimar ƙarfin ƙwaƙwalwa | 7:0 | 8 | Ya ƙunshi bayanin ID ɗin ƙarfin ƙwaƙwalwar ajiya. |
| 23 –
32 |
Ajiye | |||||
Kuna buƙatar saka kowane adireshi a cikin ɓangaren kawai kuma IP ɗin zai share wannan sashin.
Kuna buƙatar saka kowane adireshi a cikin ƙananan yanki kuma IP ɗin zai share wannan yanki na musamman.
Bayanai masu alaƙa
- Ƙirar bayanai na Na'urori masu Quad-Serial (EPCQ).
- EPCQ-L Serial Kanfigareshan Bayanan Bayanan na'urorin
- EPCQ-A Serial Kanfigareshan Bayanan Bayanan Na'urar
- Avalon Interface Takaddun Shaida
Ayyuka
Matsalolin ASMI Parallel II na Intel FPGA IP sun dace da Avalon memory-mapped interface interface. Don ƙarin cikakkun bayanai, koma zuwa ƙayyadaddun Avalon.
- Kuna buƙatar saka kowane adireshi kawai a cikin mutu kuma IP ɗin zai goge wannan takamaiman mutun.
- Don na'urorin EPCQ da EPCQ-L, toshe kariyar bit suna bit [2:4] da [6] kuma saman / kasa (TB) bit shine bit 5 na rijistar matsayi. Don na'urorin EPCQ-A. block kariya bit ne bit [2:4] kuma TB bit ne bit 5 na status rajista.
Bayanai masu alaƙa
- Avalon Interface Takaddun Shaida
Ayyukan Rijistar Matsayin Sarrafa
Kuna iya karantawa ko rubuta zuwa takamaiman adireshi ta hanyar yin amfani da Rijista Matsayin Sarrafa (CSR).
Don aiwatar da aikin karantawa ko rubuta don rijistar matsayi, bi waɗannan matakan:
- Sanya siginar avl_csr_write ko avl_csr_read yayin da
siginar avl_csr_waitrequest yayi ƙasa (idan siginar jiran aiki yayi girma, dole ne a kiyaye siginar avl_csr_write ko avl_csr_read a sama har sai siginar jiran aiki ya ragu). - A lokaci guda, saita ƙimar adireshin akan bas ɗin avl_csr_address. Idan aiki ne na rubutu, saita ƙimar bayanan akan bas ɗin avl_csr_writedata tare da adireshin.
- Idan ciniki ne na karantawa, jira har sai an tabbatar da siginar avl_csr_readdatavalid mai girma don dawo da bayanan karantawa.
- Don ayyukan da ke buƙatar ƙimar rubutu zuwa walƙiya, dole ne ka fara aiwatar da aikin rubuta ikon rubutawa.
- Dole ne ku karanta rajistar matsayin tuta duk lokacin da kuka bayar da rubutu ko goge umarni.
- Idan ana amfani da na'urorin filasha da yawa, dole ne ka rubuta zuwa guntu zaɓi rajista don zaɓar guntu daidai zaɓi kafin yin kowane aiki zuwa takamaiman na'urar filasha.
Hoto 2. Karanta Rijistar Ƙarfin Ƙwaƙwalwar Ƙwaƙwalwar Waveform Example
Hoto 3. Rubuta Kunna Rajista Waveform Example
Ayyukan ƙwaƙwalwar ajiya
Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na IP na ASMI II na FPGA yana goyan bayan fashewa da samun damar ƙwaƙwalwar walƙiya kai tsaye. Lokacin samun damar ƙwaƙwalwar ajiyar filasha kai tsaye, IP ɗin yana aiwatar da matakai masu zuwa don ba ku damar yin kowane aiki na karantawa ko rubuta kai tsaye:
- Rubuta kunna don aikin rubutawa
- Bincika rajistan halin tuta don tabbatar da an kammala aikin a filasha
- Saki siginar jiran aiki lokacin da aka gama aiki
Ayyukan ƙwaƙwalwar ajiya sun yi kama da ayyukan mu'amala da taswirar ƙwaƙwalwar ajiyar Avalon. Dole ne ku saita ƙimar daidai a bas ɗin adireshi, rubuta bayanai idan ma'amala ce ta rubutawa, fitar da ƙimar fashewa zuwa 1 don ma'amala ɗaya ko ƙimar fashewar da kuke so, sannan kunna siginar rubutu ko karantawa.
Hoto 4. 8-Kalmar Rubuta Fashe Waveform Example
Hoto 5. 8-Karanta Kalma Fashe Waveform Example
Hoto 6. 1-Byte Rubuta byteenable = 4'b0001 Waveform Example
ASMI Parallel II Intel FPGA IP Amfani Case Examples
Kas din amfani exampYi amfani da ASMI Parallel II IP da JTAG-to-Avalon Master don aiwatar da ayyukan samun damar walƙiya, kamar karanta ID na silicon, karanta ƙwaƙwalwar ajiya, rubuta ƙwaƙwalwar ajiya, goge yanki, kariyar yanki, share rajistar matsayin tuta, da rubuta nvcr.
Don gudanar da tsohonampDon haka, dole ne ku saita FPGA. Bi waɗannan matakan:
- Sanya FPGA bisa tsarin Platform Designer kamar yadda aka nuna a adadi mai zuwa.
Hoto 7. Tsarin Tsarin Platform Yana Nuna ASMI Daidaici II IP da JTAG-da-Avalon Master
- Ajiye rubutun TCL mai zuwa a cikin jagora guda ɗaya da aikin ku. Sunan rubutun azaman epcq128_access.tcl don example.
- Kaddamar da tsarin wasan bidiyo. A cikin na'ura wasan bidiyo, samo rubutun ta amfani da "source epcq128_access.tcl".
Example 1: Karanta Silicon ID na Kanfigareshan Na'urorin
Example 2: Karanta kuma Rubuta Kalma ɗaya na Bayanai a Adireshin H'40000000
Example 3: Goge Sashi na 64
Example 4: Yi Sashin Kariya a Sassan (0 zuwa 127)
Example 5: Karanta kuma Share Matsayin Tuta
Example 6: Karanta kuma Rubuta nvcr
ASMI Parallel II Intel FPGA IP Rukunin Jagorar Mai Amfani
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP.
Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.
| Intel Quartus Prime Version | IP Core Version | Jagorar Mai Amfani |
| 17.0 | 17.0 | Altera ASMI Parallel II IP Core User Guide |
Tarihin Bita na Takardu don ASMI Daidaici II Jagorar Mai Amfani da IP FPGA
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2020.07.29 | 18.0 | 18.0 | • An sabunta taken daftarin aiki zuwa ASMI Parallel II Intel FPGA IP Jagorar Mai Amfani.
• An sabunta Tebur 2: Saitunan Siga a sashe Siga. |
| 2018.09.24 | 18.0 | 18.0 | • Ƙara bayanai akan aikace-aikace da goyan bayan ASMI Parallel II Intel FPGA IP core.
• Ƙara bayanin kula don komawa zuwa Generic Serial Flash Interface Intel FPGA IP Core User Guide. • Ƙara da ASMI Parallel II Intel FPGA IP Core Amfani Case Examples sashe. |
| 2018.05.07 | 18.0 | 18.0 | • Sake suna Altera ASMI Parallel II IP core zuwa ASMI Parallel II Intel FPGA IP core ta hanyar sake suna Intel.
• Ƙara tallafi don na'urorin EPCQ-A. • Ƙara bayanin kula zuwa siginar clk a cikin Bayanin tashar jiragen ruwa tebur. • An sabunta bayanin siginar qspi_scein a cikin Bayanin tashar jiragen ruwa tebur. • Ƙara rubutu zuwa rajistar SECTOR_PROTECT a cikin Rajista taswira tebur. • An sabunta bit da faɗi don rajistar SECTOR_ERASE da SUBSECTOR_ERASE a cikin Rajista taswira tebur. • An sabunta bit da faɗi don SECTOR_PROTECT rajista a cikin Rajista taswira tebur. |
| ci gaba… | |||
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| • An sabunta bayanin zaɓi na CHIP SELECT na rijistar CONTROL a cikin Rajista taswira tebur.
• An sabunta bayanan ƙafa na SECTOR_ERASE, SUBSECTOR_ERASE, BULK_ERASE, da DIE_ERASE rajista a cikin Rajista taswira tebur. • An sabunta bayanin vl_mem_addr sigina a cikin Bayanin tashar jiragen ruwa tebur. • Ƙananan gyare-gyaren edita. |
| Kwanan wata | Sigar | Canje-canje |
| Mayu 2017 | 2017.05.08 | Sakin farko. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
Takardu / Albarkatu
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intel ASMI Parallel II Intel FPGA IP [pdf] Jagorar mai amfani ASMI Parallel II Intel FPGA IP, ASMI, Parallel II Intel FPGA IP, II Intel FPGA IP, FPGA IP |
