I-VHDL VITAL™
Umhlahlandlela Wokulingisa
Isingeniso
Le VHDL Vital Simulation Guide iqukethe ulwazi mayelana nokusebenzisa i-ModelSim ukulingisa imiklamo yamadivayisi we-Microsemi SoC. Bheka kusizo lwe-inthanethi ukuze uthole ulwazi olwengeziwe mayelana nokusebenzisa isofthiwe ye-SoC.
Bheka imibhalo efakwe nesifanisi sakho ukuze uthole ulwazi mayelana nokwenza ukulingisa.
Imibhalo ecatshangelwayo
Lo mbhalo uthatha lokhu okulandelayo:
- Ufake isofthiwe ye-Libero SoC. Lo mbhalo owesoftware ye-Libero SoC v10.0 nangaphezulu. Ukuze uthole izinguqulo zangaphambilini zesofthiwe, bheka i Legacy VHDL Vital Simulation Guide.
- Ufake isifanisi sakho se-VHDL VITAL.
- Uyazazi iziteshi zokusebenzela ze-UNIX nezinhlelo zokusebenza noma nama-PC kanye nezindawo zokusebenza ze-Windows.
- Ujwayelene ne-FPGA architecture kanye ne-FPGA design software.
Imibhalo Yesigodi
Lo mbhalo usebenzisa okuguquguqukayo okulandelayo:
- Imitapo yolwazi yomndeni ye-FPGA ikhonjiswa njenge . Faka esikhundleni sokuhluka komndeni we-FPGA oyifunayo nomndeni wedivayisi njengoba kudingeka. Okwesiboneloample: vcom -sebenza .vhd
- Imitapo yolwazi ye-VHDL ehlanganisiwe ikhonjiswa njenge . Faka esikhundleni kokuguquguquka komndeni we-VHDL oyifunayo njengoba kudingeka. Ulimi lwe-VHDL ludinga ukuthi amagama omtapo wolwazi aqale ngohlamvu lwe-alpha.
Usizo Lwe-inthanethi
Isoftware ye-Microsemi SoC iza nosizo lwe-inthanethi. Usizo lwe-inthanethi oluqondene nethuluzi ngalinye lesofthiwe luyatholakala kumenyu yosizo.
Setha
Lesi sahluko siqukethe imininingwane yokusetha isifanisi se-ModelSim ukuze silingise imiklamo ye-Microsemi SoC.
Lesi sahluko sihlanganisa izidingo zesofthiwe, izinyathelo ezichaza indlela yokuhlanganisa imitapo yolwazi ye-Microsemi SoC FPGA, nolunye ulwazi lokusetha lwethuluzi lokulingisa olisebenzisayo.
Izidingo Zesoftware
Ulwazi olukulo mhlahlandlela lusebenza ku-Microsemi Libero SoC Software v10.0 nangaphezulu kanye nezifanisi ze-VHDL ezithobela i-IEEE1076.
Ukwengeza, lo mhlahlandlela uqukethe ulwazi mayelana nokusebenzisa i-ModelSim simulators.
Ukuze uthole ulwazi oluthile mayelana nokuthi yiziphi izinguqulo ezisekelwa yilokhu kukhululwa, hamba kusistimu yosekelo lwezobuchwepheshe ku-Microsemi web isiza (http://www.actel.com/custsup/search.html) bese usesha igama elingukhiye lomuntu wesithathu.
ImodeliSim
Njengoba indlela yokufaka ihluka kumsebenzisi ngamunye kanye nokufakwa ngakunye, le dokhumenti isebenzisa i-$ALSDIR ukuze ibonise indawo lapho isofthiwe ifakwe khona. Uma ungumsebenzisi we-Unix, mane udale okuguquguqukayo kwendawo okubizwa ngokuthi i-ALSDIR bese usetha inani lakho endleleni yokufaka. Uma ungumsebenzisi we-Windows, buyisela i-$ALSDIR ngendlela yokufaka emiyalweni.
Sebenzisa le nqubo elandelayo ukuze uhlanganise imitapo yolwazi yezilingisi ze-ModelSim. Thayipha imiyalo ye-UNIX ekwazisweni kwe-UNIX. Thayipha imiyalo yeWindows kulayini womyalo wewindi le-ModelSim Transcript.
Imiyalo engezansi eyeWindows. Ukuze wenze imiyalo isebenzele i-UNIX, sebenzisa izisileshi eziya phambili esikhundleni se-backslash.
Le nqubo ihlanganisa umtapo wezincwadi we-Microsemi VITAL ohlwini lwemibhalo lwe-$ALSDIR\lib\vtl\95\mti. Kufanele uhlanganise amamodeli welabhulali ye-FPGA ukuze imitapo yolwazi ye-VITAL isebenze kahle.
Qaphela: Uma sekuvele kukhona uhla lwemibhalo lwe-MTI ohlwini lwemibhalo lwe-$ALSDIR\lib\vtl\95, imitapo yolwazi ehlanganisiwe ingase ibe khona, futhi ungase ungadingi ukwenza inqubo elandelayo.
- Dala umtapo wolwazi obizwa nge- mti kuhla lwemibhalo lwe-$ALSDIR\lib\vtl\95.
- Cela isifanisi se-ModelSim (IWindows kuphela).
- Shintshela kuhla lwemibhalo lwe-$ALSDIR\lib\vtl\95\mti. Faka umyalo olandelayo ngokushesha: cd $ALSDIR\lib\vtl\95\mti
- Dala a umtapo wolwazi womndeni. Faka umyalo olandelayo ngesikhathi sokwaziswa: vlib
- Mepha umtapo wezincwadi we-VITAL ku- umkhombandlela. Faka umyalo olandelayo ngesikhathi sokwaziswa: vmap $ALSDIR\lib\vtl\95\mti\
- Hlanganisa amalabhulali akho e-VITAL.
vcom -sebenza ../ .vhd
Okwesiboneloample, ukuze uhlanganise umtapo wezincwadi we-40MX wesilingisi sakho, thayipha umyalo olandelayo: vcom -work a40mx ../40mx.vhd - (Ongakukhetha) Hlanganisa umtapo wolwazi wokuthutha. Yenza lesi sinyathelo kuphela uma udinga ukusebenzisa ilabhulali yokuthutha. Thayipha umyalo olandelayo ngesikhathi sokwaziswa: vcom -work ../ _mig.vhd
Ukugeleza Kwedizayini
Lesi sahluko sichaza ukugeleza kwedizayini yokulingisa imiklamo ngethuluzi lokulingisa elithobela i-VHDL VITAL.
I-VHDL EBALULEKILE Ukugeleza Kwedizayini
Ukugeleza komklamo we-VHDL VITAL kunezinyathelo ezine eziyinhloko:
- Dala Idizayini
- Sebenzisa Idizayini
- Ukuhlela
- Ukuqinisekiswa Kwesistimu
Izigaba ezilandelayo zinemininingwane yalezi zinyathelo.
Dala Idizayini
Ngesikhathi sokudalwa/ukuqinisekiswa kwedizayini, idizayini ithwetshulwa kumthombo we-VHDL wezinga le-RTL (ukuziphatha) file.
Ngemva kokuthwebula umklamo, ungenza ukulingisa kokuziphatha kwe-VHDL file ukuze uqinisekise ukuthi ikhodi ye-VHDL ilungile. Ikhodi ibe isihlanganiswa ibe uhlu lwenethi lwezinga lesango (isakhiwo) se-VHDL. Ngemuva kokuhlanganiswa, ungenza isifaniso sesakhiwo sangaphambi kokuhlelwa komklamo. Okokugcina, uhlu lwenethi lwe-EDIF luyakhiqizwa ukuze lusetshenziswe ku-Libero SoC futhi uhlu lwe-VHDL lwesakhiwo lwangemuva luyakhiqizwa ukuze kufaniswe isikhathi kusifanisi esithobelana ne-VHDL VITAL.
Ukungena komthombo we-VHDL
Faka umthombo wakho wokuklama i-VHDL usebenzisa isihleli sombhalo noma umhleli we-HDL ozwela komongo. Umthombo wakho wedizayini ye-VHDL ungaqukatha ukwakhiwa kweleveli ye-RTL, kanye nokuqiniswa kwezakhi zesakhiwo, njenge-Libero SoC cores.
Ukulingisa Ukuziphatha
Yenza ukulingisa kokuziphatha komklamo wakho ngaphambi kokuhlanganisa. Ukulingisa ukuziphatha kuqinisekisa ukusebenza kwekhodi yakho ye-VHDL. Ngokuvamile, usebenzisa ukubambezeleka okunguziro kanye nebhentshi elijwayelekile lokuhlola i-VHDL ukushayela ukulingisa. Bheka imibhalo efakwe nethuluzi lakho lokulingisa ukuze uthole ulwazi mayelana nokwenza ukulingisa okusebenzayo.
I-synthesis
Ngemuva kokuthi udale umthombo wakho wokuziphatha we-VHDL, kufanele uwuhlanganise. I-synthesis iguqula i-VHDL yokuziphatha file ibe ohlwini lwenethi ezingeni lesango futhi ithuthukise idizayini yobuchwepheshe obuqondiwe. Amadokhumenti afakwe nethuluzi lakho le-synthesis aqukethe ulwazi mayelana nokwenza ukwakheka komklamo.
EDIF Netlist Generation
Ngemva kokuthi udale, wahlanganisa, futhi waqinisekisa umklamo wakho, isofthiwe ikhiqiza uhlu lwenethiwekhi lwe-EDIF lwendawo nomzila e-Libero SoC.
Lolu hlu lwenethi lwe-EDIF luphinde lusetshenziswe ukukhiqiza uhlu lwenethi lwesakhiwo lwe-VHDL ukuze lusetshenziswe ekulingiseni kwesakhiwo.
I-Structural VHDL Netlist Generation
I-Libero SoC ikhiqiza uhlu lwenethi lwezinga lesango le-VHDL ohlwini lwakho lwe-EDIF ukuze lusetshenziswe ekulingiseni kwesakhiwo sangaphambi kokuhlelwa kwangaphambili.
I file iyatholakala kuhla lwemibhalo/yokwenziwa uma ufisa ukwenza ukulingisa ngesandla.
Ukulingisa Kwesakhiwo
Enza ukulingisa kwesakhiwo ngaphambi kokubeka nokukhipha umzila. Ukulingisa kwesakhiwo kuqinisekisa ukusebenza kohlu lwakho lwenetha lwesakhiwo se-VHDL yesakhiwo sangaphambilini. Ukubambezeleka kweyunithi okufakwe kulabhulali ehlanganisiwe ye-Libero SoC VITAL kuyasetshenziswa. Bheka imibhalo efakwe nethuluzi lakho lokulingisa ukuze uthole ulwazi mayelana nokwenza ukulingisa kwesakhiwo.
Sebenzisa Idizayini
Ngesikhathi sokuqaliswa kokuklama, ubeka futhi uhambise umklamo usebenzisa i-Libero SoC. Ukwengeza, ungenza ukuhlaziya isikhathi. Ngemva kwendawo nomzila, yenza ukulingisa kwesakhiwo sokuthunyelwe (isikhathi) ngesifanisi esithobelana ne-VHDL VITAL.
Ukuhlela
Hlela idivayisi enesofthiwe yokuhlela nehadiwe kusuka ku-Microsemi SoC noma isistimu yokuhlela yenkampani yangaphandle esekelwe. Bheka kusizo lwe-inthanethi lomhleli ukuze uthole ulwazi mayelana nokuhlela idivayisi ye-Microsemi SoC.
Ukuqinisekiswa Kwesistimu
Ungenza ukuqinisekiswa kwesistimu kudivayisi ehleliwe usebenzisa ithuluzi lokuxilonga le-Silicon Explorer.
Bheka iSilicon Explorer Quick Start ukuze uthole ulwazi mayelana nokusebenzisa iSilicon Explorer.
Ukukhiqiza Uhlu
Lesi sahluko sichaza izinqubo zokukhiqiza i-EDIF kanye nohlu lwe-VHDL lwesakhiwo.
Ukukhiqiza i-EDIF Netlist
Ngemva kokuthwebula isikimu sakho noma ukuhlanganisa idizayini yakho, yenza uhlu lwenethiwekhi lwe-EDIF kusuka ekuthwebuleni kwakho okuhleliwe noma ithuluzi lokuhlanganisa. Sebenzisa uhlu lwenethi lwe-EDIF ukuze uthole indawo nomzila. Bheka imibhalo efakwe nokuthwebula kwakho okuhleliwe noma ithuluzi lokuhlanganisa ukuze uthole ulwazi mayelana nokukhiqiza uhlu lwenethi lwe-EDIF.
Ukukhiqiza i-Structural VHDL Netlist
Uhlu lwenethiwekhi lwe-Structural VHDL files akhiqizwa ngokuzenzakalela njengengxenye yephrojekthi yakho ye-Libero SoC.
Ungathola uhlu lwakho lwenethiwekhi lwe-VHDL files kumkhombandlela we-/synthesis wephrojekthi yakho ye-Libero. Okwesiboneloample, uma uhla lwemibhalo lwephrojekthi yakho luqanjwe ngokuthi i-project1, bese kuba yi-netlist yakho files iku/project1/synthesis.
Eminye imindeni ikuvumela ukuthi uthumele lezi files ngesandla ukuze zisetshenziswe kumathuluzi angaphandle. Uma idivayisi yakho isekela lesi sici ungakhipha i-netlist files kusuka ku-Amathuluzi > Khipha > I-Netlist.
Ukulingisa nge-ModelSim
Lesi sahluko sichaza izinyathelo zokwenza ukulingiswa kokuziphatha, kwesakhiwo kanye nesikhathi usebenzisa isifanisi se-ModelSim.
Izinqubo ezibonisiwe eze-PC. Izinqubo zokusetha ezifanayo zisebenza ngokufanayo ku-UNIX. Sebenzisa ama-slashs aya phambili esikhundleni se-backslashs. Kwi-PC, thayipha imiyalo efasiteleni le-MTI. Nge-UNIX, thayipha imiyalo efasiteleni le-UNIX.
Ukulingisa Ukuziphatha
Sebenzisa inqubo elandelayo ukwenza ukulingisa kokuziphatha komklamo. Bheka imibhalo
kufakwe nethuluzi lakho lokulingisa ukuze uthole ulwazi olwengeziwe mayelana nokwenza ukulingisa kokuziphatha.
- Cela isifanisi sakho se-ModelSim. (I-PC kuphela)
- Shintsha uhla lwemibhalo kuhla lwemibhalo yephrojekthi yakho. Lolu hlu lwemibhalo kufanele lufake nomklamo wakho we-VHDL files kanye ne-testbench. Uhlobo: cd
- Imephu eya kulabhulali. Uma noma yimaphi ama-cores aqinisiwe emthonjeni wakho we-VHDL, thayipha umyalo olandelayo ukuze uwafake kumephu emtapweni wezincwadi we-VITAL ohlanganisiwe: vmap $ALSDIR\lib\vtl\95\mti\
Ukuze ubhekisele kulabhulali yomndeni edizayini yakho ye-VHDL files, engeza imigqa elandelayo ekwakhiweni kwakho kwe-VHDL files: umtapo wolwazi ; sebenzisa .izingxenye.zonke; - Dala inkomba "yomsebenzi". Uhlobo: vlib umsebenzi
- Imephu eya kuhla lwemibhalo “lomsebenzi”. Thayipha umyalo olandelayo: vmap work .\work
- Yenza ukulingisa kokuziphatha komklamo wakho. Ukuze wenze ukulingisa kokuziphatha usebenzisa i-VSystem yakho noma i-ModelSim simulator, hlanganisa idizayini yakho ye-VHDL nebhentshi lokuhlola. files bese uqhuba ukulingisa. Ukuze uthole imiklamo ye-hierarchical, hlanganisa amabhulokhi edizayini ezinga eliphansi ngaphambi kokuthi amabhulokhi womklamo wezinga eliphezulu avimbe.
Imiyalo elandelayo ibonisa ukuthi ungahlanganisa kanjani ukwakheka kwe-VHDL nebhentshi lokuhlola files:
vcom -93 .vhd
vcom -93 .vhd
Ukuze ulingise umklamo, thayipha:
vsim
Okwesiboneloample:
vsim test_adder_behave
Ipheya yebhizinisi nezakhiwo ezicaciswe ukulungiselelwa okuqanjwe ngokuthi test_adder_behave kubhentshi le-test kuzolingiswa. Uma idizayini yakho iqukethe i-PLL core, sebenzisa ukulungiswa okungu-1ps:
vsim -t ps
Okwesiboneloample:
vsim -t ps test_adder_behave
Ukulingisa Kwesakhiwo
Sebenzisa inqubo elandelayo ukwenza ukulingisa kwesakhiwo.
- Khiqiza uhlu lwenetha lwesakhiwo se-VHDL. Uma usebenzisa i-Synopsys Design Compiler, yenza uhlu lwenetha lwesakhiwo se-VHDL usebenzisa leli thuluzi.
Uma usebenzisa amanye amathuluzi okuhlanganiswa, yenza i-VHDL yezinga lesango ohlwini lwakho lwenethikhi ye-EDIF ngokusebenzisa file kukhiqizwe ngokuzenzakalelayo kuphrojekthi yakho. Eminye imindeni yokuklama ikuvumela ukuthi ukhiqize files ngqo kusuka kokuthi Amathuluzi > Khipha > Imenyu ye-Netlist.
Qaphela: I-VHDL ekhiqiziwe isebenzisa okuthi std_logic kuzo zonke izimbobo. Izikhumulo zamabhasi zizoba ngokulandelana okufanayo njengoba zivela kuhlu lwe-EDIF. - Imephu eya kulabhulali ye-VITAL. Qalisa umyalo olandelayo ukuze wenze imephu yelabhulali ye-VITAL ehlanganisiwe.
vmap $ALSDIR\lib\vtl\95\mti\ - Hlanganisa i-netlist yesakhiwo. Hlanganisa idizayini yakho ye-VHDL nebhentshi lokuhlola files. Imiyalo elandelayo ibonisa ukuthi ungahlanganisa kanjani ukwakheka kwe-VHDL nebhentshi lokuhlola files:
vcom -nje e -93 .vhd
vcom -nje a -93 .vhd
vcom .vhd
Qaphela: Okokuqala, uhlelo lokusebenza luhlanganisa izinhlangano. Bese, ihlanganisa izakhiwo, njengoba kudingeka ohlwini lwe-VHDL olubhalwe ngamathuluzi athile. - Qalisa ukulingisa kwesakhiwo. Ukuze ulingise umklamo wakho, thayipha: vsim
Okwesiboneloample: vsim test_adder_structure
Ipheya yebhizinisi nezakhiwo ezicaciswe ukulungiselelwa okuqanjwe ngokuthi test_adder_structure kubhentshi lokuhlola izolingiswa.
Uma idizayini yakho iqukethe i-PLL core, sebenzisa isixazululo esingu-1ps: vsim -t ps
Okwesiboneloample: vsim -t ps test_adder_structure
Ukulingisa Isikhathi
Ukwenza ukulingisa isikhathi:
- Uma ungenzanga kanjalo, phinda uchaze umklamo wakho bese udala ibhentshi lakho lokuhlola.
- Ukuze wenze ukulingisa isikhathi usebenzisa i-V-System yakho noma i-ModelSim simulator, hlanganisa idizayini yakho ye-VHDL nebhentshi lokuhlola. files, uma zingakahlanganiswa ukuze zifaniswe nesakhiwo, futhi zisebenzise ukulingisa. Imiyalo elandelayo ibonisa ukuthi ungahlanganisa kanjani ukwakheka kwe-VHDL nebhentshi lokuhlola files:
vcom -nje e -93 .vhd
vcom -nje a -93 .vhd
vcom .vhd
Qaphela: Ukwenza izinyathelo zangaphambilini kuhlanganisa amabhizinisi kuqala bese kuba yizakhiwo, njengoba kudingeka ohlwini lwe-VHDL olubhalwe amanye amathuluzi. - Qalisa ukulingisa kwesichasiselo sasemuva usebenzisa ulwazi lwesikhathi ku-SDF file. Uhlobo: vsim -sdf[max|typ|min] / = .sdf -c
I inketho icacisa isifunda (noma indlela) yesibonelo esakhiweni lapho isichasiselo esisemuva siqala khona. Ungayisebenzisa ukuze ucacise isenzakalo esithile se-FPGA kumklamo wesistimu omkhulu noma ibhentshi lokuhlola ofisa ukulichasisa. Okwesiboneloample: vsim – sdfmax /uut=adder.sdf -c test_adder_structural
Kulesi example, i-adder yebhizinisi iqiniswe njengesibonelo "uut" ebhentshini le-test. Ipheya yebhizinisi nezakhiwo ezicaciswe ukucushwa okuqanjwe ngokuthi “test_adder_structural” kubhentshi yokuhlola izolingiswa kusetshenziswa ukubambezeleka okukhulu okucaciswe ku-SDF. file.
Uma idizayini yakho iqukethe i-PLL core, sebenzisa ukulungiswa okungu-1ps: vsim -t ps -sdf[max|typ|min] / = .sdf -c
Okwesiboneloample: vsim -t ps -sdfmax /uut=adder.sdf -c test_adder_structural
A – Ukwesekwa Komkhiqizo
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I-Microsemi Corporation (NASDAQ: MSCC) inikeza iphothifoliyo ephelele yezixazululo ze-semiconductor: i-aerospace, ukuzivikela nokuphepha; ibhizinisi kanye nokuxhumana; kanye nezimakethe zamandla ezimboni nezinye. Imikhiqizo ihlanganisa ukusebenza okuphezulu, i-analog enokwethenjelwa kakhulu kanye namadivayisi e-RF, isignali exubile namasekhethi ahlanganisiwe e-RF, ama-SoCs enziwe ngokwezifiso, ama-FPGA, namasistimu angaphansi aphelele. I-Microsemi ikomkhulu layo e-Aliso Viejo, Calif. Funda kabanzi ku- www.microsemi.com.
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