VHDL VITAL™
Simulation Guide

Taw qhia

Daim ntawv qhia VHDL Vital Simulation no muaj cov ntaub ntawv hais txog kev siv ModelSim los sim cov qauv tsim rau Microsemi SoC li. Xa mus rau kev pab online rau cov ntaub ntawv ntxiv txog kev siv SoC software.
Xa mus rau cov ntaub ntawv suav nrog koj lub simulator rau cov ntaub ntawv hais txog kev simulation.

Cov ntaub ntawv Assumption
Cov ntaub ntawv no suav nrog cov hauv qab no:

1. Koj tau nruab Libero SoC software. Cov ntaub ntawv no yog rau Libero SoC software v10.0 thiab siab dua. Rau yav dhau los versions ntawm software, saib cov Txoj Cai VHDL Tseem Ceeb Simulation Phau Ntawv Qhia.
2. Koj tau nruab koj VHDL VITAL simulator.
3. Koj paub txog UNIX chaw ua haujlwm thiab kev khiav haujlwm lossis nrog PCs thiab Windows ua haujlwm ib puag ncig.
4. Koj paub txog FPGA architecture thiab FPGA tsim software.

Cov ntaub ntawv Conventions
Cov ntaub ntawv no siv cov kev hloov pauv hauv qab no:

• FPGA tsev qiv ntawv tau pom zoo li . Hloov qhov xav tau FPGA tsev neeg hloov pauv nrog cov cuab yeej cuab tam raws li xav tau. Rau example: vcom-ua .vhd
• Muab tso ua ke VHDL cov tsev qiv ntawv tau pom zoo li . Hloov rau qhov xav tau VHDL tsev neeg hloov pauv raws li xav tau. Cov lus VHDL xav kom cov tsev qiv ntawv npe pib nrog tus cim alpha.

Kev pab online
Microsemi SoC software los nrog kev pab online. Kev pab online tshwj xeeb rau txhua lub cuab yeej software muaj los ntawm Pab Pawg.

Teeb tsa

Tshooj no muaj cov ntaub ntawv hais txog kev teeb tsa ModelSim simulator los simulate Microsemi SoC tsim.
Tshooj no suav nrog cov kev cai software, cov kauj ruam piav qhia yuav ua li cas sau Microsemi SoC FPGA cov tsev qiv ntawv, thiab lwm yam ntaub ntawv teeb tsa rau lub simulation cuab yeej koj siv.

Software Yuav Tsum Tau
Cov ntaub ntawv hauv phau ntawv qhia no siv rau Microsemi Libero SoC Software v10.0 thiab siab dua thiab IEEE1076-raws li VHDL simulators.
Tsis tas li ntawd, phau ntawv qhia no muaj cov ntaub ntawv hais txog kev siv ModelSim simulators.
Rau cov ntaub ntawv tshwj xeeb hais txog qhov twg qhov kev tso tawm no txhawb nqa, mus rau cov txheej txheem kev txhawb nqa ntawm Microsemi web xaib (http://www.actel.com/custsup/search.html) thiab tshawb nrhiav lo lus tseem ceeb thib peb.

ModelSim
Txij li thaum txoj kev teeb tsa sib txawv rau txhua tus neeg siv thiab txhua qhov kev teeb tsa, daim ntawv no siv $ALSDIR los qhia qhov chaw nyob qhov twg cov software raug teeb tsa. Yog tias koj yog ib tus neeg siv Unix, tsuas yog tsim ib qho kev hloov pauv ib puag ncig hu ua ALSDIR thiab teeb nws tus nqi rau txoj kev teeb tsa. Yog tias koj yog tus neeg siv Windows, hloov $ALSDIR nrog txoj kev teeb tsa hauv cov lus txib.
Siv cov txheej txheem hauv qab no los suav cov tsev qiv ntawv rau ModelSim simulators. Ntaus UNIX commands ntawm UNIX prompt. Ntaus Windows commands ntawm kab hais kom ua ntawm ModelSim Transcript window.
Cov lus txib hauv qab no yog rau Windows. Txhawm rau ua kom cov lus txib ua haujlwm rau UNIX, siv rau pem hauv ntej slashes es tsis txhob rov qab slashes.

Cov txheej txheem no suav nrog lub tsev qiv ntawv Microsemi VITAL hauv $ALSDIR\lib\vtl\95\mti directory. Koj yuav tsum sau cov qauv FPGA cov tsev qiv ntawv rau VITAL cov tsev qiv ntawv kom ua haujlwm tau zoo.
Nco tseg: Yog tias twb muaj MTI directory nyob rau hauv $ALSDIR\lib\vtl\95 directory, compiled libraries tej zaum yuav muaj, thiab tej zaum koj yuav tsis tau ua raws li cov txheej txheem nram qab no.

1. Tsim ib lub tsev qiv ntawv hu ua mti hauv $ALSDIR\lib\vtl\95 directory.
2. Hu rau ModelSim simulator (Windows nkaus xwb).
3. Hloov mus rau $ALSDIR\lib\vtl\95\mti directory. Nkag mus rau cov lus txib hauv qab no ntawm qhov hais kom ua: cd $ALSDIR\lib\vtl\95\mti
4. Tsim ib tsev qiv ntawv. Nkag mus rau cov lus txib hauv qab no ntawm qhov hais kom ua: vlib
5. Daim ntawv qhia VITAL libray rau lub phau ntawv. Nkag mus rau cov lus txib hauv qab no ntawm qhov hais kom ua: vmap $ALSDIR\lib\vtl\95\mti\
6. Sau koj cov tsev qiv ntawv VITAL.
   vcom ua ../ .vhd
   Rau example, txhawm rau sau 40MX tsev qiv ntawv rau koj lub simulator, ntaus cov lus txib hauv qab no: vcom -work a40mx ../40mx.vhd
7. (Yeem) Muab cov tsev qiv ntawv tsiv teb tsaws chaw. Tsuas yog ua cov kauj ruam no yog tias koj xav siv lub tsev qiv ntawv tsiv teb tsaws chaw. Ntaus cov lus txib hauv qab no ntawm qhov hais kom ua: vcom -work ../ _mig.vhd

Tsim Flow

Tshooj lus no piav qhia txog cov qauv tsim rau simulating tsim nrog VHDL VITAL-raws li simulation cuab yeej.

VHDL VITAL Design Flow
VHDL VITAL tsim ntws muaj plaub theem tseem ceeb:

1. Tsim Tsim
2. Siv cov qauv tsim
3. Programming
4. Kev txheeb xyuas qhov system

Cov ntu hauv qab no qhia txog cov kauj ruam no.

Tsim Tsim
Thaum lub sij hawm tsim tsim / pov thawj, tus tsim yog ntes nyob rau hauv RTL-level (tus cwj pwm) VHDL qhov chaw file.
Tom qab ntes tus tsim, koj tuaj yeem ua tus cwj pwm simulation ntawm VHDL file kom paub tseeb tias VHDL code yog lawm. Tom qab ntawd cov code yog synthesized rau hauv lub rooj vag-theem (structural) VHDL netlist. Tom qab kev sib txuas, koj tuaj yeem ua qhov kev xaiv ua ntej layout qauv simulation ntawm tus tsim. Thaum kawg, EDIF netlist yog tsim los siv rau hauv Libero SoC thiab VHDL cov txheej txheem tom qab kev teeb tsa netlist yog tsim los rau lub sijhawm simulation hauv VHDL VITAL-raws li simulator.

VHDL Source Entry
Nkag mus rau koj qhov chaw tsim VHDL siv cov ntawv nyeem lossis cov ntsiab lus-sensitive HDL editor. Koj qhov chaw tsim VHDL tuaj yeem muaj RTL-theem tsim, nrog rau kev ua haujlwm ntawm cov qauv tsim, xws li Libero SoC cores.

Cwj Pwm Simulation
Ua tus cwj pwm simulation ntawm koj tus qauv tsim ua ntej synthesis. Kev coj cwj pwm simulation txheeb xyuas qhov ua haujlwm ntawm koj VHDL code. Feem ntau, koj siv xoom qeeb thiab tus qauv VHDL xeem lub rooj ntev zaum tsav simulation. Xa mus rau cov ntaub ntawv suav nrog koj lub cuab yeej simulation rau cov ntaub ntawv hais txog kev ua haujlwm simulation.

Synthesis
Tom qab koj tau tsim koj tus cwj pwm VHDL tsim qhov chaw, koj yuav tsum sib txuas nws. Synthesis transforms tus cwj pwm VHDL file mus rau hauv lub rooj vag-theem netlist thiab optimizes tus tsim rau lub hom phiaj technology. Cov ntaub ntawv nrog rau koj cov cuab yeej synthesis muaj cov ntaub ntawv hais txog kev tsim qauv tsim.

EDIF Netlist Generation
Tom qab koj tau tsim, sib sau ua ke, thiab txheeb xyuas koj tus qauv tsim, software tsim EDIF netlist rau qhov chaw-thiab-txoj kev hauv Libero SoC.
Qhov EDIF netlist no kuj tseem siv los tsim cov qauv VHDL netlist rau siv hauv cov qauv simulation.

Qauv VHDL Netlist Generation
Libero SoC tsim lub rooj vag-theem VHDL netlist los ntawm koj EDIF netlist siv rau hauv kev sib txuas ua ke ua ntej ua qauv qauv simulation.
Cov file muaj nyob rau hauv /synthesis directory yog tias koj xav ua simulation manually.
Qauv Simulation
Ua ib qho kev simulation ua ntej tso-thiab-routing. Cov qauv simulation txheeb xyuas qhov ua haujlwm ntawm koj qhov kev sib txuas ua ntej ua ntej layout VHDL netlist. Chav tsev ncua sij hawm suav nrog hauv Libero SoC VITAL cov tsev qiv ntawv tau muab tso ua ke. Xa mus rau cov ntaub ntawv suav nrog koj lub cuab yeej simulation rau cov ntaub ntawv hais txog kev ua haujlwm simulation.

Siv cov qauv tsim
Thaum lub sijhawm tsim qauv, koj tso-thiab-txoj kev tsim qauv siv Libero SoC. Tsis tas li ntawd, koj tuaj yeem tshawb xyuas lub sijhawm. Tom qab qhov chaw-thiab-txoj kev, ua tom qab teeb tsa (lub sijhawm) simulation nrog VHDL VITAL-raws li simulator.
Programming
Program ib lub cuab yeej nrog programming software thiab hardware los ntawm Microsemi SoC lossis ib qho kev txhawb nqa thib peb programming. Xa mus rau tus programmer kev pab online rau cov ntaub ntawv hais txog kev tsim cov khoom siv Microsemi SoC.
Kev txheeb xyuas qhov system
Koj tuaj yeem ua qhov kev txheeb xyuas qhov system ntawm cov cuab yeej programmed siv Silicon Explorer cov cuab yeej kuaj mob.
Xa mus rau Silicon Explorer Quick Start rau cov ntaub ntawv hais txog kev siv Silicon Explorer.

Tsim Netlists

Tshooj lus no piav qhia txog cov txheej txheem tsim EDIF thiab cov txheej txheem VHDL netlists.
Tsim ib qho EDIF Netlist
Tom qab ntes koj schematic lossis synthesizing koj tus tsim, tsim ib qho EDIF netlist los ntawm koj cov schematic capture lossis synthesis tool. Siv EDIF netlist rau qhov chaw-thiab-txoj kev. Xa mus rau cov ntaub ntawv nrog rau koj cov schematic capture lossis synthesis cuab tam rau cov ntaub ntawv hais txog kev tsim EDIF netlist.
Tsim tus qauv VHDL Netlist
Tus qauv VHDL netlist files raug tsim los ua ib feem ntawm koj libero SoC qhov project.
Koj tuaj yeem pom koj VHDL netlist files nyob rau hauv /synthesis directory ntawm koj Libero project. Rau example, yog tias koj qhov project directory muaj npe project1, ces koj netlist files yog nyob rau hauv /project1/synthesis.
Qee tsev neeg pab kom koj xa tawm cov no files manually siv rau hauv cov cuab yeej sab nraud. Yog tias koj lub cuab yeej txhawb nqa qhov no koj tuaj yeem xa tawm netlist files los ntawm Cov Cuab Yeej> Export> Netlist.

Simulation nrog ModelSim

Tshooj lus no piav qhia cov kauj ruam los ua tus cwj pwm, qauv thiab lub sijhawm simulation siv ModelSim simulator.
Cov txheej txheem qhia yog rau PC. Tib txheej txheej txheej txheem ua haujlwm zoo ib yam rau UNIX. Siv rau pem hauv ntej slashes nyob rau hauv qhov chaw ntawm rov qab slashes. Rau PC, ntaus cov lus txib rau hauv MTI qhov rais. Rau UNIX, ntaus cov lus txib rau hauv lub qhov rais UNIX.

Cwj Pwm Simulation
Siv cov txheej txheem hauv qab no los ua tus cwj pwm simulation ntawm tus qauv tsim. Xa mus rau cov ntaub ntawv
suav nrog koj lub cuab yeej simulation rau cov ntaub ntawv ntxiv txog kev ua tus cwj pwm simulation.

1. Hu rau koj ModelSim simulator. (PC nkaus xwb)
2. Hloov directory rau koj qhov project directory. Phau ntawv no yuav tsum suav nrog koj tus qauv VHDL files thiab testbench. typ: cd
3. Daim ntawv qhia rau lub tsev qiv ntawv. Yog tias ib qho cores yog instantiated nyob rau hauv koj qhov chaw VHDL, ntaus cov lus txib hauv qab no los qhia lawv mus rau lub tsev qiv ntawv VITAL uas tau muab tso ua ke: vmap $ALSDIR\lib\vtl\95\mti\
   Siv cov tsev qiv ntawv tsev neeg hauv koj tus qauv VHDL files, ntxiv cov kab hauv qab no rau koj tus qauv VHDL files: qiv ; siv .components.all;
4. Tsim ib daim ntawv teev npe "ua haujlwm". Type: vlib ua
5. Daim ntawv qhia mus rau "ua haujlwm" directory. Ntaus cov lus txib nram qab no: vmap work .\work
6. Ua tus cwj pwm simulation ntawm koj tus qauv tsim. Txhawm rau ua qhov kev sim ua tus cwj pwm siv koj VSystem lossis ModelSim simulator, suav koj VHDL tsim thiab testbench files thiab khiav ib simulation. Rau cov qauv tsim hierarchical, suav cov qauv tsim qis dua ua ntej cov qauv tsim qib siab dua.

Cov lus txib hauv qab no qhia tau hais tias yuav ua li cas sau VHDL tsim thiab testbench files:
vwm -93 .vhd
vwm -93 .vhd

Txhawm rau simulate tus tsim, ntaus:
vsim
Rau example:
vsim test_adder_behave
Lub koom haum-architecture khub tau teev tseg los ntawm kev teeb tsa lub npe test_adder_behave hauv testbench yuav raug simulated. Yog tias koj tus qauv tsim muaj PLL core, siv 1ps daws teeb meem:
twm ps
Rau example:
vsim -t ps test_adder_behave

Qauv Simulation
Siv cov txheej txheem hauv qab no los ua cov qauv simulation.

1. Tsim ib tus qauv VHDL netlist. Yog tias koj siv Synopsys Design Compiler, tsim kom muaj cov qauv VHDL netlist siv cov cuab yeej no.
   Yog tias koj siv lwm cov cuab yeej sib txuas, tsim lub rooj vag-qib VHDL los ntawm koj EDIF netlist los ntawm kev siv file generated txiav hauv koj qhov project. Qee cov tsev neeg tsim pab kom koj tsim cov files ncaj qha los ntawm Cov Cuab Yeej> Export> Netlist ntawv qhia zaub mov.
   Nco tseg: Tus tsim VHDL siv std_logic rau txhua qhov chaw nres nkoj. Cov chaw nres tsheb npav yuav nyob hauv tib qhov kev txiav txim me me raws li lawv tshwm sim hauv EDIF netlist.
2. Daim ntawv qhia rau lub tsev qiv ntawv VITAL. Khiav cov lus txib hauv qab no los qhia cov tsev qiv ntawv VITAL uas tau muab tso ua ke.
   vmap ua $ALSDIR\lib\vtl\95\mti\
3. Sau cov structural netlist. Sau koj VHDL tsim thiab testbench files. Cov lus txib hauv qab no qhia tau hais tias yuav ua li cas sau VHDL tsim thiab testbench files:
   vcom e -93 .vhd
   vcom ib-93 .vhd
   vcom ua .vhd
   Nco tseg: Ua ntej, daim ntawv thov compiles cov chaw. Tom qab ntawd, nws suav nrog cov qauv tsim, raws li xav tau rau VHDL netlists sau los ntawm qee cov cuab yeej.
4. Khiav tus qauv simulation. Txhawm rau simulate koj tus qauv tsim, ntaus: vsim
   Rau example: vsim test_adder_structure
   Lub koom haum-architecture khub tau teev tseg los ntawm kev teeb tsa lub npe test_adder_structure hauv testbench yuav raug simulated.
   Yog tias koj tus qauv tsim muaj PLL core, siv 1ps daws teeb meem: vsim -t ps
   Rau example: vsim -t ps test_adder_structure

Sijhawm Simulation
Txhawm rau ua lub sijhawm simulation:

1. Yog hais tias koj tsis tau ua li ntawd, rov qab-annotate koj tsim thiab tsim koj testbench.
2. Txhawm rau ua lub sijhawm simulation siv koj lub V-System lossis ModelSim simulator, suav nrog koj tus qauv VHDL thiab testbench files, yog hais tias lawv tsis tau muab tso ua ke rau ib tug qauv simulation, thiab khiav ib simulation. Cov lus txib hauv qab no qhia tau hais tias yuav ua li cas sau VHDL tsim thiab testbench files:
   vcom e -93 .vhd
   vcom ib-93 .vhd
   vcom ua .vhd
   Nco tseg: Ua cov kauj ruam dhau los suav nrog cov chaw ua ntej thiab tom qab ntawd cov qauv tsim, raws li xav tau rau VHDL netlists sau los ntawm qee cov cuab yeej.
3. Khiav qhov rov qab-annotation simulation siv lub sijhawm cov ntaub ntawv hauv SDF file. Hom: vsim -sdf[max|typ|min] / = .sdf -c
   Cov kev xaiv qhia txog cheeb tsam (los yog txoj hauv kev) rau ib qho piv txwv nyob rau hauv ib qho kev tsim uas rov qab annotation pib. Koj tuaj yeem siv nws los qhia qhov tshwj xeeb FPGA piv txwv hauv qhov tsim qauv loj dua lossis kev sim ntsuas uas koj xav rov qab sau tseg. Rau example: vsim – sdfmax /uut=adder.sdf -c test_adder_structural
   Hauv no example, qhov chaw adder tau instantiated ua piv txwv "uut" nyob rau hauv lub testbench. Lub koom haum-architecture khub tau teev tseg los ntawm kev teeb tsa lub npe hu ua "test_adder_structural" hauv testbench yuav raug simulated siv qhov siab tshaj plaws ncua sij hawm teev tseg hauv SDF file.
   Yog tias koj tus qauv tsim muaj PLL core, siv 1ps daws teeb meem: vsim -t ps -sdf [max|typ|min] / = .sdf -c
   Rau example: vsim -t ps -sdfmax /uut=adder.sdf -c test_adder_structural

A – Cov khoom txhawb nqa

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Kev Pabcuam Cov Neeg Siv Khoom
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Fax, los ntawm txhua qhov chaw hauv ntiaj teb, 408.643.6913

Customer Technical Support Center
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Kev pab txhawb nqa
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Webqhov chaw
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Hu rau Customer Technical Support Center
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Email
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Peb niaj hnub saib xyuas tus email account txhua hnub. Thaum xa koj qhov kev thov rau peb, thov nco ntsoov suav nrog koj lub npe tag nrho, lub tuam txhab npe, thiab koj cov ntaub ntawv tiv toj kom ua tau zoo ntawm koj qhov kev thov.
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Kuv Cases
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Cov ntaub ntawv / Cov ntaub ntawv

Microchip VHDL VITAL SoC Tsim Suite Versions [ua pdf] Cov neeg siv phau ntawv qhia Versions 2024.2 txog 12.0, VHDL VITAL SoC Design Suite Versions, VHDL VITAL, SoC Tsim Suite Versions, Suite Versions, Versions

Cov ntaub ntawv

• Cov neeg siv phau ntawv