I-VHDL EBALULEKILEYO™
Isikhokelo sokulinganisa
Intshayelelo
Esi sikhokelo se-VHDL seSimulation esibalulekileyo sinolwazi malunga nokusebenzisa i-ModelSim ukulinganisa uyilo lwezixhobo ze-Microsemi SoC. Jonga kuncedo lwe-intanethi ngolwazi olongezelelweyo malunga nokusebenzisa isoftware ye-SoC.
Jonga kuxwebhu olubandakanyiweyo nesilingisi sakho ngolwazi malunga nokwenza ukulinganisa.
Iingqikelelo zoXwebhu
Olu xwebhu luthatha oku kulandelayo:
- Uyifakile isoftware yeLibero SoC. Olu xwebhu lolwe-software ye-Libero SoC v10.0 nangaphezulu. Kwiinguqulelo zangaphambili zesoftware, bona i I-VHDL yeLifa leSikhokelo sokuLingisa okuBalulekileyo.
- Ufake iVHDL VITAL simulator yakho.
- Uqhelene nezitishi zokusebenza zeUNIX kunye neenkqubo zokusebenza okanye iiPC kunye neemeko ezisebenzayo zeWindows.
- Uqhelene noyilo lweFPGA kunye nesoftware yoyilo lweFPGA.
Iindibano zoXwebhu
Olu xwebhu lusebenzisa le miba ilandelayo:
- Amathala eencwadi osapho lweFPGA aboniswa njenge . Faka endaweni yotshintsho losapho lweFPGA olufunwayo kunye nosapho lwesixhobo njengoko kufuneka. Umzekeloample: vcom -sebenza .vhd
- Amathala eencwadi eVHDL ahlanganisiweyo aboniswa njenge . Faka endaweni kuluhlu olufunwayo losapho lweVHDL njengoko kufuneka. Ulwimi lweVHDL lufuna ukuba amagama ethala leencwadi aqale ngonobumba wealpha.
Uncedo lwe-Intanethi
Isoftware yeMicrosemi SoC iza ngoncedo lwe-intanethi. Uncedo olukwi-Intanethi olukhethekileyo kwisixhobo ngasinye sesoftware luyafumaneka kwimenyu yoNcedo.
Misela
Esi sahluko siqulethe ulwazi malunga nokuseta i-ModelSim simulator ukulinganisa uyilo lwe-Microsemi SoC.
Esi sahluko sibandakanya iimfuno zesoftware, amanyathelo achaza indlela yokuqokelela iilayibrari ze-Microsemi SoC FPGA, kunye nolunye ulwazi lokuseta kwisixhobo sokulinganisa osisebenzisayo.
IiMfuno zeSoftware
Ulwazi olukule khokelo lusebenza kwi-Microsemi Libero SoC Software v10.0 nangaphezulu kunye ne-IEEE1076-ehambelana ne-VHDL simulators.
Ukongezelela, esi sikhokelo sinolwazi malunga nokusebenzisa i-ModelSim simulators.
Ngolwazi oluthile malunga nokuba zeziphi iinguqulelo ezixhasayo ezi kukhululwa, yiya kwinkqubo yenkxaso yobugcisa kwiMicrosemi web indawo (http://www.actel.com/custsup/search.html) kwaye khangela igama elingundoqo leqela lesithathu.
ImodeliSim
Ekubeni indlela yokuhlohla iyahluka kumsebenzisi ngamnye kunye nofakelo ngalunye, olu xwebhu lusebenzisa i-$ALSDIR ukubonisa indawo apho isoftware ifakwe khona. Ukuba ungumsebenzisi we-Unix, yenza ngokulula imo eguquguqukayo ebizwa ngokuba yi-ALSDIR kwaye usete ixabiso layo kwindlela yofako. Ukuba ungumsebenzisi weWindows, buyisela i-$ALSDIR ngendlela yofakelo kwimiyalelo.
Sebenzisa le nkqubo ilandelayo ukuqokelela amathala eencwadi e-ModelSim simulators. Chwetheza imiyalelo ye-UNIX kwi-UNIX yokwazisa. Chwetheza imiyalelo yeWindows kumgca womyalelo wefestile yeModelSim Transcript.
Le miyalelo ingezantsi yeyeWindows. Ukwenza imiyalelo isebenzele iUNIX, sebenzisa izilikhi eziya phambili endaweni yokusila ngasemva.
Le nkqubo iqulunqa ilayibrari yeMicrosemi VITAL kwi $ALSDIR\lib\vtl\95\mti directory. Kufuneka uqokelele imifuziselo yethala leencwadi le-FPGA ukuze iilayibrari ze-VITAL zisebenze ngokufanelekileyo.
Phawula: Ukuba sele kukho i-MTI directory kwi- $ALSDIR\lib\vtl\95 directory, amathala eencwadi ahlanganisiweyo anokubakho, kwaye akufuneki ukuba wenze le nkqubo ilandelayo.
- Yenza ithala leencwadi elibizwa ngokuba yi mti kwi $ALSDIR\lib\vtl\95 directory.
- Biza iModelSim simulator (iWindows kuphela).
- Tshintshela kulawulo lwe- $ALSDIR\lib\vtl\95\mti. Ngenisa lo myalelo ulandelayo kwi-prompt: cd $ALSDIR\lib\vtl\95\mti
- Yenza a ilayibrari yosapho. Ngenisa lo myalelo ulandelayo kwi-prompt: vlib
- Imephu ye-VITAL yelayibrari ukuya kwi ulawulo. Ngenisa lo myalelo ulandelayo kwi-prompt: vmap $ALSDIR\lib\vtl\95\mti\
- Qokelela iilayibrari zakho ezi-VITAL.
vcom -sebenza ../ .vhd
Umzekeloample, ukuqokelela ithala leencwadi le-40MX kwisilingisi sakho, chwetheza lo myalelo ulandelayo: vcom -work a40mx ../40mx.vhd - (Ngokuzithandela) Qokelela ithala leencwadi lokufuduka. Yenza eli nyathelo kuphela ukuba ufuna ukusebenzisa ilayibrari yokufuduka. Chwetheza lo myalelo ulandelayo kwi-prompt: vcom -work ../ _mig.vhd
Ukuhamba koYilo
Esi sahluko sichaza ukuhamba koyilo lokulinganisa ukuyila kunye ne-VHDL VITAL-ehambelana nesixhobo sokulinganisa.
I-VHDL EBALULEKILEYO Uyilo Flow
Ukuhamba koyilo lwe-VHDL EVITAL kunamanyathelo amane aphambili:
- Yila uyilo
- Phumeza uYilo
- Ukucwangcisa
- Ukuqinisekiswa kweNkqubo
La macandelo alandelayo achaza la manyathelo.
Yila uyilo
Ngexesha lokudalwa koyilo / ukuqinisekiswa, uyilo lufakwe kwi-RTL-level (yokuziphatha) umthombo weVHDL file.
Emva kokubamba uyilo, unokwenza ukulinganisa kokuziphatha kweVHDL file ukuqinisekisa ukuba ikhowudi yeVHDL ichanekile. Ikhowudi iye idityaniswe ibe kumgangatho wesango (ulwakhiwo) lwenethi yeVHDL. Emva kokudibanisa, unokwenza umlinganiso woyilo wangaphambili okhethiweyo woyilo. Ekugqibeleni, uluhlu lwe-EDIF lwe-netlist lwenziwa ukuba lusetyenziswe kwi-Libero SoC kunye ne-VHDL yesakhiwo se-post-layout netlist yenzelwe ukulinganisa ixesha kwi-simulator ehambelana ne-VHDL VITAL.
Ukungena koMthombo weVHDL
Ngenisa umthombo wakho woyilo weVHDL usebenzisa umhleli wokubhaliweyo okanye umhleli weHDL obuthathaka. Umthombo wakho woyilo we-VHDL unokuqulatha i-RTL-level constructs, kunye nokuqikelelwa kwezinto zesakhiwo, ezifana ne-Libero SoC cores.
Ukulinganisa Ukuziphatha
Yenza ukulinganisa kokuziphatha koyilo lwakho ngaphambi kokudibanisa. Ukulinganisa kokuziphatha kuqinisekisa ukusebenza kwekhowudi yakho yeVHDL. Ngokuqhelekileyo, usebenzisa ukulibaziseka kwe-zero kunye nebhentshi yokuvavanya ye-VHDL ukuqhuba ukulinganisa. Jonga kumaxwebhu afakiweyo kunye nesixhobo sakho sokulinganisa ngolwazi malunga nokwenza ukulinganisa okusebenzayo.
Ukudibanisa
Emva kokuba wenze umthombo woyilo wokuziphatha weVHDL, kufuneka uwenze. I-Synthesis iguqula i-VHDL yokuziphatha file kuluhlu lomnatha wesango kunye nokwandisa uyilo lwetekhnoloji ekujoliswe kuyo. Uxwebhu olubandakanyiweyo kunye nesixhobo sakho sokudityaniswa lunolwazi malunga nokwenza uyilo lwe synthesis.
EDIF Netlist Generation
Emva kokuba uyile, wadibanisa, kwaye waqinisekisa uyilo lwakho, isoftware yenza uluhlu lwe-EDIF lwenethi yendawo kunye nendlela eLibero SoC.
Olu luhlu lwenethi lwe-EDIF lukwasetyenziselwa ukuvelisa uluhlu lwenethi lwe-VHDL ukuze lusetyenziswe kukulinganisa kwesakhiwo.
Ulwakhiwo lwe-VHDL Netlist Generation
I-Libero SoC yenza uluhlu lwenethi lwe-VHDL kwinqanaba lesango kuluhlu lwakho lomnatha lwe-EDIF ukuze lusetyenziswe kwi-post-synthesis prelayout yolwakhiwo lokulinganisa.
I file iyafumaneka kulawulo lwe-/synthesis ukuba unqwenela ukwenza ufaniso ngesandla.
Ukulinganisa koLwakhiwo
Yenza ukulinganisa kwesakhiwo phambi kokubeka-kunye-nomzila. Ukulinganisa kolwakhiwo kuqinisekisa ukusebenza kwe-post-synthesis yakho yangaphambili yoyilo lwe-VHDL netlist. Ulibaziseko lweyunithi olubandakanyiweyo kumathala eencwadi eLibero SoC VITAL ehlanganisiweyo ayasetyenziswa. Jonga kumaxwebhu afakiweyo kunye nesixhobo sakho sokulinganisa ngolwazi malunga nokwenza ukulinganisa kwesakhiwo.
Phumeza uYilo
Ngexesha lokuphunyezwa koyilo, ubeka-kunye-umzila uyilo usebenzisa i-Libero SoC. Ukongeza, unokwenza uhlalutyo lwexesha. Emva kwendawo kunye nomzila, yenza i-post layout (ixesha) ukulinganisa kunye ne-VHDL VITAL-ehambelanayo simulator.
Ukucwangcisa
Cwangcisa isixhobo esinesoftware yenkqubo kunye nehardware evela kwiMicrosemi SoC okanye inkqubo yenkqubo yomntu wesithathu exhaswayo. Jonga kumdwelisi woncedo kwi-intanethi ngolwazi malunga nokucwangcisa isixhobo seMicrosemi SoC.
Ukuqinisekiswa kweNkqubo
Unokwenza uqinisekiso lwenkqubo kwisixhobo esicwangcisiweyo usebenzisa isixhobo sokuxilonga seSilicon Explorer.
Jonga kwiSilicon Explorer iQala ngokukhawuleza ngolwazi malunga nokusebenzisa iSilicon Explorer.
Ukuvelisa ii-Netlists
Esi sahluko sichaza iinkqubo zokuvelisa i-EDIF kunye noluhlu lweenethi zeVHDL.
Ukuvelisa uluhlu lwe-EDIF lweNetlist
Emva kokubamba isikimu sakho okanye ukudibanisa uyilo lwakho, yenza uluhlu lwe-EDIF lwe-netlist ukusuka kwisixhobo sakho sokubanjwa okanye isixhobo sokudibanisa. Sebenzisa uluhlu lwenethi lwe-EDIF kwindawo kunye nendlela. Jonga kumaxwebhu aqukiweyo kunye nesixhobo sakho sokubanjwa kwesikim okanye isixhobo sokudibanisa ulwazi malunga nokwenza uluhlu lwenethi lwe-EDIF.
Ukuveliswa koLuhlu lweNetlist lweVHDL
Uluhlu lwenethiwekhi lweVHDL files zenziwa ngokuzenzekelayo njengenxalenye yeprojekthi yakho yeLibero SoC.
Ungalufumana uluhlu lwakho lomnatha lweVHDL files kulawulo lwe/synthesis lweprojekthi yakho yeLibero. UmzekeloampLe, ukuba uvimba weefayili wakho weprojekthi ubizwa ngokuba yiprojekthi1, ngoko uluhlu lwakho lomnatha files ikwi/project1/synthesis.
Ezinye iintsapho zikwenza ukwazi ukuthumela ngaphandle ezi files ngesandla ukuze zisetyenziswe kwizixhobo zangaphandle. Ukuba isixhobo sakho siyaluxhasa olu phawu ungathumela ngaphandle kwe-netlist files ukusuka kwiZixhobo > Rhweba ngaphandle > Netlist.
Ukulinganisa kunye neModelSim
Esi sahluko sichaza amanyathelo okwenza ukulinganisa ukuziphatha, isakhiwo kunye nexesha usebenzisa i-ModelSim simulator.
Iinkqubo ezibonisiweyo zezePC. Iinkqubo zokuseta ezifanayo zisebenza ngokufanayo kwi-UNIX. Sebenzisa izisilayi zangaphambili endaweni yezisilayi ngasemva. KwiPC, chwetheza imiyalelo kwifestile ye-MTI. KwiUNIX, chwetheza imiyalelo kwi-UNIX yefestile.
Ukulinganisa Ukuziphatha
Sebenzisa le nkqubo ilandelayo ukwenza ukulinganisa ukuziphatha koyilo. Jonga kumaxwebhu
ifakwe kunye nesixhobo sakho sokulinganisa ngolwazi olongezelelweyo malunga nokwenza ukulinganisa ukuziphatha.
- Biza iModelSim simulator yakho. (PC kuphela)
- Guqula uvimba weefayili kwiprojekthi yakho. Olu luhlu kufuneka lubandakanye uyilo lwakho lweVHDL files kunye testbench. Uhlobo: cd
- Imephu eya kwiThala leencwadi. Ukuba naziphi na iicores zifakwe kwiVHDL yomthombo wakho, chwetheza lo myalelo ulandelayo ukuwenza imephu kwithala leencwadi eliqokelelweyo VITAL: vmap $ALSDIR\lib\vtl\95\mti\
Ukubonisa ilayibrari yosapho kuyilo lwakho lweVHDL files, yongeza le migca ilandelayo kuyilo lwakho lweVHDL files: ithala leencwadi ; sebenzisa .izixhobo.zonke; - Yenza uluhlu "lomsebenzi". Uhlobo: vlib umsebenzi
- Imephu eya kuluhlu "lomsebenzi". Chwetheza lo myalelo ulandelayo: vmap work .\work
- Yenza ukulinganisa ukuziphatha koyilo lwakho. Ukwenza ukulinganisa kokuziphatha usebenzisa iVSystem yakho okanye iModelSim simulator, qulunqa uyilo lwakho lweVHDL kunye nebhentshi yovavanyo. files kwaye uqhube ukulinganisa. Kuyilo lwemigangatho, qulunqa iibhloko zoyilo zomgangatho osezantsi phambi komgangatho ophezulu weebhloko zoyilo.
Le miyalelo ilandelayo ibonisa indlela yokuqulunqa uyilo lwe-VHDL kunye ne-testbench files:
vcom -93 .vhd
vcom -93 .vhd
Ukulinganisa uyilo, chwetheza:
vsim
Umzekeloample:
vsim test_adder_behave
Iqumrhu-i-architecture pair echazwe lulungelelwaniso olubizwa ngokuba yi-test_adder_behave kwi-testbench iya kwenziwa. Ukuba uyilo lwakho luqulathe undoqo wePLL, sebenzisa isisombululo se-1ps:
vsim -t ps
Umzekeloample:
vsim -t ps test_adder_behave
Ukulinganisa koLwakhiwo
Sebenzisa le nkqubo ilandelayo ukwenza ukulinganisa kwesakhiwo.
- Yenza uluhlu lwenethiwekhi lweVHDL. Ukuba usebenzisa i-Synopsys Design Compiler, yenza uluhlu lwe-VHDL lolwakhiwo usebenzisa esi sixhobo.
Ukuba usebenzisa ezinye izixhobo zokuhlanganisa, yenza iVHDL yomgangatho wesango kuluhlu lwakho lomnatha lweEDIF ngokusebenzisa i file yenziwe ngokuzenzekelayo kwiprojekthi yakho. Ezinye iintsapho zoyilo zikuvumela ukuba wenze i files ngqo kwi Izixhobo > Rhweba ngaphandle > Netlist menu.
Phawula: I-VHDL eyenziweyo isebenzisa std_logic kuwo onke amazibuko. Izibuko zebhasi ziya kuba kwi-bit efanayo njengoko zivela kuluhlu lwenethi lwe-EDIF. - Imephu eya kwithala leencwadi le-VITAL. Sebenzisa lo myalelo ulandelayo ukuze wenze imaphu yethala leencwadi le-VITAL elihlanganisiweyo.
vmap $ALSDIR\lib\vtl\95\mti\ - Qulunqa uluhlu lomnatha lolwakhiwo. Qokelela uyilo lwakho lweVHDL kunye nebhentshi yovavanyo files. Le miyalelo ilandelayo ibonisa indlela yokuqulunqa uyilo lwe-VHDL kunye ne-testbench files:
vcom -nje e -93 .vhd
vcom -nje a -93 .vhd
vcom .vhd
Phawula: Okokuqala, isicelo siqokelela amaziko. Emva koko, iqulunqa i-architecture, njengoko kufunwa kuluhlu lwe-VHDL olubhalwe zezinye izixhobo. - Qhuba ukulinganisa kolwakhiwo. Ukulinganisa uyilo lwakho, chwetheza: vsim
Umzekeloample: vsim test_adder_structure
Iqela lequmrhu lolwakhiwo oluchazwe lulungelelwaniso olubizwa ngokuba yi-test_adder_structure kwi-testbench iya kulinganiswa.
Ukuba uyilo lwakho luqulathe undoqo wePLL, sebenzisa isisombululo se-1ps: vsim -t ps
Umzekeloample: vsim -t ps test_adder_structure
Ixesha lokulinganisa
Ukwenza ukulinganisa ixesha:
- Ukuba awuzange wenze njalo, buyisela i-design yakho kwaye wenze i-testbench yakho.
- Ukwenza ukulinganisa ixesha usebenzisa iV-System okanye iModelSim simulator, qulunqa uyilo lwakho lweVHDL kunye nebhentshi yovavanyo. files, ukuba azikaqulunqwanga ukulinganisa kwesakhiwo, kwaye ziqhube ukulinganisa. Le miyalelo ilandelayo ibonisa indlela yokuqulunqa uyilo lwe-VHDL kunye ne-testbench files:
vcom -nje e -93 .vhd
vcom -nje a -93 .vhd
vcom .vhd
Qaphela: Ukwenza amanyathelo angaphambili kuqulunqa amaziko kuqala kuze emva koko kwenziwe ulwakhiwo, njengoko kufuneka kuluhlu lwe-VHDL olubhalwe zezinye izixhobo. - Sebenzisa ukulinganisa umva-ukulinganisa usebenzisa ulwazi lwexesha kwiSDF file. Uhlobo: vsim -sdf[max|typ|min] / = .sdf -c
I ukhetho lukhankanya ummandla (okanye umendo) kumzekelo kuyilo apho isichasiselo esingasemva siqala khona. Ungayisebenzisa ukukhankanya umzekelo othile weFPGA kuyilo lwenkqubo enkulu okanye ibhentshi yovavanyo onqwenela ukuyibuyisela ngasemva. Umzekeloample: vsim – sdfmax /uut=adder.sdf -c test_adder_structural
Kule exampLe, i-adder yequmrhu iye yaqinisekiswa njengomzekelo "uut" kwi-testbench. Iqela lequmrhu lolwakhiwo olucaciswe lulungelelwaniso olubizwa ngokuba “test_adder_structural” kwibhentshi yovavanyo iya kulinganiswa kusetyenziswa olona libaziseko luphezulu oluchazwe kwiSDF. file.
Ukuba uyilo lwakho luqulathe undoqo wePLL, sebenzisa isisombululo se-1ps: vsim -t ps -sdf[max|typ|min] / = .sdf -c
Umzekeloample: vsim -t ps -sdfmax /uut=adder.sdf -c test_adder_structural
A – Inkxaso yeMveliso
Iqela leeMveliso ze-Microsemi SoC libuyisela iimveliso zayo ngeenkonzo ezahlukeneyo zenkxaso, kubandakanywa iNkonzo yabaThengi, iZiko leNkxaso yoBugcisa boMthengi, a webindawo, i-imeyile, kunye neeofisi zentengiso yehlabathi jikelele.
Esi sihlomelo sinolwazi malunga nokuqhagamshelana ne-Microsemi SoC Products Group kunye nokusebenzisa ezi nkonzo zenkxaso.
Inkonzo eyenzelwe
Qhagamshelana neNkonzo yabaThengi ngenkxaso yemveliso engeyiyo eyobugcisa, njengamaxabiso emveliso, ukuphuculwa kwemveliso, ulwazi lokuhlaziya, isimo somyalelo kunye nokugunyaziswa.
Ukusuka eMntla Melika, fowunela 800.262.1060
Ukusuka kwihlabathi liphela, fowunela 650.318.4460
Ifeksi, naphi na ehlabathini, 408.643.6913
Iziko leNkxaso yoBugcisa boMthengi
Iqela leeMveliso ze-Microsemi SoC lisebenza kwiZiko leNkxaso yoBugcisa boMthengi kunye neenjineli ezinobuchule kakhulu ezinokukunceda ukuphendula i-hardware yakho, isofthiwe, kunye nemibuzo yoyilo malunga neeMveliso ze-Microsemi SoC. Iziko leNkxaso yoBugcisa boMthengi lichitha ixesha elininzi lidala amanqaku esicelo, iimpendulo kwimibuzo yomjikelo woyilo oluqhelekileyo, uxwebhu lwemiba eyaziwayo, kunye nee-FAQ ezahlukeneyo. Ke, ngaphambi kokuba uqhagamshelane nathi, nceda undwendwele izixhobo zethu ze-intanethi. Kusenokwenzeka ukuba sele siyiphendulile imibuzo yakho.
Uxhaso lobuchwepheshe
Ndwendwela iNkxaso yoMthengi webindawo (www.microsemi.com/soc/support/search/default.aspx) ngolwazi oluthe kratya kunye nenkxaso. Iimpendulo ezininzi ziyafumaneka kwiphendla web izibonelelo zibandakanya imizobo, imizobo, kunye namakhonkco kwezinye izixhobo kwi webindawo.
Webindawo
Ungakhangela ulwazi olwahlukeneyo lobugcisa kunye nolungezolobuchwephesha kwiphepha lasekhaya le-SoC, kwi www.microsemi.com/soc.
Ukuqhagamshelana neZiko leNkxaso yoBugcisa boMthengi
Iinjineli ezinezakhono eziphezulu zisebenza kwiZiko leNkxaso yobuGcisa. Iziko leNkxaso yobuGcisa lingaqhagamshelwa nge-imeyile okanye ngeQela leMveliso ye-Microsemi SoC webindawo.
I-imeyile
Ungathumela imibuzo yakho yobugcisa kwidilesi yethu ye-imeyile kwaye ufumane iimpendulo nge-imeyile, ngefeksi, okanye ngefowuni. Kwakhona, ukuba uneengxaki zoyilo, ungathumela i-imeyile uyilo lwakho files ukufumana uncedo.
Sihlala sibeka iliso kwiakhawunti ye-imeyile imini yonke. Xa uthumela isicelo sakho kuthi, nceda uqiniseke ukuba ufaka igama lakho elipheleleyo, igama lenkampani, kunye neenkcukacha zakho zoqhagamshelwano ukuze isicelo sakho siqhutywe ngendlela eyiyo.
Idilesi ye-imeyile yenkxaso yobugcisa yi soc_tech@microsemi.com.
Amatyala am
Abathengi beQela leeMveliso ze-Microsemi SoC banokungenisa kwaye balandelele iimeko zobugcisa kwi-intanethi ngokuya kuMatyala am.
Ngaphandle kwe-US
Abathengi abafuna uncedo ngaphandle kwemimandla yexesha lase-US banokuqhagamshelana nenkxaso yobugcisa nge-imeyile (soc_tech@microsemi.com) okanye uqhagamshelane neofisi yokuthengisa yendawo. Uluhlu lweeofisi zentengiso lunokufumaneka apha www.microsemi.com/soc/company/contact/default.aspx.
ITAR Inkxaso yobuGcisa
Ngenkxaso yobugcisa kwi-RH kunye ne-RT FPGAs ezilawulwa yi-International Traffic in Arms Regulations (ITAR), qhagamshelana nathi ngokusebenzisa soc_tech_itar@microsemi.com. Kungenjalo, ngaphakathi kwaMatyala aM, khetha Ewe kuluhlu oluhlayo lwe-ITAR. Uluhlu olupheleleyo lwe-ITAR-elawulwa yi-Microsemi FPGAs, tyelela i-ITAR web iphepha.
Ikomkhulu leMicrosemi Corporate
Ishishini elinye, Aliso Viejo CA 92656 USA
Ngaphakathi e-USA: +1 949-380-6100
Intengiso: +1 949-380-6136
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I-Microsemi Corporation (i-NASDAQ: i-MSCC) inikezela ngepotfoliyo ebanzi yezisombululo ze-semiconductor: i-aerospace, ukukhusela kunye nokhuseleko; ishishini kunye nonxibelelwano; kunye neemarike zamashishini kunye nezinye zamandla. Iimveliso zibandakanya ukusebenza okuphezulu, ukuthembeka okuphezulu kwe-analog kunye nezixhobo ze-RF, isignali edibeneyo kunye neesekethe ezidibeneyo ze-RF, ii-SoCs ezizenzekelayo, ii-FPGA, kunye ne-subsystems epheleleyo. I-Microsemi ikomkhulu e-Aliso Viejo, eCalifornia Funda ngakumbi kwi www.microsemi.com.
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Microchip VHDL EZIBALULEKILEYO SoC Design Suite Iinguqulelo [pdf] Isikhokelo somsebenzisi Iinguqulelo 2024.2 ukuya 12.0, VHDL VITAL SoC Design Suite Versions, VHDL VITAL, SoC Design Suite Versions, Suite Versions, Versions |