VHDL VITAL™
Jagorar kwaikwayo

Gabatarwa

Wannan Jagoran Kwamfuta Mai Muhimmanci na VHDL ya ƙunshi bayani game da amfani da ModelSim don kwaikwayi ƙira don na'urorin Microsemi SoC. Koma taimakon kan layi don ƙarin bayani game da amfani da software na SoC.
Koma zuwa takaddun da aka haɗa tare da na'urar kwaikwayo don bayani game da yin kwaikwayo.

Daftarin Zato
Wannan takarda tana ɗaukar abubuwa masu zuwa:

1. Kun shigar da software na Libero SoC. Wannan takarda don software na Libero SoC ne v10.0 da sama. Don nau'ikan software na baya, duba Legacy VHDL Muhimmin Jagorar kwaikwaiyo.
2. Kun shigar da na'urar kwaikwayo ta VHDL VITAL.
3. Kun saba da ayyukan UNIX da tsarin aiki ko tare da PC da mahalli masu aiki da Windows.
4. Kun saba da gine-ginen FPGA da software na ƙirar FPGA.

Takardun Yarjejeniyar
Wannan takaddar tana amfani da masu canji masu zuwa:

• Ana nuna ɗakunan karatu na iyali kamar FPGA . Sauya canjin dangin FPGA da ake so da dangin na'urar kamar yadda ake buƙata. Domin misaliample: vcom - aiki .vhd
• Ana nuna ɗakunan karatu na VHDL da aka haɗa azaman . Madadin don canjin dangin VHDL da ake so kamar yadda ake buƙata. Harshen VHDL yana buƙatar sunayen ɗakin karatu su fara da haruffan haruffa.

Taimakon Kan layi
Microsemi SoC software yana zuwa tare da taimakon kan layi. Taimakon kan layi na musamman ga kowane kayan aikin software yana samuwa daga menu na Taimako.

Saita

Wannan babin yana ƙunshe da bayanai kan kafa na'urar kwaikwayo ta ModelSim don kwaikwayi ƙirar Microsemi SoC.
Wannan babin ya ƙunshi buƙatun software, matakan da ke bayanin yadda ake haɗa ɗakunan karatu na Microsemi SoC FPGA, da sauran bayanan saitin kayan aikin kwaikwayo da kuke amfani da su.

Bukatun Software
Bayanin da ke cikin wannan jagorar ya shafi Microsemi Libero SoC Software v10.0 da sama da IEEE1076 masu jituwa VHDL na'urar kwaikwayo.
Bugu da ƙari, wannan jagorar ya ƙunshi bayani game da amfani da na'urar kwaikwayo na ModelSim.
Don takamaiman bayani game da waɗanne nau'ikan wannan sakin ke tallafawa, je zuwa tsarin tallafin fasaha akan Microsemi web shafin (http://www.actel.com/custsup/search.html) kuma bincika maɓalli na ɓangare na uku.

ModelSim
Tunda hanyar shigarwa ta bambanta ga kowane mai amfani da kowane shigarwa, wannan takaddar tana amfani da $ALSDIR don nuna wurin da aka shigar da software. Idan kai mai amfani ne na Unix, kawai ƙirƙirar canjin yanayi mai suna ALSDIR kuma saita ƙimar sa zuwa hanyar shigarwa. Idan kun kasance mai amfani da Windows, maye gurbin $ALSDIR tare da hanyar shigarwa a cikin umarni.
Yi amfani da hanya mai zuwa don haɗa dakunan karatu don ModelSim na'urar kwaikwayo. Buga umarnin UNIX a saurin UNIX. Buga umarnin Windows akan layin umarni na ModelSim Transcript taga.
Umarnin da ke ƙasa don Windows ne. Don sanya umarni suyi aiki don UNIX, yi amfani da slash na gaba maimakon yanke baya.

Wannan hanya tana haɗa ɗakin karatu na Microsemi VITAL a cikin $ALSDIR\lib\vtl\95\mti directory. Dole ne ku haɗa samfuran ɗakin karatu na FPGA don ɗakunan karatu na VITAL suyi aiki yadda ya kamata.
Lura: Idan an riga an sami kundin adireshin MTI a cikin $ALSDIR\lib\vtl\95 directory, ana iya haɗa ɗakunan karatu, kuma ƙila ba za ku buƙaci aiwatar da hanya mai zuwa ba.

1. Ƙirƙiri ɗakin karatu da ake kira mti a cikin $ALSDIR\lib\vtl\95 directory.
2. Kira ModelSim na'urar kwaikwayo (Windows kawai).
3. Canja zuwa $ALSDIR\lib\vtl\95mti directory. Shigar da umarni mai zuwa a hanzari: cd $ALSDIR\lib\vtl\95mti
4. Ƙirƙiri a ɗakin karatu na iyali. Shigar da umarni mai zuwa a hanzari: vlib
5. Taswirar laburaren VITAL zuwa ga directory. Shigar da umarni mai zuwa a gaggawa: vmap $ALSDIR \ lib \ vtl \ 95 \ mti \
6. Haɗa ɗakunan karatu na VITAL ku.
   vcom - aiki ../ .vhd
   Don misaliample, don haɗa ɗakin karatu na 40MX don na'urar kwaikwayo, rubuta umarni mai zuwa: vcom -work a40mx ../40mx.vhd
7. (Na zaɓi) Haɗa ɗakin karatu na ƙaura. Yi wannan matakin kawai idan kana buƙatar amfani da ɗakin karatu na ƙaura. Buga umarni mai zuwa a gaggawa: vcom -work ../ _mig.vhd

Tsarin Tsara

Wannan babin yana bayyana kwararar ƙira don ƙirar ƙira tare da kayan aikin kwaikwayo na VHDL VITAL.

VHDL VITAL Tsare Guda
Gudun ƙirar VHDL VITAL yana da manyan matakai guda huɗu:

1. Ƙirƙiri Zane
2. Aiwatar da Zane
3. Shirye-shirye
4. Tabbatar da Tsari

Sassan da ke gaba suna dalla-dalla waɗannan matakan.

Ƙirƙiri Zane
Lokacin ƙirƙira / tabbatarwa, ana ɗaukar ƙira a cikin tushen VHDL-matakin RTL (halayen) file.
Bayan ɗaukar ƙira, zaku iya yin simintin ɗabi'a na VHDL file don tabbatar da cewa lambar VHDL daidai ce. Ana haɗa lambar zuwa cikin jerin matakan ƙofa (tsari) VHDL. Bayan haɗawa, zaku iya yin simintin ƙirar ƙirar riga-kafi na zaɓi na zaɓi. A ƙarshe, an ƙirƙiri jerin rukunin yanar gizo na EDIF don amfani a cikin Libero SoC kuma an ƙirƙiri tsarin netlist na tsarin VHDL don ƙirar lokaci a cikin na'urar kwaikwayo ta VHDL VITAL.

Shigar da tushen VHDL
Shigar da tushen ƙirar VHDL ɗin ku ta amfani da editan rubutu ko editan HDL mai saurin yanayi. Tushen ƙirar ku na VHDL na iya ƙunsar ginin matakin-RTL, da kuma abubuwan da suka dace da kai tsaye, kamar su Labero SoC.

Kwaikwayon Hali
Yi simintin ɗabi'a na ƙirar ku kafin haɗawa. Kwaikwayon ɗabi'a yana tabbatar da aikin lambar VHDL ɗin ku. Yawanci, kuna amfani da jinkirin sifili da daidaitaccen benci na gwaji na VHDL don fitar da siminti. Koma zuwa takaddun da aka haɗa tare da kayan aikin simintin ku don bayani game da yin simintin aiki.

Magana
Bayan kun ƙirƙiri tushen ƙirar ku na VHDL, dole ne ku haɗa ta. Haɗin kai yana canza halin VHDL file a cikin jerin matakan ƙofa kuma yana haɓaka ƙira don fasaha mai niyya. Takaddun da aka haɗa tare da kayan aikin haɗin ku sun ƙunshi bayanai game da yin haɗin ƙira.

EDIF Netlist Generation
Bayan kun ƙirƙira, haɗawa, da kuma tabbatar da ƙirar ku, software tana haifar da jerin layin EDIF don wuri-da-hanyoyi a cikin Libero SoC.
Ana kuma amfani da wannan jeri na EDIF don samar da tsarin netlist na VHDL don amfani a cikin simintin tsari.

Tsari na VHDL Netlist Generation
Libero SoC yana haifar da jerin matakan VHDL na kofa daga jerin rukunin yanar gizon ku na EDIF don amfani a cikin simintin tsarin prelayout bayan kira.
The file yana samuwa a cikin kundin adireshin /synthesis idan kuna son yin kwaikwayo da hannu.
Tsarin Kwaikwayo
Yi simintin tsari kafin sanyawa-da-fitowa. Kwaikwayon tsari yana tabbatar da ayyukan netlist na VHDL na tsarin bayan-kirki na gaba-gaba. Ana amfani da jinkirin raka'a da aka haɗa a cikin haɗaɗɗun ɗakunan karatu na Libero SoC VITAL. Koma zuwa takaddun da aka haɗa tare da kayan aikin kwaikwayo na ku don bayani game da yin simintin tsari.

Aiwatar da Zane
Yayin aiwatar da ƙira, kuna sanya-da-hanyar ƙira ta amfani da Libero SoC. Bugu da ƙari, kuna iya yin nazarin lokaci. Bayan wuri-da-hanyar hanya, yi simintin shimfidar wuri (lokaci) tare da na'urar kwaikwayo mai dacewa da VHDL VITAL.
Shirye-shirye
Shirya na'ura tare da software na shirye-shirye da hardware daga Microsemi SoC ko tsarin shirye-shirye na ɓangare na uku mai goyan bayan. Koma zuwa taimakon mai shirye-shirye akan layi don bayani game da tsara na'urar Microsemi SoC.
Tabbatar da Tsari
Kuna iya tabbatar da tsarin akan na'urar da aka tsara ta amfani da kayan aikin gano Silicon Explorer.
Koma zuwa Silicon Explorer Quick Start don bayani game da amfani da Silicon Explorer.

Ƙirƙirar Netlists

Wannan babin yana bayyana hanyoyin samar da EDIF da tsarin saƙon VHDL.
Samar da EDIF Netlist
Bayan damƙar ƙirar ku ko haɗa ƙirar ku, ƙirƙira netlist na EDIF daga kayan aikin ƙirar ku ko haɗawa. Yi amfani da jeri na EDIF don wuri-da-hanya. Koma zuwa takaddun da aka haɗa tare da ƙirar ƙira ko kayan aikin haɗin kai don bayani game da samar da jerin saiti na EDIF.
Samar da Lissafin Tsari na VHDL
Tsarin netlist VHDL fileAna samar da s ta atomatik azaman ɓangare na aikin Libero SoC ɗin ku.
Kuna iya nemo jerin jerin hanyoyin sadarwar ku na VHDL files a cikin kundin tsarin aikin ku na Libero. Don misaliampHar ila yau, idan kundin tsarin aikin ku yana suna project1, to, jerin hanyoyin sadarwar ku files suna cikin /project1/synthesis.
Wasu iyalai suna ba ku damar fitar da waɗannan files da hannu don amfani a kayan aikin waje. Idan na'urarka tana goyan bayan wannan fasalin zaka iya fitarwa jerin jerin layi files daga Kayan aiki > Fitarwa > Lissafin layi.

Simulators tare da ModelSim

Wannan babin yana bayyana matakai don aiwatar da simintin ɗabi'a, tsari da lokaci ta amfani da na'urar kwaikwayo ta ModelSim.
Hanyoyin da aka nuna na PC ne. Hanyoyin saitin iri ɗaya suna aiki iri ɗaya don UNIX. Yi amfani da tsinkewar gaba a maimakon yankan baya. Don PC, rubuta umarni a cikin taga MTI. Don UNIX, rubuta umarni a cikin taga UNIX.

Kwaikwayon Hali
Yi amfani da hanya mai zuwa don aiwatar da simintin ɗabi'a na ƙira. Koma zuwa takardun
an haɗa tare da kayan aikin simintin ku don ƙarin bayani game da aiwatar da simintin ɗabi'a.

1. Kira ModelSim na'urar kwaikwayo. (PC kawai)
2. Canja kundin adireshi zuwa kundin aikin ku. Dole ne wannan littafin ya ƙunshi ƙirar VHDL ɗin ku files da testbench. Nau'i: cd
3. Taswira zuwa Laburare. Idan kowane nau'i na ma'auni yana nan take a cikin tushen VHDL, rubuta umarni mai zuwa don taswira su zuwa ɗakin karatu na VITAL da aka haɗa: vmap. $ALSDIR \ lib \ vtl \ 95 \ mti \
   Don duba ɗakin karatu na iyali a cikin ƙirar ku ta VHDL files, ƙara waɗannan layin zuwa ƙirar VHDL ɗin ku files: laburare ; amfani .bangaren.duka;
4. Ƙirƙiri kundin adireshin "aiki". Nau'in: vlib aiki
5. Taswirar zuwa kundin "aiki". Buga umarni mai zuwa: vmap work .\work
6. Yi simintin ɗabi'a na ƙirar ku. Don yin simintin ɗabi'a ta amfani da VSystem ko ModelSim na'urar kwaikwayo, haɗa ƙirar VHDL ɗin ku da benci na gwaji. files kuma gudanar da simulation. Don ƙirar ƙira, tattara ƙananan matakan ƙira kafin shingen ƙira mafi girma.

Umurnai masu zuwa suna nuna yadda ake haɗa ƙirar VHDL da testbench files:
vcom -93 .vhd
vcom -93 .vhd

Don kwaikwayi ƙirar, rubuta:
vsim
Don misaliampda:
vsim test_adder_behave
Za a kwaikwayi nau'ikan gine-ginen gine-gine da ƙayyadaddun ƙayyadaddun tsari mai suna test_adder_behave a cikin testbench. Idan ƙirar ku ta ƙunshi ainihin PLL, yi amfani da ƙudurin 1ps:
vsim -t ps
Don misaliampda:
vsim -t ps test_adder_behave

Tsarin Kwaikwayo
Yi amfani da hanya mai zuwa don yin simintin tsari.

1. Ƙirƙirar jeri na VHDL na tsari. Idan kana amfani da Synopsys Design Compiler, samar da tsarin yanar gizo na VHDL ta amfani da wannan kayan aikin.
   Idan kuna amfani da wasu kayan aikin haɗin kai, samar da matakin-ƙofa VHDL daga jerin hanyoyin sadarwar ku ta EDIF ta amfani da file haifar ta atomatik a cikin aikin ku. Wasu iyalai masu ƙira suna ba ku damar ƙirƙirar files kai tsaye daga Kayan aiki> Fitarwa> Menu na jerin layi.
   Lura: VHDL da aka samar yana amfani da std_logic don duk tashar jiragen ruwa. Tashar jiragen ruwan bas za su kasance cikin tsari iri ɗaya kamar yadda suke bayyana a cikin jerin layin EDIF.
2. Taswirar zuwa ɗakin karatu na VITAL. Gudun umarni mai zuwa don taswirar ɗimbin ɗakin karatu na VITAL.
   vmap $ALSDIR \ lib \ vtl \ 95 \ mti \
3. Ƙirƙiri lissafin tsarin tsarin. Haɗa ƙirar VHDL ɗin ku da benci na gwaji files. Umurnai masu zuwa suna nuna yadda ake haɗa ƙirar VHDL da testbench files:
   vcom - kawai e -93 .vhd
   vcom - kawai a -93 .vhd
   vcom .vhd
   Lura: Na farko, aikace-aikacen yana tattara ƙungiyoyin. Sa'an nan, yana tattara gine-ginen, kamar yadda ake buƙata don jerin ayyukan VHDL waɗanda wasu kayan aikin suka rubuta.
4. Gudanar da simintin tsarin. Don kwaikwayi ƙirar ku, rubuta: vsim
   Don misaliample: vsim test_adder_structure
   Za a kwaikwayi nau'ikan gine-ginen gine-ginen da ƙayyadaddun ƙayyadaddun tsari mai suna test_adder_structure a cikin testbench.
   Idan ƙirar ku ta ƙunshi ainihin PLL, yi amfani da ƙudurin 1ps: vsim -t ps
   Don misaliample: vsim -t ps test_adder_structure

Kwaikwayo lokaci
Don yin simintin lokaci:

1. Idan baku yi haka ba, sake ba da bayanin ƙirar ku kuma ƙirƙiri bench ɗin ku.
2. Don yin simintin lokaci ta amfani da V-System ko ModelSim na'urar kwaikwayo, haɗa ƙirar VHDL ɗin ku da benci na gwaji. files, idan ba a riga an haɗa su don simintin tsari ba, kuma a gudanar da simulation. Umurnai masu zuwa suna nuna yadda ake haɗa ƙirar VHDL da testbench files:
   vcom - kawai e -93 .vhd
   vcom - kawai a -93 .vhd
   vcom .vhd
   Lura: Yin matakan da suka gabata yana tattara ƙungiyoyin farko sannan kuma gine-ginen gine-gine, kamar yadda ake buƙata don jerin hanyoyin sadarwar VHDL waɗanda wasu kayan aikin suka rubuta.
3. Gudanar da simintin bayanan baya ta amfani da bayanan lokaci a cikin SDF file. Nau'in: vsim -sdf[max|typ|min] / = sdf -c
   The zaɓi yana ƙayyade yanki (ko hanya) zuwa misali a cikin ƙira inda aka fara bayanin baya. Kuna iya amfani da shi don tantance takamaiman misali na FPGA a cikin babban tsarin ƙira ko benci wanda kuke son mayar da bayani. Don misaliample: vsim – sdfmax /uut=adder.sdf -c test_adder_structural
   A cikin wannan exampHar ila yau, an ƙaddamar da ƙarar mahaɗan a matsayin misali "uut" a cikin testbench. Biyu-ginin gine-ginen da aka ƙayyade ta hanyar daidaitawa mai suna "test_adder_structural" a cikin testbench za a yi amfani da shi ta amfani da matsakaicin jinkiri da aka ƙayyade a cikin SDF. file.
   Idan ƙirar ku ta ƙunshi ainihin PLL, yi amfani da ƙudurin 1ps: vsim -t ps -sdf[max|typ|min] / = sdf -c
   Don misaliample: vsim -t ps -sdfmax /uut=adder.sdf -c test_adder_structural

A - Tallafin samfur

Microsemi SoC Products Group yana goyan bayan samfuran sa tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, lantarki mail, da kuma duniya tallace-tallace ofisoshin.
Wannan karin bayani ya ƙunshi bayani game da tuntuɓar Rukunin Samfuran Microsemi SoC da amfani da waɗannan sabis ɗin tallafi.

Sabis na Abokin Ciniki
Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.
Daga Arewacin Amirka, kira 800.262.1060
Daga sauran duniya, kira 650.318.4460
Fax, daga ko'ina cikin duniya, 408.643.6913

Cibiyar Taimakon Fasaha ta Abokin Ciniki
Ƙungiyar Samfuran SoC ta Microsemi tana aiki da Cibiyar Tallafin Fasaha ta Abokin Ciniki tare da ƙwararrun injiniyoyi waɗanda zasu iya taimakawa amsa kayan aikinku, software, da ƙira game da samfuran Microsemi SoC. Cibiyar Tallafawa Fasaha ta Abokin Ciniki tana ciyar da lokaci mai yawa don ƙirƙirar bayanin kula, amsoshi ga tambayoyin sake zagayowar ƙira, takaddun abubuwan da aka sani, da FAQ daban-daban. Don haka, kafin ku tuntube mu, da fatan za a ziyarci albarkatun mu na kan layi. Da alama mun riga mun amsa tambayoyinku.

Goyon bayan sana'a
Ziyarci Tallafin Abokin Ciniki webshafin (www.microsemi.com/soc/support/search/default.aspx) don ƙarin bayani da tallafi. Akwai amsoshi da yawa akan abin da ake nema web albarkatun sun haɗa da zane-zane, zane-zane, da hanyoyin haɗin kai zuwa wasu albarkatu akan abubuwan website.

Website
Kuna iya bincika bayanai na fasaha iri-iri da marasa fasaha akan shafin gida na SoC, a www.microsemi.com/soc.

Tuntuɓar Cibiyar Tallafin Fasaha ta Abokin Ciniki
ƙwararrun injiniyoyi suna aiki da Cibiyar Tallafawa Fasaha. Ana iya tuntuɓar Cibiyar Taimakon Fasaha ta imel ko ta Microsemi SoC Products Group website.
Imel
Kuna iya sadar da tambayoyin ku na fasaha zuwa adireshin imel ɗinmu kuma ku karɓi amsoshi ta imel, fax, ko waya. Hakanan, idan kuna da matsalolin ƙira, zaku iya imel ɗin ƙirar ku files don karɓar taimako.
Muna saka idanu akan asusun imel a ko'ina cikin yini. Lokacin aika buƙatun ku zuwa gare mu, da fatan a tabbatar kun haɗa da cikakken sunan ku, sunan kamfani, da bayanan tuntuɓarku don ingantaccen sarrafa buƙatarku.
Adireshin imel ɗin tallafin fasaha shine soc_tech@microsemi.com.

Al'amurana
Abokan ciniki na Rukunin Samfuran SoC na Microsemi na iya ƙaddamarwa da bin diddigin shari'o'in fasaha akan layi ta hanyar zuwa Abubuwan Nawa.
Wajen Amurka
Abokan ciniki masu buƙatar taimako a wajen yankunan lokacin Amurka na iya tuntuɓar tallafin fasaha ta imel (soc_tech@microsemi.com) ko tuntuɓi ofishin tallace-tallace na gida. Ana iya samun jerin sunayen ofisoshin tallace-tallace a www.microsemi.com/soc/company/contact/default.aspx.

Tallafin Fasaha na ITAR
Don goyan bayan fasaha akan RH da RT FPGAs waɗanda aka tsara ta hanyar Traffic in Arms Regulations (ITAR), tuntuɓe mu ta hanyar soc_tech_itar@microsemi.com. A madadin, a cikin Harkoki Na, zaɓi Ee a cikin jerin zaɓuka na ITAR. Don cikakken jerin FPGAs Microsemi da ke sarrafa ITAR, ziyarci ITAR web shafi.

Babban Ofishin Kamfanin Microsemi
Kasuwanci ɗaya, Aliso Viejo CA 92656 Amurka
A cikin Amurka: +1 949-380-6100
Talla: +1 949-380-6136
Fax: +1 949-215-4996

Kamfanin Microsemi (NASDAQ: MSCC) yana ba da cikakkiyar fayil na mafita na semiconductor don: sararin samaniya, tsaro da tsaro; kasuwanci da sadarwa; da kuma kasuwannin masana'antu da madadin makamashi. Samfuran sun haɗa da babban aiki, babban abin dogaro analog da na'urorin RF, gauraye sigina da haɗaɗɗun da'irori na RF, SoCs da za'a iya gyarawa, FPGAs, da cikakkun tsarin ƙasa. Microsemi yana da hedikwata a Aliso Viejo, Calif. Ƙara koyo a www.microsemi.com.

© 2012 Microsemi Corporation. An kiyaye duk haƙƙoƙi. Microsemi da tambarin Microsemi alamun kasuwanci ne na Kamfanin Microsemi. Duk sauran alamun kasuwanci da alamun sabis mallakin masu su ne.
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Takardu / Albarkatu

Microchip VHDL VITAL SoC Design Suite Versions [pdf] Jagorar mai amfani Juzu'i 2024.2 zuwa 12.0, VHDL VITAL SoC Design Suite Versions, VHDL VITAL, SoC Design Suite Versions, Siffofin Suite, Sigogi

Magana

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