UG-20219 iMemori yaNgaphandle yeNdibaniselwano yeIntel Agilex FPGA IP Design Example

Malunga noNxibelelwano lweMemori yaNgaphandle Intel® Agilex™ FPGA IP

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Iinguqulelo ze-IP ziyafana neenguqulelo zesoftware ye-Intel® Quartus® Prime Design Suite ukuya kuthi ga kwi-v19.1. Ukusuka kwi-Intel Quartus Prime Design Suite software version 19.2 okanye kamva, ii-IP cores zineskimu esitsha soguqulelo lwe-IP. Isikimu soguqulelo lwe-IP (XYZ) inombolo iyatshintsha ukusuka kuguqulelo lwesoftware ukuya kwenye. Utshintsho kwi:

• X ibonisa uhlaziyo olukhulu lwe IP. Ukuba uhlaziya isoftware yakho ye-Intel Quartus Prime, kufuneka uhlaziye i-IP.
• I-Y ibonisa i-IP iquka izinto ezintsha. Hlaziya i-IP yakho ukuze ibandakanye ezi mpawu zintsha.
• U-Z ubonisa i-IP ibandakanya utshintsho oluncinci. Hlaziya i-IP yakho ukubandakanya olu tshintsho.
  

  Into	Inkcazo
  IP Version	2.4.2
  Intel Quartus Prime	21.2
  Umhla wokukhupha	2021.06.21

Uyilo EksampLe Isikhokelo esiKhawulezayo sokuQala kuNxibelelwano lweMemori yaNgaphandle Intel Agilex™ FPGA IP

Uyilo oluzenzekelayo example flow iyafumaneka kwi-Intel Agilex™ ujongano lwememori yangaphandle. Ukuvelisa Example Designs iqhosha kwi Exampithebhu yoYilo ikuvumela ukuba uchaze kwaye uvelise udibaniso kunye noyilo lokulinganisa example file iiseti onokuzisebenzisa ukuqinisekisa i-EMIF IP yakho. Unokwenza iex yoyiloample ehambelana neIntel FPGA yophuhliso lwekiti, okanye nayiphi na i-EMIF IP oyenzayo. Ungasebenzisa uyilo example ukunceda uvavanyo lwakho, okanye njengendawo yokuqala yenkqubo yakho.

UYilo ngokubanzi Eksample Workflows

Ukudala iProjekthi ye-EMIF

Kuba yena Intel Quartus Prime software version 17.1 kwaye kamva, kufuneka udale Intel Quartus Prime iprojekthi phambi ukuvelisa EMIF IP kunye noyilo ex.ample.

1. Qalisa isoftware ye-Intel Quartus Prime kwaye ukhethe File ➤ Umncedisi Weprojekthi Omtsha. Cofa Okulandelayo. Uyilo EksampLe Isikhokelo esiKhawulezayo sokuQala kuNxibelelwano lweMemori yaNgaphandle Intel Agilex™ FPGA IP
2. Chaza uvimba weefayili ( ), igama leprojekthi ye-Intel Quartus Prime ( ), kunye nenqanaba eliphezulu loyilo lwegama ( ) ofuna ukuyenza. Cofa Okulandelayo.
3. Qinisekisa ukuba iProjekthi engenanto ikhethiwe. Cofa Okulandelayo amaxesha amabini.
4. Ngaphantsi koSapho, khetha i-Intel Agilex.
5. Ngaphantsi kweGama lokucoca, chwetheza inombolo yenxalenye yesixhobo.
6. Ngaphantsi kwezixhobo ezifumanekayo, khetha isixhobo esifanelekileyo.
7. Cofa Gqiba.

Ukuvelisa kunye noLungiselelo lwe-EMIF IP

La manyathelo alandelayo abonisa indlela yokuvelisa kunye nokuqwalasela i-EMIF IP. Le ndlela yokuhamba yenza i-DDR4 interface, kodwa amanyathelo ayafana kwezinye iiprothokholi. (La manyathelo alandela i-IP Catalogue (ezimeleyo) flow; ukuba ukhetha ukusebenzisa uMyili wePlatform (inkqubo) flow endaweni yoko, amanyathelo ayafana.)

1. Kwifestile yeKhathalogi ye-IP, khetha iMemori yangaphandle ye-Intel Agilex FPGA IP. (Ukuba ifestile yeKhathalogi ye-IP ayibonakali, khetha View ➤ IP Catalog.)
2. KuMhleli weParameter ye-IP, nika igama lequmrhu le-EMIF IP (igama olinikezile apha liba file igama le IP) kwaye ukhankanye uvimba weefayili. Cofa Yenza.
3. Umhleli weparameter uneethebhu ezininzi apho kufuneka uqwalasele iparameters ukubonisa uphumezo lwakho lweEMIF.

Intel Agilex EMIF Izikhokelo zomhleli weParameter
Esi sihloko sinika isikhokelo esiphakamileyo sokwenza i-parameterizing iithebhu kwi-Intel Agilex EMIF IP ipharamitha yomhleli.

Itheyibhile 1. Izikhokelo zomhleli weParameter ye-EMIF

Ithebhu yomhleli weParameter	Izikhokelo
Ngokubanzi	Qinisekisa ukuba ezi parameters zilandelayo zifakwe ngokuchanekileyo: • Inqanaba lesantya sesixhobo. • Ubuninzi bewotshi yememori. • Ubuninzi bewotshi yereferensi ye-PLL.
Inkumbulo	• Jonga kwiphepha ledatha kwisixhobo sakho sememori ukuze ufake iiparamitha kwi Inkumbulo ithebhu. • Kufuneka ufake indawo ethile ye-ALERT# iphini. (Isebenza kwiprotocol yememori yeDDR4 kuphela.)
Mem I/O	• Kuphando lokuqala lweprojekthi, ungasebenzisa useto olusisiseko kwi Mem I/O ithebhu. • Ukuqinisekisa uyilo oluphucukileyo, kufuneka wenze ukulinganisa kwebhodi ukufumana useto olululo lokuphelisa.
FPGA I/O	• Kuphando lokuqala lweprojekthi, ungasebenzisa useto olusisiseko kwi FPGA I/O ithebhu. • Ukuqinisekisa uyilo oluphucukileyo, kufuneka wenze ulinganiso lwebhodi kunye nemifuziselo ye-IBIS enxulumeneyo ukukhetha imigangatho ye-I/O efanelekileyo.
Mem Ixesha	• Kuphando lokuqala lweprojekthi, ungasebenzisa useto olusisiseko kwi Mem Ixesha ithebhu. • Ukuqinisekisa uyilo olukwinqanaba eliphezulu, kufuneka ufake iiparamitha ngokungqinelana nephepha ledatha lesixhobo sakho sememori.
Umlawuli	Cwangcisa iiparamitha zolawulo ngokoqwalaselo olufunwayo kunye nokuziphatha komlawuli wakho wememori.
Ukuxilongwa	Ungasebenzisa iiparameters kwi Ukuxilongwa isithuba ukuncedisa ekuvavanyeni nasekulungiseni inkumbulo yakho ujongano.
Example Designs	I Example Designs ithebhu ikuvumela ukuba wenze uyilo examples yokudibanisa kunye nokulinganisa. Uyilo oluvelisiweyo exampLe yinkqubo ye-EMIF epheleleyo equka i-EMIF IP kunye nomqhubi ovelisa i-traffic engahleliweyo ukuqinisekisa ujongano lwememori.

Ngolwazi oluneenkcukacha kwiiparameters zomntu ngamnye, bhekisa kwisahluko esifanelekileyo kwiprotocol yememori yakho kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.

Ukwenziwa koYilo lwe-EMIF eSinthesizable Example

Kwikiti yophuhliso lwe-Intel Agilex, kwanele ukushiya uninzi lweesetingi ze-Intel Agilex EMIF IP kumaxabiso azo angagqibekanga. Ukuvelisa i-synthesizeble design exampLe, landela la manyathelo:

1. KwiEksample uyilo isithuba, qinisekisa ukuba ibhokisi ye-Synthesis ikhangelwe.
   • Ukuba usebenzisa ujongano olunye example uyilo, qwalasela i-EMIF IP kwaye ucofe File➤ Gcina ukugcina useto lwangoku kusetyenziso olwahlukileyo lwe-IP file ( .ip).
     • Ukuba uphumeza i example uyilo olunonxibelelwano oluninzi, cacisa Inani le-IPs kwinani elifunwayo lojongano. Ungalibona inani elipheleleyo le-EMIF ID efanayo neNani elikhethiweyo le-IPs. Landela la manyathelo ukumisela ujongano ngalunye:
   •  Khetha i-Cal-IP ukucacisa uqhagamshelwano lwe-interface kwi-Calibration IP.
   • Qwalasela i-EMIF IP ngokufanelekileyo kuyo yonke iTab yoMhleli weParameter.
   • Buyela kwi-Example Yila ithebhu kwaye ucofe i-ID ye-EMIF oyifunayo.
   • Phinda inyathelo ukuya ku-c kuyo yonke i-EMIF ID.
   • Ungacofa iqhosha elithi Clear ukususa iiparamitha ezifakiweyo uze uphinde inyathelo a ukuya ku-c ukwenza utshintsho kwi-EMIF IP.
   • Cofa File➤ Gcina ukugcina useto lwangoku kusetyenziso olwahlukileyo lwe-IP file ( .ip).
2. Cofa uVelisa Example Yila kwikona ephezulu ekunene yefestile.
3. Chaza uvimba weefayili woyilo lwe-EMIF example kwaye ucofe u-OK. Ukuveliswa okuyimpumelelo yoyilo lwe-EMIF example yenza oku kulandelayo filecwangcisa phantsi kolawulo lwe qii.
4. Cofa File ➤ Phuma ukuze uphume kwifestile ye-IP yeParameter Pro. Inkqubo ikhuthaza, Utshintsho lwakutsha nje alwenziwanga. Veza ngoku? Cofa u-Hayi ukuze uqhubeke nokuhamba okulandelayo.
5. Ukuvula i-example uyilo, cofa File ➤ Vula iProjekthi, kwaye uhambe uye kwi /ample_name>/qii/ed_synth.qpf kwaye ucofe Vula.
   Phawula: Ukuze ufumane inkcazelo ekuqulunqeni kunye nenkqubo uyilo example, bhekisa ku
   Ukuqulunqa kunye nokuCwangcisa i-Intel Agilex EMIF Design Example.

Umzobo 4. Uyilo oluVeliswe kwi-Synthesizable Example File Ulwakhiwo

Ngolwazi ngolwakhiwo lwenkqubo enemidibaniso emibini okanye ngaphezulu yenkumbulo yangaphandle, bhekisa kuYila uyilo Eksample kunye neMultiple EMIF Interfaces, kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide. Ngolwazi malunga nokulungiswa kweempazamo kujongano oluninzi, bhekisa kuKuvumela i-EMIF Toolkit kuYilo olukhoyo, kwiMemori yaNgaphandle ye-Intel Agilex FPGA IP User Guide.

Phawula: Ukuba awukhethi Ufaniso okanye uHlaziyo lwebhokisi yokukhangela, ulawulo lwendawo iqulathe kuphela uyilo loMyili weQonga files, ezingadityaniswanga yi Intel Quartus Prime software ngokuthe ngqo, kodwa onokuyenza view okanye uhlele kuMyili weQonga. Kule meko ungaqhuba le miyalelo ilandelayo ukwenza udibaniso kunye nokulinganisa file iiseti.

• Ukwenza iprojekthi edibeneyo, kufuneka usebenzise i-quartus_sh -t make_qii_design.tclscript kulawulo lwendawo.
• Ukwenza iprojekthi yokulinganisa, kufuneka usebenzise i-quartus_sh -t make_sim_design.tcl iskripthi kwindawo ekuyiwa kuyo.

Phawula: Ukuba wenze i-design example kwaye wenze utshintsho kuyo kumhleli weparameter, kufuneka uhlaziye uyilo lwe exampukuze ubone utshintsho lwakho luphunyeziwe. Uyilo olusanda kuveliswa exampi-le ayibhali ngaphezulu uyilo olukhoyo example files.

Ukuvelisa i-EMIF Design Example yokulinganisa

Kwikiti yophuhliso lwe-Intel Agilex, kwanele ukushiya uninzi lweesetingi ze-Intel Agilex EMIF IP kumaxabiso azo angagqibekanga. Ukuvelisa i-design example yokulinganisa, landela la manyathelo:

1. KwiEksample uyilo isithuba, qinisekisa ukuba ibhokisi yokulinganisa ikhangelwe. Kwakhona khetha ifomathi yokulinganisa iHDL efunekayo, nokuba yiVerilog okanye iVHDL.
2. Lungisa i-EMIF IP kwaye ucofe File ➤ Gcina ukugcina useto lwangoku kusetyenziso olwahlukileyo lwe-IP file ( .ip).
3. Cofa uVelisa Example Yila kwikona ephezulu ekunene yefestile.
4. Chaza uvimba weefayili woyilo lwe-EMIF example kwaye ucofe u-OK. Ukuveliswa okuyimpumelelo yoyilo lwe-EMIF example yenza ezininzi file iiseti zeendlela ezahlukeneyo zokulingisa ezixhaswayo, phantsi kwe-sim/ed_sim directory.
5. Cofa File ➤ Phuma ukuze uphume kwifestile ye-IP yeParameter Pro. Inkqubo ikhuthaza, Utshintsho lwakutsha nje alwenziwanga. Veza ngoku? Cofa u-Hayi ukuze uqhubeke nokuhamba okulandelayo.

UYilo lokulinganisa oluveliswe Eksample File Ulwakhiwo

Phawula: I-Internal Memory Interfaces Intel Agilex FPGA IP okwangoku ixhasa kuphela i-VCS, i-ModelSim / QuestaSim, kunye ne-Xcelium simulators. Inkxaso eyongezelelweyo yesifanisi icwangciswe kukhupho oluzayo.

Phawula: Ukuba awukhethi Ufaniso okanye uHlaziyo lwebhokisi yokukhangela, ulawulo lwendawo iqulathe kuphela uyilo loMyili weQonga files, ezingadityaniswanga yi Intel Quartus Prime software ngokuthe ngqo, kodwa onokuyenza view okanye uhlele kuMyili weQonga. Kule meko ungaqhuba le miyalelo ilandelayo ukwenza udibaniso kunye nokulinganisa file iiseti.

• Ukwenza iprojekthi edibeneyo, kufuneka usebenzise i-quartus_sh -t make_qii_design.tcl iskripthi kwindawo ekuyiwa kuyo.
• Ukwenza iprojekthi yokulinganisa, kufuneka usebenzise i-quartus_sh -t make_sim_design.tcl iskripthi kwindawo ekuyiwa kuyo.

Phawula: Ukuba wenze i-design example kwaye wenze utshintsho kuyo kumhleli weparameter, kufuneka uhlaziye uyilo lwe exampukuze ubone utshintsho lwakho luphunyeziwe. Uyilo olusanda kuveliswa exampi-le ayibhali ngaphezulu uyilo olukhoyo example files.

Ukulinganisa kuNxamnye noMiselo lweHardware
Ukulinganisa ujongano lwenkumbulo yangaphandle, unokukhetha ukutsiba ulungelelwaniso okanye ulungelelwaniso olupheleleyo kwi-Diagnostics ithebhu ngexesha lesizukulwana se-IP.

Iimodeli zokulinganisa ze-EMIF
Le theyibhile ithelekisa iimpawu ze-skip calibration kunye neemodeli ezipheleleyo zokulinganisa.

Itheyibhile 2. Iimodeli zokulinganisa ze-EMIF: Tsiba ulungelelwaniso ngokuchasene noLungiso olupheleleyo

Tsiba uLungiso	Ulungelelwaniso olupheleleyo
Ukulinganisa inqanaba lenkqubo kugxile kwingqiqo yomsebenzisi.	Ukulinganisa ujongano lwememori olugxile kuhlengahlengiso.
Iinkcukacha zolungelelwaniso azifakwanga.	Ibamba zonke stagulungelelwaniso.
Iyakwazi ukugcina kwaye ikhuphe idatha.	Ibandakanya ukulinganisa, i-bit-deskew, njl.
Imele impumelelo echanekileyo.
Ayithatheli ngqalelo ibhodi skew.

Ukulinganisa kwe-RTL Versus Hardware Ukuphunyezwa
Le theyibhile igxininisa iiyantlukwano eziphambili phakathi kokulinganisa kwe-EMIF kunye nokuphunyezwa kwe-hardware.

Itheyibhile 3. Ukulinganisa kwe-EMIF RTL Versus Hardware Implementation

RTL Ukulinganisa	Ukuphunyezwa kweHardware
Ukuqaliswa kwe-Nios® kunye nekhowudi yokulinganisa iqhutywe ngokufanayo.	Ukuqaliswa kwe-Nios kunye nekhowudi yokulinganisa yenza ngokulandelelana.
Ujongano lubanga isignali ye-cal_done ngaxeshanye ekufaniseni.	Imisebenzi yeFitter imisela ulungelelwaniso lolungelelwaniso, kwaye ujongano alubangi ukuba kwenziwe ngaxeshanye.

Kuya kufuneka uqhube ukulinganisa kwe-RTL ngokusekwe kwiipateni zetrafikhi kwisicelo soyilo lwakho. Qaphela ukuba ukulinganisa kwe-RTL akubonisi ukulibaziseka kokulandelela kwe-PCB okunokubangela ukungafani kwi-latency phakathi kokulinganisa kwe-RTL kunye nokuphunyezwa kwe-hardware.

 Ukulinganisa iMemori yangaphandle ye-IP kunye neModelSim
Le nkqubo ibonisa indlela yokulinganisa uyilo lwe-EMIF example.

1. Qalisa iMentor Graphics* ModelSim isoftwe kwaye ukhethe File ➤ Guqula uvimba weefayili. Yiya kulawulo lwe-sim/ed_sim/mentor ngaphakathi koyilo olwenziweyo example folda.
2. Qinisekisa ukuba ifestile ye-Transcript iboniswe ezantsi kwesikrini. Ukuba ifestile yokuKhutshelwa ayibonakali, yibonise ngokunqakraza View ➤ Ushicilelo.
3. Kwifestile yeSikripthi, sebenzisa umthombo msim_setup.tcl.
4. Emva kokuba umthombo msim_setup.tcl ugqibile ukusebenza, sebenzisa ld_debug kwiSikripthi sefestile.
5. Emva kokuba i-ld_debug igqibile ukusebenza, qinisekisa ukuba i-Objects ifestile ibonisiwe. Ukuba i-Objects window ayibonakali, yibonise ngokunqakraza View ➤ Izinto.
6. Kwifestile yeZinto, khetha imiqondiso ofuna ukuyilinganisa ngokucofa ekunene kwaye ukhethe Yongeza i-Wave.
7. Emva kokuba ugqibile ukukhetha imiqondiso yokulinganisa, yenza ukubaleka-konke kwi-Transcript yefestile. Ukulinganisa kuqhuba de kugqitywe.
8. Ukuba ukulinganisa akubonakali, cofa View ➤ Amaza.

I-Pin yokubekwa kwe-Intel Agilex EMIF IP
Esi sihloko sibonelela ngezikhokelo zokubekwa kwephini.

Ngaphezuluview
I-Intel Agilex FPGAs inesakhiwo esilandelayo:

• Isixhobo ngasinye siqulethe ukuya kwiibhanki ze-8 ze-I / O.
• Ibhanki nganye ye-I/O iqulethe iibhanki ezi-2 ezingaphantsi kwe-I/O.
• Ibhanki nganye ye-sub-I/O iqulethe iindlela ezi-4.
• Umzila ngamnye une-12 yenjongo jikelele-injongo ye-I/O (GPIO) izikhonkwane.

Izikhokelo zePin ngokubanzi
Ezi zilandelayo zizikhokelo zephini ngokubanzi.

Phawula: Ngolwazi oluthe kratya lwephini, bhekisa kwi-Intel Agilex FPGA EMIF IP Pin kunye necandelo loCwangciso lweZibonelelo kwisahluko esithile seprotocol yeprotocol yememori yangaphandle, kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.

• Qinisekisa ukuba izikhonkwane zojongano lwenkumbulo yangaphandle zihlala ngaphakathi komqolo omnye we-I/O.
• Unxibelelwano olusebenza kwiibhanki ezininzi kufuneka lufezekise ezi mfuno zilandelayo:
  •  Iibhanki kufuneka zibe kufuphi enye kwenye. Ngolwazi kwiibhanki ezikufutshane, bhekisa kwi-EMIF Architecture: I/O yeBhanki isihloko kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.
•  Zonke iidilesi kunye nomyalelo kunye nezikhonkwane ezinxulumene nazo kufuneka zihlale ngaphakathi kwebhanki enye.
• Idilesi kunye nomyalelo kunye nezikhonkwane zedatha zingabelana ngebhanki encinci phantsi kwezi meko zilandelayo:
  • Idilesi kunye nomyalelo kunye nezikhonkwane zedatha azikwazi ukwabelana ngomzila we-I/O.
  • Kuphela umzila we-I / O ongasetyenziswanga kwidilesi kunye nebhanki yomyalelo unokuquka izikhonkwane zedatha.

Itheyibhile 4. Izithintelo zePin ngokubanzi

Uhlobo loMqondiso	Ukunyanzelwa
Idatha yeStrobe	Zonke iimpawu zeqela le-DQ kufuneka zihlale kumgca we-I/O ofanayo.
Idatha	Izikhonkwane ze-DQ ezinxulumeneyo kufuneka zihlale kumgca we-I/O ofanayo. Kwiiprothokholi ezingaxhasi imigca yedatha ye-bidirectional, imiqondiso yokufunda kufuneka ihlelwe ngokwahlukileyo kwimiqondiso yokubhala.
Idilesi kunye nomyalelo	Idilesi kunye nezikhonkwane zomyalelo kufuneka zihlale kwiindawo ezichazwe kwangaphambili ngaphakathi kwebhanki encinci ye-I/O.

Phawula: Ngolwazi oluthe kratya lwephini, bhekisa kwi-Intel Agilex FPGA EMIF IP Pin kunye necandelo loCwangciso lweZibonelelo kwisahluko esithile seprotocol yeprotocol yememori yangaphandle, kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.

• Qinisekisa ukuba izikhonkwane zojongano lwenkumbulo yangaphandle zihlala ngaphakathi komqolo omnye we-I/O.
• Unxibelelwano olusebenza kwiibhanki ezininzi kufuneka lufezekise ezi mfuno zilandelayo:
  • Iibhanki kufuneka zibe kufuphi enye kwenye. Ngolwazi kwiibhanki ezikufutshane, bhekisa kwi-EMIF Architecture: I/O yeBhanki isihloko kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.
• Zonke iidilesi kunye nomyalelo kunye nezikhonkwane ezinxulumene nazo kufuneka zihlale ngaphakathi kwebhanki enye.
• Idilesi kunye nomyalelo kunye nezikhonkwane zedatha zingabelana ngebhanki encinci phantsi kwezi meko zilandelayo:
  • Idilesi kunye nomyalelo kunye nezikhonkwane zedatha azikwazi ukwabelana ngomzila we-I/O.
  • Kuphela umzila we-I / O ongasetyenziswanga kwidilesi kunye nebhanki yomyalelo unokuquka izikhonkwane zedatha.

Ukuvelisa i-Design Example ngoKhetho loqwalaselo lweTG

Uyilo oluveliswayo lwe-EMIF example ibandakanya ibhloko yejeneretha yezithuthi (TG). Ngokungagqibekanga, uyilo exampi-le isebenzisa ibhloko ye-TG elula (altera_tg_avl) enokusetwa kwakhona ukuze iphinde iqalise ipateni yendlela enzima. Ukuba kuyimfuneko, unokukhetha ukwenza ijenereyitha yendlela elungelelanisiweyo (TG2) endaweni yoko. Kwi-generator ye-traffic generator (TG2) (altera_tg_avl_2), unokuqwalasela iphethini yendlela yokuhamba ngexesha langempela ngokusebenzisa iirejista zokulawula-oku kuthetha ukuba akudingeki ukuba uphinde udibanise uyilo lokutshintsha okanye uqalise kwakhona iphethini yendlela. Le generator yetrafikhi ibonelela ngolawulo olulungileyo kuhlobo lwetrafikhi eyithumela kujongano lolawulo lwe-EMIF. Ukongeza, ibonelela ngeerejista zobume eziqulethe ulwazi oluneenkcukacha lokungaphumeleli.

Ukwenza i-Traffic Generator kwi-Design Example

Unokwenza umenzi wendlela eqwalaselweyo ukusuka kwi-Diagnostics tab kumhleli wepharamitha ye-EMIF. Ukwenza ijenereyitha yendlela elungelelanisiweyo, vula Sebenzisa i-Avalon traffic generator 2.0 eqwalaselweyo kwi-Diagnostics thebhu.

Umzobo 6.

• Unokukhetha ukukhubaza ipateni yendlela emiselweyo stage okanye itrafikhi elungiselelwe umsebenzisi stage, kodwa kufuneka ube ne-s enye ubuncinanetage yenziwe. Ngolwazi kwezi stages, bhekisa kwiPhatheni yeTrafikhi eMiselweyo kunye nePhatheni yeTrafikhi eqwalaselweyo nguMsebenzisi kwiMemori yaNgaphandle yeNtsebenziswano yeIntel Agilex FPGA IP User Guide.
• Ubude bexesha lovavanyo lweTG2 lusebenza kuphela kwipatheni yendlela emiselweyo. Unokukhetha ubude bexesha lovavanyo elifutshane, eliphakathi, okanye elingenasiphelo.
• ungakhetha nokuba liliphi kumaxabiso amabini kwiparameter yeNdlela yoBumbeko yeTG2:
  • JTAG: Ivumela usebenziso lwe GUI kwinkqubo ye console. Ngolwazi oluthe kratya, bhekisa kwi-Traffic Generator Configuration Interface kwiMemori yangaphandle ye-Intel Agilex FPGA IP User Guide.
  • Thumela ngaphandle: Ivumela usetyenziso lwengqiqo ye-RTL ukulawula ipateni yendlela.

Ukusebenzisa i-Design Example nge EMIF Debug Toolkit

Phambi kokuphehlelela i-EMIF Debug Toolkit, qinisekisa ukuba usiqwalasele isixhobo sakho ngocwangciso. file ene-EMIF Debug Toolkit yenziwe yasebenza. Ukuphehlelela i-EMIF Debug Toolkit, landela la manyathelo:

1. Kwi-Intel Quartus Prime software, vula iSistim Console ngokukhetha iziXhobo ➤ IziXhobo zokulungisa iimpazamo ➤ Ikhonsoli yeNkqubo.
2. [Tsiba eli nyathelo ukuba iprojekthi yakho sele ivuliwe kwi-Intel Quartus Prime software.] Kwi-System Console, layisha into ye-SRAM. file (.sof) ocwangcise ngayo ibhodi (njengoko kuchaziwe kwiiMfuneko zokuSebenzisa i-EMIF Debug Toolkit, kwiMemori yaNgaphandle ye-Intel Agilex FPGA IP User Guide).
3. Khetha iimeko ukulungisa ingxaki.
4. Khetha i-EMIF Calibration Debug Toolkit yohlengahlengiso lwe-EMIF, njengoko kuchaziwe kuKuvelisa uMfanekiso woYilo.ample ngoKhetho lwe-Calibration Debug. Kungenjalo, khetha i-EMIF TG Toolkit yoqwalaselo lwetrafikhi generator debugging, njengoko kuchaziwe kuKuvelisa uMfanekiso woYilo.ample ngoKhetho loqwalaselo lweTG.
5. Cofa Vula i-Toolkit ukuvula okungundoqo view ye-EMIF Debug Toolkit.
6. Ukuba kukho iimeko ezininzi ze-EMIF kuyilo olucwangcisiweyo, khetha ikholamu (indlela eya ku-JTAG master) kunye ne-ID yojongano lwenkumbulo ye-EMIF umzekelo wokuvula isixhobo sezixhobo.
7. Cofa ku-Interface esebenzayo ukuvumela i-toolkit ukuba ifunde iiparamitha zojongano kunye nemo yokulinganisa.
8. Kufuneka ulungise ujongano olunye ngexesha; ngoko ke, ukudibanisa kolunye ujongano kuyilo, kufuneka uqale uvale ujongano lwangoku.

Ezi zilandelayo zi-exampizifundo zeengxelo ezivela kwi-EMIF Calibration Debug Toolkit kunye ne-EMIF TG Configuration Toolkit:, ngokulandelelanayo.

Phawula: Ukufumana iinkcukacha malunga nokulungiswa kweempazamo, jonga kwi-Debugging nge-External Memory Interface Debug Toolkit, kwi-Internal Memory Interfaces Intel Agilex FPGA IP User Guide.

Phawula: Ukufumana iinkcukacha malunga nokulungiswa kwe-generator ye-traffic, bhekisa kwi-Traffic Generator Configuration User Interface, kwi-Internal Memory Interfaces ye-Intel Agilex FPGA IP User Guide.

Uyilo Eksample Inkcazo yeMemori yangaphandle yeNdibaniselwano ye-Intel Agilex FPGA IP

Xa u parameterize kwaye uvelisa i EMIF IP yakho, ungakhankanya ukuba inkqubo yenza abalawuli bokulinganisa kunye nodibaniso. file iseti, kwaye wenze i file icwangcisa ngokuzenzekelayo. Ukuba ukhetha Ukulinganisa okanye uHlangano phantsi kwe-Eksample Design Files kwiEksample Uyilo tab, inkqubo yenza ukulinganisa okupheleleyo file iseti okanye indibaniselwano epheleleyo file cwangcisa, ngokuhambelana nokukhetha kwakho.

Uyilo lweNdibaniselwano Example
Uyilo lwe-synthesis exampI-le iqulethe iibhloko ezinkulu eziboniswe kumzobo ongezantsi.

• Ijenereyitha yendlela, eyi-synthesizeble Avalon®-MM exampumqhubi osebenzisa ipateni engeyonyani yofundo kwaye abhalele inani leparameterized yeedilesi. I-generator ye-traffic iphinda ibeke iliso kwidatha efundwayo kwimemori ukuqinisekisa ukuba ihambelana nedatha ebhaliweyo kwaye ithi ukusilela ngenye indlela.
• Umzekelo wojongano lwenkumbulo, olubandakanya:
  • Umlawuli wememori omodareyitha phakathi kwe-interface ye-Avalon-MM kunye ne-interface ye-AFI.
  • I-PHY, esebenza njengojongano phakathi komlawuli wememori kunye nezixhobo zememori zangaphandle ukwenza imisebenzi yokufunda nokubhala.

Umzobo 7. Uyilo lweSinthesi Example

Phawula: Ukuba enye okanye ngaphezulu kweNdlela yokwabelana ye-PLL, iNdlela yoKwabelana nge-DLL, okanye i-OCT yeNdlela yoKwabelana ngeeparamitha zicwangciswe kulo naliphi na ixabiso ngaphandle koKwabiwa, uyilo lokudityaniswa kwe-ex.ampLe iya kuqulatha i-traffic generator/memory interface iimeko. Iimeko ezimbini ze-traffic generator/memory interface zihambelana kuphela ngoqhagamshelo lwe-PLL/DLL/OCT ekwabelwana ngalo njengoko kuchaziwe kwizicwangciso zeparameter. Ijenereyitha yendlela/imizekelo yojongano lwenkumbulo ibonisa indlela onokwenza ngayo uqhagamshelo kuyilo lwakho.

Uyilo lokulinganisa Eksample
Uyilo lokulinganisa example iqulathe iibhloko ezinkulu eziboniswe kulo mfanekiso ulandelayo.

• Umzekelo woyilo lwe-synthesis example. Njengoko kuchaziwe kwicandelo langaphambili, uyilo lwe-synthesis exampi-le iqulethe ijenereyitha yendlela, icandelo lolungelelaniso, kunye nomzekelo wojongano lwenkumbulo. Ezi bloko zingagqibekanga kwiimodeli zokulinganisa ezingabonakaliyo apho kufanelekileyo ukulinganisa okukhawulezayo.
• Imodeli yememori, esebenza njengemodeli eqhelekileyo ebambelela kwiinkcukacha zeprotocol yememori. Rhoqo, abathengisi beememori babonelela ngeemodeli zokulinganisa kumacandelo abo enkumbulo onokuthi ukhuphele kuwo webiindawo.
• Umkhangeli wesimo, obeka iliso kwiimpawu zesimo ukusuka kwi-IP ye-interface yememori yangaphandle kunye nejeneretha ye-traffic, ukubonakalisa ukupasa jikelele okanye imeko yokungaphumeleli.

Umzobo 10. Uyilo lokulinganisa Example

Example UYilo lweTab yoNxibelelwano
Umhleli weparameter uquka iExample yoYilo ithebhu ekuvumela ukuba wenze iparameter kwaye uvelise uyilo lwakho lwangaphambiliamples.

Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo

Iinguqulelo ze-IP ziyafana ne-Intel Quartus Prime Design Suite iinguqulelo zesoftware ukuya kuthi ga kwi-v19.1. Ukusuka kwi-Intel Quartus Prime Design Suite software version 19.2 okanye kamva, ii-IPs zinenkqubo entsha yoguqulelo lwe-IP. Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza.

IP Core Version	Isikhokelo somsebenzisi
2.4.0	Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo
2.3.0	Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo
2.3.0	Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo
2.1.0	Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo
19.3	Ujongano lweMemori yangaphandle Intel Agilex FPGA IP Design Example ULondolozo lweeNkcukacha eziBalulekileyo

UHlaziyo lweMbali yoXwebhu lweNdibaniselwano yeMemori yaNgaphandle Intel Agilex FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2021.06.21	21.2	2.4.2	Kwi Uyilo Eksampkunye nokuQalisa ngokukhawuleza isahluko: • Yongeza inqaku kwi Ukuqulunqa kunye nokuCwangcisa i-Intel Agilex EMIF Design Example isihloko. • Ukulungiswa kwesihloko se Ukuvelisa i-Design Example ngoKhetho lwe-Calibration Debug isihloko. • Yongeza i Ukuvelisa i-Design Example ngoKhetho loqwalaselo lweTG kwaye Ukwenza i-Traffic Generator kwi-Design Example izihloko. • Amanyathelo alungisiweyo 2, 3, no-4, ahlaziya amanani amaninzi, kwaye wongeze inqaku, kwi Ukusebenzisa i-Design Example nge EMIF Debug Toolkit isihloko.
2021.03.29	21.1	2.4.0	Kwi Uyilo Eksampkunye nokuQalisa ngokukhawuleza isahluko: • Yongeza inqaku kwi Ukwenziwa koYilo lwe-EMIF eSinthesizable Example kwaye Ukuvelisa i-EMIF Design Example yokulinganisa izihloko. • Hlaziya i File Umzobo wesakhiwo kwi Ukuvelisa i-EMIF Design Example yokulinganisa isihloko.
2020.12.14	20.4	2.3.0	Kwi Uyilo Eksampkunye nokuQalisa ngokukhawuleza isahluko, yenza olu tshintsho lulandelayo: • Hlaziya i Ukwenziwa koYilo lwe-EMIF eSinthesizable Example isihloko ukubandakanya uyilo lwe-EMIF emininzi. • Ukuhlaziya umzobo wenyathelo lesi-3, kwi Ukuvelisa i-EMIF Design Example yokulinganisa isihloko.
2020.10.05	20.3	2.3.0	Kwi Uyilo Eksample Quick Start Guide isahluko, yenza olu tshintsho lulandelayo: • Ngaphakathi Ukudala iProjekthi ye-EMIF, ihlaziye umfanekiso kwinyathelo lesi-6. • Ngaphakathi Ukwenziwa koYilo lwe-EMIF eSinthesizable Example, uhlaziywe umzobo kwinyathelo lesi-3. • Ngaphakathi Ukuvelisa i-EMIF Design Example yokulinganisa, uhlaziywe umzobo kwinyathelo lesi-3. • Ngaphakathi Ukulinganisa kuNxamnye noMiselo lweHardware, ilungise i-typo encinci kwitheyibhile yesibini. • Ngaphakathi Ukusebenzisa i-Design Example nge EMIF Debug Toolkit, inyathelo lesi-6 elilungisiweyo, longezwe inyathelo lesi-7 nelesi-8.
iqhubekile...

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2020.04.13	20.1	2.1.0	• Kwi Malunga isahluko, ilungiswe itafile kwi NONE isihloko. • Kwi Uyilo Eksample Quick Start Guide isahluko: - Inyathelo lesi-7 elilungisiweyo kunye nomfanekiso ohambelana nawo, kwi Ukwenziwa koYilo lwe-EMIF eSinthesizable Example isihloko. -Ilungisiwe i Ukuvelisa i-Design Example ngoKhetho lweDebug isihloko. -Ilungisiwe i Ukusebenzisa i-Design Example nge EMIF Debug Toolkit isihloko.
2019.12.16	19.4	2.0.0	• Kwi Uyilo Eksampkunye nokuQalisa ngokukhawuleza isahluko: — Uhlaziywe umzekeliso kwinyathelo lesi-6 le Ukudala iProjekthi ye-EMIF isihloko. — Uhlaziywe umzekeliso kwinyathelo lesi-4 le Ukwenziwa koYilo lwe-EMIF eSinthesizable Example isihloko. — Uhlaziywe umzekeliso kwinyathelo lesi-4 le Ukuvelisa i-EMIF Design Example yokulinganisa isihloko. - Inyathelo elilungisiweyo le-5 kwi Ukuvelisa i-EMIF Design Example yokulinganisa isihloko. -Ilungisiwe i Izikhokelo zePin ngokubanzi kwaye Iibhanki ezikufuphi amacandelo I-Pin yokubekwa kwe-Intel Agilex EMIF IP isihloko.
2019.10.18	19.3		• Kwi Ukudala iProjekthi ye-EMIF isihloko, sihlaziye umfanekiso ngenqaku lesi-6. • Kwi Ukuvelisa kunye noLungiselelo lwe-EMIF IP isihloko, uhlaziywe umzobo ngenyathelo loku-1. • Kwitafile kwi Intel Agilex EMIF Izikhokelo zomhleli weParameter isihloko, sitshintshe inkcazo ye Ibhodi ithebhu. • Kwi Ukwenziwa koYilo lwe-EMIF eSinthesizable Example kwaye Ukuvelisa i-EMIF Design Example yokulinganisa izihloko, zihlaziywe umfanekiso kwinyathelo lesi-3 lesihloko ngasinye. • Kwi Ukuvelisa i-EMIF Design Example yokulinganisa isihloko, ihlaziywe i UYilo lokulinganisa oluveliswe Eksample File Ulwakhiwo umfanekiso kwaye ulungise inqaku elilandela umzobo. • Kwi Ukwenziwa koYilo lwe-EMIF eSinthesizable Example isihloko, yongezwe inyathelo kunye nenani lojongano oluninzi.
2019.07.31	19.2	1.2.0	• Ifakwe Malunga neMemori yangaphandle ye-Intel Agilex FPGA IP isahluko kunye noLwazi lokuKhupha. • Imihla ehlaziyiweyo kunye namanani enguqulelo. • Uphuculo olungephi kwi Uyilo lweNdibaniselwano Example umfanekiso kwi Uyilo lweNdibaniselwano Example isihloko.
2019.04.02	19.1		• Ukukhululwa kokuqala.

UHlaziyo lweMbali yoXwebhu lweNdibaniselwano yeMemori yaNgaphandle Intel Agilex FPGA IP Design Example Isikhokelo somsebenzisi

Amaxwebhu / Izibonelelo

I-intel UG-20219 iMemori yangaphandle yeNdibaniselwano ye-Intel Agilex FPGA IP Design Example [pdf] Isikhokelo somsebenzisi UG-20219 iMemori yaNgaphandle yeNdibaniselwano yeIntel Agilex FPGA IP Design Example, UG-20219, iMemori yaNgaphandle Ujongano lweIntel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

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