UG-20219 Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example

Nezve Yekunze Memory Interfaces Intel® Agilexâ„¢ FPGA IP

Kuburitsa Ruzivo

IP shanduro dzakafanana neIntel® Quartus® Prime Design Suite software shanduro kusvika v19.1. Kubva kuIntel Quartus Prime Design Suite software vhezheni 19.2 kana gare gare, IP cores ine itsva IP shanduro chirongwa. Iyo IP versioning scheme (XYZ) nhamba inoshanduka kubva kune imwe software kuenda kune imwe. Shanduko mu:

• X inoratidza kudzokororwa kukuru kweIP. Kana iwe ukagadziridza yako Intel Quartus Prime software, unofanira kudzorera IP.
• Y inoratidza iyo IP inosanganisira zvinhu zvitsva. Gadzirisa IP yako kuti ubatanidze zvinhu zvitsva izvi.
• Z inoratidza iyo IP inosanganisira shanduko diki. Gadzirisa IP yako kuti ubatanidze shanduko idzi.
  

  Item	Tsanangudzo
  IP Version	2.4.2
  Intel Quartus Prime	21.2
  Release Date	2021.06.21

Design Exampuye Kurumidza Kutanga Gwaro reKunze Memory Interfaces Intel Agilex™ FPGA IP

Imwe otomatiki dhizaini example kuyerera inowanikwa yeIntel Agilex ™ yekunze yekurangarira nzvimbo. The Gadzira Example Dhizaini bhatani pane Example Dhizaini tab inobvumidza iwe kutsanangura uye kugadzira iyo synthesis uye simulation dhizaini example file seti dzaunogona kushandisa kusimbisa yako EMIF IP. Iwe unogona kugadzira dhizaini exampiyo inofanana neIntel FPGA yekuvandudza kit, kana chero EMIF IP yaunogadzira. Unogona kushandisa dhizaini example kubatsira ongororo yako, kana senzvimbo yekutanga kune yako system.

General Design Example Workflows

Kugadzira chirongwa cheEMIF

Kwaiye Intel Quartus Prime software vhezheni 17.1 uye gare gare, iwe unofanirwa kugadzira Intel Quartus Prime purojekiti usati wagadzira iyo EMIF IP uye dhizaini ex.ample.

1. Tangisa Intel Quartus Prime software uye sarudza File ➤ New Project Wizard. Click Next. Design Exampuye Kurumidza Kutanga Gwaro reKunze Memory Interfaces Intel Agilex™ FPGA IP
2. Taura dhairekitori ( ), zita reIntel Quartus Prime project ( ), uye zita repamusoro-soro rekugadzira zita ( ) yaunoda kugadzira. Click Next.
3. Tarisa kuti Empty Project yakasarudzwa. Dzvanya Next kaviri.
4. Pasi peMhuri, sarudza Intel Agilex.
5. Pasi peZita sefa, nyora nhamba yechikamu chemudziyo.
6. Pazasi Zvishandiso Zvinowanikwa, sarudza mudziyo wakakodzera.
7. Dzvanya Finish.

Kugadzira uye Kugadzirisa iyo EMIF IP

Matanho anotevera anoratidza maitiro ekugadzira uye kugadzirisa iyo EMIF IP. Kufamba uku kunogadzira DDR4 interface, asi matanho akafanana kune mamwe maprotocol. (Matanho aya anotevera IP Catalog (yakamira) kuyerera; kana ukasarudza kushandisa Platform Designer (system) inoyerera panzvimbo, matanho akafanana.)

1. Mune iyo IP Catalog hwindo, sarudza Yekunze Memory Interfaces Intel Agilex FPGA IP. (Kana iyo IP Catalog hwindo isingaonekwe, sarudza View ➤ IP Catalog.)
2. MuIP Parameter Mharidzo, ipa zita remubatanidzwa reEMIF IP (zita raunopa pano rinova file zita reIP) uye tsanangura dhairekitori. Dzvanya Gadzira.
3. Iyo parameter mupepeti ine akati wandei ma tabo kwaunofanirwa kugadzirisa ma parameter kuratidza yako EMIF kuita.

Intel Agilex EMIF Parameter Edhita Mazano
Ichi chinyorwa chinopa yakakwira-mwero gwara rekuita parameterizing ma tabo muIntel Agilex EMIF IP parameter mupepeti.

Tafura 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Guidelines
General	Ita shuwa kuti anotevera ma parameter aiswa nemazvo: • The kumhanya giredhi kuti mudziyo. • Kuwanda kwewachi yendangariro. • The PLL referensi wachi frequency.
Memory	• Tarisa kune data sheet yendangariro mudziyo wako kuti uise ma paramita pa Memory tab. • Unofanira kuisawo nzvimbo chaiyo yepini yeALERT#. (Inoshanda kuDDR4 memory protocol chete.)
Mem I/O	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa Mem I/O tab. • Kuti ugadzirise dhizaini yepamusoro, unofanirwa kuita simulation yebhodhi kuti uwane marongero ekupedzisira ekupedzisira.
FPGA I/O	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa FPGA I/O tab. • Pakusimbisa magadzirirwo epamusoro, unofanira kuita simulation yebhodhi nemhando dzeBIS dzakabatana kuti usarudze maitiro akakodzera eI/O.
Mem Timing	• Pakuferefeta kwekutanga kweprojekiti, unogona kushandisa marongero akasarudzika pa Mem Timing tab. • Kuti ugadzirise dhizaini yepamusoro, unofanira kuisa parameters zvinoenderana nebepa redata remudziyo wako.
Controller	Seta iyo controller paramita zvinoenderana nekwaunoda kumisikidzwa uye maitiro kune yako ndangariro controller.
Diagnostics	Iwe unogona kushandisa iyo parameter pane Diagnostics tab yekubatsira mukuyedza uye kugadzirisa ndangariro yako.
Example Designs	The Example Designs tab inokutendera iwe kugadzira dhizaini examples yekubatanidza uye yekufananidza. Iyo yakagadzirwa yakagadzirwa example ndeye yakakwana EMIF sisitimu inosanganisira iyo EMIF IP uye mutyairi anogadzira isina kujairika traffic kusimbisa iyo memory interface.

Kuti uwane ruzivo rwakadzama pamaparamita ega ega, tarisa kuchitsauko chakakodzera chendangariro yako protocol muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.

Kugadzira iyo Synthesizable EMIF Dhizaini Example

Kune iyo Intel Agilex yekuvandudza kit, inokwana kusiya akawanda eIntel Agilex EMIF IP marongero pamaitiro avo ekutanga. Kugadzira iyo synthesizable dhizaini example, tevera matanho aya:

1. Pamusoro peExample Dhizaini tab, ita shuwa kuti Synthesis bhokisi rakatariswa.
   • Kana iwe uri kuita imwe interface example dhizaini, gadzirisa iyo EMIF IP uye tinya File➤ Chengetedza kuchengetedza iko zvino kurongeka mushandisi IP musiyano file ( .ip).
     • Kana uri kuita example dhizaini ine akawanda mainterface, tsanangura Nhamba yeIPs kune inodiwa nhamba yemainterfaces. Iwe unogona kuona iyo yakazara nhamba yeEMIF ID yakafanana neiyo yakasarudzwa Nhamba yeIPs. Tevedza nhanho idzi kugadzirisa imwe neimwe interface:
   •  Sarudza iyo Cal-IP kutsanangura kubatana kweiyo interface kune Calibration IP.
   • Gadzirisa iyo EMIF IP zvinoenderana mune ese Parameter Edhita Tab.
   • Dzokera kuna Eksample Dhizaini tebhu uye tinya Bata pane yaunoda EMIF ID.
   • Dzokorora danho a kusvika c kune ese EMIF ID.
   • Unogona kudzvanya Bvisa bhatani kuti ubvise akabatwa ma paramita uye wodzokorora nhanho a kusvika c kuita shanduko kuEMIF IP.
   • Dzvanya File➤ Chengetedza kuchengetedza iko zvino kurongeka mushandisi IP musiyano file ( .ip).
2. Dzvanya Gadzira Example Dhizaini mukona yepamusoro-kurudyi yehwindo.
3. Taura dhairekitori reiyo EMIF dhizaini example uye tinya OK. Kubudirira kugadzirwa kweEMIF dhizaini example anogadzira zvinotevera fileset pasi pe qii directory.
4. Dzvanya File ➤ Buda kubuda iyo IP Parameter Edhiyo Pro hwindo. Iyo sisitimu inosimudzira, Shanduko dzichangoburwa hadzina kugadzirwa. Gadzira ikozvino? Dzvanya Kwete kuti uenderere mberi nekuyerera kunotevera.
5. Kuvhura example design, tinya File ➤ Vhura Project, uye famba uchienda ku /ample_name>/qii/ed_synth.qpf wobva wadzvanya Vhura.
   Cherechedza: Kuti uwane ruzivo rwekugadzira uye kuronga iyo dhizaini example, kureva
   Kunyora uye Kuronga iyo Intel Agilex EMIF Dhizaini Example.

Mufananidzo 4. Yakagadzirwa Synthesizable Design Example File Chimiro

Kuti uwane ruzivo rwekugadzira sisitimu ine maviri kana anopfuura ekunze memory interfaces, tarisa Kugadzira Dhizaini Example ine Multiple EMIF Interfaces, mune Yekunze Memory Interfaces Intel Agilex FPGA IP User Guide. Kuti uwane ruzivo rwekugadzirisa maitiro akawanda, tarisa Kugonesa iyo EMIF Toolkit muIripo Dhizaini, mune Yekunze Memory Interfaces Intel Agilex FPGA IP User Guide.

Cherechedza: Kana ukasasarudza bhokisi reSimulation kana Synthesis, dhairekitori rekuenda rine chete Platform Designer dhizaini. files, iyo isingabatanidzwe neIntel Quartus Prime software zvakananga, asi izvo zvaunogona view kana gadzirisa muPlatform Designer. Mune ino mamiriro iwe unogona kumhanya inotevera mirairo kugadzira synthesis uye simulation file sets.

• Kuti ugadzire chirongwa chinosanganisirwa, unofanira kumhanya quartus_sh -t make_qii_design.tclscript mudhairekitori rekuenda.
• Kuti ugadzire purojekiti yekufananidza, unofanirwa kumhanya quartus_sh -t make_sim_design.tcl script mudhairekitori rekuenda.

Cherechedza: Kana iwe wakagadzira dhizaini example uye wobva waita shanduko kwairi muparameter mupepeti, iwe unofanirwa kudzoreredza iyo dhizaini exampuye kuona shanduko dzako dzichiitwa. Iyo ichangobva kugadzirwa dhizaini example haanyori dhizaini iripo example files.

Kugadzira iyo EMIF Dhizaini Example for Simulation

Kune iyo Intel Agilex yekuvandudza kit, inokwana kusiya akawanda eIntel Agilex EMIF IP marongero pamaitiro avo ekutanga. Kugadzira iyo dhizaini example yekufananidza, tevera matanho aya:

1. Pamusoro peExample Dhizaini tab, ita shuwa kuti Simulation bhokisi rakatariswa. Sarudza zvakare inodiwa Simulation HDL fomati, ingave Verilog kana VHDL.
2. Gadzirisa iyo EMIF IP uye tinya File ➤ Chengetedza kuchengetedza iko zvino kurongeka mushandisi IP musiyano file ( .ip).
3. Dzvanya Gadzira Example Dhizaini mukona yepamusoro-kurudyi yehwindo.
4. Taura dhairekitori reiyo EMIF dhizaini example uye tinya OK. Kubudirira kugadzirwa kweEMIF dhizaini example inogadzira akawanda file seti yeakasiyana anotsigirwa simulators, pasi pe sim/ed_sim dhairekitori.
5. Dzvanya File ➤ Buda kubuda iyo IP Parameter Edhiyo Pro hwindo. Iyo sisitimu inosimudzira, Shanduko dzichangoburwa hadzina kugadzirwa. Gadzira ikozvino? Dzvanya Kwete kuti uenderere mberi nekuyerera kunotevera.

Yakagadzirwa Simulation Dhizaini Example File Chimiro

Cherechedza: Iyo Yekunze Memory Interfaces Intel Agilex FPGA IP parizvino inotsigira chete VCS, ModelSim/QuestaSim, uye Xcelium simulators. Yekuwedzera simulator rutsigiro inorongwa mune ramangwana kuburitswa.

Cherechedza: Kana ukasasarudza bhokisi reSimulation kana Synthesis, dhairekitori rekuenda rine chete Platform Designer dhizaini. files, iyo isingabatanidzwe neIntel Quartus Prime software zvakananga, asi izvo zvaunogona view kana gadzirisa muPlatform Designer. Mune ino mamiriro iwe unogona kumhanya inotevera mirairo kugadzira synthesis uye simulation file sets.

• Kuti ugadzire chirongwa chinosanganiswa, unofanira kumhanya quartus_sh -t make_qii_design.tcl script mudhairekitori rekuenda.
• Kuti ugadzire purojekiti yekufananidza, unofanirwa kumhanya quartus_sh -t make_sim_design.tcl script mudhairekitori rekuenda.

Cherechedza: Kana iwe wakagadzira dhizaini example uye wobva waita shanduko kwairi muparameter mupepeti, iwe unofanirwa kudzoreredza iyo dhizaini exampuye kuona shanduko dzako dzichiitwa. Iyo ichangobva kugadzirwa dhizaini example haanyori dhizaini iripo example files.

Simulation Versus Hardware Implementation
Kune ekunze ndangariro interface simulation, unogona kusarudza kusvetuka calibration kana yakazara calibration paDiagnostics tab panguva yeIP chizvarwa.

EMIF Simulation Models
Iyi tafura inofanidza maitiro eiyo skip calibration uye yakazara calibration modhi.

Tafura 2. EMIF Simulation Models: Skip Calibration maringe ne Full Calibration

Skip Calibration	Full Calibration
System-level simulation inotarisa pane mushandisi mantiki.	Memory interface simulation inotarisa pane calibration.
Details of calibration haina kutorwa.	Inobata zvese stages of calibration.
Inokwanisa kuchengetedza uye kutora data.	Inosanganisira kuenzana, per-bit deskew, nezvimwe.
Inomiririra kunyatsoshanda.
Haisi kufunga bhodhi skew.

RTL Simulation Versus Hardware Implementation
Iyi tafura inoburitsa misiyano yakakosha pakati peEMIF simulation uye kuita kwehardware.

Tafura 3. EMIF RTL Simulation Versus Hardware Implementation

RTL Simulation	Hardware Implementation
Nios® yekutanga uye calibration kodhi inoteedzera zvakafanana.	Nios kutanga uye calibration kodhi inoteedzana.
Mainterface anoti cal_done siginecha panguva imwe chete mukufananidza.	Fitter mashandiro anotarisisa marongero ekugadzirisa, uye nzvimbo dzekupindirana hadzitaure cal_done panguva imwe chete.

Iwe unofanirwa kumhanyisa RTL simulations zvichienderana netraffic mapatani ekushandisa kwedhizaini yako. Ziva kuti RTL simulation haifanire PCB kunonoka kuteedzera izvo zvinogona kukonzera mutsauko mukunonoka pakati peRTL simulation nekuitwa kwehardware.

 Simulating Yekunze Memory Interface IP ine ModelSim
Iyi nzira inoratidza maitiro ekutevedzera iyo EMIF dhizaini example.

1. Tangisa iyo Mentor Graphics * ModelSim software uye sarudza File ➤ Chinja Dhairekitori. Enda kune sim/ed_sim/mentor dhairekitori mukati meyakagadzirwa dhizaini example folder.
2. Tarisa kuti iyo Transcript hwindo inoratidzwa pazasi pechidzitiro. Kana iyo Transcript hwindo isingaonekwe, iratidze nekudzvanya View ➤ Zvinyorwa.
3. Muhwindo reTranscript, mhanya kunobva msim_setup.tcl.
4. Kana source msim_setup.tcl yapedza kushanda, mhanya ld_debug muTranscript window.
5. Mushure mokunge ld_debug yapedza kushanda, simbisa kuti hwindo reZvinhu rinoratidzwa. Kana hwindo reZvinhu risingaonekwe, riratidze nekudzvanya View ➤ Zvinhu.
6. Muwindo reZvinhu, sarudza masaini aunoda kutevedzera nekudzvanya-kurudyi uye kusarudza Wedzera Wave.
7. Mushure mekunge wapedza kusarudza masaini ekufananidza, ita run -ese muTranscript hwindo. Iyo simulation inomhanya kusvika yapera.
8. Kana simulation isingaonekwe, tinya View ➤ Wave.

Pin Kuiswa kweIntel Agilex EMIF IP
Ichi chinyorwa chinopa nhungamiro yekuiswa kwepini.

Overview
Intel Agilex FPGAs ine inotevera chimiro:

• Chishandiso chega chega chine mabhangi anosvika 8 I/O.
• Bhangi rega rega reI/O rine mabhanga maviri epasi-I/O.
• Imwe neimwe sub-I/O bhangi ine 4 nzira.
• Imwe neimwe nzira ine 12 general-chinangwa I/O (GPIO) pini.

General Pin Guidelines
Izvi zvinotevera general pini nhungamiro.

Cherechedza: Kuti uwane rumwe ruzivo rwepini, tarisa kuIntel Agilex FPGA EMIF IP Pin uye Resource Planning chikamu muchikamu cheprotocol-chaiyo cheiyo yekunze memory protocol, muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.

• Ita shuwa kuti mapini eiyo yakapihwa yekunze memory interface anogara mukati meiyo imwechete I / O mutsara.
• Interfaces inotora mabhangi akawanda inofanirwa kuzadzisa zvinotevera zvinodiwa:
  •  Mabhangi anofanira kunge ari padyo neimwe. Kuti uwane ruzivo pamusoro pemabhangi ari padyo, tarisa kune EMIF Architecture: I/O Bank musoro muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.
•  Yese kero uye yekuraira uye mapini akabatana anofanira kugara mukati mebhangi rimwe chete.
• Kero uye yekuraira uye pini yedata inogona kugovera sub-bhangi pasi pemamiriro anotevera:
  • Kero uye kuraira uye pini yedata haigone kugovera I/O mugwagwa.
  • Chete nzira isina kushandiswa yeI/O mukero uye bhangi rekuraira inogona kuve nepini yedata.

Tafura 4. General Pin Constraints

Signal Type	Constraint
Data Strobe	Zvese zviratidzo zveboka reDQ zvinofanirwa kugara munzira imwechete yeI/O.
Data	Mapini eDQ ane hukama anofanirwa kugara munzira imwechete yeI/O. Kune maprotocol asingatsigire bidirectional data mitsara, masaini ekuverenga anofanirwa kuiswa mumapoka akaparadzana kubva pakunyora masaini.
Kero uye Raira	Kero uye Raira pini dzinofanirwa kugara munzvimbo dzakafanotsanangurwa mukati meI/O sub-bhangi.

Cherechedza: Kuti uwane rumwe ruzivo rwepini, tarisa kuIntel Agilex FPGA EMIF IP Pin uye Resource Planning chikamu muchikamu cheprotocol-chaiyo cheiyo yekunze memory protocol, muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.

• Ita shuwa kuti mapini eiyo yakapihwa yekunze memory interface anogara mukati meiyo imwechete I / O mutsara.
• Interfaces inotora mabhangi akawanda inofanirwa kuzadzisa zvinotevera zvinodiwa:
  • Mabhangi anofanira kunge ari padyo neimwe. Kuti uwane ruzivo pamusoro pemabhangi ari padyo, tarisa kune EMIF Architecture: I/O Bank musoro muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.
• Yese kero uye yekuraira uye mapini akabatana anofanira kugara mukati mebhangi rimwe chete.
• Kero uye yekuraira uye pini yedata inogona kugovera sub-bhangi pasi pemamiriro anotevera:
  • Kero uye kuraira uye pini yedata haigone kugovera I/O mugwagwa.
  • Chete nzira isina kushandiswa yeI/O mukero uye bhangi rekuraira inogona kuve nepini yedata.

Kugadzira Dhizaini Example neTG Configuration Option

Iyo yakagadzirwa EMIF dhizaini example inosanganisira traffic jenareta block (TG). By default, dhizaini example inoshandisa yakapfava TG block (altera_tg_avl) iyo inogona chete kusetwa patsva kuitira kuti itangezve yakaoma-coded traffic traffic. Kana zvichidikanwa, unogona kusarudza kugonesa iyo inogadziriswa traffic jenareta (TG2) panzvimbo. Mune inogadziriswa traffic jenareta (TG2) (altera_tg_avl_2), unogona kugadzirisa iyo traffic pateni munguva chaiyo kuburikidza nekudzora marejista-zvichireva kuti haufanirwe kudzokorodza dhizaini kuti uchinje kana kuvhurazve traffic traffic. Iyi jenareta yetraffic inopa kutonga kwakanaka pamusoro pemhando yetraffic iyo yainotumira pane iyo EMIF control interface. Pamusoro pezvo, inopa marejista emamiriro ane ruzivo rwakadzama rwekutadza.

Kugonesa iyo Traffic jenareta mune Dhizaini Example

Iwe unogona kugonesa iyo inogadziriswa traffic jenareta kubva kuDiagnostics tebhu mune EMIF paramende mupepeti. Kugonesa iyo inogadziriswa traffic jenareta, vhura Shandisa inogadziriswa Avalon traffic jenareta 2.0 pane Diagnostics tab.

Mufananidzo 6.

• Iwe unogona kusarudza kudzima iyo default traffic pateni stage kana iyo userconfigured traffic stage, asi unofanira kuva nes rimwechetetage enabled. Kuti uwane ruzivo pamusoro peizvi stages, tarisa kuDefault Traffic Pattern uye Mushandisi-yakagadziriswa Traffic Pateni mune Yekunze Memory Interfaces Intel Agilex FPGA IP Mushandisi Wekushandisa.
• Iyo TG2 bvunzo yenguva paramende inoshanda chete kune yakasarudzika traffic pateni. Unogona kusarudza bvunzo yenguva pfupi, yepakati, kana isingaperi.
• unogona kusarudza imwe yemhando mbiri dzeTG2 Configuration Interface Mode parameter:
  • JTAG: Inobvumira kushandiswa kweGUI mune system console. Kuti uwane rumwe ruzivo, tarisa kuTraffic Generator Configuration Interface mune Yekunze Memory Interfaces Intel Agilex FPGA IP User Guide.
  • Export: Inobvumira kushandiswa kwetsika RTL logic kudzora traffic traffic.

Kushandisa Dhizaini Example neEMIF Debug Toolkit

Usati watanga iyo EMIF Debug Toolkit, ita shuwa kuti wagadzirisa mudziyo wako uine chirongwa. file iyo ine EMIF Debug Toolkit inogoneswa. Kuti utange iyo EMIF Debug Toolkit, tevera matanho aya:

1. MuIntel Quartus Prime software, vhura iyo System Console nekusarudza Zvishandiso ➤ System Debugging Zvishandiso ➤ System Console.
2. [Svetukira danho iri kana chirongwa chako chatovhurwa muIntel Quartus Prime software.] MuSystem Console, isa chinhu cheSRAM. file (.sof) yawakaronga nayo bhodhi (sekutsanangurwa kwazvinoitwa paKushandisa EMIF Debug Toolkit, muExternal Memory Interfaces Intel Agilex FPGA IP User Guide).
3. Sarudza zviitiko kugadzirisa.
4. Sarudza EMIF Calibration Debug Toolkit yeEMIF calibration debugging, sezvinotsanangurwa muKugadzira Dhizaini Ex.ample neCalibration Debug Option. Neimwe nzira, sarudza EMIF TG Configuration Toolkit ye ​​traffic jenareta debugging, sezvinotsanangurwa muKugadzira Dhizaini Ex.ample neTG Configuration Option.
5. Dzvanya Vhura Toolkit kuvhura main view yeEMIF Debug Toolkit.
6. Kana paine akawanda EMIF zviitiko mune yakarongwa dhizaini, sarudza iyo column (nzira inoenda kuJTAG master) uye memory interface ID yeiyo EMIF muenzaniso yekumisikidza iyo toolkit.
7. Dzvanya Activate Interface kuti ubvumire kiti yezvishandiso kuverenga iyo interface paramita uye chimiro chekuenzanisa.
8. Iwe unofanirwa kugadzirisa imwe interface panguva; saka, kuti ubatanidze kune imwe interface mudhizaini, unofanirwa kutanga wadzima iyo ikozvino interface.

Vanotevera ndeva exampzvimwe zvemishumo kubva kuEMIF Calibration Debug Toolkit uye EMIF TG Configuration Toolkit:, zvichiteerana.

Cherechedza: Kuti uwane rumwe ruzivo nezve calibration debugging, tarisa kuDebugging neExternal Memory Interface Debug Toolkit, muExternal Memory Interfaces Intel Agilex FPGA IP User Guide.

Cherechedza: Kuti uwane rumwe ruzivo nezve traffic jenareta debugging, tarisa kune Traffic Jenareta Configuration Mushandisi Interface, mune Yekunze Memory Interfaces Intel Agilex FPGA IP Mushandisi Yekushandisa.

Design ExampTsananguro yeKunze Memory Interfaces Intel Agilex FPGA IP

Paunoisa parameter uye kugadzira yako EMIF IP, unogona kutsanangura kuti sisitimu inogadzira madhairekitori ekufananidza uye synthesis. file sets, uye kugadzira iyo file anoseta otomatiki. Kana ukasarudza Simulation kana Synthesis pasi Example Dhizaini Files paEksample Dhizaini tab, iyo sisitimu inogadzira simulation yakakwana file seti kana mubatanidzwa wakakwana file seta, zvinoenderana nesarudzo yako.

Synthesis Dhizaini Example
Iyo synthesis dhizaini example ine mabhuroko makuru anoratidzwa mumufananidzo uri pazasi.

• Iyo traffic jenareta, inova synthesizable Avalon®-MM exampmutyairi anoshandisa pseudo-random pateni yekuverenga uye anonyora kune parameterized nhamba yekero. Iyo jenareta yetraffic zvakare inotarisisa iyo data yakaverengwa kubva mundangariro kuti ive nechokwadi chekuti inoenderana neiyo yakanyorwa data uye ichiti kukundikana neimwe nzira.
• Muenzaniso weiyo memory interface, inosanganisira:
  • Mutongi wekurangarira anoyera pakati peAvalon-MM interface uye AFI interface.
  • Iyo PHY, inoshanda senge interface pakati peyekurangarira controller uye ekunze ndangariro zvishandiso kuita kuverenga nekunyora mashandiro.

Mufananidzo 7. Synthesis Design Example

Cherechedza: Kana imwe kana kupfuura yePLL yekugovera Mode, DLL yekugovera Mode, kana OCT yekugovera Mode paramita yakaiswa kune chero kukosha kunze kweKwete Kugovera, iyo synthesis dhizaini ex.ample ichave iine maviri traffic jenareta/memory interface zviitiko. Iwo maviri traffic jenareta/memory interface mamiriro ane hukama chete nekugovaniswa kwePLL/DLL/OCT sekutsanangurwa kwazvinoitwa neparameter. Iyo traffic jenareta / memory interface mamiriro anoratidza maitiro aungaita aya makubatanidza mune ako madhizaini.

Simulation Dhizaini Example
The simulation dhizaini example ine mabhuroko makuru anoratidzwa mumufananidzo unotevera.

• Muenzaniso weiyo synthesis dhizaini example. Sezvakatsanangurwa muchikamu chakapfuura, iyo synthesis dhizaini example ine jenareta yetraffic, calibration chikamu, uye muenzaniso weiyo memory interface. Izvi zvinovharira kusarudzika kune abstract simulation modhi pazvinokodzera kukurumidza kutevedzera.
• Modhi yekurangarira, iyo inoshanda seyakajairwa modhi inoomerera kune ndangariro protocol yakatarwa. Kazhinji, vatengesi vekuyeuka vanopa mamodheru ekufananidza kune avo chaiwo endangariro zvikamu zvaunogona kudhawunirodha kubva kwavari webnzvimbo.
• Chitarisiko chekutarisa, chinotarisisa masiginecha kubva kune yekunze memory interface IP uye traffic jenareta, kuratidza kupasa kwese kana kutadza mamiriro.

Mufananidzo 10. Simulation Design Example

Example Dhizaini Interface Tab
Iyo parameter editor inosanganisira Example Dhizaini tab iyo inokutendera iwe kumisa uye kugadzira yako dhizaini examples.

Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives

IP shanduro dzakafanana neIntel Quartus Prime Design Suite software shanduro kusvika v19.1. Kubva kuIntel Quartus Prime Design Suite software vhezheni 19.2 kana gare gare, IPs ine itsva IP shanduro chirongwa. Kana IP core vhezheni isina kunyorwa, gwara remushandisi rekare IP core version rinoshanda.

IP Core Version	User Guide
2.4.0	Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives
2.3.0	Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives
2.3.0	Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives
2.1.0	Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives
19.3	Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide Archives

Gwaro Rekudzokorora Nhoroondo yeKunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2021.06.21	21.2	2.4.2	Mu Design Exampuye Quick Start chitsauko: • Yakawedzera chinyorwa kune Kunyora uye Kuronga iyo Intel Agilex EMIF Dhizaini Example topic. • Yakanatsiridza zita re Kugadzira Dhizaini Example neCalibration Debug Option topic. • Added the Kugadzira Dhizaini Example neTG Configuration Option uye Kugonesa iyo Traffic jenareta mune Dhizaini Example misoro. • Yakagadziridzwa nhanho 2, 3, uye 4, yakagadziridza nhamba dzakawanda, uye yakawedzera chinyorwa, mu Kushandisa Dhizaini Example neEMIF Debug Toolkit topic.
2021.03.29	21.1	2.4.0	Mu Design Exampuye Quick Start chitsauko: • Yakawedzera chinyorwa kune Kugadzira iyo Synthesizable EMIF Dhizaini Example uye Kugadzira iyo EMIF Dhizaini Example for Simulation misoro. • Updated the File Chimiro dhayagiramu mu Kugadzira iyo EMIF Dhizaini Example for Simulation topic.
2020.12.14	20.4	2.3.0	Mu Design Exampuye Quick Start chitsauko, akaita shanduko dzinotevera: • Updated the Kugadzira iyo Synthesizable EMIF Dhizaini Example musoro wekubatanidza akawanda-EMIF dhizaini. • Yakagadziridza mufananidzo wedanho 3, mu Kugadzira iyo EMIF Dhizaini Example for Simulation topic.
2020.10.05	20.3	2.3.0	Mu Design Exampuye Quick Start Guide chitsauko, akaita shanduko dzinotevera: • In Kugadzira chirongwa cheEMIF, yakagadziridza mufananidzo mudanho rechitanhatu. • In Kugadzira iyo Synthesizable EMIF Dhizaini Example, yakagadziridza chimiro mudanho rechitatu. • In Kugadzira iyo EMIF Dhizaini Example for Simulation, yakagadziridza chimiro mudanho rechitatu. • In Simulation Versus Hardware Implementation, yakagadzirisa kataipa kadiki patafura yechipiri. • In Kushandisa Dhizaini Example neEMIF Debug Toolkit, yakagadziridzwa nhanho yechitanhatu, yakawedzera nhanho 6 ne7.
akaenderera…

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2020.04.13	20.1	2.1.0	• Mu About chitsauko, yakagadziridza tafura mu Kuburitsa Ruzivo topic. • Mu Design Exampuye Quick Start Guide chitsauko: - Yakagadziridzwa nhanho 7 uye mufananidzo wakabatana, mune Kugadzira iyo Synthesizable EMIF Dhizaini Example topic. - Modified the Kugadzira iyo Dhizaini Example neiyo Debug Option topic. - Modified the Kushandisa Dhizaini Example neEMIF Debug Toolkit topic.
2019.12.16	19.4	2.0.0	• Mu Design Exampuye Quick Start chitsauko: - Yakagadziridza mufananidzo mudanho rechitanhatu re Kugadzira chirongwa cheEMIF topic. - Yakagadziridza mufananidzo mudanho rechitanhatu re Kugadzira iyo Synthesizable EMIF Dhizaini Example topic. - Yakagadziridza mufananidzo mudanho rechitanhatu re Kugadzira iyo EMIF Dhizaini Example for Simulation topic. - Yakagadziridzwa nhanho 5 mu Kugadzira iyo EMIF Dhizaini Example for Simulation topic. - Modified the General Pin Guidelines uye Pedyo neMabhangi zvikamu zve Pin Kuiswa kweIntel Agilex EMIF IP topic.
2019.10.18	19.3		• Mu Kugadzira chirongwa cheEMIF musoro, yakagadziridza mufananidzo nepoint 6. • Mu Kugadzira uye Kugadzirisa iyo EMIF IP musoro, yakagadziridza chimiro nedanho 1. • Mutafura mu Intel Agilex EMIF Parameter Edhita Mazano musoro, yakashandura tsananguro ye Board tab. • Mu Kugadzira iyo Synthesizable EMIF Dhizaini Example uye Kugadzira iyo EMIF Dhizaini Example for Simulation misoro, yakagadziridza mufananidzo mudanho rechitatu remusoro wega wega. • Mu Kugadzira iyo EMIF Dhizaini Example for Simulation topic, yakagadziridzwa the Yakagadzirwa Simulation Dhizaini Example File Chimiro mufananidzo uye akagadzirisa chinyorwa chinotevera mufananidzo. • Mu Kugadzira iyo Synthesizable EMIF Dhizaini Example musoro, yakawedzera nhanho uye nhamba yeakawanda interfaces.
2019.07.31	19.2	1.2.0	• Yakawedzerwa Nezve Yekunze Memory Interfaces Intel Agilex FPGA IP chitsauko uye Ruzivo Rwokuburitswa. • Mazuva akavandudzwa uye nhamba dzeshanduro. • Kuwedzeredzwa kudiki kune Synthesis Dhizaini Example mufananidzo mu Synthesis Dhizaini Example topic.
2019.04.02	19.1		• Kusunungurwa kwekutanga.

Gwaro Rekudzokorora Nhoroondo yeKunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example User Guide

Zvinyorwa / Zvishandiso

intel UG-20219 Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi UG-20219 Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Example, UG-20219, Yekunze Memory Interfaces Intel Agilex FPGA IP Dhizaini Ex.ample, Interfaces Intel Agilex FPGA IP Dhizaini Example, Agilex FPGA IP Dhizaini Example

References

• User Manual