UG-20219 Fa'asinoala i fafo Intel Agilex FPGA IP Design Example

E uiga i Feso'ota'iga Fa'amatalaga i fafo Intel® Agilex™ FPGA IP

Fa'asalalau Fa'amatalaga

IP versions e tutusa ma le Intel® Quartus® Prime Design Suite software versions up to v19.1. Mai le Intel Quartus Prime Design Suite software version 19.2 poʻo mulimuli ane, IP cores o loʻo i ai se polokalame faʻaliliuga IP fou. O le numera o le fa'aliliuina o le IP (XYZ) e suia mai le tasi polokalame fa'akomepiuta i le isi. Se suiga i:

• X o loʻo faʻaalia se toe iloiloga tele o le IP. Afai e te fa'afouina lau polokalama Intel Quartus Prime, e tatau ona e toe fa'afouina le IP.
• Y faʻaalia le IP e aofia ai foliga fou. Toe fa'afouina lau IP e fa'aofi ai nei foliga fou.
• O le Z o loʻo faʻaalia ai le IP e aofia ai suiga laiti. Toe fa'afouina lau IP e fa'aofi ai nei suiga.
  

  Aitema	Fa'amatalaga
  IP Version	2.4.2
  Intel Quartus Palemia	21.2
  Aso Fa'asalalau	2021.06.21

Design Example Ta'iala Amata vave mo Feso'ota'iga Manatu i fafo Intel Agilex™ FPGA IP

Ose mamanu otometi exampO lo'o avanoa le tafe mo feso'ota'iga manatua fafo Intel Agilex™. Le Fa'atupu Example fa'amau Designs i le Example Designs tab e mafai ai ona e faʻamaonia ma faʻatupuina le faʻasologa ma le faʻataʻitaʻiga faʻataʻitaʻigaample file seti e mafai ona e faʻaogaina e faʻamaonia ai lau EMIF IP. E mafai ona e faia se mamanu exampe fetaui ma le Intel FPGA development kit, poʻo soʻo se EMIF IP e te gaosia. E mafai ona e faʻaogaina le mamanu example fesoasoani i lau iloiloga, po'o se amataga mo lau lava faiga.

Fuafuaga Lautele Example Galulue

Fausia se Poloketi EMIF

Mo ia Intel Quartus Prime software version 17.1 ma mulimuli ane, e tatau ona e fatuina se Intel Quartus Prime project aʻo leʻi faia le EMIF IP ma le mamanu example.

1. Tatala le polokalama Intel Quartus Prime ma filifili File ➤ Fa'atonu Poloketi Fou. Kiliki le Next. Design Example Ta'iala Amata vave mo Feso'ota'iga Manatu i fafo Intel Agilex™ FPGA IP
2. Fa'ailoa se lisi ( ), o se igoa mo le poloketi Intel Quartus Prime ( ), ma se igoa o le kamupani mamanu pito i luga ( ) e te manaʻo e fai. Kiliki le Next.
3. Fa'amautinoa ua filifilia le Poloketi Gaogao. Kiliki le Next faalua.
4. I lalo o le Aiga, filifili Intel Agilex.
5. I lalo ole faamama Igoa, lolomi le numera vaega ole masini.
6. I lalo o masini avanoa, filifili le masini talafeagai.
7. Kiliki Fa'auma.

Fausiaina ma Fa'atonu le EMIF IP

O laasaga nei o loʻo faʻaalia ai le faʻatupuina ma le faʻatulagaina o le EMIF IP. O lenei savaliga e fausia ai se DDR4 interface, ae o laasaga e tutusa mo isi faʻasalalauga. (O laasaga nei e mulimuli i le IP Catalog (tutoatasi) tafe; afai e te filifili e faʻaoga le Platform Designer (system) tafe nai lo, o laasaga e tutusa.)

1. I le faamalama IP Catalog, filifili Feso'ota'iga Fa'amatalaga i fafo Intel Agilex FPGA IP. (Afai e le o iloa le faamalama IP Catalog, filifili View ➤ IP Catalog.)
2. I le IP Parameter Editor, tuʻu se igoa faʻapitoa mo le EMIF IP (o le igoa e te tuʻuina atu iinei e avea ma file igoa mo le IP) ma faʻamaonia se lisi. Kiliki Fausia.
3. O le fa'atonu fa'ata'ita'i e tele fa'amau e tatau ona e fa'atulaga ai fa'asologa e atagia ai lau fa'atinoga EMIF.

Intel Agilex EMIF Parameter Editor Taiala
O lenei autu o loʻo tuʻuina atu ai taʻiala maualuga mo le faʻavasegaina o laupepa i le Intel Agilex EMIF IP editor parameter.

Laulau 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Taiala
lautele	Ia mautinoa o lo'o sa'o le tu'uina o ta'iala nei: • Le saosaoa togi mo le masini. • Ole taimi ole uati manatua. • Ole taimi ole uati fa'asino ile PLL.
Manatu	• Va'ai i le pepa fa'amaumauga mo lau masini manatua e fa'aoga ai fa'amaufa'ailoga i luga o le Manatu laupepa. • E tatau foi ona e ulufale i se nofoaga patino mo le pine ALERT#. (E fa'aoga ile DDR4 memory protocol.)
Mem I/O	• Mo su'esu'ega muamua o le poloketi, e mafai ona e fa'aogaina tulaga fa'aletonu i le Mem I/O laupepa. • Mo le fa'amaoniaina o mamanu fa'apitoa, e tatau ona e faia fa'ata'ita'iga a le laupapa e maua mai ai le fa'amutaina sili ona lelei.
FPGA I/O	• Mo su'esu'ega muamua o le poloketi, e mafai ona e fa'aogaina tulaga fa'aletonu i le FPGA I/O laupepa. • Mo le fa'amaoniaina o mamanu fa'apitoa, e tatau ona e faia fa'ata'ita'iga a le laupapa fa'atasi ma fa'ata'ita'iga IBIS e fa'atatau i le filifilia o tulaga I/O talafeagai.
Mem Taimi	• Mo su'esu'ega muamua o le poloketi, e mafai ona e fa'aogaina tulaga fa'aletonu i le Mem Taimi laupepa. • Mo le fa'amaoniaina o le mamanu fa'apitoa, e tatau ona e fa'auluina fa'amaufa'ailoga e tusa ai ma lau pepa fa'amaumauga a lau masini manatua.
Pule	Seti le ta'otoga fa'atonu e tusa ai ma le fa'atulagaina ma le amio e mana'omia mo lau fa'atonuga manatua.
Su'esu'ega	E mafai ona e faʻaogaina faʻamau i luga o le Su'esu'ega tab e fesoasoani i le suʻeina ma le faʻapipiʻiina o lau atinaʻe manatua.
Example Fuafuaga	O le Example Fuafuaga tab e mafai ai ona e fatuina mamanu examples mo le tuufaatasia ma mo le simulation. Le mamanu fa'atupu example o se faiga atoa EMIF e aofia ai le EMIF IP ma se avetaʻavale e faʻatupuina feoaiga faʻafuaseʻi e faʻamaonia ai le atinaʻe manatua.

Mo fa'amatalaga au'ili'ili e uiga i ta'iala ta'itasi, va'ai i le mataupu talafeagai mo lau fa'atonuga manatua i le Fa'asinomaga Fa'asinoala i fafo Intel Agilex FPGA IP Taiala.

Fausiaina le Synthesizable EMIF Design Example

Mo le Intel Agilex development kit, ua lava le tu'u o le tele o le Intel Agilex EMIF IP fa'atulagaina i latou tulaga le aoga. Le fa'atupuina o le mamanu synthesizable example, mulimuli i laasaga nei:

1. I le Example Designs tab, faʻamautinoa ua siaki le pusa Synthesis.
   • Afai o loʻo e faʻaaogaina le tasi faʻaoga faʻatasiample mamanu, configure le EMIF IP ma kiliki File➤ Fa'asao e fa'asaoina le tulaga o lo'o i ai nei i le fa'aogaina o le IP fa'aoga file ( .ip).
     • Afai o loʻo e faʻatinoina se example mamanu ma le tele o fesoʻotaʻiga, faʻamaonia Numera o IP i le numera manaʻomia o fesoʻotaʻiga. E mafai ona e vaʻai i le aofaʻi o le EMIF ID tutusa ma le numera o IP ua filifilia. Mulimuli i laasaga nei e fetuutuunai ai atinaʻe taʻitasi:
   •  Filifili le Cal-IP e faʻamaonia ai le fesoʻotaʻiga o le atinaʻe i le Calibration IP.
   • Fa'atulaga le EMIF IP e tusa ai i le Parameter Editor Tab.
   • Toe foʻi i le Esoample Design tab ma kiliki Capture i luga ole ID EMIF manaʻomia.
   • Toe fai le laasaga a i le c mo ID EMIF uma.
   • E mafai ona e kiliki le ki manino e aveese ai le tapulaʻa na puʻeina ma toe fai le laasaga a i le c e fai ai suiga ile EMIF IP.
   • Kiliki File➤ Fa'asao e fa'asaoina le tulaga o lo'o i ai nei i le fa'aogaina o le IP fa'aoga file ( .ip).
2. Kiliki Fausia Example Design i le tulimanu pito i luga taumatau o le faamalama.
3. Fa'ailoa se lisi mo le EMIF design example ma kiliki OK. Fausiaina manuia o le mamanu EMIF example faia mea nei fileseti i lalo o le qii directory.
4. Kiliki File ➤ Alu e alu ese mai le faamalama IP Parameter Editor Pro. O lo'o fa'ailoa mai e le faiga, E le'i faia suiga lata mai. Fausia nei? Kiliki Leai e fa'aauau ai le isi tafega.
5. E tatala le example mamanu, kiliki File ➤ Tatala Poloketi, ma fa'afeiloa'i i le /ample_name>/qii/ed_synth.qpf ma kiliki Tatala.
   Fa'aaliga: Mo faʻamatalaga i le tuʻufaʻatasia ma le faʻatulagaina o le mamanu example, faasino i
   Tuufaatasia ma Polokalama le Intel Agilex EMIF Design Example.

Ata 4. Fuafuaina Synthesizable Design Example File Fauga

Mo faʻamatalaga i le fausiaina o se faiga e lua pe sili atu fesoʻotaʻiga manatua i fafo, faʻafesoʻotaʻi le Fausiaina o se Design Example fa'atasi ai ma le tele o feso'ota'iga EMIF, i totonu o le Fa'asinomaga Fa'asinoala i fafo Intel Agilex FPGA IP Ta'iala mo Tagata Fa'aoga. Mo faʻamatalaga e uiga i le faʻaogaina o fesoʻotaʻiga e tele, faʻafesoʻotaʻi le Enabling the EMIF Toolkit in a Existing Design, i le External Memory Interfaces Intel Agilex FPGA IP User Guide.

Fa'aaliga: Afai e te le filifilia le Fa'ata'ita'iga po'o le Synthesis pusa siaki, o le fa'atonuga o lo'o i ai na'o le fa'atulagaina o le Platform Designer files, e le mafai ona tuufaatasia e le Intel Quartus Prime software tuusao, ae e mafai view po'o le fa'ata'ita'i i totonu o le Platform Designer. I lenei tulaga e mafai ona e faʻataʻitaʻiina tulafono nei e faʻatupuina faʻatasi ma faʻataʻitaʻiga file seti.

• Ina ia fatuina se galuega faʻapipiʻi, e tatau ona e faʻatautaia le quartus_sh -t make_qii_design.tclscript i le lisi o mea e alu i ai.
• Ina ia fatuina se poloketi faʻataʻitaʻiga, e tatau ona e faʻataʻitaʻiina le quartus_sh -t make_sim_design.tcl script i le lisi o taunuuga.

Fa'aaliga: Afai na e fatuina se mamanu example ona fai lea o suiga i le fa'atonu fa'amaufa'ailoga, e tatau ona e toe fa'afouina le mamanu fa'atasiample vaai i au suiga ua faatino. Le mamanu fou fa'atupu exampe le toe fa'asili le mamanu o lo'o iaiample files.

Fausia le EMIF Design Example mo Simulation

Mo le Intel Agilex development kit, ua lava le tu'u o le tele o le Intel Agilex EMIF IP fa'atulagaina i latou tulaga le aoga. Le fa'atupuina o le mamanu example mo faʻataʻitaʻiga, mulimuli i laasaga nei:

1. I le Example Designs tab, faʻamautinoa ua siaki le pusa Simulation. Filifili foʻi le faʻatulagaina o le Simulation HDL, pe Verilog poʻo le VHDL.
2. Fa'atulaga le EMIF IP ma kiliki File ➤ Fa'asao e fa'asaoina le tulaga o lo'o i ai nei i le fa'aogaina o le IP fa'aoga file ( .ip).
3. Kiliki Fausia Example Design i le tulimanu pito i luga taumatau o le faamalama.
4. Fa'ailoa se lisi mo le EMIF design example ma kiliki OK. Fausiaina manuia o le mamanu EMIF example faia tele file seti mo simulators lagolago eseese, i lalo o se fa'atonuga sim/ed_sim.
5. Kiliki File ➤ Alu e alu ese mai le faamalama IP Parameter Editor Pro. O lo'o fa'ailoa mai e le faiga, E le'i faia suiga lata mai. Fausia nei? Kiliki Leai e fa'aauau ai le isi tafega.

Fausia Fa'ata'ita'iga Fuafuaga Example File Fauga

Fa'aaliga: Ole External Memory Interfaces Intel Agilex FPGA IP o loʻo lagolagoina nei naʻo le VCS, ModelSim/QuestaSim, ma le Xcelium simulators. O lo'o fuafuaina le fesoasoani fa'aopoopo simulator i fa'asalalauga i le lumana'i.

Fa'aaliga: Afai e te le filifilia le Fa'ata'ita'iga po'o le Synthesis pusa siaki, o le fa'atonuga o lo'o i ai na'o le fa'atulagaina o le Platform Designer files, e le mafai ona tuufaatasia e le Intel Quartus Prime software tuusao, ae e mafai view po'o le fa'ata'ita'i i totonu o le Platform Designer. I lenei tulaga e mafai ona e faʻataʻitaʻiina tulafono nei e faʻatupuina faʻatasi ma faʻataʻitaʻiga file seti.

• Ina ia fatuina se poloketi faʻapipiʻi, e tatau ona e faʻatautaia le quartus_sh -t make_qii_design.tcl script i le lisi o mea e alu i ai.
• Ina ia fatuina se poloketi faʻataʻitaʻiga, e tatau ona e faʻataʻitaʻiina le quartus_sh -t make_sim_design.tcl script i le lisi o taunuuga.

Fa'aaliga: Afai na e fatuina se mamanu example ona fai lea o suiga i le fa'atonu fa'amaufa'ailoga, e tatau ona e toe fa'afouina le mamanu fa'atasiample vaai i au suiga ua faatino. Le mamanu fou fa'atupu exampe le toe fa'asili le mamanu o lo'o iaiample files.

Fa'ata'ita'iga Fa'asaga i Meafaigaluega Fa'atinoga
Mo fa'ata'ita'iga fa'ata'ita'iga o mafaufauga i fafo, e mafai ona e filifili pe fa'ase'e le fa'avasegaina po'o le fa'avasegaina atoa i luga o le Fa'ailoga Fa'ailoga i le taimi o le fa'atupuina o le IP.

EMIF Fa'ata'ita'iga Fa'ata'ita'iga
O lenei laulau e faʻatusatusa ai uiga o le faʻailoga faʻafefe ma faʻataʻitaʻiga atoatoa.

Laulau 2. EMIF Fa'ata'ita'iga Fa'ata'ita'iga: Fa'ase'e le Fa'avasegaina fa'asaga i le Fa'atonu Atoa

Fa'ase'e le Fa'atonu	Fa'atonu atoatoa
System-level simulation e taulaʻi i le faʻaogaina o tagata faʻaoga.	Fa'ata'ita'iga fa'ata'ita'iga manatua fa'atatau ile fa'avasegaina.
O fa'amatalaga o le fa'avasegaina e le o pu'eina.	Pu'e uma stage o le fa'avasegaina.
E iai le tomai e teu ma toe aumai faʻamaumauga.	E aofia ai le fa'ata'atiaga, kesi pa'u, ma isi.
Fa'atusa sa'o lelei.
E le manatu o le laupapa skew.

RTL Simulation Versus Hardware Faatinoga
O lenei laulau o loʻo faʻamaonia ai eseesega taua i le va o le simulation EMIF ma le faʻatinoina o meafaigaluega.

Fuafuaga 3. EMIF RTL Fa'ata'ita'iga Fa'asaga i Meafaigaluega Fa'atinoga

RTL Simulation	Fa'atinoga o Meafaigaluega
Nios® fa'aulufalega ma le fa'ailoga fa'ailoga e fa'atino tutusa.	Nios initialization ma calibration code e faatino faasolosolo.
Fa'afeso'ota'i fa'ailoa fa'ailoga cal_done i le taimi e tasi i fa'ata'ita'iga.	O fa'agaioiga fa'apipi'i e iloa ai le fa'asologa o le fa'avasegaina, ma e le fa'ailoa e feso'ota'iga le cal_done i le taimi e tasi.

E tatau ona e fa'ata'ita'iina fa'ata'ita'iga a le RTL e fa'atatau i fa'asologa o ta'avale mo le fa'aogaina o lau mamanu. Manatua o le RTL simulation e le faʻataʻitaʻiina PCB faʻatuai faʻasologa e ono mafua ai se eseesega i le va o le RTL simulation ma le faʻaogaina o meafaigaluega.

 Fa'ata'ita'iga Fa'amatalaga Fa'amatalaga Fa'apitoa IP Fa'atasi ma ModelSim
O lenei faiga o loʻo faʻaalia ai le faʻaogaina o le mamanu EMIF example.

1. Tatala le Mentor Graphics* ModelSim software ma filifili File ➤ Suia le Fa'atonu. Su'e ile fa'atonuga o le sim/ed_sim/mentor i totonu ole fa'ata'ita'iga fa'atusaample faila.
2. Fa'amautinoa o lo'o fa'aalia le fa'amalama Transcript i le pito i lalo ole lau. Afai e le o iloa le faamalama Transcript, fa'aali ile kiliki View ➤ Tusitusi.
3. I le fa'amalama Transcript, fa'asolo le puna msim_setup.tcl.
4. A mae'a le puna msim_setup.tcl, fa'agasolo le ld_debug ile fa'amalama Transcript.
5. A maeʻa le ld_debug, faʻamaonia o loʻo faʻaalia le faamalama o Mea. Afai e le o iloa le faamalama Objects, faʻaali ile kiliki View ➤ Mea.
6. I le Objects window, filifili faailo e te manaʻo e faʻataʻitaʻiina e ala i le kiliki-saʻo ma filifili Add Wave.
7. A maeʻa ona e filifilia faʻailoga mo faʻataʻitaʻiga, faʻatino le taʻavale -uma i le faamalama Transcript. O le faʻataʻitaʻiga e faʻatautaia seia maeʻa.
8. Afai e le o iloa le faʻataʻitaʻiga, kiliki View ➤ Galu.

Fa'amauina pine mo Intel Agilex EMIF IP
O lenei autu o loʻo tuʻuina atu taʻiala mo le tuʻuina o pine.

Ua umaview
Intel Agilex FPGA o loʻo i ai le fausaga nei:

• O masini ta'itasi e o'o atu i le 8 I/O faletupe.
• O faletupe I/O ta'itasi e iai le 2 sub-I/O faletupe.
• O faletupe laiti ta'itasi e iai laina e 4.
• O laina ta'itasi e iai ni pine I/O (GPIO) e 12.

Fa'atonuga Fa'amau
O ta'iala masani fa'amau nei.

Fa'aaliga: Mo nisi fa'amatalaga fa'amatalaga pine, va'ai i le Intel Agilex FPGA EMIF IP Pin ma le Fuafuaga o Punaoa vaega i le mataupu fa'apitoa mo lau fa'asologa o mafaufauga i fafo, i le External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Ia mautinoa o pine mo se atina'e manatua i fafo o lo'o i totonu ole laina I/O tutusa.
• O feso'ota'iga e tele faletupe e tatau ona fa'amalieina mana'oga nei:
  •  O faletupe e tatau ona vavalalata le tasi i le isi. Mo fa'amatalaga i faletupe lata ane, va'ai ile EMIF Architecture: I/O Bank autu ile External Memory Interfaces Intel Agilex FPGA IP User Guide.
•  O tuatusi uma ma fa'atonuga ma pine fa'atasi e tatau ona nofo i totonu o se faletupe e tasi.
• tuatusi ma fa'atonuga ma pine fa'amaumauga e mafai ona fa'asoa se faletupe laiti i lalo o tulaga nei:
  • O tuatusi ma fa'atonuga ma pine fa'amaumauga e le mafai ona fa'asoa se laina I/O.
  • Na'o se laina I/O e le'i fa'aogaina i le tuatusi ma le faletupe o le poloaiga e mafai ona i ai pine fa'amaumauga.

Fuafuaga 4. Fa'agata Fa'amau

Ituaiga Faailoga	Taofi
Fa'amatalaga Strobe	O fa'ailo uma o le vaega DQ e tatau ona nofo i le laina I/O tutusa.
Fa'amaumauga	O pine DQ fa'atatau e tatau ona nofo i le laina I/O tutusa. Mo fa'atonuga e le lagolagoina laina fa'amaumauga e lua, o fa'ailoga faitau e tatau ona fa'avasega ese mai fa'ailoga tusitusi.
Tulaga ma Poloaiga	O pine tuatusi ma Poloaiga e tatau ona nofo i nofoaga ua uma ona fa'avasegaina i totonu ole faletupe ole I/O.

Fa'aaliga: Mo nisi fa'amatalaga fa'amatalaga pine, va'ai i le Intel Agilex FPGA EMIF IP Pin ma le Fuafuaga o Punaoa vaega i le mataupu fa'apitoa mo lau fa'asologa o mafaufauga i fafo, i le External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Ia mautinoa o pine mo se atina'e manatua i fafo o lo'o i totonu ole laina I/O tutusa.
• O feso'ota'iga e tele faletupe e tatau ona fa'amalieina mana'oga nei:
  • O faletupe e tatau ona vavalalata le tasi i le isi. Mo fa'amatalaga i faletupe lata ane, va'ai ile EMIF Architecture: I/O Bank autu ile External Memory Interfaces Intel Agilex FPGA IP User Guide.
• O tuatusi uma ma fa'atonuga ma pine fa'atasi e tatau ona nofo i totonu o se faletupe e tasi.
• tuatusi ma fa'atonuga ma pine fa'amaumauga e mafai ona fa'asoa se faletupe laiti i lalo o tulaga nei:
  • O tuatusi ma fa'atonuga ma pine fa'amaumauga e le mafai ona fa'asoa se laina I/O.
  • Na'o se laina I/O e le'i fa'aogaina i le tuatusi ma le faletupe o le poloaiga e mafai ona i ai pine fa'amaumauga.

Fausiaina o se Design Example faʻatasi ma le TG Configuration Option

Le mamanu EMIF fa'atupuample aofia ai se poloka afi afi (TG). Ona o le faaletonu, o le mamanu exampLe fa'aaogaina se poloka TG faigofie (altera_tg_avl) e na'o le toe fa'afo'iina ina ia toe fa'aola ai se fa'asologa o fe'avea'i faigata. Afai e mana'omia, e mafai ona e filifili e fa'aagaina se afi fa'aola fe'avea'i (TG2). I le configurable traffic generator (TG2) (altera_tg_avl_2), e mafai ona e fetuutuunai le faiga o feoaiga i le taimi moni e ala i le puleaina o resitala-o lona uiga e te le toe faʻapipiʻiina le mamanu e sui pe toe faʻaleleia le faʻasologa o auala. O lenei afi afi e maua ai le pulea lelei o le ituaiga o felauaiga o loʻo tuʻuina atu i luga o le faʻaogaina o le EMIF. E le gata i lea, o lo'o tu'uina atu ai fa'amaumauga o tulaga o lo'o iai fa'amatalaga fa'aletonu.

Fa'aagaoioi le Ta'avale Ta'avale i se Fa'ata'ita'iga Fa'atusaample

E mafai ona e fa'agaoioia le fa'aputuga o fefa'ataua'iga mai le Diagnostics tab i le EMIF fa'atonu fa'atonu. Ina ia mafai ona fa'aogaina le afi afi fe'avea'i, fa'aoga Fa'aaoga afi afi afi Avalon 2.0 i luga o le Fa'ailoga Fa'ailoga.

Ata 6.

• E mafai ona e filifili e fa'amalo le fa'asologa o feoaiga fa'aletonu stagu po'o le fa'aoga fa'aogaina felauaiga stagu, ae e tatau ona i ai ia le itiiti ifo ma le tasi stage mafai. Mo fa'amatalaga i nei stags, fa'asino ile Fa'asologa o Ta'avale Ta'avale ma le Fa'asologa o Ta'avale Fa'atonu a le Fa'aoga i le Fa'amatalaga Fa'amatalaga Fafo Intel Agilex FPGA IP Taiala.
• Ole fa'ata'ita'iga ole umi ole su'ega TG2 e fa'aoga ile na'o le fa'asologa o feoaiga fa'aletonu. E mafai ona e filifilia se umi ole su'ega o le pupuu, feololo, po'o le le i'u.
• e mafai ona e filifilia se tasi o tau e lua mo le TG2 Configuration Interface Mode parameter:
  • JTAG: Fa'ataga le fa'aogaina o se GUI i le fa'amafanafanaga. Mo nisi fa'amatalaga, va'ai i le Feso'ota'iga Feso'ota'iga Fa'atupu Ta'avale i le Fa'asinomaga Fa'afofoga Intel Agilex FPGA IP.
  • auina atu i fafo: Fa'ataga le fa'aogaina o le fa'aoga masani RTL e pulea ai le faiga o feoaiga.

Fa'aaogaina o le Design Exampma le EMIF Debug Toolkit

A'o le'i tatalaina le EMIF Debug Toolkit, ia mautinoa ua e fa'atulagaina lau masini i se polokalame file lea ua mafai ai le EMIF Debug Toolkit. Ina ia faʻalauiloa le EMIF Debug Toolkit, mulimuli i laasaga nei:

1. I le polokalama Intel Quartus Prime, tatala le System Console i le filifilia o Meafaigaluega ➤ System Debugging Tools ➤ System Console.
2. [Fa'ase'e le la'asaga lenei pe afai ua uma ona tatala lau poloketi i le polokalama Intel Quartus Prime.] I totonu o le System Console, uta le SRAM object file (.sof) lea na e fa'apolokalameina ai le laupapa (e pei ona fa'amatalaina i mea e mana'omia muamua mo le fa'aaogaina o le EMIF Debug Toolkit, i le External Memory Interfaces Intel Agilex FPGA IP User Guide).
3. Filifili fa'ata'ita'iga e debug.
4. Filifili le EMIF Calibration Debug Toolkit mo le EMIF calibration debugging, e pei ona faamatalaina i le Fausiaina o se Design Example fa'atasi ma le Filifiliga Debug Option. I le isi itu, filifili EMIF TG Configuration Toolkit mo le faʻaogaina o afi afi, e pei ona faʻamatalaina i le Fausiaina o se Design Example faʻatasi ma le TG Configuration Option.
5. Kiliki Open Toolkit e tatala ai le autu view o le EMIF Debug Toolkit.
6. Afai e tele faʻataʻitaʻiga EMIF i le mamanu faʻatulagaina, filifili le koluma (ala i le JTAG matai) ma le ID faʻaoga manatua ole faʻataʻitaʻiga EMIF lea e faʻagaoioia ai le pusa meafaigaluega.
7. Kiliki Activate Interface e fa'ataga ai le pusa meafaigaluega e faitau le fa'asologa o feso'ota'iga ma le fa'avasegaina o tulaga.
8. E tatau ona e debug tasi le atina'e i le taimi; o le mea lea, ina ia faʻafesoʻotaʻi i se isi atinaʻe i le mamanu, e tatau ona e faʻagata muamua le atinaʻe o loʻo iai nei.

O mea nei o example tele o lipoti mai le EMIF Calibration Debug Toolkit ma le EMIF TG Configuration Toolkit:, i le faasologa.

Fa'aaliga: Mo fa'amatalaga i le fa'avasegaina o le fa'avasegaina, fa'asino ile Debugging ma le External Memory Interface Debug Toolkit, ile External Memory Interfaces Intel Agilex FPGA IP User Guide.

Fa'aaliga: Mo faʻamatalaga i luga o le faʻaogaina o afi afi, vaʻai i le Faʻaogaina o le Faʻaogaina o le Taʻavale Taʻavale, i le Faʻamatalaga Faʻamatalaga i fafo Intel Agilex FPGA IP User Guide.

Design Example Faʻamatalaga mo Faʻamatalaga Faʻamatalaga i fafo Intel Agilex FPGA IP

A e faʻavasegaina ma faʻatupu lau EMIF IP, e mafai ona e faʻamaonia o le faiga e fausia ai faʻamaumauga mo faʻataʻitaʻiga ma faʻasologa file seti, ma gaosia le file seti otometi. Afai e te filifilia le Simulation poʻo le Synthesis i lalo ole Example Lisiina Files i luga o le Example Designs tab, o le faiga e fatuina ai se faʻataʻitaʻiga atoatoa file seti poʻo se faʻasologa atoatoa file seti, e tusa ai ma lau filifiliga.

Fuafuaga Fa'atusa Fa'atasiample
O le fa'asologa fa'atusa example o loʻo i ai poloka tetele o loʻo faʻaalia i le ata o loʻo i lalo.

• O se afi afi, lea o se synthesizable Avalon®-MM example aveta'avale e fa'atinoina se fa'ata'ita'iga fa'atusa o le faitau ma tusi i se numera fa'avasegaina o tuatusi. E mataituina foi e le afi afi le faʻamatalaga faitau mai le manatua ina ia mautinoa e fetaui ma faʻamaumauga tusitusia ma faʻamaonia se toilalo i se isi itu.
• O se faʻataʻitaʻiga o le atinaʻe manatua, lea e aofia ai:
  • O se fa'atonuga manatua e fa'afetaui i le va o le Avalon-MM fa'aoga ma le fa'aoga AFI.
  • O le PHY, lea e avea o se fesoʻotaʻiga i le va o le masini manatua ma masini manatua fafo e faʻatino ai galuega faitau ma tusitusi.

Ata 7. Fuafuaga Fa'atusa Example

Fa'aaliga: Afai o se tasi pe sili atu o le PLL Fetufaaiga Faiga, DLL Fetufaaiga Faiga, po o le OCT Fa'asoa Fa'asologa Fa'amaufa'ailoga e fa'atulaga i so'o se tau e ese mai i le Leai Fa'asoa, o le fa'asologa fa'asologa fa'atasi.ampO le a iai ni fa'asologa o fefa'ataua'iga/fa'ailoga fa'amanatuga se lua. O fa'ata'ita'iga fa'atupu fe'avea'i/fa'amanatuga e lua e feso'ota'i na'o feso'ota'iga fa'asoa PLL/DLL/OCTe pei ona fa'amalamalamaina e le fa'asologa o le fa'asologa. O fa'ata'ita'iga fa'aola afi/fa'amanatuga fa'ata'ita'iga pe fa'apefea ona e faia so'otaga fa'apea i au lava mamanu.

Fuafuaga Fa'ata'ita'iga Example
Le fa'ata'ita'iga mamanu example o loʻo i ai poloka tetele o loʻo faʻaalia i le ata o loʻo i lalo.

• O se fa'ata'ita'iga o le fa'asologa o le fa'asologa eample. E pei ona faamatalaina i le vaega muamua, o le synthesis design exampLe o loʻo i ai se afi afi afi, vaega faʻavasegaina, ma se faʻataʻitaʻiga o le atinaʻe manatua. O poloka nei e le mafai ona fa'aogaina fa'ata'ita'iga fa'ata'ita'iga pe a talafeagai mo fa'ata'ita'iga vave.
• O se fa'ata'ita'iga fa'amanatu, lea e fai ma fa'ata'ita'iga lautele e fa'apipi'i i fa'amatalaga fa'asologa o manatua. O le tele o taimi, e tu'uina atu e le au fa'atau manatua fa'ata'ita'iga fa'ata'ita'iga mo a latou vaega fa'amanatu fa'apitoa e mafai ona e siiina mai ia latou webnofoaga.
• O se su'esu'ega tulaga, lea e mata'ituina ai fa'ailoga tulaga mai le fa'aoga mafaufauga i fafo IP ma le afi afi, e fa'ailo ai se tulaga atoa o le pasi po'o le le manuia.

Ata 10. Fa'atusa Fa'ata'ita'iga Example

Example Designs Interface Tab
O le fa'atonu fa'asologa e aofia ai le Example Designs tab lea e mafai ai e oe ona faʻavasegaina ma faʻatupu lau mamanu muamuaamples.

Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives

IP versions e tutusa ma le Intel Quartus Prime Design Suite software versions up to v19.1. Mai le Intel Quartus Prime Design Suite software version 19.2 poʻo mulimuli ane, o IPs e iai se polokalame faʻaliliuga IP fou. Afai e le o lisiina se fa'asologa autu o le IP, e fa'aoga le ta'iala mo le fa'asologa muamua o le IP.

IP Core Version	Fa'aoga Taiala
2.4.0	Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives
2.3.0	Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives
2.3.0	Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives
2.1.0	Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives
19.3	Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide Archives

Fa'amatalaga Toe Iloiloga o Fa'amaumauga mo Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2021.06.21	21.2	2.4.2	I le Design Example Amata vave mataupu: • Faaopoopoina se faamatalaga i le Tuufaatasia ma Polokalama le Intel Agilex EMIF Design Example autu. • Suia le igoa o le Fausiaina o se Design Example fa'atasi ma le Filifiliga Debug Option autu. • Faaopoopo le Fausiaina o se Design Example faʻatasi ma le TG Configuration Option ma Fa'aagaoioi le Ta'avale Ta'avale i se Fa'ata'ita'iga Fa'atusaample mataupu. • Suia Laasaga 2, 3, ma le 4, faafou ni fuainumera, ma faaopoopo se faamatalaga, i le Fa'aaogaina o le Design Exampma le EMIF Debug Toolkit autu.
2021.03.29	21.1	2.4.0	I le Design Example Amata vave mataupu: • Faaopoopoina se faamatalaga i le Fausiaina le Synthesizable EMIF Design Example ma Fausia le EMIF Design Example mo Simulation mataupu. • Fa'afouina le File Ata fa'atulagaina i le Fausia le EMIF Design Example mo Simulation autu.
2020.12.14	20.4	2.3.0	I le Design Example Amata vave mataupu, faia suiga nei: • Fa'afouina le Fausiaina le Synthesizable EMIF Design Example autu e aofia ai le tele-EMIF mamanu. • Fa'afouina le ata mo le Laasaga 3, i le Fausia le EMIF Design Example mo Simulation autu.
2020.10.05	20.3	2.3.0	I le Design Example Taiala Amata vave mataupu, faia suiga nei: • I totonu Fausia se Poloketi EMIF, faafou le ata i le Laasaga 6. • I totonu Fausiaina le Synthesizable EMIF Design Example, faafou le ata i le Laasaga 3. • I totonu Fausia le EMIF Design Example mo Simulation, faafou le ata i le Laasaga 3. • I totonu Fa'ata'ita'iga Fa'asaga i Meafaigaluega Fa'atinoga, fa'asa'o se tama'i sese i le laulau lona lua. • I totonu Fa'aaogaina o le Design Exampma le EMIF Debug Toolkit, suia Laasaga 6, faaopoopo Laasaga 7 ma le 8.
faaauau…

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	IP Version	Suiga
2020.04.13	20.1	2.1.0	• I le E uiga i mataupu, suia le laulau i le Fa'asalalau Fa'amatalaga autu. • I le Design Example Taiala Amata vave mataupu: — Suia Laasaga 7 ma le ata fesootai, i le Fausiaina le Synthesizable EMIF Design Example autu. — Suia le Fausiaina o le Design Example ma le Filifiliga Debug autu. — Suia le Fa'aaogaina o le Design Exampma le EMIF Debug Toolkit autu.
2019.12.16	19.4	2.0.0	• I le Design Example Amata vave mataupu: — Faʻafouina le faʻataʻitaʻiga i le Laasaga 6 o le Fausia se Poloketi EMIF autu. — Faʻafouina le faʻataʻitaʻiga i le Laasaga 4 o le Fausiaina le Synthesizable EMIF Design Example autu. — Faʻafouina le faʻataʻitaʻiga i le Laasaga 4 o le Fausia le EMIF Design Example mo Simulation autu. — Suia Laasaga 5 i le Fausia le EMIF Design Example mo Simulation autu. — Suia le Fa'atonuga Fa'amau ma Faletupe tuaoi vaega o le Fa'amauina pine mo Intel Agilex EMIF IP autu.
2019.10.18	19.3		• I le Fausia se Poloketi EMIF autu, faʻafouina le ata i le mata 6. • I le Fausiaina ma Fa'atonu le EMIF IP autu, faafou le ata i le Laasaga 1. • I le laulau i le Intel Agilex EMIF Parameter Editor Taiala autu, suia le faamatalaga mo le Komiti Fa'atonu laupepa. • I le Fausiaina le Synthesizable EMIF Design Example ma Fausia le EMIF Design Example mo Simulation autu, faafou le ata i le Laasaga 3 o autu taitasi. • I le Fausia le EMIF Design Example mo Simulation autu, faafou le Fausia Fa'ata'ita'iga Fuafuaga Example File Fauga fa'atusa ma suia le fa'amatalaga e mulimuli i le ata. • I le Fausiaina le Synthesizable EMIF Design Example autu, faaopoopo se laasaga ma se ata mo le tele o fesoʻotaʻiga.
2019.07.31	19.2	1.2.0	• Faaopoopo E uiga i Fa'amatalaga Fa'amatalaga i fafo Intel Agilex FPGA IP mataupu ma Fa'amatalaga Fa'asalalau. • Fa'afouina aso ma numera o fa'amatalaga. • Laititi faaleleia i le Fuafuaga Fa'atusa Fa'atasiample ata i le Fuafuaga Fa'atusa Fa'atasiample autu.
2019.04.02	19.1		• Fa'asalalauga muamua.

Fa'amatalaga Toe Iloiloga o Fa'amaumauga mo Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example User Guide

Pepa / Punaoa

intel UG-20219 Fa'asinomaga Fafo i fafo Intel Agilex FPGA IP Design Example [pdf] Taiala mo Tagata Fa'aoga UG-20219 Fa'asinoala i fafo Intel Agilex FPGA IP Design Example, UG-20219, Feso'ota'iga Manatu i fafo Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

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