intel UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide

User Guide for intel models including: UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example, UG-20219, External Memory Interfaces Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

External Memory Interfaces Intel Agilex™ FPGA IP Design Example User Guide

Updated for Intel Quartus Prime Design Suite: 21.2, IP Version: 2.4.2. The External Memory Interfaces Intel Agilex EMIF IP Design Example User Guide provides quick start information for using the design example.

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External Memory Interfaces Intel Agilex™ FPGA IP Design ...

21 giu 2021 — The External Memory Interfaces Intel Agilex EMIF IP Design Example User Guide provides quick start information for using the design example.

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2.9. Generating a Design Example with the Calibration Debug Option

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External Memory Interfaces Intel® AgilexTM FPGA IP Design Example User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.2 IP Version: 2.4.2

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UG-20219

ID: 683162 Version: 2021.06.21

Contents
Contents
1. About the External Memory Interfaces Intel® AgilexTM FPGA IP.......................................3 1.1. Release Information...............................................................................................3
2. Design Example Quick Start Guide for External Memory Interfaces Intel AgilexTM FPGA IP .................................................................................................................... 4 2.1. Creating an EMIF Project........................................................................................ 4 2.2. Generating and Configuring the EMIF IP....................................................................7 2.2.1. Intel Agilex EMIF Parameter Editor Guidelines................................................7 2.3. Generating the Synthesizable EMIF Design Example................................................... 8 2.4. Generating the EMIF Design Example for Simulation................................................. 11 2.5. Simulation Versus Hardware Implementation........................................................... 13 2.6. Simulating External Memory Interface IP With ModelSim........................................... 14 2.7. Pin Placement for Intel Agilex EMIF IP.....................................................................14 2.8. Compiling and Programming the Intel Agilex EMIF Design Example.............................16 2.9. Generating a Design Example with the Calibration Debug Option................................ 16 2.10. Generating a Design Example with the TG Configuration Option................................17 2.10.1. Enabling the Traffic Generator in a Design Example.....................................17 2.11. Using the Design Example with the EMIF Debug Toolkit........................................... 18
3. Design Example Description for External Memory Interfaces Intel Agilex FPGA IP ...... 23 3.1. Synthesis Design Example.................................................................................... 23 3.2. Simulation Design Example................................................................................... 24 3.3. Example Designs Interface Tab.............................................................................. 24
4. External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives.................................................................................................................. 25
5. Document Revision History for External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide..................................................................................... 26

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1. About the External Memory Interfaces Intel® AgilexTM FPGA IP

1.1. Release Information

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
· X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
· Y indicates the IP includes new features. Regenerate your IP to include these new features.
· Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

IP Version Intel Quartus Prime Release Date

Item

2.4.2 21.2 2021.06.21

Description

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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2. Design Example Quick Start Guide for External Memory Interfaces Intel AgilexTM FPGA IP

Figure 1.

An automated design example flow is available for Intel AgilexTM external memory interfaces.
The Generate Example Designs button on the Example Designs tab allows you to specify and generate the synthesis and simulation design example file sets which you can use to validate your EMIF IP.
You can generate a design example that matches the Intel FPGA development kit, or for any EMIF IP that you generate. You can use the design example to assist your evaluation, or as a starting point for your own system.
General Design Example Workflows

Compilation (Simulator)

Functional Simulation

Intel Quartus Prime Project
Creation

EMIF IP Configuration

Design Example Generation

Compilation (Quartus Prime)

Timing Analysis (Quartus Prime)

Hardware Testing

2.1. Creating an EMIF Project
For the Intel Quartus Prime software version 17.1 and later, you must create an Intel Quartus Prime project before generating the EMIF IP and design example.
1. Launch the Intel Quartus Prime software and select File New Project Wizard. Click Next.

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2. Specify a directory (<user project directory>), a name for the Intel Quartus Prime project (<user project name>), and a top-level design entity name (<user toplevel instance name>) that you want to create. Click Next.

3. Verify that Empty Project is selected. Click Next two times.

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4. Under Family, select Intel Agilex. 5. Under Name filter, type the device part number. 6. Under Available devices, select the appropriate device.

7. Click Finish.
External Memory Interfaces Intel® AgilexTM FPGA IP Design Example User Guide 6

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2.2. Generating and Configuring the EMIF IP
The following steps illustrate how to generate and configure the EMIF IP. This walkthrough creates a DDR4 interface, but the steps are similar for other protocols. (These steps follow the IP Catalog (standalone) flow; if you choose to use the Platform Designer (system) flow instead, the steps are similar.) 1. In the IP Catalog window, select External Memory Interfaces Intel Agilex
FPGA IP. (If the IP Catalog window is not visible, select View IP Catalog.)
2. In the IP Parameter Editor, provide an entity name for the EMIF IP (the name that you provide here becomes the file name for the IP) and specify a directory. Click Create.

3. The parameter editor has multiple tabs where you must configure parameters to reflect your EMIF implementation.

2.2.1. Intel Agilex EMIF Parameter Editor Guidelines
This topic provides high-level guidance for parameterizing the tabs in the Intel Agilex EMIF IP parameter editor.

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Table 1.

EMIF Parameter Editor Guidelines

Parameter Editor Tab

Guidelines

General

Ensure that the following parameters are entered correctly: · The speed grade for the device. · The memory clock frequency. · The PLL reference clock frequency.

Memory

· Refer to the data sheet for your memory device to enter the parameters on the Memory tab.
· You should also enter a specific location for the ALERT# pin. (Applies to DDR4 memory protocol only.)

Mem I/O

· For initial project investigations, you may use the default settings on the Mem I/O tab.
· For advanced design validation, you should perform board simulation to derive optimal termination settings.

FPGA I/O

· For initial project investigations, you may use the default settings on the FPGA I/O tab.
· For advanced design validation, you should perform board simulation with associated IBIS models to select appropriate I/O standards.

Mem Timing Controller

· For initial project investigations, you may use the default settings on the Mem Timing tab.
· For advanced design validation, you should enter parameters according to your memory device's data sheet.
Set the controller parameters according to the desired configuration and behavior for your memory controller.

Diagnostics

You can use the parameters on the Diagnostics tab to assist in testing and debugging your memory interface.

Example Designs

The Example Designs tab lets you generate design examples for synthesis and for simulation. The generated design example is a complete EMIF system consisting of the EMIF IP and a driver that generates random traffic to validate the memory interface.

For detailed information on individual parameters, refer to the appropriate chapter for your memory protocol in the External Memory Interfaces Intel Agilex FPGA IP User Guide.

2.3. Generating the Synthesizable EMIF Design Example
For the Intel Agilex development kit, it is sufficient to leave most of the Intel Agilex EMIF IP settings at their default values. To generate the synthesizable design example, follow these steps:
1. On the Example Designs tab, ensure that the Synthesis box is checked.

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Figure 2.

· If you are implementing single interface example design, configure the EMIF IP and click File Save to save the current setting into the user IP variation file (<user instance name>.ip).

Figure 3.

· If you are implementing an example design with multiple interfaces, specify Number of IPs to the desired number of interfaces. You can see the total number of EMIF ID same as the selected Number of IPs. Follow these steps to configure each interface:
a. Select the Cal-IP to specify the connection of the interface to the Calibration IP.
b. Configure the EMIF IP accordingly in all the Parameter Editor Tab.
c. Return to Example Design tab and click Capture on the desired EMIF ID.
d. Repeat step a to c for all EMIF ID.
e. You may click the Clear button to remove the captured parameters and repeat step a to c to make changes to the EMIF IP.
f. Click File Save to save the current setting into the user IP variation file (<user instance name>.ip).

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2. Click Generate Example Design in the upper-right corner of the window.
3. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates the following fileset under a qii directory.

Figure 4.

4. Click File Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
5. To open the example design, click File Open Project, and navigate to the <project_directory>/<design_example_name>/qii/ed_synth.qpf and click Open.
Note: For information on compiling and programming the design example, refer to Compiling and Programming the Intel Agilex EMIF Design Example.
Generated Synthesizable Design Example File Structure

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Note: Note:

For information on constructing a system with two or more external memory interfaces, refer to Creating a Design Example with Multiple EMIF Interfaces, in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
For information on debugging multiple interfaces, refer to Enabling the EMIF Toolkit in an Existing Design, in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
If you don't select the Simulation or Synthesis checkbox, the destination directory contains only Platform Designer design files, which are not compilable by the Intel Quartus Prime software directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets.
· To create a compilable project, you must run the
quartus_sh -t make_qii_design.tcl script in the destination directory.
· To create a simulation project, you must run the
quartus_sh -t make_sim_design.tcl script in the destination directory.
If you have generated a design example and then make changes to it in the parameter editor, you must regenerate the design example to see your changes implemented. The newly generated design example does not overwrite the existing design example files.

2.4. Generating the EMIF Design Example for Simulation
For the Intel Agilex development kit, it is sufficient to leave most of the Intel Agilex EMIF IP settings at their default values. To generate the design example for simulation, follow these steps:

1. On the Example Designs tab, ensure that the Simulation box is checked. Also choose the required Simulation HDL format, either Verilog or VHDL.
2. Configure the EMIF IP and click File Save to save the current setting into the user IP variation file (<user instance name>.ip).
3. Click Generate Example Design in the upper-right corner of the window.

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4. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates multiple file sets for various supported simulators, under a sim/ed_sim directory.

Figure 5.

5. Click File Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
Generated Simulation Design Example File Structure

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Note: Note:

Note: The External Memory Interfaces Intel Agilex FPGA IP currently supports only the VCS, ModelSim/QuestaSim, and Xcelium simulators. Additional simulator support is planned in future releases.
If you don't select the Simulation or Synthesis checkbox, the destination directory contains only Platform Designer design files, which are not compilable by the Intel Quartus Prime software directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets.
· To create a compilable project, you must run the
quartus_sh -t make_qii_design.tcl
script in the destination directory.
· To create a simulation project, you must run the
quartus_sh -t make_sim_design.tcl
script in the destination directory.
If you have generated a design example and then make changes to it in the parameter editor, you must regenerate the design example to see your changes implemented. The newly generated design example does not overwrite the existing design example files.

2.5. Simulation Versus Hardware Implementation

For external memory interface simulation, you can select either skip calibration or full calibration on the Diagnostics tab during IP generation.

EMIF Simulation Models

This table compares the characteristics of the skip calibration and full calibration models.

Table 2.

EMIF Simulation Models: Skip Calibration versus Full Calibration

Skip Calibration

Full Calibration

System-level simulation focusing on user logic.

Memory interface simulation focusing on calibration.

Details of calibration are not captured.

Captures all stages of calibration.

Has ability to store and retrieve data.

Includes leveling, per-bit deskew, etc.

Represents accurate efficiency.

Does not consider board skew.

RTL Simulation Versus Hardware Implementation
This table highlights key differences between EMIF simulation and hardware implementation.

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Table 3.

EMIF RTL Simulation Versus Hardware Implementation

RTL Simulation
Nios® initialization and calibration code execute in parallel.
Interfaces assert cal_done signal simultaneously in simulation.

Hardware Implementation
Nios initialization and calibration code execute sequentially.
Fitter operations determine the order of calibration, and interfaces do not assert cal_done simultaneously.

You should run RTL simulations based on traffic patterns for your design's application. Note that RTL simulation does not model PCB trace delays which may cause a discrepancy in latency between RTL simulation and hardware implementation.

2.6. Simulating External Memory Interface IP With ModelSim
This procedure shows how to simulate the EMIF design example.

1. Launch the Mentor Graphics* ModelSim software and select File Change Directory. Navigate to the sim/ed_sim/mentor directory within the generated design example folder.
2. Verify that the Transcript window is displayed at the bottom of the screen. If the Transcript window is not visible, display it by clicking View Transcript.
3. In the Transcript window, run source msim_setup.tcl.
4. After source msim_setup.tcl finishes running, run ld_debug in the Transcript window.
5. After ld_debug finishes running, verify that the Objects window is displayed. If the Objects window is not visible, display it by clicking View Objects.
6. In the Objects window, select the signals that you want to simulate by rightclicking and selecting Add Wave.
7. After you finish selecting the signals for simulation, execute run -all in the Transcript window. The simulation runs until it is completed.
8. If the simulation is not visible, click View Wave.

2.7. Pin Placement for Intel Agilex EMIF IP
This topic provides guidelines for pin placement.
Overview Intel Agilex FPGAs have the following structure: · Each device contains up to 8 I/O banks. · Each I/O bank contains 2 sub-I/O banks. · Each sub-I/O bank contains 4 lanes. · Each lane contains 12 general-purpose I/O (GPIO) pins.
General Pin Guidelines The following are general pin guidelines.

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Note:

For more detailed pin information, refer to the Intel Agilex FPGA EMIF IP Pin and Resource Planning section in the protocol-specific chapter for your external memory protocol, in the External Memory Interfaces Intel Agilex FPGA IP User Guide.

· Ensure that the pins for a given external memory interface reside within the same I/O row.
· Interfaces that span multiple banks must meet the following requirements:
-- The banks must be adjacent to one another. For information on adjacent banks, refer to the EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
· All address and command and associated pins must reside within a single subbank.
· Address and command and data pins can share a sub-bank under the following conditions:
-- Address and command and data pins cannot share an I/O lane.
-- Only an unused I/O lane in the address and command bank can contain data pins.

Table 4.

General Pin Constraints

Signal Type

Constraint

Data Strobe

All signals belonging to a DQ group must reside in the same I/O lane.

Data Address and Command

Related DQ pins must reside in the same I/O lane. For protocols that do not support bidirectional data lines, read signals should be grouped separately from write signals.
Address and Command pins must reside in predefined locations within an I/O sub-bank.

Adjacent Banks
For banks to be considered adjacent, they must reside in the same I/O row. To determine if banks are adjacent, refer to the EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel Agilex FPGA IP User Guide.

Pin Assignments
To determine locations for all EMIF I/O pins you should refer to the pin table for your device. When referring to the pin table, the bank numbers, I/O bank indices, and pin names are provided. You can find the pin indices for address and command pins in the Intel Agilex EMIF Pin Table at the following location: https://www.intel.com/ content/www/us/en/programmable/support/literature/lit-dp.html.
You can perform pin assignments in a variety of ways. The recommended approach is to manually constrain some interface signals and let the Intel Quartus Prime Fitter handle the rest. This method consists of consulting the pin tables to find legal

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positions for some of the interface pins and assigning them through the .qsf file that is generated with the EMIF design example. For this method of I/O placement, you must constrain the following signals: · CK0 · One DQS pin per group · PLL reference clock · RZQ
Based on the above constraints, the Intel Quartus Prime Fitter rotates pins within each lane as necessary.
2.8. Compiling and Programming the Intel Agilex EMIF Design Example
After you have made the necessary pin assignments in the .qsf file, you can compile the design example in the Intel Quartus Prime software.
1. Navigate to the Intel Quartus Prime folder containing the design example directory.
2. Open the Intel Quartus Prime project file, (.qpf). 3. To begin compilation, click Processing Start Compilation. The successful
completion of compilation generates a .sof file, which enables the design to run on hardware. 4. To program your device with the compiled design, open the programmer by clicking Tools Programmer. 5. In the programmer, click Auto Detect to detect supported devices. 6. Select the Intel Agilex device and then select Change File. 7. Navigate to the generated ed_synth.sof file and select Open. 8. Click Start to begin programming the Intel Agilex device. When the device is successfully programmed, the progress bar at the top-right of the window should indicate 100% (Successful).
Refer to Using the Design Example with the EMIF Debug Toolkit for guidance in debugging your external memory interface.
2.9. Generating a Design Example with the Calibration Debug Option
You can use the External Memory Interface (EMIF) Debug Toolkit to assist in debugging your external memory interface. The toolkit provides access to data collected by the Nios II sequencer during memory calibration, and analysis tools to evaluate the stability of the calibrated interface.
The available task and analysis capabilities include the following:

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· Requesting calibration of the memory interface. · Reading probe data or writing source data to the In-System Sources and Probes
(ISSPs) instances in the design. · Viewing the delay setting on any pin in the selected interface and changing it if
necessary. · Rerunning the traffic generator in the design example. · Running driver margining on the interface. · Calibrating or changing termination settings. 1. Navigate to the Diagnostics tab of the EMIF parameter editor. 2. Click Intel Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Add
EMIF Debug Interface. 3. If you are planning to use Driver Margining or ISSPs, ensure that the Enable In-
System Sources and Probes option is enabled. 4. After you have completed parameterizing your interface, click Generate Example
Design.
The resulting generated design example has the debug toolkit enabled and all the necessary components connected as required for a single interface.
2.10. Generating a Design Example with the TG Configuration Option
The generated EMIF design example includes a traffic generator block (TG). By default, the design example uses a simple TG block (altera_tg_avl) which can only be reset in order to relaunch a hard-coded traffic pattern. If necessary, you may choose to enable a configurable traffic generator (TG2) instead.
In the configurable traffic generator (TG2) (altera_tg_avl_2), you can configure the traffic pattern in real time through control registers--meaning that you do not have to recompile the design to change or relaunch the traffic pattern. This traffic generator provides fine control over the type of traffic that it sends on the EMIF control interface. Additionally, it provides status registers that contain detailed failure information.
2.10.1. Enabling the Traffic Generator in a Design Example
You can enable the configurable traffic generator from the Diagnostics tab in the EMIF parameter editor.
To enable the configurable traffic generator, turn on Use configurable Avalon traffic generator 2.0 on the Diagnostics tab.
Figure 6.

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· You may choose to disable the default traffic pattern stage or the userconfigured traffic stage, but you must have at least one stage enabled. For information on these stages, refer to Default Traffic Pattern and User-configured Traffic Pattern in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
· The TG2 test duration parameter applies only to the default traffic pattern. You may choose a test duration of short, medium, or infinite.
· You may choose either of two values for the TG2 Configuration Interface Mode parameter:
-- JTAG: Allows use of a GUI in the system console. For more information, refer to Traffic Generator Configuration Interface in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
-- Export: Allows use of custom RTL logic to control the traffic pattern.
2.11. Using the Design Example with the EMIF Debug Toolkit
Before launching the EMIF Debug Toolkit, ensure that you have configured your device with a programming file that has the EMIF Debug Toolkit enabled. To launch the EMIF Debug Toolkit, follow these steps:
1. In the Intel Quartus Prime software, open the System Console by selecting Tools System Debugging Tools System Console.
2. [Skip this step if your project is already open in the Intel Quartus Prime software.] In the System Console, load the SRAM object file (.sof) with which you programmed the board (as described in Prerequisites for Using the EMIF Debug Toolkit, in the External Memory Interfaces Intel Agilex FPGA IP User Guide).
3. Select instances to debug.
4. Select EMIF Calibration Debug Toolkit for EMIF calibration debugging, as described in Generating a Design Example with the Calibration Debug Option. Alternatively, select EMIF TG Configuration Toolkit for traffic generator debugging, as described in Generating a Design Example with the TG Configuration Option.
5. Click Open Toolkit to open the main view of the EMIF Debug Toolkit.

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6. If there are multiple EMIF instances in the programmed design, select the column (path to JTAG master) and memory interface ID of the EMIF instance for which to activate the toolkit.
7. Click Activate Interface to allow the toolkit to read the interface parameters and calibration status.

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8. You must debug one interface at a time; therefore, to connect to another interface in the design, you must first deactivate the current interface.
The following are examples of reports from the EMIF Calibration Debug Toolkit and the EMIF TG Configuration Toolkit:, respectively

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Note: Note:

For details on calibration debugging, refer to Debugging with the External Memory Interface Debug Toolkit, in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
For details on traffic generator debugging, refer to Traffic Generator Configuration User Interface, in the External Memory Interfaces Intel Agilex FPGA IP User Guide.

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3. Design Example Description for External Memory Interfaces Intel Agilex FPGA IP
When you parameterize and generate your EMIF IP, you can specify that the system create directories for simulation and synthesis file sets, and generate the file sets automatically. If you select Simulation or Synthesis under Example Design Files on the Example Designs tab, the system creates a complete simulation file set or a complete synthesis file set, in accordance with your selection.
3.1. Synthesis Design Example
The synthesis design example contains the major blocks shown in the figure below. · A traffic generator, which is a synthesizable Avalon®-MM example driver that
implements a pseudo-random pattern of reads and writes to a parameterized number of addresses. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise. · An instance of the memory interface, which includes: -- A memory controller that moderates between the Avalon-MM interface and the
AFI interface. -- The PHY, which serves as an interface between the memory controller and
external memory devices to perform read and write operations. Figure 7. Synthesis Design Example

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Note:

If one or more of the PLL Sharing Mode, DLL Sharing Mode, or OCT Sharing Mode parameters are set to any value other than No Sharing, the synthesis design example will contain two traffic generator/memory interface instances. The two traffic generator/memory interface instances are related only by shared PLL/DLL/OCT connections as defined by the parameter settings. The traffic generator/memory interface instances demonstrate how you can make such connections in your own designs.

3.2. Simulation Design Example
The simulation design example contains the major blocks shown in the following figure.
· An instance of the synthesis design example. As described in the previous section, the synthesis design example contains a traffic generator, calibration component, and an instance of the memory interface. These blocks default to abstract simulation models where appropriate for rapid simulation.
· A memory model, which acts as a generic model that adheres to the memory protocol specifications. Frequently, memory vendors provide simulation models for their specific memory components that you can download from their websites.
· A status checker, which monitors the status signals from the external memory interface IP and the traffic generator, to signal an overall pass or fail condition.
Figure 10. Simulation Design Example

3.3. Example Designs Interface Tab
The parameter editor includes an Example Designs tab which allows you to parameterize and generate your design examples.

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4. External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version 2.4.0 2.3.0 2.3.0 2.1.0 19.3

User Guide External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide Archives

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5. Document Revision History for External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide

Document Version 2021.06.21

Intel Quartus Prime Version
21.2

IP Version 2.4.2

2021.03.29

21.1

2.4.0

2020.12.14

20.4

2.3.0

2020.10.05

20.3

2.3.0

Changes
In the Design Example Quick Start chapter: · Added a note to the Compiling and Programming
the Intel Agilex EMIF Design Example topic. · Modified the title of the Generating a Design
Example with the Calibration Debug Option topic. · Added the Generating a Design Example with the TG Configuration Option and Enabling the Traffic Generator in a Design Example topics. · Modified steps 2, 3, and 4, updated several figures, and added a note, in the Using the Design Example with the EMIF Debug Toolkit topic.
In the Design Example Quick Start chapter: · Added a note to the Generating the
Synthesizable EMIF Design Example and Generating the EMIF Design Example for Simulation topics. · Updated the File Structure diagram in the Generating the EMIF Design Example for Simulation topic.
In the Design Example Quick Start chapter, made the following changes: · Updated the Generating the Synthesizable EMIF
Design Example topic to include multi-EMIF designs. · Updated the figure for step 3, in the Generating the EMIF Design Example for Simulation topic.
In the Design Example Quick Start Guide chapter, made the following changes: · In Creating an EMIF Project, updated the image
in step 6. · In Generating the Synthesizable EMIF Design
Example, updated the figure in step 3. · In Generating the EMIF Design Example for
Simulation, updated the figure in step 3. · In Simulation Versus Hardware Implementation,
corrected a minor typo in the second table. · In Using the Design Example with the EMIF
Debug Toolkit, modified step 6, added steps 7 and 8.
continued...

ISO 9001:2015 Registered

5. Document Revision History for External Memory Interfaces Intel Agilex FPGA IP Design Example User Guide
683162 | 2021.06.21

Document Version 2020.04.13

Intel Quartus Prime Version
20.1

IP Version 2.1.0

2019.12.16

19.4

2.0.0

2019.10.18

19.3

2019.07.31

19.2

1.2.0

2019.04.02

19.1

Changes
· In the About chapter, modified the table in the Release Information topic.
· In the Design Example Quick Start Guide chapter: -- Modified step 7 and the associated image, in the Generating the Synthesizable EMIF Design Example topic. -- Modified the Generating the Design Example with the Debug Option topic. -- Modified the Using the Design Example with the EMIF Debug Toolkit topic.
· In the Design Example Quick Start chapter: -- Updated the illustration in step 6 of the Creating an EMIF Project topic. -- Updated the illustration in step 4 of the Generating the Synthesizable EMIF Design Example topic. -- Updated the illustration in step 4 of the Generating the EMIF Design Example for Simulation topic. -- Modified step 5 in the Generating the EMIF Design Example for Simulation topic. -- Modified the General Pin Guidelines and Adjacent Banks sections of the Pin Placement for Intel Agilex EMIF IP topic.
· In the Creating an EMIF Project topic, updated the image with point 6.
· In the Generating and Configuring the EMIF IP topic, updated the figure with step 1.
· In the table in the Intel Agilex EMIF Parameter Editor Guidelines topic, changed the description for the Board tab.
· In the Generating the Synthesizable EMIF Design Example and Generating the EMIF Design Example for Simulation topics, updated the image in step 3 of each topic.
· In the Generating the EMIF Design Example for Simulation topic, updated the Generated Simulation Design Example File Structure figure and modified the note following the figure.
· In the Generating the Synthesizable EMIF Design Example topic, added a step and a figure for multiple interfaces.
· Added About the External Memory Interfaces Intel Agilex FPGA IP chapter and Release Information.
· Updated dates and version numbers. · Minor enhancement to the Synthesis Design
Example figure in the Synthesis Design Example topic.
· Initial release.

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