UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example

Za External Memory Interfaces Intel® Agilex™ FPGA IP

Kutulutsa Zambiri

Mitundu ya IP ndi yofanana ndi mitundu ya Intel® Quartus® Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP. Nambala ya IP versioning scheme (XYZ) imasintha kuchoka pa pulogalamu ina kupita ku ina. Kusintha kwa:

• X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu yanu ya Intel Quartus Prime, muyenera kukonzanso IP.
• Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
• Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.
  

  Kanthu	Kufotokozera
  Mtundu wa IP	2.4.2
  Intel Quartus Prime	21.2
  Tsiku lotulutsa	2021.06.21

Design Examplembani Upangiri Woyambira Wachangu wa Ma Memory Akunja a Intel Agilex™ FPGA IP

Kapangidwe kongopanga kaleample flow ikupezeka kwa Intel Agilex ™ kunja kukumbukira mawonekedwe. The Generate Example Designs batani pa Example Designs tabu imakupatsani mwayi wofotokozera ndikupanga kaphatikizidwe ndi kamangidwe kayeseleledwe kakaleample file seti zomwe mungagwiritse ntchito kutsimikizira EMIF IP yanu. Mutha kupanga ex designample zomwe zimagwirizana ndi zida zachitukuko za Intel FPGA, kapena EMIF IP iliyonse yomwe mumapanga. Mutha kugwiritsa ntchito ex designample kukuthandizani kuwunika kwanu, kapena ngati poyambira pa dongosolo lanu.

General Design Exampndi Workflows

Kupanga Pulojekiti ya EMIF

Kwa iye Intel Quartus Prime software version 17.1 ndipo kenako, muyenera kupanga Intel Quartus Prime projekiti musanapange EMIF IP ndi kapangidwe kakale.ample.

1. Tsegulani pulogalamu ya Intel Quartus Prime ndikusankha File ➤ Project Wizard Watsopano. Dinani Kenako. Design Examplembani Upangiri Woyambira Wachangu wa Ma Memory Akunja a Intel Agilex™ FPGA IP
2. Tchulani chikwatu ( ), dzina la polojekiti ya Intel Quartus Prime ( ), ndi dzina lachipangidwe chapamwamba kwambiri ( ) zomwe mukufuna kupanga. Dinani Kenako.
3. Onetsetsani kuti Empty Project yasankhidwa. Dinani Next nthawi ziwiri.
4. Pansi pa Banja, sankhani Intel Agilex.
5. Pansi pa Name filter, lembani gawo la chipangizocho.
6. Pazida Zomwe Zilipo, sankhani chipangizo choyenera.
7. Dinani Malizani.

Kupanga ndi Kukonza EMIF IP

Njira zotsatirazi zikuwonetsa momwe mungapangire ndikusintha EMIF IP. Kuyenda uku kumapanga mawonekedwe a DDR4, koma masitepe ndi ofanana ndi ma protocol ena. (Masitepewa amatsata mayendedwe a IP Catalog (standalone); ngati mungasankhe kugwiritsa ntchito Platform Designer (system) kuyenda m'malo mwake, masitepewo ndi ofanana.)

1. Pazenera la IP Catalog, sankhani External Memory Interfaces Intel Agilex FPGA IP. (Ngati zenera la IP Catalog silikuwoneka, sankhani View ➤ Khatalogi ya IP.)
2. Mu IP Parameter Editor, perekani dzina la bungwe la EMIF IP (dzina lomwe mumapereka apa limakhala file dzina la IP) ndipo tchulani chikwatu. Dinani Pangani.
3. Mkonzi wa parameter ali ndi ma tabo angapo pomwe muyenera kusintha magawo kuti awonetse EMIF yanu.

Malangizo a Intel Agilex EMIF Parameter Editor
Mutuwu umapereka chitsogozo chapamwamba pakuyika ma tabo mu Intel Agilex EMIF IP parameter editor.

Table 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Malangizo
General	Onetsetsani kuti magawo otsatirawa alowetsedwa bwino: • Kuthamanga kwa chipangizocho. • Kuchuluka kwa wotchi yokumbukira. • Mafupipafupi a wotchi ya PLL.
Memory	• Onani pepala la data la chipangizo chanu chokumbukira kuti mulowetse magawo pa Memory tabu. • Muyeneranso kuyika malo enieni a pini ya ALERT#. (Imagwira pa DDR4 memory protocol yokha.)
Mem I/O	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa Mem I/O tabu. • Kuti mutsimikizire mamangidwe apamwamba, muyenera kupanga kayeseleledwe ka bolodi kuti mupeze makonda abwino kwambiri othetsa.
FPGA I/O	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa FPGA I/O tabu. • Kuti mutsimikizire mapangidwe apamwamba, muyenera kuchita zofananira ndi ma IBIS kuti musankhe miyezo yoyenera ya I/O.
Mem Timing	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa Mem Timing tabu. • Kuti mutsimikizire mapangidwe apamwamba, muyenera kuyika magawo molingana ndi pepala la data lachipangizo chanu.
Wolamulira	Khazikitsani magawo owongolera molingana ndi kasinthidwe komwe mukufuna ndi machitidwe a wowongolera kukumbukira kwanu.
Diagnostics	Mukhoza kugwiritsa ntchito parameters pa Diagnostics tabu kuti ikuthandizireni kuyesa ndikusintha mawonekedwe anu a kukumbukira.
Exampndi Designs	The Exampndi Designs tabu imakupatsani mwayi wopanga zojambula zakaleamples pa kaphatikizidwe ndi kayeseleledwe. Mapangidwe opangidwa example ndi dongosolo lathunthu la EMIF lopangidwa ndi EMIF IP ndi dalaivala yemwe amapanga magalimoto osasintha kuti atsimikizire mawonekedwe a kukumbukira.

Kuti mumve zambiri pamagawo amtundu uliwonse, onani mutu woyenera wa protocol yanu ya kukumbukira mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

Kupanga Synthesizable EMIF Design Example

Kwa zida zachitukuko za Intel Agilex, ndizokwanira kusiya zosintha zambiri za Intel Agilex EMIF IP pazokhazikika zawo. Kupanga kapangidwe ka synthesizeble example, tsatirani izi:

1. Pa Eksample Designs tabu, onetsetsani kuti bokosi la Synthesis lafufuzidwa.
   • Ngati mukugwiritsa ntchito single interface example design, konzani EMIF IP ndikudina File➤ Sungani kuti musunge zomwe zilipo pakusintha kwa IP file ( .ip).
     • Ngati mukugwiritsa ntchito example design yokhala ndi mawonekedwe angapo, tchulani Nambala ya ma IP ku chiwerengero chomwe mukufuna. Mutha kuwona kuchuluka kwa ID ya EMIF yofanana ndi Nambala yosankhidwa ya ma IP. Tsatirani izi kuti mukonze mawonekedwe aliwonse:
   •  Sankhani Cal-IP kuti mufotokoze kugwirizana kwa mawonekedwe ku Calibration IP.
   • Konzani EMIF IP molingana ndi Tab yonse ya Parameter Editor.
   • Bwererani ku Eksample Design tabu ndikudina Jambulani pa ID ya EMIF yomwe mukufuna.
   • Bwerezani sitepe A mpaka c pa ID yonse ya EMIF.
   • Mutha kudina Chotsani batani kuti muchotse magawo omwe adagwidwa ndikubwereza sitepe a mpaka c kuti musinthe EMIF IP.
   • Dinani File➤ Sungani kuti musunge zomwe zilipo pakusintha kwa IP file ( .ip).
2. Dinani Pangani Example Design pakona yakumanja kwa zenera.
3. Tchulani chikwatu cha kapangidwe ka EMIF example ndikudina Chabwino. Kupanga bwino kwa EMIF design example amalenga zotsatirazi filekhalani pansi pa chikwatu cha qii.
4. Dinani File ➤ Tulukani kuti mutuluke pawindo la IP Parameter Editor Pro. Dongosolo limalimbikitsa, Zosintha zaposachedwa sizinapangidwe. Pangani tsopano? Dinani Ayi kuti mupitirize ndi kutuluka kwina.
5. Kutsegula example design, dinani File ➤ Tsegulani Pulojekiti, ndikupita ku /ample_name>/qii/ed_synth.qpf ndikudina Open.
   Zindikirani: Kuti mudziwe zambiri pakupanga ndi kupanga mapangidwe apangidwe example, tchulani
   Kupanga ndi Kukonza Intel Agilex EMIF Design Example.

Chithunzi 4. Zopangidwa Zopangidwa ndi Synthesizable Design Example File Kapangidwe

Kuti mudziwe zambiri pakupanga makina okhala ndi zolumikizira ziwiri kapena zingapo zakunja, onani Kupanga Design Exampndi Multiple EMIF Interfaces, mu External Memory Interfaces Intel Agilex FPGA IP User Guide. Kuti mumve zambiri pakuwongolera ma interfaces angapo, tchulani Kuthandizira EMIF Toolkit mu Design yomwe ilipo, mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

Zindikirani: Ngati simusankha bokosi loyang'ana la Simulation kapena Synthesis, chikwatu chomwe mukupita chili ndi mapangidwe a Platform Designer okha. files, zomwe siziphatikizidwa ndi Intel Quartus Prime software mwachindunji, koma zomwe mungathe view kapena sinthani mu Platform Designer. M'menemo mukhoza kuthamanga malamulo otsatirawa kupanga kaphatikizidwe ndi kayeseleledwe file seti.

• Kuti mupange pulojekiti yolumikizana, muyenera kuyendetsa quartus_sh -t make_qii_design.tclscript mu bukhu lofikira.
• Kuti mupange pulojekiti yoyerekeza, muyenera kuyendetsa quartus_sh -t make_sim_design.tcl script mu bukhu lofikira.

Zindikirani: Ngati mwapanga ex designample ndiyeno musinthe muzosintha za parameter, muyenera kukonzanso kapangidwe kakeampndikuwona zosintha zanu zikukwaniritsidwa. Mapangidwe omwe angopangidwa kumene example samalemba zomwe zilipo kaleample files.

Kupanga EMIF Design Example kwa Simulation

Kwa zida zachitukuko za Intel Agilex, ndizokwanira kusiya zosintha zambiri za Intel Agilex EMIF IP pazokhazikika zawo. Kupanga kapangidwe example poyerekezera, tsatirani izi:

1. Pa Eksample Designs tabu, onetsetsani kuti bokosi la Simulation lafufuzidwa. Sankhaninso mtundu wofunikira wa Simulation HDL, mwina Verilog kapena VHDL.
2. Konzani EMIF IP ndikudina File ➤ Sungani kuti musunge zomwe zilipo pakusintha kwa IP file ( .ip).
3. Dinani Pangani Example Design pakona yakumanja kwa zenera.
4. Tchulani chikwatu cha kapangidwe ka EMIF example ndikudina Chabwino. Kupanga bwino kwa EMIF design example amapanga angapo file imayika zoyeserera zosiyanasiyana zothandizidwa, pansi pa chikwatu cha sim/ed_sim.
5. Dinani File ➤ Tulukani kuti mutuluke pawindo la IP Parameter Editor Pro. Dongosolo limalimbikitsa, Zosintha zaposachedwa sizinapangidwe. Pangani tsopano? Dinani Ayi kuti mupitirize ndi kutuluka kwina.

Mapangidwe Oyerekeza Opangidwa Example File Kapangidwe

Zindikirani: External Memory Interfaces Intel Agilex FPGA IP pakadali pano imathandizira ma VCS, ModelSim/QuestaSim, ndi Xcelium simulators okha. Thandizo lowonjezera la simulator likukonzekera kutulutsidwa mtsogolo.

Zindikirani: Ngati simusankha bokosi loyang'ana la Simulation kapena Synthesis, chikwatu chomwe mukupita chili ndi mapangidwe a Platform Designer okha. files, zomwe siziphatikizidwa ndi Intel Quartus Prime software mwachindunji, koma zomwe mungathe view kapena sinthani mu Platform Designer. M'menemo mukhoza kuthamanga malamulo otsatirawa kupanga kaphatikizidwe ndi kayeseleledwe file seti.

• Kuti mupange pulojekiti yolumikizana, muyenera kuyendetsa quartus_sh -t make_qii_design.tcl script mu bukhu lofikira.
• Kuti mupange pulojekiti yoyerekeza, muyenera kuyendetsa quartus_sh -t make_sim_design.tcl script mu bukhu lofikira.

Zindikirani: Ngati mwapanga ex designample ndiyeno musinthe muzosintha za parameter, muyenera kukonzanso kapangidwe kakeampndikuwona zosintha zanu zikukwaniritsidwa. Mapangidwe omwe angopangidwa kumene example samalemba zomwe zilipo kaleample files.

Simulation Versus Hardware Implementation
Pakuyerekeza kwa mawonekedwe akunja amakumbukidwe, mutha kusankha kudumpha kusanja kapena kuwongolera kwathunthu pa Diagnostics tabu panthawi ya IP.

EMIF Simulation Models
Gome ili likufananiza mawonekedwe a skip calibration ndi ma calibration athunthu.

Table 2. Zitsanzo Zofananitsa za EMIF: Dumphani Kuwongolera ndi Kuyesa Kwathunthu

Dumphani Kuwongolera	Kuwongolera Kwathunthu
Kayeseleledwe kadongosolo kachitidwe koyang'ana malingaliro a ogwiritsa ntchito.	Memory mawonekedwe kayeseleledwe kuyang'ana pa calibration.
Tsatanetsatane wa calibration si anajambulidwa.	Imagwira zonse stagndi calibration.
Imatha kusunga ndi kupezanso deta.	Zimaphatikizapo kusanja, per-bit deskew, etc.
Zimayimira kuchita bwino.
Osaganizira za board skew.

RTL Simulation Versus Hardware Implementation
Gome ili likuwonetsa kusiyana kwakukulu pakati pa kayesedwe ka EMIF ndi kukhazikitsa kwa hardware.

Table 3. EMIF RTL Simulation Versus Hardware Implementation

Chithunzi cha RTL	Kukhazikitsa kwa Hardware
Kuyambitsa kwa Nios® ndikuwongolera kachidindo kofanana.	Kuyambitsa kwa Nios ndi ma code calibration kumachita motsatizana.
Mawonekedwe amatsimikizira kuti cal_done siginecha nthawi imodzi poyerekezera.	Zochita za Fitter zimatsimikizira dongosolo la kayitanidwe, ndipo zolumikizira sizimatsimikizira kuti cal_done nthawi imodzi.

Muyenera kuyendetsa zoyezera za RTL kutengera momwe magalimoto amayendera pamapangidwe anu. Dziwani kuti kayesedwe ka RTL simatengera kuchedwa kwa PCB komwe kungayambitse kusiyana pakati pa kayesedwe ka RTL ndi kukhazikitsa kwa hardware.

 Kutengera Chiyankhulo Chakunja cha Memory IP Ndi ModelSim
Njira iyi ikuwonetsa momwe mungatsanzirire kapangidwe ka EMIF example.

1. Yambitsani pulogalamu ya Mentor Graphics* ModelSim ndikusankha File ➤ Sinthani Dawunilodi. Yendetsani ku chikwatu cha sim/ed_sim/mentor mkati mwa mapangidwe opangidwa kaleampndi foda.
2. Onetsetsani kuti zenera la Transcript likuwonetsedwa pansi pazenera. Ngati zenera la Transcript silikuwoneka, liwonetseni podina View ➤ Zolemba.
3. Pazenera la Transcript, tsegulani gwero la msim_setup.tcl.
4. Gwero la msim_setup.tcl likamaliza, thamangani ld_debug pawindo la Transcript.
5. ld_debug ikamaliza, onetsetsani kuti zenera la Zinthu likuwonetsedwa. Ngati zenera la Zinthu silikuwoneka, liwonetseni podina View ➤ Zinthu.
6. Pazenera la Zinthu, sankhani zizindikiro zomwe mukufuna kutengera podina kumanja ndikusankha Add Wave.
7. Mukamaliza kusankha ma siginecha kuti muyesere, yesani run -all pawindo la Transcript. Kuyesereraku kumayenda mpaka kukamaliza.
8. Ngati kuyerekezera sikukuwoneka, dinani View ➤ Mafunde.

Pin Kuyika kwa Intel Agilex EMIF IP
Mutuwu umapereka malangizo oyika mapini.

Zathaview
Intel Agilex FPGAs ili ndi mawonekedwe awa:

• Chida chilichonse chili ndi mabanki 8 a I/O.
• Banki iliyonse ya I/O ili ndi mabanki awiri a sub-I/O.
• Banki iliyonse ya sub-I/O ili ndi mayendedwe anayi.
• Msewu uliwonse uli ndi zikhomo 12 za I/O (GPIO).

General Pin Guidelines
Zotsatirazi ndi malangizo a pini.

Zindikirani: Kuti mumve zambiri za pini, onani gawo la Intel Agilex FPGA EMIF IP Pin ndi Resource Planning mugawo lachidziwitso la protocol yanu yakunja, mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Onetsetsani kuti mapini amakumbukidwe akunja akunja amakhala mkati mwa mzere womwewo wa I/O.
• Zolumikizana zomwe zimayendera mabanki angapo ziyenera kukwaniritsa izi:
  •  Mabanki ayenera kukhala moyandikana wina ndi mzake. Kuti mudziwe zambiri zamabanki oyandikana nawo, onani mutu wa EMIF Architecture: I/O Bank mu External Memory Interfaces Intel Agilex FPGA IP User Guide.
•  Ma adilesi onse ndi malamulo ndi ma pin ogwirizana ayenera kukhala mkati mwa banki imodzi.
• Ma adilesi ndi malamulo ndi ma pin a data amatha kugawana mabanki ang'onoang'ono pamikhalidwe iyi:
  • Adilesi ndi malamulo ndi ma pini a data sangathe kugawana njira ya I/O.
  • Njira yokhayo ya I/O yosagwiritsidwa ntchito mu adilesi ndi banki yolamula ingakhale ndi ma pini a data.

Table 4. General Pin Zoletsa

Mtundu wa Signal	Kukakamiza
Data Strobe	Zizindikiro zonse za gulu la DQ ziyenera kukhala mumsewu womwewo wa I/O.
Deta	Zikhomo za DQ zogwirizana ziyenera kukhala mumsewu womwewo wa I/O. Kwa ma protocol omwe sagwirizana ndi mizere ya data ya bidirectional, zizindikiro zowerengera ziyenera kugawidwa mosiyana ndi zizindikiro zolembera.
Adilesi ndi Command	Adilesi ndi zikhomo za Command ziyenera kukhala m'malo omwe afotokozedweratu mkati mwa banki yaying'ono ya I/O.

Zindikirani: Kuti mumve zambiri za pini, onani gawo la Intel Agilex FPGA EMIF IP Pin ndi Resource Planning mugawo lachidziwitso la protocol yanu yakunja, mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

• Onetsetsani kuti mapini amakumbukidwe akunja akunja amakhala mkati mwa mzere womwewo wa I/O.
• Zolumikizana zomwe zimayendera mabanki angapo ziyenera kukwaniritsa izi:
  • Mabanki ayenera kukhala moyandikana wina ndi mzake. Kuti mudziwe zambiri zamabanki oyandikana nawo, onani mutu wa EMIF Architecture: I/O Bank mu External Memory Interfaces Intel Agilex FPGA IP User Guide.
• Ma adilesi onse ndi malamulo ndi ma pin ogwirizana ayenera kukhala mkati mwa banki imodzi.
• Ma adilesi ndi malamulo ndi ma pin a data amatha kugawana mabanki ang'onoang'ono pamikhalidwe iyi:
  • Adilesi ndi malamulo ndi ma pini a data sangathe kugawana njira ya I/O.
  • Njira yokhayo ya I/O yosagwiritsidwa ntchito mu adilesi ndi banki yolamula ingakhale ndi ma pini a data.

Kupanga Design Example ndi TG Configuration Option

Mapangidwe a EMIF exampLe ikuphatikizapo chipika chojambulira magalimoto (TG). Mwachikhazikitso, kapangidwe example amagwiritsa ntchito chipika chosavuta cha TG (altera_tg_avl) chomwe chingakhazikitsidwenso kuti muyambitsenso mawonekedwe amayendedwe olimba. Ngati n'koyenera, mukhoza kusankha kuyatsa configurable traffic jenereta (TG2) m'malo. Mu configurable traffic jenereta (TG2) (altera_tg_avl_2), mutha kusintha mawonekedwe amayendedwe munthawi yeniyeni kudzera m'marejista owongolera - kutanthauza kuti simuyenera kukonzanso kapangidwe kake kuti musinthe kapena kuyambitsanso mawonekedwe amagalimoto. Jenereta yamagalimoto iyi imapereka chiwongolero chabwino pamtundu wamagalimoto omwe amatumiza pa mawonekedwe owongolera a EMIF. Kuphatikiza apo, imapereka ma registry omwe ali ndi zambiri zolephera.

Kuthandizira Jenereta Yamagalimoto mu Design Example

Mutha kuyatsa jenereta yosinthika yama traffic kuchokera pa Diagnostics tabu mu EMIF parameter editor. Kuti mutsegule jenereta yosinthika, yatsani Gwiritsani ntchito jenereta yosinthika ya Avalon 2.0 pa Diagnostics tabu.

Chithunzi 6.

• Mutha kusankha kuletsa mawonekedwe amtundu wa traffic stage kapena trafficconfigured traffic stage, koma muyenera kukhala ndi s osachepera imodzitagndi zinatheka. Kuti mudziwe zambiri pa izi stages, tchulani za Default Traffic Pattern ndi Magalimoto Osinthidwa Ogwiritsa Ntchito mu External Memory Interfaces Intel Agilex FPGA IP User Guide.
• Nthawi yoyezetsa ya TG2 imagwira ntchito pamayendedwe okhazikika. Mutha kusankha nthawi yoyeserera yaifupi, yapakatikati, kapena yopanda malire.
• mutha kusankha chimodzi mwazinthu ziwiri za TG2 Configuration Interface Mode parameter:
  • JTAG: Amalola kugwiritsa ntchito GUI mu konsoni yamakina. Kuti mumve zambiri, onani Chiyankhulo Chosinthira Magalimoto a Traffic Generator mu External Memory Interfaces Intel Agilex FPGA IP User Guide.
  • Tumizani kunja: Amalola kugwiritsa ntchito malingaliro a RTL kuti azitha kuyang'anira kuchuluka kwa magalimoto.

Pogwiritsa ntchito Design Exampndi EMIF Debug Toolkit

Musanayambitse EMIF Debug Toolkit, onetsetsani kuti mwakonza chipangizo chanu ndi pulogalamu. file yomwe ili ndi EMIF Debug Toolkit yathandizidwa. Kuti mutsegule EMIF Debug Toolkit, tsatirani izi:

1. Mu pulogalamu ya Intel Quartus Prime, tsegulani System Console posankha Zida ➤ Zida Zowonongeka Zowonongeka ➤ System Console.
2. [Dumphani sitepe iyi ngati polojekiti yanu yatsegulidwa kale mu pulogalamu ya Intel Quartus Prime.] Mu System Console, lowetsani chinthu cha SRAM file (.sof) yomwe mudapanga nawo bolodi (monga momwe zafotokozedwera mu Zofunika Kwambiri Kugwiritsa Ntchito EMIF Debug Toolkit, mu External Memory Interfaces Intel Agilex FPGA IP User Guide).
3. Sankhani zochitika kuti mukonze zolakwika.
4. Sankhani EMIF Calibration Debug Toolkit for EMIF calibration debugging, monga tafotokozera mu Kupanga Design Ex.ample ndi Calibration Debug Option. Kapenanso, sankhani EMIF TG Configuration Toolkit kuti mukonze zolakwika za traffic, monga zafotokozedwera mu Kupanga Design Ex.ample ndi TG Configuration Option.
5. Dinani Open Toolkit kutsegula chachikulu view ya EMIF Debug Toolkit.
6. Ngati pali zochitika zingapo za EMIF pamapangidwe okonzedwa, sankhani ndime (njira yopita ku JTAG master) ndi ID ya mawonekedwe okumbukira a chitsanzo cha EMIF choyambitsa zida.
7. Dinani Yambitsani Chiyankhulo kuti mulole zida kuti ziwerenge magawo a mawonekedwe ndi mawonekedwe ake.
8. Muyenera kusintha mawonekedwe amodzi panthawi; chifukwa chake, kuti mulumikizane ndi mawonekedwe ena pamapangidwewo, choyamba muyenera kuyimitsa mawonekedwe apano.

Otsatirawa ndi akaleampza malipoti ochokera ku EMIF Calibration Debug Toolkit ndi EMIF TG Configuration Toolkit:, motsatana.

Zindikirani: Kuti mumve zambiri pakusintha kosintha, onani Kuthetsa vuto ndi External Memory Interface Debug Toolkit, mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

Zindikirani: Kuti mumve zambiri pazakusintha kwa jenereta yamagalimoto, onani za Traffic Generator Configuration User Interface, mu External Memory Interfaces Intel Agilex FPGA IP User Guide.

Design Example Kufotokozera kwa External Memory Interfaces Intel Agilex FPGA IP

Mukapanga parameter ndi kupanga EMIF IP yanu, mutha kufotokoza kuti dongosololi limapanga zolemba zofananira ndi kaphatikizidwe. file seti, ndi kupanga ma file imakhazikitsa zokha. Ngati musankha Kuyerekeza kapena Kaphatikizidwe pansi pa Eksampndi Design Files pa Eksample Designs tabu, dongosololi limapanga kuyerekezera kwathunthu file seti kapena kaphatikizidwe kokwanira file khazikitsani, molingana ndi kusankha kwanu.

Synthesis Design Example
The synthesis design example lili ndi midadada ikuluikulu yomwe ikuwonetsedwa pachithunzichi pansipa.

• Jenereta wamagalimoto, yemwe ndi wopangidwa ndi Avalon®-MM wakaleample driver yemwe amagwiritsa ntchito ma pseudo-random pattern of reads ndikulembera ku ma adilesi angapo. Wopanga magalimoto amayang'aniranso zomwe zawerengedwa kuchokera kukumbukira kuti zitsimikizire kuti zikugwirizana ndi zomwe zalembedwa ndikutsimikizira kulephera kwina.
• Chitsanzo cha mawonekedwe a kukumbukira, omwe akuphatikizapo:
  • Wowongolera kukumbukira omwe amawongolera pakati pa mawonekedwe a Avalon-MM ndi mawonekedwe a AFI.
  • PHY, yomwe imakhala ngati mawonekedwe pakati pa owongolera kukumbukira ndi zida zamakumbukiro zakunja kuti achite ntchito zowerengera ndi kulemba.

Chithunzi 7. Kapangidwe Kapangidwe Example

Zindikirani: Ngati imodzi kapena zingapo za PLL Sharing Mode, DLL Sharing Mode, kapena OCT Sharing Mode magawo ayikidwa pamtengo wina uliwonse kupatula No Sharing, kapangidwe kake kakaleample idzakhala ndi ma jenereta awiri a traffic/memory interface. Majenereta awiri amtundu wa magalimoto / mawonekedwe okumbukira amangolumikizidwa ndi kulumikizana kwa PLL/DLL/OCT monga kufotokozeredwa ndi zoikamo. Zosintha zamagalimoto / zokumbukira zikuwonetsa momwe mungapangire kulumikizana koteroko pamapangidwe anu.

Simulation Design Example
Kapangidwe ka kayeseleledwe kakaleample lili ndi midadada ikuluikulu yomwe ikuwonetsedwa pachithunzi chotsatirachi.

• Chitsanzo cha kaphatikizidwe kapangidwe kakaleample. Monga tafotokozera m'gawo lapitalo, kaphatikizidwe kapangidwe kakaleample ili ndi jenereta yamagalimoto, chigawo cha calibration, ndi chitsanzo cha mawonekedwe a kukumbukira. Izi zimatchinga kusasinthika kwa zitsanzo zongoyerekeza ngati kuli koyenera kuyerekeza mwachangu.
• Mtundu wa kukumbukira, womwe umakhala ngati generic model womwe umatsatira ndondomeko ya memory protocol. Nthawi zambiri, ogulitsa kukumbukira amapereka zitsanzo zofananira zamagulu awo amakumbukiro omwe mutha kutsitsa kuchokera pawo webmasamba.
• Chowunikira, chomwe chimayang'anira ma siginecha kuchokera ku mawonekedwe akunja okumbukira IP ndi jenereta yamagalimoto, kuwonetsa kupitilira kapena kulephera konse.

Chithunzi 10. Mapangidwe Oyerekeza Example

Exampndi Designs Interface Tab
The parameter editor imaphatikizapo Example Designs tabu yomwe imakupatsani mwayi wowonera ndi kupanga kapangidwe kanu wakaleamples.

Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives

Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP ali ndi dongosolo latsopano la IP. Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.

IP Core Version	Wogwiritsa Ntchito
2.4.0	Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives
2.3.0	Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives
2.3.0	Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives
2.1.0	Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives
19.3	Memory Interfaces Zakunja Intel Agilex FPGA IP Design Exampndi User Guide Archives

Mbiri Yowunikiranso Zolemba za Zolumikizira Zakunja za Memory Intel Agilex FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.06.21	21.2	2.4.2	Mu Design Exampndi Quick Start mutu: • Anawonjezera kalata ku Kupanga ndi Kukonza Intel Agilex EMIF Design Example mutu. • Adasinthidwa mutu wa Kupanga Design Example ndi Calibration Debug Option mutu. • Anawonjezera Kupanga Design Example ndi TG Configuration Option ndi Kuthandizira Jenereta Yamagalimoto mu Design Example mitu. • Zosinthidwa masitepe 2, 3, ndi 4, zidasinthidwa zingapo, ndikuwonjezera cholemba, mu Pogwiritsa ntchito Design Exampndi EMIF Debug Toolkit mutu.
2021.03.29	21.1	2.4.0	Mu Design Exampndi Quick Start mutu: • Anawonjezera kalata ku Kupanga Synthesizable EMIF Design Example ndi Kupanga EMIF Design Example kwa Simulation mitu. • Kusinthidwa File Chithunzi chojambula mu Kupanga EMIF Design Example kwa Simulation mutu.
2020.12.14	20.4	2.3.0	Mu Design Exampndi Quick Start mutu, adasintha izi: • Kusinthidwa Kupanga Synthesizable EMIF Design Example mutu kuti ukhale ndi mapangidwe amitundu yambiri ya EMIF. • Sinthani chithunzi cha sitepe 3, mu Kupanga EMIF Design Example kwa Simulation mutu.
2020.10.05	20.3	2.3.0	Mu Design Exampndi Quick Start Guide mutu, adasintha izi: • Mu Kupanga Pulojekiti ya EMIF, yasintha chithunzichi mu gawo 6. • Mu Kupanga Synthesizable EMIF Design Example, sinthani chithunzichi mu gawo 3. • Mu Kupanga EMIF Design Example kwa Simulation, sinthani chithunzichi mu gawo 3. • Mu Simulation Versus Hardware Implementation, anakonza katayipo kakang'ono patebulo lachiwiri. • Mu Pogwiritsa ntchito Design Exampndi EMIF Debug Toolkit, kusinthidwa sitepe 6, kuwonjezera masitepe 7 ndi 8.
anapitiriza…

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2020.04.13	20.1	2.1.0	• Mu Za mutu, adasintha tebulo mu Kutulutsa Zambiri mutu. • Mu Design Exampndi Quick Start Guide mutu: - Gawo 7 losinthidwa ndi chithunzi chogwirizana, mu Kupanga Synthesizable EMIF Design Example mutu. - Kusintha kwa Kupanga Design Example ndi Debug Option mutu. - Kusintha kwa Pogwiritsa ntchito Design Exampndi EMIF Debug Toolkit mutu.
2019.12.16	19.4	2.0.0	• Mu Design Exampndi Quick Start mutu: - Kusinthidwa fanizo mu sitepe 6 ya Kupanga Pulojekiti ya EMIF mutu. - Kusinthidwa fanizo mu sitepe 4 ya Kupanga Synthesizable EMIF Design Example mutu. - Kusinthidwa fanizo mu sitepe 4 ya Kupanga EMIF Design Example kwa Simulation mutu. - Gawo 5 losinthidwa mu Kupanga EMIF Design Example kwa Simulation mutu. - Kusintha kwa General Pin Guidelines ndi Mabanki Apafupi magawo a Pin Kuyika kwa Intel Agilex EMIF IP mutu.
2019.10.18	19.3		• Mu Kupanga Pulojekiti ya EMIF mutu, wasintha chithunzicho ndi mfundo 6. • Mu Kupanga ndi Kukonza EMIF IP mutu, sinthani chithunzicho ndi gawo 1. • Mu tebulo mu Malangizo a Intel Agilex EMIF Parameter Editor mutu, adasintha kufotokozera kwa Bungwe tabu. • Mu Kupanga Synthesizable EMIF Design Example ndi Kupanga EMIF Design Example kwa Simulation mitu, adasintha chithunzichi mu gawo 3 la mutu uliwonse. • Mu Kupanga EMIF Design Example kwa Simulation mutu, zasinthidwa ndi Mapangidwe Oyerekeza Opangidwa Example File Kapangidwe chithunzi ndikusintha cholemba kutsatira chithunzicho. • Mu Kupanga Synthesizable EMIF Design Example mutu, wowonjezerapo sitepe ndi chithunzi cha mawonekedwe angapo.
2019.07.31	19.2	1.2.0	• Wowonjezera Za External Memory Interfaces Intel Agilex FPGA IP mutu ndi Zambiri Zotulutsidwa. • Madeti osinthidwa ndi manambala amtundu. • Kupititsa patsogolo pang'ono kwa Synthesis Design Example chithunzi mu Synthesis Design Example mutu.
2019.04.02	19.1		• Kutulutsidwa koyamba.

Mbiri Yowunikiranso Zolemba za Zolumikizira Zakunja za Memory Intel Agilex FPGA IP Design Exampndi User Guide

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Intel UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito UG-20219 External Memory Interfaces Intel Agilex FPGA IP Design Example, UG-20219, External Memory Interfaces Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

Maumboni

• Buku Logwiritsa Ntchito