Memory Interfaces Zakunja Intel Stratix 10 FPGA IP Design Example

Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP

Mawonekedwe atsopano komanso kapangidwe kake kakaleample flow ikupezeka kwa Intel® Stratix® 10 yolumikizira kunja kukumbukira. The Example Designs tabu mu mkonzi wa parameter imakupatsani mwayi wofotokozera momwe mungapangire kaphatikizidwe ndi kuyerekezera file seti zomwe mungagwiritse ntchito kutsimikizira EMIF IP yanu. Mutha kupanga example mapangidwe makamaka a Intel FPGA chitukuko cha zida, kapena EMIF IP iliyonse yomwe mumapanga.

Chithunzi 1. General Design Exampndi Workflows

Chithunzi 2. Kupanga EMIF Example Design Ndi Intel Stratix 10 Development Kit

Kupanga Pulojekiti ya EMIF

Pa mtundu wa Intel Quartus® Prime software 17.1 ndi pambuyo pake, muyenera kupanga Intel Quartus Prime projekiti musanapange EMIF IP ndi kapangidwe kakale.ample.

1. Tsegulani pulogalamu ya Intel Quartus Prime ndikusankha File ➤ Project Wizard Watsopano. Dinani Kenako.
2. Tchulani chikwatu ndi nme za polojekiti yomwe mukufuna kupanga. Dinani Kenako.
3. Onetsetsani kuti Empty Project yasankhidwa. Dinani Next nthawi ziwiri.
4. Pansi pa Name filter, lembani gawo la chipangizocho.
5. Pazida Zomwe Zilipo, sankhani chipangizo choyenera.
6. Dinani Malizani.

Kupanga ndi Kukonza EMIF IP

Njira zotsatirazi zikuwonetsa momwe mungapangire ndikusintha EMIF IP. Kuyenda uku kumapanga mawonekedwe a DDR4, koma masitepe ndi ofanana ndi ma protocol ena.

1. Pazenera la IP Catalog, sankhani Intel Stratix 10 External Memory Interfaces. (Ngati zenera la IP Catalog silikuwoneka, sankhani View ➤ Zothandizira Windows ➤ IP Catalog.)
2. Mu IP Parameter Editor, perekani dzina la bungwe la EMIF IP (dzina lomwe mumapereka apa limakhala file dzina la IP) ndipo tchulani chikwatu. Dinani Pangani.
3. Mkonzi wa parameter ali ndi ma tabo angapo pomwe muyenera kusintha magawo kuti awonetse kukhazikitsa kwanu kwa EMIF:

Malangizo a Intel Stratix 10 EMIF Parameter Editor

Table 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Malangizo
General	Onetsetsani kuti magawo otsatirawa alowetsedwa bwino: • Kuthamanga kwa chipangizocho. • Kuchuluka kwa wotchi yokumbukira. • Mafupipafupi a wotchi ya PLL.
Memory	• Onani pepala la data la chipangizo chanu chokumbukira kuti mulowetse magawo pa Memory tabu. • Muyeneranso kuyika malo enieni a pini ya ALERT#. (Imagwira pa DDR4 memory protocol yokha.)
Mem Ine/O	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa Mem I/O tabu. • Kuti mutsimikizire mamangidwe apamwamba, muyenera kupanga kayeseleledwe ka bolodi kuti mupeze makonda abwino kwambiri othetsa.
FPGA I/O	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa FPGA I/O tabu. • Kuti mutsimikizire mapangidwe apamwamba, muyenera kuchita zofananira ndi ma IBIS kuti musankhe miyezo yoyenera ya I/O.
Mem Timing	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa Mem Timing tabu. • Kuti mutsimikizire mapangidwe apamwamba, muyenera kuyika magawo molingana ndi pepala la data lachipangizo chanu.
Bungwe	• Pakufufuza koyambirira kwa polojekiti, mutha kugwiritsa ntchito makonda osakhazikika pa Bungwe tabu. • Kuti mutsimikizire mapangidwe apamwamba ndi kutseka nthawi yolondola, muyenera kupanga kayeseleledwe ka bolodi kuti mupeze zolondola za intersymbol interference (ISI)/ crosstalk and board and package skew information, ndikuziyika pa Bungwe tabu.
Wolamulira	Khazikitsani magawo owongolera molingana ndi kasinthidwe komwe mukufuna ndi machitidwe a wowongolera kukumbukira kwanu.
Diagnostics	Mukhoza kugwiritsa ntchito parameters pa Diagnostics tabu kuti ikuthandizireni kuyesa ndikusintha mawonekedwe anu a kukumbukira.
Exampndi Designs	The Exampndi Designs tabu imakupatsani mwayi wopanga zojambula zakaleamples pa kaphatikizidwe ndi kayeseleledwe. Mapangidwe opangidwa example ndi dongosolo lathunthu la EMIF lopangidwa ndi EMIF IP ndi dalaivala yemwe amapanga magalimoto osasintha kuti atsimikizire mawonekedwe a kukumbukira.

Kuti mumve zambiri pamagawo amtundu uliwonse, onani mutu woyenera wa protocol yanu ya kukumbukira mu Intel Stratix 10 External Memory Interfaces IP User Guide.

Kupanga Synthesizable EMIF Design Example

Kwa zida zachitukuko za Intel Stratix 10, ndizokwanira kusiya zosintha zambiri za Intel Stratix 10 EMIF IP pazosintha zawo. Kupanga kapangidwe ka synthesizeble example, tsatirani izi:

1. Pa Diagnostics tabu, yambitsani EMIF Debug Toolkit/On-Chip Debug Port ndi In-System-Sources-and-Probes kuti mupereke mwayi wopeza zomwe zilipo.
2. Pa Eksample Designs tabu, onetsetsani kuti bokosi la Synthesis lafufuzidwa.
3. Konzani EMIF IP ndikudina Generate Example Design pakona yakumanja kwa zenera.
4. Tchulani chikwatu cha kapangidwe ka EMIF example ndikudina Chabwino. Kupanga bwino kwa EMIF design example amalenga zotsatirazi filekhalani pansi pa chikwatu cha qii.

Chithunzi 3. Zopangidwa Zopangidwa ndi Synthesizable Design Example File Kapangidwe

Zindikirani: Ngati simusankha bokosi loyang'anira Simulation kapena Synthesis, chikwatu chomwe mukupita chikhala ndi kapangidwe ka Platform Designer. files, zomwe siziphatikizidwa ndi pulogalamu ya Intel Quartus Prime mwachindunji, koma zitha kukhala viewed kapena kusinthidwa pansi pa Platform Designer. M'menemo mukhoza kuthamanga malamulo otsatirawa kupanga kaphatikizidwe ndi kayeseleledwe file seti.

• Kuti mupange pulojekiti yolumikizana, muyenera kuyendetsa quartus_sh -t make_qii_design.tcl script mu bukhu lofikira.
• Kuti mupange pulojekiti yoyerekeza, muyenera kuyendetsa quartus_sh -t make_sim_design.tcl script mu bukhu lofikira.

Zambiri Zogwirizana

• Synthesis Example Design patsamba 19
• Mafotokozedwe a Intel Stratix 10 EMIF IP Parameter a DDR3
• Mafotokozedwe a Intel Stratix 10 EMIF IP Parameter a DDR4
• Kufotokozera kwa Intel Stratix 10 EMIF IP Parameter kwa QDRII/II+/Xtreme
• Mafotokozedwe a Intel Stratix 10 EMIF IP Parameter a QDR-IV
• Mafotokozedwe a Intel Stratix 10 EMIF IP Parameter a RLDRAM 3

Kupanga EMIF Design Example kwa Simulation
Kwa zida zachitukuko za Intel Stratix 10, ndizokwanira kusiya zosintha zambiri za Intel Stratix 10 EMIF IP pazosintha zawo. Kupanga kapangidwe example kwa
kayeseleledwe, tsatirani izi:

1. Pa Diagnostics tabu, mutha kusankha pakati pa mitundu iwiri yoyezera: Dumphani Kuwongolera ndi Kuwongolera Kwathunthu. (Kuti mumve zambiri pamitundu iyi, onani Kufanizira Kuyerekeza ndi Kukhazikitsa kwa Hardware, kenako m'mutu uno.) Kuti muchepetse nthawi yofananira, sankhani Abstract PHY kuti muyesere mwachangu.
2. Pa Eksample Designs tabu, onetsetsani kuti bokosi la Simulation lafufuzidwa. Sankhaninso mtundu wofunikira wa Simulation HDL, mwina Verilog kapena VHDL.
3. Konzani EMIF IP ndikudina Generate Example Design pakona yakumanja kwa zenera.
4. Tchulani chikwatu cha kapangidwe ka EMIF example ndikudina Chabwino.

Kupanga bwino kwa EMIF design example amapanga angapo file imayika zoyeserera zosiyanasiyana zothandizidwa, pansi pa chikwatu cha sim/ed_sim.

Chithunzi 4. Zopanga Zofananira Zopanga Example File Kapangidwe

Zindikirani: Ngati simusankha bokosi loyang'ana la Simulation kapena Synthesis, chikwatu chomwe mukupita chimakhala ndi mapangidwe a Platform Designer files, zomwe siziphatikizidwa ndi pulogalamu ya Intel Quartus Prime mwachindunji, koma zitha kukhala viewed kapena kusinthidwa pansi pa Platform Designer. M'menemo mukhoza kuthamanga malamulo otsatirawa kupanga kaphatikizidwe ndi kayeseleledwe file seti.

• Kuti mupange pulojekiti yolumikizana, muyenera kuyendetsa quartus_sh -t make_qii_design.tcl script mu bukhu lofikira.
• Kuti mupange pulojekiti yoyerekeza, muyenera kuyendetsa quartus_sh -t make_sim_design.tcl script mu bukhu lofikira.

Zambiri Zogwirizana
• Kuyerekezera Eksampndi Design pa
• Intel Stratix 10 EMIF IP – Simulating Memory IP
• Kuyerekezera Kulimbana ndi Kukhazikitsa kwa Hardware pa

Simulation Versus Hardware Implementation
Pakuyerekeza kwa mawonekedwe akunja amakumbukidwe, mutha kusankha kudumpha kusanja kapena kuwongolera kwathunthu pa Diagnostics tabu panthawi ya IP.
EMIF Simulation Models
Gome ili likufananiza mawonekedwe a skip calibration ndi ma calibration athunthu.

Table 2. Zitsanzo Zofananitsa za EMIF: Dumphani Kuwongolera ndi Kuyesa Kwathunthu

Dumphani Kuwongolera	Kuwongolera Kwathunthu
Kayeseleledwe kadongosolo kachitidwe koyang'ana malingaliro a ogwiritsa ntchito.	Memory mawonekedwe kayeseleledwe kuyang'ana pa calibration.
Tsatanetsatane wa calibration si anajambulidwa.	Imagwira zonse stagndi calibration.
Imatha kusunga ndi kupezanso deta.	Zimaphatikizapo kusanja, per-bit deskew, etc.
Zimayimira kuchita bwino.
Osaganizira za board skew.

RTL Simulation Versus Hardware Implementation

Gome ili likuwonetsa kusiyana kwakukulu pakati pa kayesedwe ka EMIF ndi kukhazikitsa kwa hardware.

Table 3. EMIF RTL Simulation Versus Hardware Implementation

Chithunzi cha RTL	Kukhazikitsa kwa Hardware
Kuyambitsa kwa Nios® ndikuwongolera kachidindo kofanana.	Kuyambitsa kwa Nios ndi ma code calibration kumachita motsatizana.
Zolumikizira zimatsimikizira siginecha ya cal_done munthawi imodzi poyerekezera.	Zochita za Fitter zimatsimikizira dongosolo la kayitanidwe, ndipo zolumikizira sizimatsimikizira kuti cal_done nthawi imodzi.

Muyenera kuyendetsa zoyezera za RTL kutengera momwe magalimoto amayendera pamapangidwe anu. Dziwani kuti kayesedwe ka RTL simatengera kuchedwa kwa PCB komwe kungayambitse kusiyana pakati pa kayesedwe ka RTL ndi kukhazikitsa kwa hardware.

Kutengera Chiyankhulo Chakunja cha Memory IP Ndi ModelSim

Njira iyi ikuwonetsa momwe mungatsanzirire kapangidwe ka EMIF example.

1. Yambitsani pulogalamu ya Mentor Graphics* ModelSim ndikusankha File ➤ Sinthani Dawunilodi. Yendetsani ku chikwatu cha sim/ed_sim/mentor mkati mwa mapangidwe opangidwa kaleampndi foda.
2. Onetsetsani kuti zenera la Transcript likuwonetsedwa pansi pazenera. Ngati zenera la Transcript silikuwoneka, liwonetseni podina View ➤ Zolemba.
3. Pazenera la Transcript, tsegulani gwero la msim_setup.tcl.
4. Gwero la msim_setup.tcl likamaliza, thamangani ld_debug pawindo la Transcript.
5. ld_debug ikamaliza, onetsetsani kuti zenera la Zinthu likuwonetsedwa. Ngati zenera la Zinthu silikuwoneka, liwonetseni podina View ➤ Zinthu.
6. Pazenera la Zinthu, sankhani ma sign omwe mukufuna kutengera ndikudina kumanja ndikusankha Add Wave.
7. Mukamaliza kusankha ma siginecha kuti muyesere, yesani run -onse pawindo la VTranscript. Kuyesereraku kumayenda mpaka kukamaliza.
8. Ngati kuyerekezera sikukuwoneka, dinani View ➤ Mafunde.

Zambiri Zogwirizana
Intel Stratix 10 EMIF IP - Simulating Memory IP

Pin Kuyika kwa Intel Stratix 10 EMIF IP

Mutuwu umapereka malangizo oyika mapini.

Zathaview

Intel Stratix 10 FPGAs ili ndi izi:

• Chida chilichonse chili ndi pakati pa 2 ndi 3 I/O mizati.
• Gawo lililonse la I/O lili ndi mabanki 12 a I/O.
• Banki iliyonse ya I/O ili ndi mayendedwe anayi.
• Msewu uliwonse uli ndi zikhomo 12 za I/O (GPIO).

General Pin Guidelines
Mfundo zotsatirazi zimapereka malangizo achinsinsi:

• Onetsetsani kuti mapini amakumbukidwe akunja amakhala mkati mwa gawo limodzi la I/O.
• Zolumikizana zomwe zimayendera mabanki angapo ziyenera kukwaniritsa izi:
  • Mabanki ayenera kukhala moyandikana wina ndi mzake. Kuti mumve zambiri zamabanki oyandikana nawo, onani Intel Stratix 10 External Memory Interfaces IP User Guide.
  • Adilesi ndi banki yolamula iyenera kukhala mu banki yapakati kuti muchepetse kuchedwa. Ngati mawonekedwe okumbukira akugwiritsa ntchito mabanki angapo, adilesi ndi banki yolamula ikhoza kukhala m'mabanki awiriwa.
• Mapini osagwiritsidwa ntchito atha kugwiritsidwa ntchito ngati ma pini a I/O.
• Ma adilesi onse ndi malamulo ndi ma pin ogwirizana ayenera kukhala mkati mwa banki imodzi.
• Ma adilesi ndi malamulo ndi ma pin a data amatha kugawana banki pamikhalidwe iyi:
  • Adilesi ndi malamulo ndi ma pini a data sangathe kugawana njira ya I/O.
  • Njira yokhayo ya I/O yosagwiritsidwa ntchito mu adilesi ndi banki yolamula ingagwiritsidwe ntchito pamapini a data.

Table 4. General Pin Zoletsa

Mtundu wa Signal	Kukakamiza
Data Strobe	Zizindikiro zonse za gulu la DQ ziyenera kukhala mumsewu womwewo wa I/O.
Deta	Zikhomo za DQ zogwirizana ziyenera kukhala mumsewu womwewo wa I/O. Kwa ma protocol omwe sagwirizana ndi mizere ya data ya bidirectional, zizindikiro zowerengera ziyenera kugawidwa mosiyana ndi zizindikiro zolembera.
Adilesi ndi Command	Adilesi ndi zikhomo za Command ziyenera kukhala m'malo omwe afotokozedweratu mkati mwa banki ya I/O.

Mabanki Apafupi

Kuti mabanki aziganiziridwa moyandikana, ayenera kukhala pamndandanda womwewo wa I/O, Kuti mudziwe ngati mabanki ali moyandikana, tchulani Mabanki a Modular I/O Malo ndi Pin Counts mu gawo la Zida 10 la Stratix 10 General Purpose I. /O
Wogwiritsa Ntchito.

Pofotokoza za matebulo a Stratix 10 General Purpose I/O User Guide, ndibwino kuganiza kuti mabanki onse omwe akuwonetsedwa ali pafupi, pokhapokha chizindikiro cha '-' chilipo; chizindikiro cha '-' chimasonyeza kuti banki siinagwirizane ndi phukusi.
Pin Ntchito

Kuti mudziwe malo a mapini onse a EMIF I/O muyenera kutchula tebulo la pini la chipangizo chanu. Ponena za tebulo la pini, manambala aku banki, ma indices aku banki a I/O, ndi mayina a pini amaperekedwa. Mutha kupeza ma pini a adilesi ndi zikhomo zolamula mu Stratix 10 Scheme Table yomwe ili pa Intel FPGA. webmalo. Mutha kugwira ntchito za pini m'njira zosiyanasiyana. Njira yovomerezeka ndikukakamiza pamanja ma siginecha ena ndikulola Intel Quartus Prime Fitter kuti igwire zina zonse. Njirayi imakhala yowonana ndi ma pin tables kuti mupeze malo ovomerezeka a ma pini ena ndikuwagawa kudzera mu .qsf. file zomwe zimapangidwa ndi EMIF design example. Panjira iyi yoyika I/O, muyenera kuletsa zizindikiro zotsatirazi:

• Mtengo wa CK0
• Pini imodzi ya DQS pagulu
• Wotchi yowonetsera ya PLL
• Mtengo RZQ

Kutengera zopinga zomwe zili pamwambapa, Intel Quartus Prime Fitter imazungulira mapini mkati mwanjira iliyonse ngati pakufunika. Chithunzi chotsatirachi chikuwonetsa exampmagawo a pini a mawonekedwe a DDR3 x72 okhala ndi zisankho zotsatirazi:

• Adilesi ndi pini yolamula imayikidwa mu banki 2M ndipo imafuna misewu itatu.
  • CK0 imakakamizika kusindikiza 8 mu banki 2M.
  • Zikhomo za wotchi ya PLL zimakakamizika kukhala ndi mapini 24 ndi 25 mu banki 2M.
  • RZQ imakakamizika kusindikiza 26 mu banki 2M.
• Deta imayikidwa m'mabanki 2N, 2M, ndi 2L, ndipo imafuna mayendedwe 9.
  • Magulu a DQS 1-4 amayikidwa mu banki 2N.
  • Gulu la DQS 0 limayikidwa ku banki 2M.
  • Magulu a DQS 5-8 amayikidwa mu banki 2L.

Chithunzi 5. Pini Ntchito Example: DDR3 x73 Interface

Mu example, kukakamiza CK0 kusindikiza 8 mu banki 2M, mungawonjezere mzere wotsatira ku .qsf file, kutengera tebulo loyenera la pini:

Mapangidwe a pini pamwambapa atha kugwiritsidwa ntchito pamapini onse:

Zambiri Zogwirizana

• Ma Modular I/O Banks mu Intel Stratix 10 Devices
• Intel Stratix 10 EMIF IP DDR3
• Intel Stratix 10 EMIF IP ya DDR4
• Intel Stratix 10 EMIF IP ya QDRII/II+/Xtreme
• Intel Stratix 10 EMIF IP ya QDR-IV
• Intel Stratix 10 EMIF IP ya RLDRAM 3

Kupanga ndi Kukonza Intel Stratix 10 EMIF Design Example

Mukapanga ma pini ofunikira mu .qsf file, mukhoza kusonkhanitsa zojambula zakaleample mu pulogalamu ya Intel Quartus Prime.

1. Pitani ku chikwatu cha Intel Quartus Prime chomwe chili ndi kapangidwe kakaleampndi directory.
2. Tsegulani polojekiti ya Intel Quartus Prime file, (.qpf).
3. Kuti muyambe kusanja, dinani Kukonza ➤ Yambani Kuphatikiza. Kutsirizitsa bwino kophatikiza kumapanga .sof file, zomwe zimathandiza kuti mapangidwewo azigwira ntchito pa hardware.
4. Kuti mupange chipangizo chanu ndi kapangidwe kake, tsegulani pulogalamuyo podina Zida ➤ Wopanga Mapulogalamu.
5. Mu pulogalamuyo, dinani Auto Detect kuti muwone zida zothandizira.
6. Sankhani chipangizo cha Intel Stratix 10 ndikusankha Sinthani File.
7. Pitani ku ed_synth.sof yopangidwa file ndi kusankha Open.
8. Dinani Start kuti muyambe kukonza chipangizo cha Intel Stratix 10. Chidacho chikakonzedwa bwino, kapamwamba komwe kali kumanja kwa zenera kuyenera kuwonetsa 100% (Yopambana).

Kuthetsa vuto la Intel Stratix 10 EMIF Design Example
EMIF Debug Toolkit ilipo kuti ithandizire kukonza mawonekedwe akunja a kukumbukira. Chida chothandizira chimakulolani kuti muwonetse malire owerengera ndi kulemba ndikupanga zojambula zamaso. Mukakonza zida zachitukuko za Intel Stratix 10, mutha kutsimikizira ntchito yake pogwiritsa ntchito EMIF Debug Toolkit.

1. Kuti mutsegule EMIF Debug Toolkit, pitani ku Zida ➤ Zipangizo Zothetsera Vuto la System ➤ Toolkit External Memory Interface.
2. Dinani Yambitsani Malumikizidwe.
3. Dinani Link Project ku chipangizo. Iwindo likuwoneka; onetsetsani kuti chipangizo cholondola chasankhidwa komanso kuti .sof yolondola file amasankhidwa.
4. Dinani Pangani Memory Interface Connection. Landirani zosintha zokhazikika podina Chabwino.

Zida zachitukuko za Intel Stratix 10 tsopano zakhazikitsidwa kuti zizigwira ntchito ndi EMIF Debug Toolkit, ndipo mutha kupanga lipoti lililonse mwa kudina kawiri panjira yofananira:

• Yambitsaninso calibration. Amapanga lipoti la ma calibration akufotokoza mwachidule momwe ma calibration alili pa gulu la DQ/DQS pamodzi ndi m'mphepete mwa pini iliyonse ya DQ/DQS.
• Driver Margining. Amapanga lipoti lofotokozera mwachidule malire owerengera ndi kulemba pa pini ya I/O. Izi zimasiyana ndi machedwe a ma calibration chifukwa malire a dalaivala amatengedwa panthawi yomwe ali ndi magalimoto ambiri m'malo mosintha.
• Pangani Diso la Diso. Amapanga zithunzi zowerengera ndi kulemba za diso pa pini iliyonse ya DQ kutengera masanjidwe a data.
• Yerekezerani Kuyimitsa. Imasesa zikhalidwe zosiyanasiyana zoyimitsa ndikuwonetsa m'mphepete mwake momwe mtengo uliwonse woyimitsa umapereka. Gwiritsani ntchito izi kuti muthandizire kusankha njira yoyenera yosinthira kukumbukira kukumbukira.

Zambiri Zogwirizana
Intel Stratix 10 EMIF IP Debugging

Design Example Kufotokozera kwa External Memory Interfaces Intel Stratix 10 FPGA IP

Mukapanga parameter ndi kupanga EMIF IP yanu, mutha kufotokoza kuti dongosololi limapanga zolemba zofananira ndi kaphatikizidwe. file seti, ndi kupanga ma file imakhazikitsa zokha. Ngati musankha Kuyerekeza kapena Kaphatikizidwe pansi pa Eksampndi Design Files pa Eksample Designs tabu, dongosololi limapanga kuyerekezera kwathunthu file seti kapena kaphatikizidwe kokwanira file khazikitsani, molingana ndi kusankha kwanu.

Synthesis Exampndi Design

The synthesis example design ili ndi midadada ikuluikulu yomwe ikuwonetsedwa pachithunzi pansipa.

• Jenereta wamagalimoto, yemwe ndi wopangidwa ndi Avalon®-MM wakaleample driver yemwe amagwiritsa ntchito ma pseudo-random pattern of reads ndikulembera ku ma adilesi angapo. Wopanga magalimoto amayang'aniranso zomwe zawerengedwa kuchokera kukumbukira kuti zitsimikizire kuti zikugwirizana ndi zomwe zalembedwa ndikutsimikizira kulephera kwina.
• Chitsanzo cha mawonekedwe a kukumbukira, omwe akuphatikizapo:
  • Wowongolera kukumbukira omwe amawongolera pakati pa mawonekedwe a Avalon-MM ndi mawonekedwe a AFI.
  • PHY, yomwe imakhala ngati mawonekedwe pakati pa owongolera kukumbukira ndi zida zamakumbukiro zakunja kuti achite ntchito zowerengera ndi kulemba.

Chithunzi 6. Kaphatikizidwe Eksampndi Design

Ngati mukugwiritsa ntchito mawonekedwe a Ping Pong PHY, ma synthesis example design imaphatikizapo majenereta awiri apamsewu opereka malamulo kuzipangizo ziwiri zodziyimira pawokha kudzera paowongolera awiri odziyimira pawokha ndi PHY wamba, monga zikuwonetsedwa pachithunzi chotsatira.

Chithunzi 7. Kaphatikizidwe Eksample Design ya Ping Pong PHY

Ngati mukugwiritsa ntchito RLDRAM 3, jenereta yamagalimoto mu kaphatikizidwe kakaleample design imalankhulana mwachindunji ndi PHY pogwiritsa ntchito AFI, monga momwe tawonetsera pachithunzichi.

Chithunzi 8. Kaphatikizidwe Eksample Design ya RLDRAM 3 Interfaces

Zindikirani: Ngati chimodzi kapena zingapo za PLL Sharing Mode, DLL Sharing Mode, kapena OCT Sharing Mode magawo ayikidwa pamtengo wina uliwonse kupatula Palibe Kugawana, kaphatikizidwe kale.ample design idzakhala ndi ma jenereta awiri a traffic / mawonekedwe okumbukira. Zosintha ziwiri za jenereta / zokumbukira zimangolumikizidwa ndi kulumikizana kwa PLL/DLL/OCT monga momwe zimafotokozedwera ndi zoikamo. Zosintha zamagalimoto / zokumbukira zikuwonetsa momwe mungapangire kulumikizana koteroko pamapangidwe anu.
Zindikirani: Kaphatikizidwe ka chipani chachitatu monga tafotokozera mu Intel Quartus Prime Standard Edition User Guide: Third-party Synthesis sikuyenda kwa EMIF IP.
Zambiri Zogwirizana
Kupanga Synthesizable EMIF Design Example pa

Simulation Exampndi Design
Kayeseleledwe example design ili ndi midadada ikuluikulu yomwe ikuwonetsedwa pachithunzi chotsatirachi.

• Chitsanzo cha synthesis exampndi design. Monga tafotokozera m'gawo lapitalo, kaphatikizidwe wakaleample design ili ndi jenereta yamagalimoto ndi chitsanzo cha mawonekedwe a kukumbukira. Izi zimatchinga kusasinthika kwa zitsanzo zongoyerekeza ngati kuli koyenera kuyerekeza mwachangu.
• Mtundu wa kukumbukira, womwe umakhala ngati generic model womwe umatsatira ndondomeko ya memory protocol. Nthawi zambiri, ogulitsa kukumbukira amapereka zitsanzo zofananira zamagulu awo amakumbukiro omwe mutha kutsitsa kuchokera pawo webmasamba.
• Chowunikira, chomwe chimayang'anira ma siginecha kuchokera ku mawonekedwe akunja okumbukira IP ndi jenereta yamagalimoto, kuwonetsa kupitilira kapena kulephera konse.

Chithunzi 9. Kuyerekezera Eksampndi Design

Ngati mukugwiritsa ntchito mawonekedwe a Ping Pong PHY, zoyeserera zakaleample design imaphatikizapo majenereta awiri apamsewu opereka malamulo kuzipangizo ziwiri zodziyimira pawokha kudzera paowongolera awiri odziyimira pawokha ndi PHY wamba, monga zikuwonetsedwa pachithunzi chotsatira.

Chithunzi 10. Kuyerekezera Eksample Design ya Ping Pong PHY

Ngati mukugwiritsa ntchito RLDRAM 3, jenereta yamagalimoto muzoyerekeza zakaleample design imalankhulana mwachindunji ndi PHY pogwiritsa ntchito AFI, monga momwe tawonetsera pachithunzichi.

Chithunzi 11. Kuyerekezera Eksample Design ya RLDRAM 3 Interfaces

Zambiri Zogwirizana
Kupanga EMIF Design Example kwa Simulation pa

Exampndi Designs Interface Tab
The parameter editor imaphatikizapo Example Designs tabu yomwe imakupatsani mwayi wopanga mawonekedwe ndi kupanga wanu wakaleampndi mapangidwe.l
Zopezeka Eksample Designs Gawo
The Select design pulldown imakupatsani mwayi wosankha zomwe mukufunaampndi design. Pakadali pano, EMIF Example Design ndiye chisankho chokhacho chomwe chilipo, ndipo chimasankhidwa mwachisawawa.

Mbiri Yowunikiranso Zolemba pazakunja kwa Memory Interface Intel Stratix 10 FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Zosintha
2021.03.29	21.1	• Mu Exampndi Design Quick Start Chaputala, chochotsa zonena za NCSim* simulator.
2018.09.24	18.1	• Ziwerengero zosinthidwa mu Kupanga Synthesizable EMIF Design Example ndi Kupanga EMIF Design Example kwa Simulation mitu.
2018.05.07	18.0	• Kusintha mutu wa chikalata kuchokera Intel Stratix 10 External Memory Interfaces IP Design Exampndi User Guide ku Memory Interfaces Zakunja Intel Stratix 10 FPGA IP Design Exampndi User Guide. • Zoloza zipolopolo zakonzedwa Zathaview gawo la Pin Kuyika kwa Intel Stratix 10 EMIF IP mutu.

Tsiku	Baibulo	Zosintha
Novembala 2017	2017.11.06	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Zolemba / Zothandizira

Intel External Memory Interfaces Intel Stratix 10 FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito Memory Interfaces Zakunja Intel Stratix 10 FPGA IP Design Example, Zakunja, Memory Interfaces Intel Stratix 10 FPGA IP Design Example, Intel Stratix 10 FPGA IP Design Example, 10 FPGA IP Design Example

Maumboni

• Buku Logwiritsa Ntchito