UG-20219 ebe nchekwa mpụga Intel Agilex FPGA IP Design Example

Banyere Interface ebe nchekwa mpụga Intel® Agilexâ„¢ FPGA IP

Ozi mwepụta

Ụdị IP bụ otu ụdị sọftụwia Intel® Quartus® Prime Design Suite ruo v19.1. Site na ụdị sọftụwia Intel Quartus Prime Design Suite 19.2 ma ọ bụ karịa, IP cores nwere atụmatụ mbipụta IP ọhụrụ. Nọmba mbipute IP (XYZ) na-agbanwe site n'otu ụdị ngwanrọ gaa na nke ọzọ. Mgbanwe na:

• X na-egosi ntughari isi nke IP. Ọ bụrụ na imelite ngwa ngwa Intel Quartus Prime gị, ị ga-emerịrị IP ahụ.
• Y na-egosi na IP gụnyere atụmatụ ọhụrụ. Megharịa IP gị ka ịtinye atụmatụ ọhụrụ ndị a.
• Z na-egosi na IP gụnyere obere mgbanwe. Megharịa IP gị ka ịtinye mgbanwe ndị a.
  

  Ihe	Nkọwa
  Ụdị IP	2.4.2
  Intel Quartus Prime	21.2
  Ụbọchị mwepụta	2021.06.21

Imepụta Exampna Ntuziaka mmalite ngwa ngwa maka ihu ebe nchekwa mpụga Intel Agilex™ FPGA IP

Nhazi akpaka example eruba dị maka Intel Agilex™ oghere ebe nchekwa mpụga. The Generate Example Designs bọtịnụ na Example Designs tab na-enye gị ohere ịkọwapụta na mepụta njikọ na ịme anwansị simulation example file ntọala nke ị nwere ike iji kwado IP EMIF gị. Ị nwere ike ịmepụta imewe exampnke ahụ dabara na ngwa mmepe Intel FPGA, ma ọ bụ maka IP EMIF ọ bụla ị na-emepụta. Ị nwere ike iji imewe exampiji nyere aka nyocha gị, ma ọ bụ dị ka mmalite maka usoro nke gị.

General Design Exampna usoro ọrụ

Ịmepụta ọrụ EMIF

Maka ya ụdị sọftụwia Intel Quartus Prime 17.1 na emesia, ị ga-emerịrị ọrụ Intel Quartus Prime tupu ịmepụta EMIF IP na imewe ex.ample.

1. Ẹkedori Intel Quartus Prime software wee họrọ File ➤ Ọkachamara Project ọhụrụ. Pịa Ọzọ. Imepụta Exampna Ntuziaka mmalite ngwa ngwa maka ihu ebe nchekwa mpụga Intel Agilex™ FPGA IP
2. Ezipụta akwụkwọ ndekọ aha ( ), aha maka ọrụ Intel Quartus Prime ( ), na aha ụlọ ọrụ imewe dị elu ( ) nke ị chọrọ ịmepụta. Pịa Ọzọ.
3. Nyochaa na ahọpụtara Project efu. Pịa ugboro abụọ na-esote.
4. N'okpuru Ezinụlọ, họrọ Intel Agilex.
5. N'okpuru nzacha aha, pịnye nọmba akụkụ ngwaọrụ.
6. N'okpuru ngwaọrụ dị, họrọ ngwaọrụ kwesịrị ekwesị.
7. Pịa N'ikpeazụ.

Ịmepụta na ịhazi EMIF IP

Usoro ndị a na-egosi otu esi ewepụta na hazie IP EMIF. Nke a na-eme njem na-emepụta DDR4 interface, mana usoro ndị ahụ yiri ụkpụrụ ndị ọzọ. (Usoro ndị a na-eso katalọgụ IP (nkeonwe) eruba; ọ bụrụ na ịhọrọ iji Platform Designer (sistemụ) eruba kama, usoro ndị a yiri.)

1. Na mpio katalọgụ IP, họrọ Interfaces ebe nchekwa mpụga Intel Agilex FPGA IP. (Ọ bụrụ na ahụghị windo katalọgụ IP, họrọ View ➤ IP katalọgụ.)
2. Na IP Parameter Editor, nye aha aha maka EMIF IP (aha ị nyere ebe a na-aghọ file aha maka IP) ma kọwaa ndekọ. Pịa Mepụta.
3. Onye ndezi paramita nwere ọtụtụ taabụ ebe ị ga-ahazirịrị paramita iji gosipụta mmejuputa EMIF gị.

Ntuziaka nchịkọta akụkọ nke Intel Agilex EMIF Parameter
Isiokwu a na-enye ntụzịaka dị elu maka ịmegharị taabụ na Intel Agilex EMIF IP parameter editọ.

Tebụl 1. EMIF Parameter Editor Guidelines

Parameter Editor Tab	Ntuziaka
Izugbe	Gbaa mbọ hụ na etinyere paramita ndị a nke ọma: • Ọsọ ọsọ maka ngwaọrụ. • Ugboro elekere ebe nchekwa. • Ugboro elekere ntụaka PLL.
Ebe nchekwa	• Rụtụ aka na mpempe data maka ngwaọrụ ebe nchekwa gị ka itinye paramita dị na Ebe nchekwa tab. • Ị ga-etinyekwa otu ebe maka ntụtụ ALART#. (Na-emetụta naanị DDR4 protocol ebe nchekwa.)
Mem I/O	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na Mem I/O tab. • Maka nkwado imewe dị elu, ịkwesịrị ịme simulation bọọdụ iji nweta ntọala nkwụsị kacha mma.
FPGA I/O	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na FPGA I/O tab. • Maka nkwado imewe dị elu, ị kwesịrị ịme simulation bọọdụ nwere ụdị IBIS metụtara iji họrọ ụkpụrụ I/O kwesịrị ekwesị.
Oge Mem	• Maka nyocha ọrụ mbụ, ịnwere ike iji ntọala ndabara na Oge Mem tab. • Maka nkwado imewe dị elu, ịkwesịrị itinye paramita dịka mpempe data ngwaọrụ ebe nchekwa gị siri dị.
Onye njikwa	Tọọ paramita njikwa dịka nhazi na omume achọrọ maka njikwa ebe nchekwa gị.
Nchọpụta nchọpụta	Ị nwere ike iji paramita ndị dị na ya Nchọpụta nchọpụta tab iji nyere aka n'ịnwale na debugging interface ebe nchekwa gị.
Example Designs	Nke Example Designs tab na-ahapụ gị ịmepụta imewe examples maka synthesis na maka ịme anwansị. Ihe emepụtara example bụ usoro EMIF zuru oke nke nwere EMIF IP na onye ọkwọ ụgbọ ala na-emepụta okporo ụzọ na-enweghị usoro iji kwado interface ebe nchekwa.

Maka ozi zuru ezu na parampat onye ọ bụla, rụtụ aka na isiakwụkwọ dabara adaba maka usoro ebe nchekwa gị na ntuziaka onye ọrụ IP Intel Agilex FPGA Mpụga.

Na-amụpụta EMIF Design Synthesizable Example

Maka ngwa mmepe Intel Agilex, o zuru ezu ịhapụ ọtụtụ ntọala Intel Agilex EMIF IP na ụkpụrụ ndabara ha. Iji mepụta synthesizable imewe example, soro usoro ndị a:

1. Na Exampna Designs tab, hụ na enyochala igbe Synthesis.
   • Ọ bụrụ na ị na-emejuputa otu interface exampiji chepụta, hazie EMIF IP wee pịa File➤ Chekwaa iji chekwaa ntọala dị ugbu a n'ime ụdị IP onye ọrụ file ( .ip).
     • Ọ bụrụ na ị na-emejuputa atumatu example imewe na otutu interfaces, ezipụta Number nke IPs na chọrọ ọnụ ọgụgụ nke interfaces. Ị nwere ike ịhụ ngụkọta ọnụ ọgụgụ nke EMIF ID dị ka ọnụọgụ IP ahọpụtara. Soro usoro ndị a iji hazie interface ọ bụla:
   •  Họrọ Cal-IP iji kọwapụta njikọ nke interface na Calibration IP.
   • Hazie EMIF IP otu a na Parameter Editor Tab niile.
   • Laghachi na ExampChepụta taabụ wee pịa Weghara na ID EMIF achọrọ.
   • Tinyegharịa nzọụkwụ a ruo c maka ID EMIF niile.
   • Ị nwere ike pịa bọtịnụ Kpochapụ ka ịwepụ paramita ewepụtara wee kwugharịa nzọụkwụ a na c iji mee mgbanwe na EMIF IP.
   • Pịa File➤ Chekwaa iji chekwaa ntọala dị ugbu a n'ime ụdị IP onye ọrụ file ( .ip).
2. Pịa n'ịwa Example Chepụta na elu-nri akuku nke window.
3. Ezipụta akwụkwọ ndekọ aha maka imewe EMIF example wee pịa OK. Ọgbọ na-aga nke ọma nke imewe EMIF example emepụta ihe ndị a filesetịpụrụ n'okpuru ndekọ qii.
4. Pịa File ➤ Wepụ ka ịpụ na windo Parameter Editor Pro. Sistemu na-akpalite, emebeghị mgbanwe na nso nso a. Mepụta ugbu a? Pịa Mba ka ịga n'ihu na usoro na-esote.
5. Iji mepee example imewe, pịa File ➤ Mepee Project, wee gaa na nke /ample_name>/qii/ed_synth.qpf wee pịa Mepee.
   Mara: Maka ozi gbasara mkpokọta na mmemme imewe example, rụtụ aka
   Ịchịkọta na ịhazi Intel Agilex EMIF Design Example.

Ọgụgụ 4. Emepụtara Synthesizable Design Example File Nhazi

Maka ozi gbasara ịrụ sistemu nwere oghere ebe nchekwa abụọ ma ọ bụ karịa, rụtụ aka na Ịmepụta Nhazi Exampnwere otutu EMIF Interfaces, n'ime ihe nrụnye ebe nchekwa mpụga Intel Agilex FPGA IP ntuziaka onye ọrụ. Maka ozi gbasara nbibi ọtụtụ ihu, rụtụ aka na-enyere EMIF Toolkit ke dị adị, na Mpụga ebe nchekwa Interfaces Intel Agilex FPGA IP Ntuziaka.

Mara: Ọ bụrụ na ị họrọghị igbe nrịbama nke Simulation ma ọ bụ Synthesis, ndekọ ebe ị na-aga nwere naanị ihe nrụpụta Platform files, nke Intel Quartus Prime software anaghị achịkọta ozugbo, mana nke ị nwere ike view ma ọ bụ dezie na Platform Designer. N'ọnọdụ a ị nwere ike ịme iwu ndị a ka ịmepụta njikọ na simulation file tent.

• Iji mepụta ọrụ anakọtara, ị ga-agbarịrị quartus_sh -t make_qii_design.tclscript na ndekọ ebe aga.
• Iji mepụta ọrụ ịme anwansị, ị ga-agbarịrị script quartus_sh -t make_sim_design.tcl n'ime ndekọ ebe aga.

Mara: Ọ bụrụ na ị mepụtala design example wee mee mgbanwe na ya na paramita nchịkọta akụkọ, ị ga-emeghachite imewe exampka ịhụ mgbanwe gị emejuputara. Nhazi emepụtara ọhụrụ example adịghị overwrite ndị dị imewe example files.

Na-emepụta EMIF Design Example maka Simulation

Maka ngwa mmepe Intel Agilex, o zuru ezu ịhapụ ọtụtụ ntọala Intel Agilex EMIF IP na ụkpụrụ ndabara ha. Iji mepụta imewe exampmaka ịme anwansị, soro usoro ndị a:

1. Na Exampsite Designs tab, hụ na enyochala igbe Simulation. Họrọkwa usoro HDL Simulation achọrọ, ma ọ bụ Verilog ma ọ bụ VHDL.
2. Hazie EMIF IP wee pịa File ➤ Chekwaa iji chekwaa ntọala dị ugbu a n'ime ụdị IP onye ọrụ file ( .ip).
3. Pịa n'ịwa Example Chepụta na elu-nri akuku nke window.
4. Ezipụta akwụkwọ ndekọ aha maka imewe EMIF example wee pịa OK. Ọgbọ na-aga nke ọma nke imewe EMIF example emepụta otutu file setịpụrụ maka simulators dị iche iche na-akwado, n'okpuru ndekọ ndekọ sim/ed_sim.
5. Pịa File ➤ Wepụ ka ịpụ na windo Parameter Editor Pro. Sistemu na-akpalite, emebeghị mgbanwe na nso nso a. Mepụta ugbu a? Pịa Mba ka ịga n'ihu na usoro na-esote.

Emepụtara Simulation Design Example File Nhazi

Mara: Interface ebe nchekwa mpụga Intel Agilex FPGA IP na-akwado naanị VCS, ModelSim/QuestaSim, na Xcelium simulators. A na-eme atụmatụ nkwado simulator agbakwunyere na mwepụta n'ọdịnihu.

Mara: Ọ bụrụ na ị họrọghị igbe nrịbama nke Simulation ma ọ bụ Synthesis, ndekọ ebe ị na-aga nwere naanị ihe nrụpụta Platform files, nke Intel Quartus Prime software anaghị achịkọta ozugbo, mana nke ị nwere ike view ma ọ bụ dezie na Platform Designer. N'ọnọdụ a ị nwere ike ịme iwu ndị a ka ịmepụta njikọ na simulation file tent.

• Iji mepụta ọrụ anakọtara, ị ga-agbarịrị edemede quartus_sh -t make_qii_design.tcl na ndekọ ebe aga.
• Iji mepụta ọrụ ịme anwansị, ị ga-agbarịrị script quartus_sh -t make_sim_design.tcl n'ime ndekọ ebe aga.

Mara: Ọ bụrụ na ị mepụtala design example wee mee mgbanwe na ya na paramita nchịkọta akụkọ, ị ga-emeghachite imewe exampka ịhụ mgbanwe gị emejuputara. Nhazi emepụtara ọhụrụ example adịghị overwrite ndị dị imewe example files.

Simulation Versus Ngwaike mmejuputa iwu
Maka ịme anwansị interface ebe nchekwa mpụga, ị nwere ike họrọ ma ịwụsa nhazi ma ọ bụ nhazi zuru oke na taabụ Diagnostics n'oge ọgbọ IP.

Ụdị Simulation EMIF
Tebụl a na-atụnyere njirimara nke nlegharị anya na-awụ elu na ụdị nhazi zuru oke.

Tebụl 2. Ụdị ịme anwansị EMIF: Kwụsịa calibration na nhazi zuru oke

Mafee nhazigharị	Nhazi zuru oke
Simulation ọkwa sistemụ na-elekwasị anya na mgbagha onye ọrụ.	Simulation interface ebe nchekwa na-elekwasị anya na nhazigharị.
Ededeghị nkọwapụta nke mmezi.	Na-ejide stages nke calibration.
Nwere ikike ịchekwa na weghachite data.	Na-agụnye nhazi ọkwa, kwa-bit deskew, wdg.
Na-anọchite anya arụmọrụ ziri ezi.
Ọ naghị echebara skew osisi.

RTL Simulation Versus Mmejuputa ngwaike
Tebụl a na-akọwapụta isi ihe dị iche n'etiti simulation EMIF na mmejuputa ngwaike.

Tebụl 3. EMIF RTL Simulation Versus Hardware Mmejuputa

RTL Simulation	Mmejuputa ngwaike
Nios® mmalite na koodu mmezi na-arụ n'otu oge.	Nios mbido na koodu mmezi na-eme n'usoro.
Interface na-ekwupụta akara cal_done n'otu oge na simulation.	Arụmọrụ fitter na-ekpebi usoro nhazigharị, na ihu adịghị ekwupụta cal_done n'otu oge.

Ịkwesịrị ịme ihe ngosi RTL dabere na usoro okporo ụzọ maka ngwa imewe gị. Rịba ama na ịme anwansị RTL anaghị egosipụta igbu oge nchọta PCB nke nwere ike ime ka enweghị nghọta dị n'etiti simulation RTL na mmejuputa ngwaike.

 Iji ModelSim na-eme ka Interface ebe nchekwa dị na mpụga IP
Usoro a na-egosi otu esi eme ka EMIF chepụta example.

1. Ẹkedori Mentor Graphics* ModelSim software wee họrọ File ➤ Gbanwee ndekọ. Gaa na ndekọ ndekọ aha sim/ed_sim/ndụ n'ime ihe emepụtara example folda.
2. Nyochaa na egosipụtara mpio transcript n'okpuru ihuenyo ahụ. Ọ bụrụ na ahụghị windo transcript, gosi ya site na ịpị View ➤ transcript.
3. Na mpio transcript, mee isi iyi msim_setup.tcl.
4. Mgbe isi mmalite msim_setup.tcl gwụchara ọsọ, mee ld_debug na mpio transcript.
5. Mgbe ld_debug mechara ọsọ, chọpụta na egosipụtara mpio Ihe. Ọ bụrụ na ahụghị mpio ihe, gosi ya site na ịpị View ➤ Ihe.
6. Na mpio ihe, họrọ akara ngosi nke ịchọrọ ịme emume site na ịpị aka nri na họrọ Tinye Wave.
7. Mgbe ịmechara ịhọrọ akara ngosi maka ịme anwansị, mebie ọsọ - niile na mpio transcript. Simulation na-agba ọsọ ruo mgbe emechara.
8. Ọ bụrụ na anaghị ahụ simulation ahụ, pịa View ➤ Wave.

Ntinye pin maka Intel Agilex EMIF IP
Isiokwu a na-enye ntuziaka maka ntinye ntụtụ.

gafereview
Intel Agilex FPGA nwere usoro ndị a:

• Ngwa ọ bụla nwere ihe ruru ụlọ akụ I/O 8.
• Ụlọ akụ I/O ọ bụla nwere ụlọ akụ sub-I/O 2.
• Ụlọ akụ sub-I/O ọ bụla nwere ụzọ anọ.
• Ụzọ nke ọ bụla nwere ntụtụ I/O (GPIO) iri na abụọ.

Ntuziaka Pin General
Ndị a bụ ntuziaka ntụtụ izugbe.

Mara: Maka ozi ntụtụ zuru ezu karị, rụtụ aka na ngalaba Intel Agilex FPGA EMIF IP Pin na Resource Planing na ngalaba-kpọmkwem protocol maka usoro ebe nchekwa mpụga gị, na Mpụga ebe nchekwa Interfaces Intel Agilex FPGA IP User Guide.

• Gbaa mbọ hụ na ntụtụ maka interface ebe nchekwa mpụga nyere dị n'otu ahịrị I/O.
• Interface nke gafere ọtụtụ ụlọ akụ ga-enwerịrị ihe ndị a chọrọ:
  •  Ụlọ akụ ga-adị n'akụkụ ibe ha. Maka ozi gbasara ụlọ akụ dị n'akụkụ, rụtụ aka na EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
•  Adreesị na iwu yana ntụtụ ndị metụtara ga-ebirịrị n'ime otu ụlọ akụ subbank.
• Adreesị na iwu na ntụtụ data nwere ike ịkekọrịta obere ụlọ akụ n'okpuru ọnọdụ ndị a:
  • Adreesị na iwu na ntụtụ data enweghị ike ịkekọrịta ụzọ I/O.
  • Naanị ụzọ I/O ejighi ya na adreesị yana ụlọ akụ iwu nwere ike ịnwe ntụtụ data.

Tebụl 4. Ihe mgbochi ntụtụ n'ozuzu

Ụdị mgbaàmà	Mmachi
Data Strobe	Mgbama niile nke otu DQ ga-ebirịrị n'otu ụzọ I/O.
Data	Ntụtụ DQ emetụtara ga-ebirịrị n'otu ụzọ I/O. Maka protocol na-akwadoghị ahịrị data bidirectional, ekwesịrị ịchịkọta akara agụ iche na akara ederede.
Adreesị na Iwu	Adreesị na ntụtụ iwu ga-ebirịrị n'ebe ndị eburu ụzọ kọwaa n'ime obere ụlọ akụ I/O.

Mara: Maka ozi ntụtụ zuru ezu karị, rụtụ aka na ngalaba Intel Agilex FPGA EMIF IP Pin na Resource Planing na ngalaba-kpọmkwem protocol maka usoro ebe nchekwa mpụga gị, na Mpụga ebe nchekwa Interfaces Intel Agilex FPGA IP User Guide.

• Gbaa mbọ hụ na ntụtụ maka interface ebe nchekwa mpụga nyere dị n'otu ahịrị I/O.
• Interface nke gafere ọtụtụ ụlọ akụ ga-enwerịrị ihe ndị a chọrọ:
  • Ụlọ akụ ga-adị n'akụkụ ibe ha. Maka ozi gbasara ụlọ akụ dị n'akụkụ, rụtụ aka na EMIF Architecture: I/O Bank topic in the External Memory Interfaces Intel Agilex FPGA IP User Guide.
• Adreesị na iwu yana ntụtụ ndị metụtara ga-ebirịrị n'ime otu ụlọ akụ subbank.
• Adreesị na iwu na ntụtụ data nwere ike ịkekọrịta obere ụlọ akụ n'okpuru ọnọdụ ndị a:
  • Adreesị na iwu na ntụtụ data enweghị ike ịkekọrịta ụzọ I/O.
  • Naanị ụzọ I/O ejighi ya na adreesị yana ụlọ akụ iwu nwere ike ịnwe ntụtụ data.

Ịmepụta Nhazi Example na nhọrọ nhazi TG

Ihe emepụtara EMIF example gụnyere ngọngọ generator block (TG). Site na ndabara, imewe example na-eji ngọngọ TG dị mfe (altera_tg_avl) nke enwere ike ịtọgharịa naanị iji maliteghachi usoro okporo ụzọ nwere koodu siri ike. Ọ bụrụ na ọ dị mkpa, ị nwere ike họrọ ime ka onye nrụpụta okporo ụzọ ahazigharị (TG2) kama. Na configurable okporo ụzọ generator (TG2) (altera_tg_avl_2), ị nwere ike hazi usoro okporo ụzọ ozugbo site akara ndekọ-pụtara na ị na-adịghị na-achịkọta imewe ka ịgbanwe ma ọ bụ malitegharịa okporo ụzọ. Onye na-emepụta okporo ụzọ a na-enye njikwa dị mma n'ụdị okporo ụzọ ọ na-eziga na interface njikwa EMIF. Na mgbakwunye, ọ na-enye ndekọ ọkwa nwere ozi ọdịda zuru ezu.

Na-enyere ndị na-emepụta okporo ụzọ aka na imewe Example

Ị nwere ike ime ka onye na-emepụta okporo ụzọ ahazigharị site na taabụ Diagnostics dị na nchịkọta nhọrọ EMIF. Iji mee ka ndị na-emepụta okporo ụzọ ahazigharị, gbanye Jiri configurable Avalon trafic generator 2.0 na taabụ Diagnostics.

Onyonyo 6.

• Ị nwere ike họrọ iji gbanyụọ ụkpụrụ okporo ụzọ stage ma ọ bụ onye ọrụ ahaziri okporo ụzọ stage, mana ị ga-enwerịrị opekata mpe otu stage nyeere. Maka ozi gbasara stages, rụtụ aka na ụkpụrụ okporo ụzọ ahazi na ụkpụrụ okporo ụzọ ahaziri onye ọrụ na ntụzịaka onye ọrụ IP Intel Agilex FPGA Mpụga.
• Oke oge ule TG2 na-emetụta naanị ụkpụrụ okporo ụzọ ndabara. Ị nwere ike ịhọrọ oge ule nke mkpụmkpụ, ọkara ma ọ bụ enweghi ngwụcha.
• ị nwere ike họrọ nke ọ bụla n'ime ụkpụrụ abụọ maka ihe nrụnye TG2 Configuration Interface:
  • JTAG: Na-enye ohere iji GUI na njikwa sistemụ. Maka ozi ọzọ, rụtụ aka na Interface Generator Configuration Interface na Mpụga ebe nchekwa Interfaces Intel Agilex FPGA IP Ntuziaka.
  • Mbupu: Na-enye ohere iji mgbagha RTL omenala jikwaa ụkpụrụ okporo ụzọ.

Iji Design Exampya na EMIF Debug Toolkit

Tupu ịmalite EMIF Debug Toolkit, hụ na ị haziela ngwaọrụ gị na mmemme. file nke nwere EMIF Debug Toolkit agbanyere. Iji malite EMIF Debug Toolkit, soro usoro ndị a:

1. N'ime sọftụwia Intel Quartus Prime, mepee njikwa sistemụ site na ịhọrọ Ngwaọrụ ➤ Ngwaọrụ nbipu sistemu ➤ Sistemụ njikwa.
2. [Kwuo nzọụkwụ a ma ọ bụrụ na ọrụ gị emeghelarị na sọftụwia Intel Quartus Prime.] N'ime Sistemu Console, buru ihe SRAM. file (.sof) nke ị jiri hazie bọọdụ ahụ (dị ka akọwara na ihe achọrọ maka iji EMIF Debug Toolkit, na Mpụga ebe nchekwa Interfaces Intel Agilex FPGA IP User Guide).
3. Họrọ ihe atụ iji mebie.
4. Họrọ EMIF Calibration Debug Toolkit maka EMIF mmezi mmezi, dị ka akọwara na Ịmepụta Nhazi Ex.ample ya na nhọrọ ndozi mmezi. N'aka nke ọzọ, họrọ EMIF TG Configuration Toolkit maka nrụpụta ihe nrụpụta okporo ụzọ, dị ka akọwara n'imepụta Design Ex.ample na nhọrọ nhazi TG.
5. Pịa Mepee Toolkit ka imepe isi view nke EMIF Debug Toolkit.
6. Ọ bụrụ na enwere ọtụtụ EMIF n'ime atụmatụ akwadoro, họrọ kọlụm (ụzọ na-aga JTAG nna ukwu) na ID interface ebe nchekwa nke ihe atụ EMIF nke iji mee ka ngwa ngwa rụọ ọrụ.
7. Pịa Interface rụọ ọrụ ka ikwe ka ngwa ngwa gụọ paramita interface yana ọkwa nhazi.
8. Ị ga-ehichapụ otu interface n'otu oge; ya mere, iji jikọọ na interface ọzọ na imewe, ị ga-ebu ụzọ gbanyụọ interface dị ugbu a.

Ndị a bụ examples nke akụkọ sitere na EMIF Calibration Debug Toolkit na EMIF TG Configuration Toolkit:, n'otu n'otu.

Mara: Maka nkọwapụta na nzizi mmezi, rụtụ aka na Nchọpụta nbibi site na iji ngwa nbibi ihe nrụnye ebe nchekwa dị na mpụga, na ntụzịaka onye ọrụ IP Agilex FPGA Mpụga.

Mara: Maka nkọwa na nbipu ihe nbibi jenerato okporo ụzọ, rụtụ aka na Interface Onye ọrụ nhazi Generator Configuration, na ntụzịaka onye ọrụ IP Intel Agilex FPGA Mpụga.

Imepụta ExampNkọwa maka Interfaces ebe nchekwa mpụga Intel Agilex FPGA IP

Mgbe ị mebere ma mepụta IP EMIF gị, ị nwere ike ịkọwapụta na sistemụ ahụ na-emepụta akwụkwọ ndekọ aha maka ịme anwansị na njikọ. file setịpụ, ma mepụta ihe file na-esetịpụ na-akpaghị aka. Ọ bụrụ na ịhọrọ Simulation ma ọ bụ Synthesis n'okpuru Example Design Files na Exampna Designs tab, usoro na-emepụta a zuru ezu simulation file setịpụrụ ma ọ bụ njikọ zuru oke file setịpụ, dịka nhọrọ gị siri dị.

Nhazi nhazi Example
Nhazi nhazi example nwere nnukwu ihe mgbochi egosiri na foto dị n'okpuru.

• Onye na-emepụta okporo ụzọ, nke bụ Avalon®-MM example ọkwọ ụgbọ ala nke na-emejuputa atumatu pseudo-random nke na-agụ na-ede na a parameterized ọnụ ọgụgụ nke adreesị. Onye na-emepụta okporo ụzọ na-enyochakwa data a na-agụ site na ebe nchekwa iji hụ na ọ dabara na data edere wee kwupụta ọdịda ma ọ bụghị ya.
• Ihe atụ nke interface ebe nchekwa, nke gụnyere:
  • Ihe njikwa ebe nchekwa na-agafe n'etiti interface Avalon-MM na interface AFI.
  • PHY, nke na-arụ ọrụ dị ka interface n'etiti ihe njikwa ebe nchekwa na ngwaọrụ ebe nchekwa mpụga iji rụọ ọrụ ịgụ na ide.

Onyonyo 7. Synthesis Design Example

Mara: Ọ bụrụ na otu ma ọ bụ karịa nke PLL Sharing Mode, DLL Sharing Mode, ma ọ bụ OCT Ịkekọrịta Mode ka edobere na uru ọ bụla ọzọ karịa Enweghị Ịkekọrịta, nhazi nhazi ex.ample ga-enwe ihe abụọ okporo ụzọ generator/ncheta interface ihe atụ. A na-ejikọta ihe atụ generator/ntụgharị ebe nchekwa okporo ụzọ abụọ naanị site na njikọ PLL/DLL/OCT nkekọrịta dịka ntọala oke akọwapụtara. Ihe atụ ihe na-emepụta okporo ụzọ/ihe ebe nchekwa na-egosi otu ị ga-esi mee njikọ dị otú ahụ n'ụdị nke gị.

Imepụta ihe ngosi Example
Ihe ngosi simulation example nwere nnukwu ihe mgbochi egosiri na foto a.

• Ihe atụ nke nhazi nhazi example. Dị ka akọwara na ngalaba gara aga, nhazi nhazi example nwere ihe na-emepụta okporo ụzọ, akụrụngwa mmezi, na ihe atụ nke interface ebe nchekwa. Ndị a na-egbochi ndabara na ụdị ịme anwansị nkịtị ebe ọ dabara adaba maka ịme anwansị ngwa ngwa.
• Ụdị ebe nchekwa, nke na-arụ ọrụ dị ka ihe atụ nke na-agbaso nkọwa usoro ebe nchekwa. Ọtụtụ mgbe, ndị na-ere ebe nchekwa na-enye ụdị ịme anwansị maka akụrụngwa ebe nchekwa ha akọwapụtara nke ị nwere ike ibudata na ha websaịtị.
• Onye na-enyocha ọkwa, nke na-enyocha akara ọkwa site na interface ebe nchekwa IP na mpụta okporo ụzọ, iji gosi ọkwa ngafe ma ọ bụ ọnọdụ dara.

Onyonyo 10. Nkịtị ịme anwansị Example

Exampma chepụta Interface Tab
Onye nchịkọta akụkọ parameter gụnyere Example Designs tab nke na-enye gị ohere ịmegharị ma mepụta imewe gị bụbuamples.

Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ

Ụdị IP bụ otu ụdị sọftụwia Intel Quartus Prime Design Suite ruo v19.1. Site na ụdị sọftụwia Intel Quartus Prime Design Suite 19.2 ma ọ bụ karịa, IP nwere atụmatụ mbipụta IP ọhụrụ. Ọ bụrụ na edepụtaghị ụdị isi IP, ntuziaka onye ọrụ maka ụdị IP isi gara aga na-emetụta.

Ụdị IP Core	Ntuziaka onye ọrụ
2.4.0	Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ
2.3.0	Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ
2.3.0	Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ
2.1.0	Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ
19.3	Interface ebe nchekwa mpụga Intel Agilex FPGA IP Design ExampEbe nchekwa ihe ntuziaka onye ọrụ

Akụkọ ndozigharị akwụkwọ maka ntụgharị ebe nchekwa mpụga Intel Agilex FPGA IP Design Example ntuziaka onye ọrụ

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2021.06.21	21.2	2.4.2	N'ime Imepụta Exampna Ndenye Mmalite isi: • Etinyere ndetu na Ịchịkọta na ịhazi Intel Agilex EMIF Design Example isiokwu. • gbanwee aha nke Ịmepụta Nhazi Example ya na nhọrọ ndozi mmezi isiokwu. • gbakwunyere ya Ịmepụta Nhazi Example na nhọrọ nhazi TG na Na-enyere ndị na-emepụta okporo ụzọ aka na imewe Example isiokwu. • Megharịrị nzọụkwụ 2, 3, na 4, emelitere ọtụtụ ọnụ ọgụgụ, tinyekwa ndetu, na Iji Design Exampya na EMIF Debug Toolkit isiokwu.
2021.03.29	21.1	2.4.0	N'ime Imepụta Exampna Ndenye Mmalite isi: • Etinyere ndetu na Na-amụpụta EMIF Design Synthesizable Example na Na-emepụta EMIF Design Example maka Simulation isiokwu. • emelitere ya File Eserese ihe owuwu dị na Na-emepụta EMIF Design Example maka Simulation isiokwu.
2020.12.14	20.4	2.3.0	N'ime Imepụta Exampna Ndenye Mmalite isi, mere mgbanwe ndị a: • emelitere ya Na-amụpụta EMIF Design Synthesizable Example isiokwu ịgụnye ọtụtụ EMIF aghụghọ. • Emelitere ọnụ ọgụgụ maka nzọụkwụ 3, na Na-emepụta EMIF Design Example maka Simulation isiokwu.
2020.10.05	20.3	2.3.0	N'ime Imepụta Exampna Ntuziaka mmalite ngwa ngwa isi, mere mgbanwe ndị a: • N'ime Ịmepụta ọrụ EMIF, emelitere onyonyo na nzọụkwụ 6. • N'ime Na-amụpụta EMIF Design Synthesizable Example, emelitere ọnụ ọgụgụ na nzọụkwụ 3. • N'ime Na-emepụta EMIF Design Example maka Simulation, emelitere ọnụ ọgụgụ na nzọụkwụ 3. • N'ime Simulation Versus Ngwaike mmejuputa iwu, doziri obere typo na tebụl nke abụọ. • N'ime Iji Design Exampya na EMIF Debug Toolkit, nzọụkwụ 6 gbanwere, gbakwunyere nzọụkwụ 7 na 8.
gara n'ihu…

Ụdị akwụkwọ	Intel Quartus Prime Version	Ụdị IP	Mgbanwe
2020.04.13	20.1	2.1.0	• N'ime Ihe gbasara isi, gbanwetụrụ tebụl na Ozi mwepụta isiokwu. • N'ime Imepụta Exampna Ntuziaka mmalite ngwa ngwa isi: - gbanwetụrụ nzọụkwụ 7 na ihe oyiyi metụtara, na Na-amụpụta EMIF Design Synthesizable Example isiokwu. - Gbanwee ya Na-emepụta ihe osise Example na Nhọrọ Debug isiokwu. - Gbanwee ya Iji Design Exampya na EMIF Debug Toolkit isiokwu.
2019.12.16	19.4	2.0.0	• N'ime Imepụta Exampna Ndenye Mmalite isi: - Emelitere ihe atụ na nzọụkwụ 6 nke Ịmepụta ọrụ EMIF isiokwu. - Emelitere ihe atụ na nzọụkwụ 4 nke Na-amụpụta EMIF Design Synthesizable Example isiokwu. - Emelitere ihe atụ na nzọụkwụ 4 nke Na-emepụta EMIF Design Example maka Simulation isiokwu. - Gbanwee nzọụkwụ 5 na Na-emepụta EMIF Design Example maka Simulation isiokwu. - Gbanwee ya Ntuziaka Pin General na Ụlọ akụ dị n'akụkụ ngalaba nke Ntinye pin maka Intel Agilex EMIF IP isiokwu.
2019.10.18	19.3		• N'ime Ịmepụta ọrụ EMIF isiokwu, jiri isi 6 emelitere onyonyo a. • N'ime Ịmepụta na ịhazi EMIF IP isiokwu, jiri nzọụkwụ 1 emelitere ọnụ ọgụgụ ahụ. • Na tebụl na Ntuziaka nchịkọta akụkọ nke Intel Agilex EMIF Parameter isiokwu, gbanwere nkọwa maka bọọdụ tab. • N'ime Na-amụpụta EMIF Design Synthesizable Example na Na-emepụta EMIF Design Example maka Simulation isiokwu, emelitere onyonyo na nzọụkwụ 3 nke isiokwu ọ bụla. • N'ime Na-emepụta EMIF Design Example maka Simulation isiokwu, emelitere na Emepụtara Simulation Design Example File Nhazi chepụta ma gbanwee ndetu na-esote ọnụ ọgụgụ ahụ. • N'ime Na-amụpụta EMIF Design Synthesizable Example isiokwu, gbakwunyere nzọụkwụ na ọnụ ọgụgụ maka otutu interfaces.
2019.07.31	19.2	1.2.0	• agbakwunyere Banyere Interface ebe nchekwa mpụga Intel Agilex FPGA IP isi na Ozi mwepụta. • Ụbọchị emelitere na nọmba ụdị. • Nkwalite obere na Nhazi nhazi Example chepụta na Nhazi nhazi Example isiokwu.
2019.04.02	19.1		• Ntọhapụ mbụ.

Akụkọ ndozigharị akwụkwọ maka ntụgharị ebe nchekwa mpụga Intel Agilex FPGA IP Design Example ntuziaka onye ọrụ

Akwụkwọ / akụrụngwa

intel UG-20219 ebe nchekwa mpụga Intel Agilex FPGA IP Design Example [pdf] Ntuziaka onye ọrụ UG-20219 ebe nchekwa mpụga Intel Agilex FPGA IP Design Example, UG-20219, Interfaces ebe nchekwa mpụga Intel Agilex FPGA IP Design Example, Interfaces Intel Agilex FPGA IP Design Example, Agilex FPGA IP Design Example

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